SIC MOSFET semiconductor package and related method

Abstract

The present invention is entitled "SIC MOSFET semiconductor package and related methods". The present invention discloses a semiconductor package. A specific embodiment of the semiconductor package may include: one or more semiconductor dies, the one or more semiconductor dies are coupled between a base frame and a clamp, the base frame includes a gate pad of the base frame coupled to the gate pad of the one or more semiconductor dies and a source pad of the base frame coupled to the source pad of the one or more semiconductor dies, wherein the gate pad of the base frame extends beyond the periphery of the one or more semiconductor dies.

Description

[0001] Cross-references to related patent applications

[0002] This document claims the benefit of the filing date of U.S. Provisional Patent Application 62 / 733,793 to Estacio et al., entitled “SiC MOSFET Semiconductor Packages and Related Methods,” filed on September 20, 2018, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Aspects of this document generally relate to systems and methods for packaging semiconductor devices. More specific embodiments also include packages for silicon carbide semiconductor devices. Background Art

[0004] The semiconductor device is enclosed in a package to achieve electrical and mechanical connection with a circuit board or other electronic devices coupled to the package. Summary of the invention

[0005] An embodiment of a semiconductor package may include: one or more semiconductor dies, the one or more semiconductor dies coupled between a baseframe and a fixture, the baseframe including a gate pad of the baseframe coupled to a gate pad of the one or more semiconductor dies and a source pad of the baseframe coupled to a source pad of the one or more semiconductor dies, wherein the gate pad of the baseframe extends beyond the periphery of the one or more semiconductor dies.

[0006] Embodiments of the semiconductor package may include one, all, or any of the following:

[0007] The Ag sintered layer may be coupled between the one or more semiconductor dies, the fixture, and the base frame.

[0008] The clamp may include a drain pad, and the clamp is coupled to the drain pads of the one or more semiconductor dies.

[0009] A mold compound may encapsulate one or more of the one or more semiconductor dies on four sides of the die.

[0010] A redistribution layer may be included between gate pads of the one or more semiconductor dies and a gate pad of the base frame.

[0011] A heat sink may be directly coupled to one or more semiconductor dies through a die attach material.

[0012] The package may be configured to provide electrical isolation between a terminal ring of the one or more semiconductor dies and a source pad of the one or more semiconductor dies over an operating voltage range of 400V to 1700V.

[0013] An embodiment of a semiconductor package may include: one or more semiconductor dies coupled between a base and a heat sink, the base including a gate pad of the base coupled to a gate pad of the one or more semiconductor dies and a source pad of the base coupled to a source pad of the one or more semiconductor dies, wherein the gate pad of the base extends beyond the periphery of the one or more semiconductor dies.

[0014] Embodiments of the semiconductor package may include one, all, or any of the following:

[0015] The Ag sintered layer may be coupled between the one or more semiconductor dies, the heat sink, and the base frame.

[0016] The heat sink may include a drain pad, and the heat sink may be coupled to the drain pads of the one or more semiconductor dies.

[0017] The mold compound may encapsulate the one or more semiconductor dies on four sides of the die.

[0018] A redistribution layer may be included between gate pads of the one or more semiconductor dies and a gate pad of the base frame.

[0019] An embodiment of a method for forming a semiconductor package may include: providing a base frame; providing two or more semiconductor dies, each of which is coupled to a heat sink or a clamp, and the two or more semiconductor dies are coupled together through a wafer carrier; coupling an Ag sintering material to one or more gate pads and one or more source pads of the base frame; pressure-sintering one or more gate pads and one or more source pads of the one or more semiconductor dies with the Ag sintering material; molding a molding compound over the base frame and the two or more semiconductor dies; and grinding away the wafer carrier to expose the heat sink or clamp, each of which includes a drain contact.

[0020] Embodiments of a method of forming a semiconductor package may include one, all, or any of the following:

[0021] The method may include coupling the two or more semiconductor dies to a fixture after the pressure sintering.

[0022] The method may include coupling a clamp to a base frame.

[0023] The gate pad of the pedestal may extend beyond the perimeter of the two or more semiconductor dies.

[0024] The two or more semiconductor dies may have all four sides of each of the two or more semiconductor dies encapsulated by the molding compound.

[0025] The method may include including the package in an automotive high power module (AHPM) module.

[0026] The foregoing and other aspects, features and advantages will be apparent to those skilled in the art from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Embodiments will be described below in conjunction with the accompanying drawings, in which like reference numerals represent like elements, and:

[0028] Figure 1 shows an exploded view of a first package embodiment, including a top (live worm) view and a bottom (dead worm) view;

[0029] Figure 2 Shows Figure 1 A top perspective view and a side partial see-through view of a package of FIG.

[0030] Figure 3 shows a package design in which two SiC MOSFETs are coupled with the gate sides facing each other;

[0031] Figure 4 A top perspective view showing a side view of a redistribution layer (RDL) formed by a combination of an internal RDL and a pedestal structure;

[0032] Figure 5 A pad structure is shown in which the height of the polyimide passivation creates a gap in the polyimide, thereby preventing pressure sintering from occurring between the Ag sintering material and the pad material;

[0033] Figure 6 shows a pad structure in which the height of the polyimide passivation creates a gap in the Cu pad material, thereby preventing pressure sintering from occurring between the Ag sintering material and the pad material;

[0034] Fig. 7A Three separate Ag sintered layers applied directly over each source contact of a SiC device are shown;

[0035] Figure 7B A single Ag sintered layer is shown applied directly over all source contacts of a SiC device;

[0036] Figure 8 Shows Fig. 7A and Figure 7B Side view of

[0037] Fig. 9 Shows the formation and Figure 1 Embodiments of a method for a semiconductor package similar to the package shown in ;

[0038] Fig.10 shows a top view of a single SiC MOSFET die and a side view of a Cu heat sink coupled to the back side of the die via a pressure assisted Ag sintering material, and shows an embodiment of a method of coupling the heat sink to the SiC die;

[0039] Fig.11 A process flow of an embodiment of a method of coupling a SiC die to a heat sink is shown;

[0040] Fig.12 A process flow of an embodiment of a method of forming a semiconductor package without using a drain fixture is shown;

[0041] Fig.13 Various views showing alternative semiconductor package embodiments;

[0042] Fig.14 It shows that Fig.13 The internal structure of the package shown;

[0043] Fig.14A and Fig. 14B It is along Fig.14 A cross-sectional view taken along the indicated section line;

[0044] Fig.15 shows a close up view of an embodiment of an automotive high power module including two SiC MOSFET packages;

[0045] Fig.16 The following are shown: an embodiment showing a pre-molded pedestal with four dies placed thereon; and a side view and an end view showing the thickness of the molding compound on the pedestal;

[0046] Fig.17 Shown after applying additional molding compound Fig.16 packaging; and

[0047] Fig.18 Shown after grinding Fig.17 An implementation of a package. DETAILED DESCRIPTION

[0048] The present disclosure, its various aspects, and embodiments are not limited to the specific components, assembly processes, or method elements disclosed herein. Many other components, assembly processes, and / or method elements known in the art that are consistent with the intended semiconductor package will obviously be used with the specific embodiments of the present disclosure. Thus, for example, although the present invention discloses specific embodiments, such embodiments and implementation components may include any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, etc. known in the art for such semiconductor packages and implementation components and methods that are consistent with the intended operation and method.

[0049] A wide variety of semiconductor devices are made from a wide variety of semiconductor substrates. In this document, a fan-out package design for a metal oxide field effect transistor (MOSFET) device fabricated on a silicon carbide semiconductor substrate is disclosed. Although the structure shown in the solution is specific to the MOSFET design disclosed in this document, the principles disclosed herein can be applied to other semiconductor device types (rectifiers, insulated gate bipolar transistors [IGBTs], bipolar junction transistors, etc.) formed on any of a wide variety of semiconductor substrate types, such as (by way of non-limiting example) single crystal silicon, polycrystalline silicon, glass, silicon on insulator, gallium arsenide, sapphire, ruby, or any other semiconductor substrate type.

[0050] refer to Figure 1 , showing an exploded view of a first package embodiment, including a top (live worm) view and a bottom (dead worm) view. As shown, the base of the package design includes a metal base frame 2. In various embodiments, the base frame 2 can be made of copper with Ag plating on contact pads, which are designed to interact / combine with the circuit board to which the package will be coupled. In various embodiments, the base frame 2 can be etched, such as, by non-limiting example, half-etched or etched to another desired portion of the base frame thickness. As shown, on various tube core support portions, a layer of Ag sintered material 4 is placed. In various embodiments, the Ag sintered material 4 can be 30 microns thick, but in various embodiments, the material can be thicker or less thick. In the package shown, four SiC MOSFET devices 6 are each individually placed above the Ag sintered material 4, which serves as an interconnect and bonding material with the base frame 2. As shown, the SiC MOSFET devices 6 are flipped from the side on which these devices are manufactured to the back metal side of the tube core (flip chip). Additional Ag sintered material 4 is coupled over the back metal of each die.

[0051] As shown, a metal clamp 10 is coupled to the Ag sintered material 4 and the SIC MOSFET device 6. In various embodiments, the clamp 10 is bare copper with Ag plating on the contact pads and can be etched to various thicknesses, such as any thickness disclosed herein in various embodiments. A molding compound 12 (shown in dashed lines in this see-through view) is used to cover the clamp 10 and the base frame 2. Since the SiC MOSFET devices 6 are coupled between the base frame 2 and the clamp 10, they are also completely encapsulated by the molding compound 12 (see the unexploded top and bottom views). In various embodiments, as shown, all four sides of the SiC MOSFET die 6 are encapsulated by the molding compound 12, which can minimize die corner stress and exposed silicon drain metallization.

[0052] refer to Figure 2 , showing Figure 1 A top perspective view and a side partial see-through view of the package. As shown, the shape of the sides of the clamp 10 and the sides of the base frame 2 include various portions that are designed to become contacts 14 that extend beyond the perimeter of the various SiC MOSFET dies, allowing the package to be coupled to a motherboard or circuit board. Since the contacts 14 are located outside the perimeter of the die, the package design can be referred to as a "fan-out" package design. Figure 3 A package design is shown in which two SiC MOSFETs 6 are coupled with the gate sides facing each other. The structure of the gate contact in this package is shown, showing the various layers coupled between the base frame 2 (intermediate layer 18, STM layer 20 and internal redistribution layer 22). Note how the perimeter of the material of the base frame 2 forms a contact that extends beyond the perimeter of the SiC die 6, fanning out from the contact at a physical location away from the actual gate contact location of the SiC die. Figure 3 It is also shown how the clamp 10 covers the entire surface of the SiC MOSFET die 6 .

[0053] exist Figure 4, a specific design of a redistribution layer formed by a combination of the internal RDL and the structure of the base frame 2 is shown in . In various embodiments, because the size of the gate contact 24 is specifically much larger than the physical size of the gate contact on the SiC die itself, the gate contact 24 "fans out" the gate contact of the SiC die to a larger area. Moreover, because a single large contact pad 26 is used to couple with the three source pads of the SiC die, the size of the source pad 26 can be maximized. This method of maximizing the size of the gate contact 24 is contrary to those design methods that are designed to make the gate pad occupy the minimum area in the package so that the source active area of ​​the SiC MOSFET device can be maximized. In such an embodiment, although maximizing the size of the source contact 26 in the package enables the device to be lower in resistivity and minimize hot spots, the design rules dictate that there must be a minimum distance between the source pad 26 and the gate pad 24. Some lead frame designs do not allow SiC MOSFETs to achieve this minimum spacing (300μm in some embodiments). However, because fan-out technology is used for gate pad 24, the size of source pad 26 can increase as the material of gate pad 24 extends over the perimeter of die 6 into the area covered by mold compound 12. In this way, minimum spacing can be achieved and the size of source pad 26 is maximized in the lead frame design.

[0054] One of the reasons for using a larger gate contact size is that the design rules for various embodiments using Ag pressure sintered materials require that any contact used in the process needs to be at least 1 mm x 1 mm in size. Without the gate contacts on the die being at least that size, attempts to use 1 mm x 1 mm sized Ag sintered materials overlaid with smaller contacts result in an increased risk of STM lift-off due to the topography of the polyimide passivation (in various embodiments, the layer is at most about 5 microns to about 18 microns or more thick). Figure 5 and Figure 6 Two different pad structures are shown, where the height of the polyimide (PI) passivation 28 is such that the polyimide itself ( Figure 5 ) or Cu pad material 30( Figure 6 ) creates a gap, thereby preventing pressure sintering from occurring between the Ag sintering material and the pad material itself.

[0055] The new contact design disclosed herein allows the Ag sintering material to be applied in either of two patterns: Fig. 7A In a pattern where three separate layers 32 are applied directly over each source contact of a SiC device; or in a pattern where Figure 7B, a single large layer 34 is applied over all three source contacts of the SiC device. Since the gate contacts in this package can fan out beyond the die perimeter itself, the redistribution layer coupled over the gate contacts allows the source contacts to extend over the perimeter of the gate contacts of the SiC die in some embodiments, thereby maximizing the size of the source contacts of the package. In various embodiments, the use of the redistribution layer also eliminates the need to apply the Ag sintering material directly to the gate contacts of the SiC die itself, meaning that the Ag sintering material can be applied only over a completely flat surface of the redistribution layer, thereby eliminating issues regarding the height of the polyimide passivation material around the gate contacts of the SiC die, while still allowing Ag sintering to be employed. Figure 8 yes Fig. 7A or Figure 7B A side view of any structure of FIG. 1 shows the height of the Ag sintered material 4, the location of the redistribution layer 22, the source contact 26 and the gate contact 24 of the SiC device itself, and shows the fan-out effect of the gate pad 24 of the package.

[0056] In various embodiments, use of the novel fan-out contact design disclosed herein can allow the use of gate pad sizes ranging from about 0.1 mm x 0.1 mm to about 2 mm x 2 mm. This range of gate pad sizes allows the size of the gate pad to be selected based on device characteristics and reduces the need to control pad size through process design rule requirements.

[0057] In various embodiments, the thickness and type of molding compound between the die isolation ring or terminal ring and the RDL in the package or the metal source contact in the package can be selected to provide sufficient electrical isolation for operating voltages of about 400 V to about 1700 V. In addition to operating voltage considerations, the thickness and type of molding compound will also vary depending on the type of semiconductor device being packaged (IGBT, SiC MOSFET, etc.).

[0058] refer to Fig. 9 , showing the formation and Figure 1An embodiment of a method for a semiconductor package similar to the package shown in . As shown in the figure, on the left side, the processing of the base frame 2 begins with applying the Ag sintered film 4 to the lead frame pad designed to be coupled to the SiC tube core 6 (film transfer on the base frame step). On the right side, the process of processing the fixture 10 is shown, wherein the SiC tube core 6 is each individually coupled to the fixture portion of the fixture 10 using the tube core attachment material, and then the Ag sinter 4 is applied, and the pressure sintering process is used to bond the Ag sinter 8 to the gate pad and source pad of the SiC tube core. As shown in the figure, the fixture 10 is then flipped (the tube core is also flipped), and the Ag sintered material 4 on the base frame 2 is coupled to the SiC tube core 6. The pressure Ag sintering process is then used to bond the Ag sintered material 4 to the SiC tube core 6. In some embodiments, after the pressure Ag sintering process, a solvent cleaning process can be used to remove any residues, followed by plasma cleaning. The die molding process is then performed via any of a wide variety of molding techniques, including (by way of non-limiting example) transfer molding, compression molding, injection molding, and the like. A post-molding curing (PMC) molding process is then used to complete the curing of the molding material covering the fixture 10 and the base frame 2. After the PMC molding process, the package is then ground to expose the upper surface of the fixture 10. In various embodiments, the base frame side of the package may also be ground to expose the contacts and / or heat sink (as will be disclosed in more detail below). After grinding the package, a cutting process is performed to separate the various packages from each other (because the process is performed on two or more lead frames at a time). By way of non-limiting example, the cutting process may be a sawing process, a laser process, a spray ablation process, or a plasma etching process.

[0059] In various package implementations, cooling of the SiC MOSFET dies may be performed using a heat sink coupled directly to each die. Fig.10 On the right is shown a top view of a single SiC MOSFET die 6 and a side view showing a copper heat sink 36 (brick) coupled to the back side of the die 6 via a pressure assisted Ag sintering material similar to those disclosed in this document. Other materials may be used to couple the heat sink 36 to the die, such as (by way of non-limiting example) a non-conductive tacky adhesive, a die attach film, a conductive epoxy, a metal, a metal alloy, or any other material capable of bonding the die to the heat sink material. In various embodiments, the heat sink 36 may have a thickness between about 100 microns and about 500 microns, depending on the desired thermal performance.

[0060] Fig.10The processing flow on the right shows an embodiment of a method for coupling a heat sink to a SiC die. As shown, a wafer carrier 38 is provided, which can be made of (by non-limiting example) a semiconductor substrate, glass, metal, polymer material, composite material, or other materials capable of supporting a die and a heat sink. Then, on the wafer carrier 38, each heat sink 36 is coupled at a predetermined position with an adhesive material, which in some embodiments can be a non-conductive adhesive adhesive. Each SiC die 6 is then coupled above each heat sink 36 using any of the above-mentioned die bonding materials. The wafer carrier 38 is then cut to separate the heat sink 36 and the die 6 from each other. At this point, the combined SiC die / heat sink / wafer carrier can be processed by various processing steps to couple the die 6 to the base frame 2 and the fixture 10, and an additional grinding step is added to remove the wafer carrier material from the heat sink. In various embodiments, a grinding step may be performed prior to processing with the fixture 10 and the pedestal 2 to remove the wafer carrier material from the heat sink.

[0061] Fig.10 A process is shown where a single heat sink is paired with a single SiC die. This embodiment forms a Fig. 9 However, in other package embodiments, a method of coupling a SiC die to a heat sink may allow for simultaneous processing and parallel assembly of multiple SiC dies through the package formation steps. Fig.11 , a process flow of an embodiment of the method is shown on the right. A wafer carrier 38 (which can be any of those disclosed in this document) is provided, and then each heat sink 36 (in this case a copper block) is mounted on the wafer carrier at a predetermined position using an adhesive (such as a non-conductive adhesive adhesive). In various embodiments, the predetermined positions can be designed to form an arrangement of SiC dies 6, which can then be subsequently processed in parallel through the remaining package assembly process. Fig.11 The schematic diagram in shows a four-sided arrangement, indicating that 4 dies can be processed in parallel. However, in various method embodiments, more or less than 4 dies can be processed.

[0062] In various method embodiments, the SiC die 6 can then be mounted to the heat sink 36 using a pressure-assisted Ag sintering process similar to any disclosed in this document. In other embodiments, any other die adhesive material disclosed herein can be employed to bond the heat sink to the die. The wafer carrier 38 is then cut to allow two or more of the SiC die 6 / heat sink 36 to be combined together, allowing the combined dies to be processed in parallel through the remainder of the packaging process. A wafer carrier grinding step is then added to the packaging process to remove the wafer carrier 38 and expose the heat sink 36.

[0063] In various embodiments where the SiC die are processed in parallel using a wafer carrier material, where Ag sintering is performed, the material of the heat sink itself can form the material of the drain contact. Where the package design permits, the parallel die can all share the same drain contact, which can double as a heat transfer structure. Fig.11 The left side of the figure shows a top view of four parallel SiC dies sharing a common source and gate, and below is a bottom view of the same four dies showing a common drain 40 formed from a heat sink material. In a package formed using a parallel processing method embodiment, the drain fixture 10 may not be included in the package structure, and thus the processing method steps involving the drain fixture 10 may be omitted. Fig.12 An embodiment of this method is shown, indicating that when the fixture is omitted and parallel processing using the integrated heat sink 36 is included, it is no longer necessary to perform Fig. 9 While the base frame 2 is still used to form the source / drain connections, the heat spreader 36 (or a metal layer formed thereon) forms the common drain 40 connection.

[0064] Fig.13 Another embodiment of a package formed using the principles disclosed herein is shown, showing different orientations / shapes of the source contact 44, gate contact 42, and drain contact 40 of the device. These contact designs can be used for various SiC dies using various pedestal 2 and etch fixture 10 designs. There are a wide variety of possible source contact, gate contact, and drain contact arrangements, shapes, locations, and orientations using the principles disclosed in this document. Fig.14 include Fig.13 The internal structure of the package is shown in the figure, Fig.14A and Fig. 14B Along Fig.14 The cross-sectional views taken along the various cut lines shown illustrate the die and the locations of the gate and source pads.

[0065] The various semiconductor packages disclosed herein may be included as components in additional semiconductor package types to allow them to be ported out in a manner that meets the requirements of various applications. Fig.15 A general view and a close-up view of an automotive high power module (AHPM) in which two SiC MOSFET packages are included are shown. These figures show how the various contacts on the device are then routed to pins and contacts, allowing the device to operate by contacting the gate, source and drain regions of the two packages. A wide variety of package designs can employ the packages disclosed in this document as sub-components using the principles disclosed herein.

[0066] In various semiconductor package embodiments, the substrate 2 may be pre-molded on the first side of the substrate 2 before the SiC die is coupled to the substrate 2 . Fig.16 The following are shown: an embodiment of a pre-molded pedestal 2 showing four dies 6 placed thereon; and a side view and an end view showing the thickness of the molding compound on the pedestal 2. After the dies are coupled to the pedestal 2 (which can be done using any of the techniques and systems disclosed in this document), a fan-out RDL layer can be applied to the pedestal 2 to form gate and source contacts. An additional die molding step is then performed to cover the sides of the dies, leaving the gate and source contacts exposed. The molding compound on the sides of the pedestal 2 opposite the gate and source contacts is then ground away to expose the drain contacts of the pedestal 2. Fig.17 After applying additional molding compound 46 Fig.16 The package and Fig.18 An embodiment of the package is shown after the grinding step. This particular technique can be modified, including using any of the processes disclosed in this document to attach the heat sink to the die. In various method embodiments, Ag sintering materials and pressure assisted sintering processes similar to those disclosed in this document can also be utilized.

[0067] Various semiconductor package embodiments disclosed herein may include a heat spreader directly coupled to one or more semiconductor dies via a die attach material.

[0068] Various semiconductor package embodiments may be configured to provide electrical isolation between a terminal ring of one or more semiconductor dies and a source pad of one or more semiconductor dies over an operating voltage range of 400V to 1700V.

[0069] The semiconductor package may also include a molding compound encapsulating one or more of the one or more semiconductor dies on four sides of the die.

[0070] The semiconductor package may further include an Ag sintering layer coupled between the one or more semiconductor dies, the heat sink, and the base frame.

[0071] In various semiconductor packages, a gate pad of one or more gate pads of a pedestal may extend beyond a perimeter of two or more semiconductor dies.

[0072] In various semiconductor packages, two or more semiconductor dies may have all four sides of each of the two or more semiconductor dies encapsulated by a molding compound.

[0073] The method may also include including the semiconductor package in an automotive high power module (AHPM) module.

[0074] Where specific embodiments of semiconductor packages and implementing components, sub-components, methods and sub-methods are mentioned in the above description, it should be apparent that various modifications may be made without departing from the essence thereof, and that these embodiments, implementing components, sub-components, methods and sub-methods may be applied to other semiconductor packages.

Claims

1. A semiconductor package, comprising: a first semiconductor die coupled between the base frame and the fixture; as well as A second semiconductor die is coupled between the base frame and the fixture, the base frame comprising: a first gate pad of the base frame, the first gate pad of the base frame being coupled to a gate pad of the first semiconductor die; and a second gate pad of the base frame, the second gate pad of the base frame being coupled to a gate pad of the second semiconductor die; a first source pad of the base frame, the first source pad of the base frame being coupled to a source pad of the first semiconductor die; and a second source pad of the base frame, the second source pad of the base frame being coupled to a source pad of the second semiconductor die; wherein the first source pad of the base frame extends beyond the periphery of the source pad of the first semiconductor die toward the gate pad of the first semiconductor die; wherein the second source pad of the base frame extends beyond the periphery of the source pad of the second semiconductor die toward the gate pad of the second semiconductor die; wherein the gate pad of the first semiconductor die extends beyond a perimeter of the first gate pad of the base frame; wherein the gate pad of the second semiconductor die extends beyond a perimeter of the second gate pad of the base frame; wherein the first gate pad of the base frame extends beyond a perimeter of the first semiconductor die; and The second gate pad of the base frame extends beyond the periphery of the second semiconductor die. 2 . The semiconductor package of claim 1 , further comprising an Ag sintering layer coupled between the first semiconductor die, the clamp, and the base frame. 3 . The semiconductor package of claim 1 , wherein the clamp comprises a drain pad, the clamp being configured to be coupled to the drain pad of the first semiconductor die. 4 . The semiconductor package of claim 1 , further comprising a redistribution layer between the gate pad of the first semiconductor die and the first gate pad of the base frame.

5. A semiconductor package, comprising: A plurality of semiconductor dies are coupled between a base frame and a heat sink, the base frame comprising: a gate pad of the base frame, the gate pad of the base frame coupled to gate pads of the plurality of semiconductor dies; and a source pad of the base frame, the source pad of the base frame being coupled to source pads of the plurality of semiconductor dies; wherein a surface of the gate pad of the base frame facing the plurality of semiconductor dies and a surface of the source pad of the base frame facing the plurality of semiconductor dies are located in the same plane; wherein the source pad of the base frame extends beyond the periphery of the source pad of the plurality of semiconductor dies toward the gate pads of the plurality of semiconductor dies; and The gate pad of the pedestal extends beyond a perimeter of a corresponding semiconductor die among the plurality of semiconductor dies. 6 . The semiconductor package of claim 5 , wherein the heat sink comprises a drain pad, the heat sink being configured to be coupled to the drain pads of the plurality of semiconductor dies. 7 . The semiconductor package of claim 5 , further comprising a redistribution layer between the gate pads of the plurality of semiconductor dies and the gate pad of the base frame.

8. A method of forming a semiconductor package, comprising: Provide a base frame; providing two or more semiconductor dies, the two or more semiconductor dies each coupled to a heat sink or a clamp, the two or more semiconductor dies coupled together by a wafer carrier; coupling an Ag sintered material to one or more gate pads and one or more source pads of the base frame; Using the Ag sintering material to pressure-sinter one or more gate pads and one or more source pads of one or more semiconductor dies; molding a molding compound over the base frame and the two or more semiconductor dies; as well as The wafer carrier is ground away to expose the heat sink or the clamp, each of which includes a drain contact. 9 . The method of claim 8 , further comprising coupling the two or more semiconductor dies to the fixture after pressure sintering.

10. The method of claim 9, further comprising coupling the clamp to the base frame.

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