Semiconductor memory device and manufacturing method thereof

Abstract

An embodiment provides a semiconductor memory device capable of improving operational reliability and a method for manufacturing the same. The semiconductor memory device of the embodiment comprises: a logic circuit disposed on a substrate; a first region disposed on the logic circuit and having a plurality of first insulating layers (33) and a plurality of conductive layers (35_0 to 35_7, 36) alternately stacked in a first direction; a plurality of memory pillars (MP) extending in a first direction in the first region; a second region disposed on the logic circuit and having a plurality of first insulating layers (33) and a plurality of second insulating layers (50) alternately stacked in the first direction; and a contact plug (CP1) extending in the first direction in the second region and connected to the logic circuit.

Description

[0001] [Related Applications]

[0002] This application claims priority from Japanese Patent Application No. 2018-175669 (filing date: September 20, 2018), which is a basic application, and the present application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor memory device and a method for manufacturing the same. Background Art

[0004] A semiconductor memory device in which memory cells are three-dimensionally arrayed is known. Summary of the Invention

[0005] Embodiments provide a semiconductor memory device capable of improving operational reliability and a method for manufacturing the same.

[0006] A semiconductor storage device of an embodiment includes: a logic circuit, which is arranged on a substrate; a first region, which is arranged on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternately stacked in a first direction; a plurality of storage pillars, which extend in the first direction in the first region; a second region, which is arranged on the logic circuit and has the plurality of first insulating layers and a plurality of second insulating layers alternately stacked in the first direction; and a contact plug, which extends in the first direction in the second region and is connected to the logic circuit.

[0007] In addition, a first separation region surrounding the second region and extending in the first direction may be further provided.

[0008] In addition, a first separation region provided between the first region and the second region and extending in the first direction may be further provided.

[0009] In addition, a second separation region may be further provided, wherein the second separation region is arranged in the first region and extends in the first direction and a second direction intersecting the first direction to separate the conductive layer, and the upper surface of the first separation region is lower than the upper surface of the second separation region.

[0010] Furthermore, the first separation region may have a plate shape extending in a second direction intersecting the first direction.

[0011] Furthermore, the first separation region may include a plurality of columnar bodies continuously arranged in a second direction intersecting the first direction, and each of the columnar bodies may extend in the first direction.

[0012] Furthermore, the first separation region may include at least one of a silicon oxide layer and an aluminum oxide layer.

[0013] Alternatively, the first separation region may include the same film as that included in the memory pillar.

[0014] Alternatively, the first insulating layer may include a silicon oxide layer, and the second insulating layer may include a silicon nitride layer.

[0015] According to the embodiment, the operational reliability of the semiconductor memory device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a block diagram showing the circuit configuration of the semiconductor memory device according to the first embodiment.

[0017] Figure 2 This is a circuit diagram of a block included in the memory cell array according to the first embodiment.

[0018] Figure 3 This is a layout diagram showing structural blocks in the semiconductor memory device according to the first embodiment.

[0019] Figure 4 It is a diagram showing a planar structure of the semiconductor memory device according to the first embodiment.

[0020] Figure 5 It is along Figure 4 Cross-sectional view of line A-A'.

[0021] Figure 6 It is along Figure 4 Cross-sectional view of line BB'.

[0022] Figure 7 It is a cross-sectional view of a memory cell transistor in the cell array region in the first embodiment.

[0023] Figure 8 4 and 5. These are cross-sectional views showing the structure of the semiconductor memory device according to the first embodiment in each manufacturing step.

[0024] Figure 9 4 and 5. These are cross-sectional views showing the structure of the semiconductor memory device according to the first embodiment in each manufacturing step.

[0025] Figure 10 4 and 5. These are cross-sectional views showing the structure of the semiconductor memory device according to the first embodiment in each manufacturing step.

[0026] Figure 11 4 and 5. These are cross-sectional views showing the structure of the semiconductor memory device according to the first embodiment in each manufacturing step.

[0027] Figure 12 4 and 5. These are cross-sectional views showing the structure of the semiconductor memory device according to the first embodiment in each manufacturing step.

[0028] Figure 13 4 and 5. These are cross-sectional views showing the structure of the semiconductor memory device according to the first embodiment in each manufacturing step.

[0029] Figure 14 It is a diagram showing a planar structure of a first modified example of the first embodiment.

[0030] Figure 15 It is a diagram showing a planar structure of a second modified example of the first embodiment.

[0031] Figure 16 It is a diagram showing a planar structure of a semiconductor memory device according to a second embodiment.

[0032] Figure 17 This is a cross-sectional view taken along line AA′ in the semiconductor memory device according to the second embodiment.

[0033] Figure 18 It is a cross-sectional view showing the structure of the semiconductor memory device in each manufacturing step according to the second embodiment.

[0034] Figure 19 It is a cross-sectional view showing the structure of the semiconductor memory device in each manufacturing step according to the second embodiment.

[0035] Figure 20 It is a diagram showing a planar structure of a first modified example of the second embodiment.

[0036] Figure 21 It is a diagram showing a planar structure of a second modified example of the second embodiment.

[0037] Figure 22 It is a diagram showing a planar structure of a third modified example of the second embodiment.

[0038] Figure 23 It is a diagram showing a planar structure of a semiconductor memory device according to a third embodiment.

[0039] Figure 24 This is a cross-sectional view taken along line AA′ in the semiconductor memory device according to the third embodiment.

[0040] Figure 25 It is a cross-sectional view showing the structure of the semiconductor memory device in the manufacturing steps according to the third embodiment.

[0041] Figure 26 A diagram showing a cross-sectional structure of a semiconductor memory device according to a fourth embodiment.

[0042] Figure 27 It is a cross-sectional view of the structure of the semiconductor memory device in the manufacturing steps according to the fourth embodiment.

[0043] Figure 28 It is a cross-sectional view of the structure of the semiconductor memory device in the manufacturing steps according to the fourth embodiment.

[0044] Figure 29 It is a cross-sectional view of the structure of the semiconductor memory device in the manufacturing steps according to the fourth embodiment.

[0045] Figure 30 It is a cross-sectional view of the structure of the semiconductor memory device in the manufacturing steps according to the fourth embodiment.

[0046] Figure 31 It is a cross-sectional view of the structure of the semiconductor memory device in the manufacturing steps according to the fourth embodiment.

[0047] Figure 32 It is a cross-sectional view of the structure of the semiconductor memory device in the manufacturing steps according to the fourth embodiment.

[0048] Figure 33 (a) to (c) are diagrams showing the planar structure of the semiconductor memory device according to the fifth embodiment.

[0049] Figure 34 It is a diagram showing a cross-sectional structure of a semiconductor memory device according to a fifth embodiment.

[0050] Figure 35 It is a diagram showing the structure of the semiconductor memory device in each manufacturing step according to the fifth embodiment.

[0051] Figure 36 It is a diagram showing the structure of the semiconductor memory device in each manufacturing step according to the fifth embodiment.

[0052] Figure 37 (a) to (c) are diagrams showing the structure of the semiconductor memory device according to the fifth embodiment in each manufacturing step.

[0053] Figure 38 It is a diagram showing the structure of the semiconductor memory device in each manufacturing step according to the fifth embodiment.

[0054] Figure 39 (a) to (c) are diagrams showing the structure of the semiconductor memory device according to the fifth embodiment in each manufacturing step.

[0055] Figure 40 A diagram showing the structure of a semiconductor memory device according to a fifth embodiment in each manufacturing step.

[0056] Figure 41 (a) to (c) are diagrams showing the structure of the semiconductor memory device according to the fifth embodiment in each manufacturing step.

[0057] Figure 42It is a diagram showing the structure of the semiconductor memory device in each manufacturing step according to the fifth embodiment.

[0058] Figure 43 (a) to (c) are diagrams showing the structure of the semiconductor memory device according to the fifth embodiment in each manufacturing step.

[0059] Figure 44 It is a diagram showing the structure of the semiconductor memory device in each manufacturing step according to the fifth embodiment.

[0060] Figure 45 (a) to (c) are diagrams showing the structure of the semiconductor memory device according to the fifth embodiment in each manufacturing step.

[0061] Figure 46 It is a diagram showing the structure of the semiconductor memory device in each manufacturing step according to the fifth embodiment. DETAILED DESCRIPTION

[0062] The following describes the embodiments with reference to the accompanying drawings. In the following description, components having the same function and configuration are denoted by common reference numerals. Furthermore, each embodiment described below is intended to illustrate an embodiment of a device or method for embodying the technical concept of that embodiment, and does not specify the material, shape, structure, or arrangement of the components as described below.

[0063] Each functional block can be implemented as either hardware, computer software, or a combination of both. The functional blocks do not necessarily need to be distinguished as shown in the following examples. For example, a portion of the functions may be performed by a functional block different from the illustrated functional block. Furthermore, the illustrated functional block may be divided into smaller functional sub-blocks. Here, a three-dimensional stacked NAND (Not And) flash memory in which memory cell transistors are stacked on a semiconductor substrate is used as an example for explanation.

[0064] 1. First Implementation

[0065] Hereinafter, a semiconductor memory device according to the first embodiment will be described.

[0066] 1.1 Circuit Block Structure of a Semiconductor Memory Device

[0067] First, the circuit block configuration of the semiconductor memory device according to the first embodiment will be described. Figure 1This is a block diagram showing the circuit configuration of a semiconductor memory device according to the first embodiment. A NAND flash memory 10, serving as a semiconductor memory device, includes a memory cell array 11, a row decoder 12, a driver 13, a sense amplifier 14, an address register 15, a command register 16, and a sequencer 17. Furthermore, a controller 20 is externally connected to the NAND flash memory 10 via, for example, a NAND bus. The controller 20 accesses and controls the NAND flash memory 10.

[0068] 1.1.1 Composition of each block

[0069] The memory cell array 11 includes a plurality of blocks BLK0, BLK1, BLK2, ..., BLKn (n is an integer greater than or equal to 0), each containing a plurality of nonvolatile memory cells corresponding to rows and columns. Hereinafter, when referred to as a block BLK, each block BLK0-BLKn is represented. The memory cell array 11 stores data provided by the controller 20. Details of the memory cell array 11 and the blocks BLK are described below.

[0070] The row decoder 12 selects any block BLK and further selects a word line in the selected block BLK. The row decoder 12 will be described in detail below.

[0071] The driver 13 supplies a voltage to the selected block BLK via the row decoder 12 .

[0072] During data read, the sense amplifier 14 senses the data DAT read from the memory cell array 11, performs necessary calculations, and then outputs the data DAT to the controller 20. During data write, the sense amplifier 14 transmits the write data DAT received from the controller 20 to the memory cell array 11.

[0073] The address register 15 stores an address ADD received from the controller 20. The address ADD includes a block address specifying a block BLK to be operated on and a page address indicating a word line to be operated on within the specified block. The command register 16 stores a command CMD received from the controller 20. The command CMD includes, for example, a write command to instruct the sequencer 17 to perform a write operation and a read command to instruct the sequencer 17 to perform a read operation.

[0074] The sequencer 17 controls the operation of the NAND flash memory 10 based on the command CMD stored in the command register 16. Specifically, the sequencer 17 controls the row decoder 12, driver 13, and sense amplifier 14 based on the write command stored in the command register 16 to write to the plurality of memory cell transistors specified by the address ADD. The sequencer 17 also controls the row decoder 12, driver 13, and sense amplifier 14 based on the read command stored in the command register 16 to read from the plurality of memory cell transistors specified by the address ADD.

[0075] As described above, the NAND flash memory 10 is connected to the controller 20 via a NAND bus. The NAND bus transmits and receives signals according to the NAND interface. Specifically, the NAND bus includes, for example, a bus that communicates the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, the input / output signal I / O, and the ready / busy signal R / Bn. The input / output signal I / O is transmitted with an 8-bit bus width. The input / output signal I / O communicates commands CMD, addresses ADD, and data DAT.

[0076] 1.1.2 Circuit Configuration of Memory Cell Array 11

[0077] As described above, the memory cell array 11 includes blocks BLK0 to BLKn. Each block BLK0 to BLKn has the same structure. The circuit structure of one block BLK will be described below.

[0078] Figure 2 This is a circuit diagram of a block BLK included in the memory cell array 11. As shown in the figure, the block BLK includes, for example, four string units SU0 to SU3. Hereinafter, when referred to as a string unit SU, each string unit SU0 to SU3 is represented. The string unit SU includes multiple NAND strings NS.

[0079] Each NAND string NS includes, for example, eight memory cell transistors MT0 to MT7 and select transistors S1 and S2. Hereinafter, when referred to as a memory cell transistor MT, each memory cell transistor MT0 to MT7 is represented. The memory cell transistor (hereinafter also referred to as a memory cell) MT includes a control gate and a charge storage layer, and stores data in a nonvolatile manner. The memory cell transistor MT is connected in series between the source of the select transistor S1 and the drain of the select transistor S2.

[0080] The gates of the select transistors S1 in each of the string units SU0-SU3 are connected to select gate lines SGD0-SGD3, respectively. In contrast, the gates of the select transistors S2 in each of the string units SU0-SU3 are connected to, for example, a single select gate line SGS. The gates of the select transistors S2 can also be connected to select gate lines SGS0-SGS3 that differ for each string unit. Furthermore, the control gates of the memory cell transistors MT0-MT7 in the string units SU0-SU3 within the block BLK are connected to word lines WL0-WL7, respectively.

[0081] In addition, the memory cell array 11 shares bit lines BL0 to BL(L-1) between multiple blocks BLK0 to BLKn. Here, L is a natural number greater than or equal to 2. In the multiple string components SU0 to SU3 within the block BLK, each bit line BL is commonly connected to the drain of the selection transistor S1 of the NAND string NS in the same row. That is, each bit line BL connects the NAND string NS in common between the multiple string components SU0 to SU3 in the same row. Furthermore, the sources of the multiple selection transistors S2 are commonly connected to the source line SL. In other words, the string component SU includes multiple NAND strings NS connected to different bit lines BL and connected to the same selection gate line SGD.

[0082] In addition, the block BLK includes a plurality of string elements SU that share the word lines WL.

[0083] The multiple memory cell transistors MT connected to a common word line WL within a string unit SU are referred to as a unit unit CU. The storage capacity of the unit unit CU varies depending on the number of bits of data stored by the memory cell transistors MT. For example, if each memory cell transistor MT stores 1 bit of data, the unit unit CU stores one page of data; if it stores 2 bits of data, the unit unit CU stores two pages of data; and if it stores 3 bits of data, the unit unit CU stores three pages of data.

[0084] Furthermore, the configuration of the memory cell array 11 is not limited to the configuration described above. For example, the number of string components SU included in each block BLK can be set to any number. The number of memory cell transistors MT and select gate transistors S1 and S2 included in each NAND string NS can also be set to any number.

[0085] The structure of the memory cell array 11 is described, for example, in U.S. Patent Application No. 12 / 407,403, filed on March 19, 2009, entitled "Three-Dimensional Stacked Nonvolatile Semiconductor Memory." Furthermore, the structure is described in U.S. Patent Application No. 12 / 406,524, filed on March 18, 2009, entitled "Three-Dimensional Stacked Nonvolatile Semiconductor Memory," U.S. Patent Application No. 12 / 679,991, filed on March 25, 2010, entitled "Non-Volatile Semiconductor Storage Device and Method of Manufactured the Same," and U.S. Patent Application No. 12 / 532,030, filed on March 23, 2009, entitled "Semiconductor Memory and Method for Manufactured the Same." The entirety of these patent applications is incorporated by reference into this specification.

[0086] 1.2 Overall Structure of a Semiconductor Memory Device

[0087] Second, use Figure 3 , the structure of the semiconductor storage device according to the first embodiment is described. Figure 3 FIG. 1 is a layout diagram showing a structural block in a semiconductor memory device according to the first embodiment. Figure 3 In the following figures, two directions that are orthogonal (or intersecting) to each other and parallel to the semiconductor substrate surface are defined as the X direction (A-A' line direction) and the Y direction (BB' line direction), and a direction that is orthogonal (or intersecting) to these X and Y directions (XY plane) is defined as the Z direction.

[0088] like Figure 3 As shown, the semiconductor memory device includes a cell array region CA, a bit line hookup region BHU, a word line hookup region WHU, a contact region CRI, and a contact region CRE.

[0089] A plurality of cell array regions CA and bit line relay regions BHU are arranged in rows and columns in the X and Y directions. The bit line relay regions BHU are arranged between the cell array regions CA in the Y direction. The word line relay regions WHU are arranged at the ends of the cell array region CA in the X direction. The contact regions CRE are arranged on the side of the word line relay region WHU opposite to the side where the cell array region CA is arranged in the X direction. Furthermore, the contact regions CRI are arranged between the cell array regions CA and between the bit line relay regions BHU in the X direction.

[0090] In the bit line relay region BHU and the cell array region CA, a plurality of bit lines BL extending in the Y direction are arranged in the X direction. Furthermore, in the word line relay region WHU, a plurality of word lines WL extending in the X direction are arranged in the Y direction.

[0091] 1.2.1 Planar Structure of Semiconductor Memory Devices

[0092] Second, use Figure 4 , the planar structure of the semiconductor storage device according to the first embodiment is described. Figure 4 It is a plan view schematically showing the planar structure of the semiconductor memory device according to the first embodiment.

[0093] like Figure 4 As shown, a bit line relay region BHU is provided between the cell array region CA in the Y direction. A slit (or separation region) ST1 is provided between the cell array region CA and the bit line relay region BHU. The slit ST1 has a plate shape extending in the X and Z directions. The slit ST1 separates the cell array region CA from the bit line relay region BHU.

[0094] In each cell array region CA, a plurality of memory pillars MP and slits SLT are provided. The memory pillars MP are arranged in a staggered pattern. The slits SLT have a plate shape extending in the X and Z directions. The slits SLT separate the memory pillars MP in the cell array region CA in the X direction.

[0095] A plurality of contact plugs CC are provided in the word line relay region WHU at the Y-direction end of the cell array region CA. Wiring layers electrically connected to the contact plugs CC are provided on the contact plugs CC. These wiring layers function as word lines WL.

[0096] In the bit line relay region BHU, a plurality of contact plugs CP1 are arranged in a staggered pattern. The bit lines BL in the bit line relay region BHU and in the cell array region CA are electrically connected to the memory pillars MP and the contact plugs CP1, respectively.

[0097] In the contact region CRE, a plurality of contact plugs CP2 are arranged in a staggered pattern. The contact plugs CP2 are electrically connected to an upper wiring layer (not shown). Furthermore, in the contact region CRI, a plurality of contact plugs (not shown) are arranged in a staggered pattern.

[0098] 1.2.2 Cross-sectional Structure of a Semiconductor Memory Device

[0099] Second, use Figure 5 and Figure 6 , a cross-sectional structure of the semiconductor memory device according to the first embodiment is described. Figure 5 It is along Figure 4 Cross-sectional view of line A-A'. Figure 6 It is along Figure 4 The cross-sectional view of the line BB' in FIG. In addition, the number of the memory pillars MP and the contact plugs CP1 and CP2 is arbitrary. Figure 4 The same applies to the following embodiments as well, in the case where the numbers of the memory pillars MP and the contact plugs CP1 and CP2 in the cross-sectional view do not match.

[0100] First, a cross-sectional structure of the semiconductor memory device taken along line AA′ will be described.

[0101] like Figure 5 As shown, a peripheral circuit layer PE is provided on a semiconductor substrate (e.g., a silicon single crystal substrate) 30. Peripheral circuits (or logic circuits), such as the row decoder 12, driver 13, sense amplifier 14, address register 15, instruction register 16, and sequencer 17, are provided in the peripheral circuit layer PE. Specifically, element isolation regions 30A are formed on the semiconductor substrate 30, and a CMOS (Complementary Metal Oxide Semiconductor) circuit including an n-channel MOS (Metal Oxide Semiconductor) field-effect transistor (hereinafter, nMOS transistor) NT and a p-channel MOS field-effect transistor (hereinafter, pMOS transistor) PT is formed between the element isolation regions 30A.

[0102] To describe in more detail, a source region and a drain region (not shown) are formed between the element isolation region 30A, and a gate electrode GE is formed on the semiconductor substrate 30 between the source region and the drain region via a gate insulating film. A through hole C1 is formed on the source region and the drain region, respectively. A wiring layer D0 is formed on the through hole C1, and a wiring layer (or electrode pad) D1 is formed on the wiring layer D0 via a through hole C2. A contact plug CP1 described below is provided on the wiring layer D1. Furthermore, an insulating layer 31 is provided around the nMOS transistor NT and the pMOS transistor PT, the wiring layers D0 and D1, and the through holes C1 and C2. The wiring layers D0 and D1 and the through holes C1 and C2 contain, for example, tungsten (W). The insulating layer 31 contains, for example, a silicon oxide layer.

[0103] Conductive layer 32 is provided on insulating layer 31. Conductive layer 32 includes conductive layers 32A, 32B, and 32C arranged from the insulating layer 31 side. Conductive layer 32 functions as source line SL. Conductive layers 32A, 32B, and 32C are made of, for example, polysilicon or tungsten (W).

[0104] On the conductive layer 32, a laminate is formed by alternating layers of insulating layers 33 and conductive layers 34, 35_0, 35_1, 35_2, 35_3, 35_4, 35_5, 35_6, 35_7, and 36 in the Z direction. Conductive layers 34, 35_0 to 35_7, and 36 have a plate shape parallel to the XY plane (or the surface of the semiconductor substrate 30) and extend in the X direction. Each conductive layer 34, 35_0 to 35_7, and 36 extending in the X direction is electrically connected to a wiring layer (not shown) extending in the X direction in the word line relay region WHU via a contact plug. Conductive layer 34 functions as select gate line SGS. Conductive layers 35_0 to 35_7 function as word lines WL0 to WL7. Conductive layer 36 functions as select gate line SGD. The insulating layer 33 comprises, for example, a silicon oxide layer. Conductive layers 34 , 35_0 to 35_7 , and 36 include, for example, tungsten (W) or polysilicon.

[0105] A plurality of columnar memory pillars MP are provided in a stacked structure comprising multiple insulating layers 33 and multiple conductive layers 34, 35_0 to 35_7, and 36. Each memory pillar MP extends in the Z direction. Each memory pillar MP is arranged so as to penetrate the insulating layers 33 and the conductive layers 34, 35_0 to 35_7, and 36 in the stacking direction, extending from the top surface of the topmost insulating layer 33 to the conductive layer 32. Specifically, the memory pillars MP are connected to the source line SL from the top surface of the insulating layer 33 through the select gate line SGD, multiple word lines WL0 to WL7, the select gate line SGS, and multiple insulating layers 33. Details of the memory pillars MP will be described below.

[0106] Furthermore, a plurality of slits SLT are provided in the laminate comprising the plurality of insulating layers 33 and the plurality of conductive layers 34, 35_0 to 35_7, and 36. The slits SLT separate the laminate comprising the plurality of insulating layers 33 and the plurality of conductive layers 34, 35_0 to 35_7, and 36. The slits SLT have a plate shape extending in the X and Z directions. The slits SLT are formed of an insulating material, such as an insulating layer filled with a silicon oxide layer.

[0107] An insulating layer 37 is provided on the insulating layer 33. A through-hole V1 extending in the Z direction is provided in the insulating layer 37 on the memory column MP. An insulating layer 38 is provided on the through-hole V1 and on the insulating layer 37. A through-hole V2 extending in the Z direction is provided in the insulating layer 38 on the through-hole V1. Furthermore, a conductive layer (or wiring, upper layer wiring) 39 is provided on the through-hole V2 and on the insulating layer 38. The conductive layer 39 is electrically connected to the memory column MP via the through-holes V2 and V1, and further, in the bit line relay area BHU, is electrically connected to the contact plug CP1 via the through-holes V2 and V1. The conductive layer 39 functions as the bit line BL. The insulating layer 37 includes, for example, a silicon oxide layer. The conductive layer 39 and the through-holes V1 and V2 include, for example, tungsten (W).

[0108] In addition, if Figure 5 As shown, the bit line relay region BHU is sandwiched by a slit ST1. The slit ST1 has a plate shape extending in the X and Z directions. The slit ST1 separates the laminated body on the conductive layer 32 in the cell array region CA from the laminated body on the conductive layer 32 in the bit line relay region BHU. The upper surface of the slit ST1 is lower than the upper surface of the slit SLT. In other words, the height of the slit ST1 from the semiconductor substrate surface is lower than the height of the slit SLT from the semiconductor substrate surface. The slit ST1 is formed of an insulating material, for example, an insulating layer filled with at least one of a silicon oxide layer and an aluminum oxide layer.

[0109] In bit line relay region BHU, an insulating layer 33 is provided on a conductive layer 32, and a conductive layer 34 is provided on the insulating layer 33. A laminated structure formed by alternating multiple insulating layers 33 and multiple insulating layers 50 in the Z direction is provided on the conductive layer 34. An insulating layer 37 is provided on the topmost insulating layer 33.

[0110] Multiple columnar contact plugs CP1 are provided in the insulating layer 37, the multiple insulating layers 33, the multiple insulating layers 50, the conductive layers 34 and 32, and the insulating layer 31. Each contact plug CP1 extends in the Z direction. Each contact plug CP1 is arranged so as to penetrate the multiple insulating layers 33, the multiple insulating layers 50, the conductive layers 34 and 32, and the insulating layer 31 in the stacking direction, and reaches from the top surface of the topmost insulating layer 33 to the wiring layer D1. In other words, the contact plug CP1 extends from the top surface of the insulating layer 33 through the multiple insulating layers 33, the multiple insulating layers 50, the select gate line SGS, the source line SL, and the insulating layer 31 to the wiring layer D1 of the peripheral circuit layer PE.

[0111] Contact plug CP1 includes, for example, a conductive layer 52 disposed within the contact plug CP1 and an insulating layer 53 disposed on the outer periphery of the conductive layer 52. An insulating layer 51 is disposed between the insulating layer 53 of the contact plug CP1 and the conductive layers 32 and 34. The insulating layer 51 strengthens the insulation between the contact plug CP1 and the conductive layers 32 and 34. The conductive layer 52 includes, for example, tungsten. The insulating layers 51 and 53 include, for example, silicon oxide layers.

[0112] Second, use Figure 6 , a cross-sectional structure of the semiconductor memory device taken along line BB' will be described. Figure 6 1 is a cross-sectional view of the contact region CRE, the word line relay region WHU, and the bit line relay region BHU. In the bit line relay region BHU, as described above, each contact plug CP1 is provided so as to extend through the plurality of insulating layers 33, the plurality of insulating layers 50, the conductive layers 34 and 32, and the insulating layer 31 in the stacking direction, and to reach from the upper surface of the uppermost insulating layer 33 to the wiring layer D1.

[0113] In the word line relay region WHU, multiple insulating layers 33 and multiple insulating layers 50 are arranged in a stair-like manner in the X direction. Furthermore, in the contact region CRE, each contact plug CP2 is arranged so that the insulating layers 37, 33, 32, and 31 extend in the stacking direction, extending from the top surface of the topmost insulating layer 33 to the wiring layer D1. An insulating layer 51 is provided between the insulating layer 53 of the contact plug CP2 and the conductive layer 32. The insulating layer 51 strengthens the insulation between the contact plug CP2 and the conductive layer 32.

[0114] 1.2.3 Structure of Memory Pillar MP (Memory Cell Transistor)

[0115] Second, use Figure 7 , a cross-sectional structure of the memory cell transistor MT of the memory pillar MP provided in the cell array area CA will be described. Figure 7 1 is a cross-sectional view of a memory cell transistor in the cell array region CA in the first embodiment. Figure 7 The interlayer insulating film between the conductive layers is omitted.

[0116] like Figure 7 As shown, the cell array region CA includes conductive layers 32, 34, 35_0 to 35_7, and 36, and memory pillars MP. The conductive layer 32 is formed in a plate shape along the XY plane and functions as a source line SL as described above.

[0117] Conductive layers 34, 35_0 through 35_7, and 36 are sequentially arranged on conductive layer 32, starting from the bottom. Adjacent conductive layers in the Z direction are stacked with interlayer insulating films interposed between them. Conductive layers 34, 35_0 through 35_7, and 36 are each formed into a plate shape extending along the XY plane. As described above, conductive layer 34 functions as select gate line SGS. Conductive layers 35_0 through 35_7, starting from the bottom, function as word lines WL0 through WL7, respectively. Conductive layer 36 functions as select gate line SGD.

[0118] Multiple memory pillars MP are arranged in a staggered pattern, for example, in the X and Y directions. Each memory pillar MP functions as a NAND string NS. Each memory pillar MP is disposed so as to extend from the upper surface of conductive layer 36 to the upper surface of conductive layer 32, passing through conductive layers 34, 35_0 to 35_7, and 36.

[0119] The memory column MP, for example, includes a unit insulating film 40, a semiconductor layer 41, and a core insulating film 42, which are arranged in sequence from the conductive layer side. The unit insulating film 40 has a blocking insulating film 40A, a charge storage film (or also called a charge storage layer) 40B, and a tunnel insulating film 40C. Specifically, a blocking insulating film 40A is provided on the inner wall of the memory hole used to form the memory column MP. A charge storage film 40B is provided on the inner wall of the blocking insulating film 40A. A tunnel insulating film 40C is provided on the inner wall of the charge storage film 40B. A semiconductor layer 41 is provided on the inner wall of the tunnel insulating film 40C. Furthermore, a core insulating layer (for example, a silicon oxide layer) 42 is provided inside the semiconductor layer 41.

[0120] In the configuration of the memory column MP, the portion where the memory column MP intersects the conductive layer 34 functions as a select gate transistor S2. The portions where the memory column MP intersects the conductive layers 35_0 to 35_7 function as memory cell transistors MT0 to MT7, respectively. Each memory cell transistor MT0 to MT7 is a memory cell capable of storing data. Data is written to each memory cell transistor MT0 to MT7 through a write operation. Furthermore, the portion where the memory column MP intersects the conductive layer 36 functions as a select gate transistor S1.

[0121] The semiconductor layer 41 functions as a channel layer for the memory cell transistor MT and the select gate transistors S1 and S2. A current path for the NAND string NS is formed inside the semiconductor layer 41.

[0122] The charge storage film 40B has a function of storing, in the memory cell transistor MT, charges injected from the semiconductor layer 41. The charge storage film 40B includes, for example, a silicon nitride film.

[0123] The tunnel insulating film 40C functions as a potential barrier when charges are injected from the semiconductor layer 41 into the charge storage film 40B or when charges stored in the charge storage film 40B are diffused into the semiconductor layer 41. The tunnel insulating film 40C includes, for example, a silicon oxide film.

[0124] The blocking insulating film 40A prevents the charges stored in the charge storage film 40B from diffusing to the conductive layers (word lines WL) 35_0 to 35_7. The blocking insulating film 40A includes, for example, a silicon oxide film and a silicon nitride film.

[0125] A through-hole V1 is provided on the memory pillar MP, and a wiring layer (not shown) serving as a bit line BL is provided on the memory pillar MP.

[0126] The configuration of the memory cell array 11 including the cell array area CA is not limited to the configuration described above. Furthermore, the number of word lines WL, and select gate lines SGD and SGS, may vary depending on the number of memory cell transistors MT and select gate transistors S1 and S2, respectively. Select gate line SGS may also be composed of multiple conductive layers, and select gate line SGD may also be composed of multiple conductive layers.

[0127] 1.3 Method for Manufacturing a Semiconductor Memory Device

[0128] Second, use Figures 8 to 13 , a method for manufacturing the semiconductor memory device according to the first embodiment is described. Figures 8 to 13 is a cross-sectional view of the structure of the semiconductor memory device in each manufacturing step of the first embodiment, and is taken along Figure 4 A cross-sectional view along the line AA' (Y direction) in FIG.

[0129] First, if Figure 8As shown, a peripheral circuit layer PE, conductive layers 32A, 32D, 32C, and 34 are formed on a semiconductor substrate 30, and multiple insulating layers 33 and 50 are stacked to form memory pillars MP. Specifically, a CMOS circuit including, for example, nMOS transistors and pMOS transistors is formed on the semiconductor substrate 30, and vias C1, wiring layers D0 and C2, and wiring layers D1 are formed to connect these transistors. Furthermore, an insulating layer 31 is formed on wiring layer D1. Thus, a peripheral circuit layer PE including the row decoder 12, driver 13, sense amplifier 14, address register 15, instruction register 16, and sequencer 17 is formed on the semiconductor substrate 30.

[0130] Next, for example, using CVD (chemical vapor deposition) (or ALD (atomic layer deposition)), a conductive layer 32A, a sacrificial layer (not shown), a conductive layer 32D, a sacrificial layer (not shown), and a conductive layer 32C are sequentially formed on the insulating layer 31. Furthermore, for example, using CVD (or ALD), insulating layers 33 and 34 are sequentially formed on the conductive layer 32C. Conductive layer 32D comprises, for example, a polysilicon layer. The sacrificial layer comprises, for example, a silicon oxide layer. Furthermore, in the bit line relay region BHU, in the region where contact plug CP1 is to be formed, an insulating layer 51 is formed that extends the conductive layers 32A, 32D, 32C, and 34 in the Z direction.

[0131] Next, multiple insulating layers 33 and multiple insulating layers 50 are alternately stacked on the conductive layer 34, for example, using CVD (or ALD). This forms a laminate comprising the insulating layers 33, the conductive layer 34, and the alternate stacking of the multiple insulating layers 33 and the multiple insulating layers 50. Next, memory pillars MP extending in the Z direction are formed on the laminate and the conductive layers 32A, 32D, and 32C.

[0132] Secondly, if Figure 9 and Figure 10 As shown, a slit ST1 is formed between the cell array region CA and the bit line relay region BHU. Specifically, for example, by using CVD (or ALD), an insulating layer 37 is formed on the memory pillar MP and the insulating layer 33. Furthermore, for example, by using RIE (Reactive ion etching) method, as shown in FIG. Figure 9As shown, a slit ST1 trench 54 extending in the X and Z directions is formed in the insulating layer 37, the plurality of insulating layers 33, and the plurality of insulating layers 50 between the cell array region CA and the bit line relay region BHU. Next, an insulating material, such as at least one of a silicon oxide layer and an aluminum oxide layer, is embedded in the trench 54 using, for example, CVD (or ALD). This forms the slit ST1 between the cell array region CA and the bit line relay region BHU.

[0133] Secondly, if Figure 11 and Figure 12 As shown, the insulating layer (for example, silicon nitride layer) 50 is replaced with a conductive layer (for example, tungsten layer) 35_0 to 35_7, 36, and then a slit SLT is formed to separate the conductive layers 35_0 to 35_7, 36. In addition, the conductive layer (source line SL) 32 is connected to the storage column MP. Specifically, a stacked body formed by stacking the insulating layer 37, multiple insulating layers 33, multiple insulating layers 50, the conductive layer 34, the insulating layer 33 and the conductive layer 32 is formed by, for example, using the RIE method. The groove 55 extends from the surface of the insulating layer 37 to the conductive layer 32. Then, the conductive layer (polysilicon layer) 32D (see Figure 10 ) and the sacrificial layers above and below conductive layer 32D are removed. This creates a gap between conductive layer 32A and conductive layer 32C. Furthermore, conductive layer 32B is formed using CVD (or ALD) to fill the gap between conductive layer 32A and conductive layer 32C. This connects conductive layer 32B to memory pillar MP.

[0134] Next, in the cell array region CA, the insulating layer (silicon nitride layer) 50 is removed through the groove 55 by wet etching using, for example, a phosphoric acid solution. This wet etching process leaves the insulating layer (silicon oxide layer) 33 unremoved and untouched. This forms gaps between the insulating layers 33. Furthermore, the gaps between the insulating layers 33 are filled with a conductive material, such as tungsten, using CVD (or ALD) to form conductive layers 35_0 to 35_7 and 36. Next, the groove 55 is filled with an insulating material, such as a silicon oxide layer, using, for example, CVD (or ALD). This forms the slit SLT.

[0135] On the other hand, in the bit line relay region BHU, during the wet etching using the phosphoric acid solution, the phosphoric acid solution is blocked by the slit ST1 and does not reach the insulating layer 50 within the bit line relay region BHU. Therefore, the insulating layer 50 within the bit line relay region BHU is not removed but remains. In other words, during the step of replacing the insulating layer 50 with the conductive layers 35_0 to 35_7 and 36, the insulating layer 50 within the bit line relay region BHU is not replaced with the conductive layer. The stacked structure of the multiple insulating layers 33 and the multiple insulating layers 50 remains within the bit line relay region BHU.

[0136] Secondly, if Figure 13 As shown, a contact plug CP1 is formed in the bit line relay region BHU. Specifically, an insulating layer 37 is formed on the slit SLT and further on the insulating layer 37, for example, using CVD (or ALD). Next, a hole for the contact plug CP1 is formed in the stacked structure formed by the insulating layer 37, the plurality of insulating layers 33, the plurality of insulating layers 50, and the insulating layer 51 in the bit line relay region BHU, for example, using RIE. Next, an insulating layer 53 is formed on the inner wall of the hole for the contact plug CP1, for example, using CVD (or ALD), and a conductive layer 52 is embedded in the insulating layer 53. Thus, the contact plug CP1 is formed in the bit line relay region BHU.

[0137] Secondly, if Figure 5 As shown, through holes V1 and V2 and a conductive layer 39 connected to the storage column MP and the contact plug CP1 are formed. Specifically, for example, by using the CVD (or ALD) method, an insulating layer 37 is further formed on the contact plug CP1 and the insulating layer 37. Then, a through hole V1 is formed on the storage column MP and the insulating layer 37 on the contact plug CP1. Furthermore, an insulating layer 38 is formed on the through hole V1 and the insulating layer 37. Then, a through hole V2 is formed in the insulating layer 38 on the through hole V1. Furthermore, a conductive layer 39 is formed on the through hole V2 and the insulating layer 38. Based on the above, the manufacture of the semiconductor storage device according to the first embodiment is completed.

[0138] 1.4 Variation 1

[0139] Second, use Figure 14 , a first variation of the first embodiment will be described. In the first variation, the differences from the first embodiment will be mainly described. The same applies to the following variations. Figure 14 FIG. 1 shows a planar structure of a semiconductor memory device according to a first modification of the first embodiment, showing a cell array region CA, a word line relay region WHU, and a bit line relay region BHU.

[0140] The bit line relay region BHU is arranged between the cell array regions CA in the Y direction. Multiple contact plugs CP1 and a slit (or isolation region) ST2 are provided in the bit line relay region BHU. The slit ST2 surrounds the multiple contact plugs CP1 and is arranged around them. The slit ST2 is formed by filling an insulating material, such as at least one of a silicon oxide layer and an aluminum oxide layer.

[0141] Outside the slit ST2, a laminate of multiple insulating layers 33 and multiple conductive layers 34, 35_0 to 35_7, and 36 is arranged. Inside the slit ST2, a laminate of multiple insulating layers 33 and multiple insulating layers 50 is arranged. In other words, the area surrounded by the slit ST2 comprises a laminate of multiple insulating layers 33 and multiple insulating layers 50. The slit ST2 extends in the Z direction, separating the laminate outside the slit ST2 from the laminate inside. Contact plug CP1 extends in the Z direction through the multiple insulating layers 33 and multiple insulating layers 50 and reaches the wiring layer D1 of the peripheral circuit layer PE.

[0142] That is, the region surrounded by slit ST2 does not have multiple insulating layers 50 replaced with conductive layers 35_0 to 35_7 and 36 as is done outside slit ST2. Instead, multiple insulating layers 50 remain in place. Contact plug CP1 is provided to penetrate multiple insulating layers 33 and multiple insulating layers 50, with one end connected to wiring layer D1 disposed between semiconductor substrate 30 and cell array area CA. The remaining structure is the same as that of the first embodiment.

[0143] 1.5 Variation 2

[0144] Second, use Figure 15 , a second variation of the first embodiment is described. Figure 15 The planar structure of a semiconductor memory device according to a second modification of the first embodiment is shown, including a cell array region CA, a word line relay region WHU, and a bit line relay region BHU.

[0145] In the bit line relay region BHU, a plurality of contact plugs CP1 and a plurality of slits (or isolation regions) ST3 are provided. Each slit ST3 is arranged around each contact plug CP1 so as to surround the contact plug CP1. The slit ST3 is formed by filling an insulating material, such as at least one of a silicon oxide layer and an aluminum oxide layer.

[0146] Outside the slit ST3, a laminate of multiple insulating layers 33 and multiple conductive layers 34, 35_0 to 35_7, and 36 is arranged. Inside the slit ST3, a laminate of multiple insulating layers 33 and multiple insulating layers 50 is arranged. In other words, the area surrounded by the slit ST3 comprises a laminate of multiple insulating layers 33 and multiple insulating layers 50. The slit ST3 extends in the Z direction, separating the laminate outside the slit ST3 from the laminate inside. Contact plug CP1 extends the multiple insulating layers 33 and multiple insulating layers 50 in the Z direction, reaching the wiring layer D1 of the peripheral circuit layer PE.

[0147] That is, the region surrounded by the slit ST3 is not replaced with the conductive layers 35_0 to 35_7 and 36 as is the case outside the slit ST3. Instead, the plurality of insulating layers 50 are directly disposed. The contact plug CP1 is provided to penetrate the plurality of insulating layers 33 and the plurality of insulating layers 50, with one end connected to the wiring layer D1 disposed between the semiconductor substrate 30 and the cell array area CA. The remaining structure is the same as that of the first embodiment.

[0148] 1.4 Effects of the First Implementation

[0149] According to the first embodiment, a semiconductor memory device capable of improving reliability of operations such as writing, reading, and erasing can be provided.

[0150] The effects of the first embodiment are described in detail below. For example, a three-dimensional multilayer nonvolatile semiconductor memory device includes a laminated body formed by stacking an insulating layer (e.g., a silicon oxide layer) and a conductive layer (e.g., a metal layer) serving as a word line, and a contact plug that penetrates the laminated body. The contact plug connects an upper wiring layer disposed above the laminated body to a lower wiring layer disposed below the laminated body, or to a wiring layer of a peripheral circuit disposed below the laminated body. In this structure, there is a possibility of degradation in the dielectric strength between the contact plug penetrating the laminated body and the conductive layer.

[0151] Therefore, in the first embodiment, the laminated structure in the region where contact plug CP1 is provided is configured as a laminated structure comprising an insulating layer (e.g., a silicon oxide layer) 33 and an insulating layer (e.g., a silicon nitride layer) 50. Thus, insulating layer 50 is disposed between contact plug CP1 and conductive layers 35_0 to 35_7 and 36. As a result, the dielectric strength between contact plug CP1, which penetrates the laminated structure, and conductive layers 35_0 to 35_7 and 36 can be improved.

[0152] For example, during the manufacturing process of a three-dimensional stacked nonvolatile semiconductor memory device, a hole is formed in the stacking direction of a stacked structure composed of a silicon oxide layer and a silicon nitride layer, and a memory functional film is formed within the hole. Subsequently, multiple trenches are formed, the silicon nitride layer is removed from the trenches, and the gaps between the silicon oxide layers are filled with metal material to form word lines WL. In this manufacturing process, the region where the contact plugs penetrating the stacked structure are formed is farther from the trenches than the memory cell array region. This can lead to problems such as poor removal of the silicon nitride layer or poor filling of the metal material, which can cause problems such as damage to the silicon oxide layer due to heat in subsequent steps.

[0153] Therefore, in the first embodiment, before removing the insulating layer (e.g., silicon nitride layer) 50 and filling the gaps between the insulating layers (e.g., silicon oxide layer) 33 with a metal material, slits ST1, ST2, and ST3 are formed, which are different from the slits SLT separating the conductive line layers 35_0 to 35_7 and 36 in the cell array area CA. The slits ST1, ST2, and ST3 are arranged to separate the stacked body in the region where the memory pillars MP are formed from the stacked body in the region where the contact plugs CP1 are formed, or to surround the region where the contact plugs CP1 are formed.

[0154] Thus, during the step of removing insulating layer 50, the etching liquid is blocked by slits ST1, ST2, or ST3, preventing it from reaching insulating layer 50 in the area where contact plug CP1 is formed. Consequently, insulating layer 50 in the area where contact plug CP1 is formed is not removed and remains. Thus, insulating layer 50 is positioned between contact plug CP1 and conductive layers 35_0 to 35_7 and 36. As a result, the dielectric strength between contact plug CP1, which penetrates the stacked structure, and conductive layers 35_0 to 35_7 and 36 can be improved.

[0155] As described above, according to the semiconductor memory device of the first embodiment, reliability of operations such as writing, reading, and erasing can be improved.

[0156] 2. Second Implementation

[0157] Next, a semiconductor memory device according to a second embodiment will be described. In the second embodiment, the cell array region CA and the bit line relay region BHU are separated using a member comprising the same film as the memory pillars MP, or using a member similar to the support pillars arranged in the word line relay region WHU and supporting the word lines WL. The circuit block configuration of the second embodiment is the same as that of the first embodiment. The second embodiment will be described primarily regarding the differences from the first embodiment.

[0158] 2.1 Structure of Semiconductor Memory Device

[0159] Next, the structure of the semiconductor memory device according to the second embodiment will be described.

[0160] 2.1.1 Planar Structure of Semiconductor Memory Devices

[0161] Second, use Figure 16 , the planar structure of the semiconductor storage device according to the second embodiment is described. Figure 16 It is a plan view of the cell array region CA and the bit line relay region BHU in the semiconductor memory device according to the second embodiment.

[0162] like Figure 16 As shown, a separation region MPL is provided between the cell array region CA and the bit line relay region BHU. The separation region MPL has a plate shape extending in the X and Z directions. The separation region MPL separates the cell array region CA from the bit line relay region BHU.

[0163] In the cell array region CA, memory pillars MP are arranged in a staggered pattern, and in the bit line relay region BHU, a plurality of contact plugs CP1 are arranged.

[0164] 2.1.2 Cross-sectional structure of a semiconductor memory device

[0165] Second, use Figure 17 , a cross-sectional structure of a semiconductor storage device according to a second embodiment is described. Figure 17 is a cross-sectional view of a semiconductor memory device according to a second embodiment, showing a direction corresponding to Figure 4 The cross section of the line A-A' in .

[0166] like Figure 17 As shown, the bit line relay region BHU is sandwiched by the isolation region MPL. The isolation region MPL has a plate shape extending in the X and Z directions. The isolation region MPL separates the laminate comprising multiple insulating layers 33 and multiple conductive layers 34, 35_0 to 35_7, and 36 in the cell array region CA from the laminate comprising multiple insulating layers 33 and multiple insulating layers 50 in the bit line relay region BHU. The height of the upper surface of the isolation region MPL is the same as the height of the upper surface of the storage pillar MP. In other words, the height of the isolation region MPL from the semiconductor substrate surface is the same as the height of the storage pillar MP from the semiconductor substrate surface. The isolation region MPL is formed in the same step as the storage pillar MP and has a film made of the same material.

[0167] In the bit line relay region BHU, an insulating layer 33 is provided on a conductive layer 32, and a conductive layer 34 is provided on the insulating layer 33. A laminate formed by alternating multiple insulating layers 33 and multiple insulating layers 50 in the Z direction is provided on the conductive layer 34. An insulating layer 37 is provided on the topmost insulating layer 33. Multiple contact plugs CP1 are provided on the insulating layer 37, the multiple insulating layers 33, the multiple insulating layers 50, the conductive layers 34 and 32, and the insulating layer 31. The remaining structure is the same as that of the first embodiment.

[0168] 2.2 Method for Manufacturing a Semiconductor Memory Device

[0169] Next, a method for manufacturing the semiconductor memory device according to the second embodiment will be described. Figure 18 and Figure 19 is a cross-sectional view of the structure of the semiconductor memory device in each manufacturing step of the second embodiment, showing the structure of the semiconductor memory device along the Figure 4 The cross section along the line AA' (Y direction) in FIG.

[0170] like Figure 18 As shown, along with the formation of the memory pillars MP, a separation region MPL is formed between the cell array region CA and the bit line relay region BHU. Specifically, for example, using CVD (or ALD), an insulating layer 33, a conductive layer 34, and a laminate formed by alternating multiple insulating layers 33 and multiple insulating layers 50 are formed on the conductive layer 32C. Next, along with forming the memory pillars MP extending in the Z direction on the laminate and the conductive layers 32A, 32D, and 32C, a separation region MPL extending in the Z direction is also formed. In other words, the separation region MPL is formed in the same step as the memory pillars MP. Therefore, the separation region MPL has a film made of the same material as the memory pillars MP.

[0171] Next, the insulating layer (e.g., silicon nitride layer) 50 is replaced with conductive layers (e.g., tungsten layers) 35_0 to 35_7 and 36, and slits SLT are formed to separate the conductive layers 35_0 to 35_7 and 36. Furthermore, the conductive layer (source line SL) 32 is connected to the memory pillar MP. Specifically, a trench 55 for the slit SLT is formed in a laminate formed by laminating the insulating layer 37, multiple insulating layers 33, multiple insulating layers 50, the conductive layer 34, the insulating layer 33, and the conductive layer 32, for example, using RIE. Then, similar to the first embodiment, the conductive layer 32B is connected to the memory pillar MP. Furthermore, in the cell array area CA, the insulating layer 50 is removed by wet etching using a phosphoric acid solution and replaced with the conductive layers 35_0 to 35_7 and 36. Next, an insulating material is embedded in the trench 55 to form the slit SLT.

[0172] Meanwhile, in the step of removing the insulating layer (silicon nitride layer) 50 in the bit line relay region BHU using wet etching using a phosphoric acid solution, the phosphoric acid solution is blocked by the isolation region MPL and does not reach the insulating layer 50 within the bit line relay region BHU. Therefore, the insulating layer 50 within the bit line relay region BHU is not removed and remains as is. In other words, the insulating layer 50 within the bit line relay region BHU is not replaced with a conductive layer, and the stack of multiple insulating layers 33 and multiple insulating layers 50 remains within the bit line relay region BHU. Subsequent steps are identical to those of the manufacturing method of the first embodiment.

[0173] 2.3 Variation 1

[0174] Second, use Figure 20 , a first variation of the second embodiment is described. Figure 20 This is a plan view of the cell array region CA and the bit line relay region BHU in the semiconductor memory device of the first modification. In the first modification, the differences from the second embodiment are mainly described. The same applies to the following modifications.

[0175] like Figure 20 As shown, a separation region MPS is provided between the cell array area CA and the bit line relay area BHU. The separation region MPS is composed of a plurality of memory pillars MP arranged continuously in the X direction. Specifically, a plurality of memory pillars MP extending in the Z direction are arranged in a bead-like pattern in the X direction to form the separation region MPS. The separation region MPS is formed in the same process as the memory pillars MP and comprises a film of the same material.

[0176] The isolation region MPS separates the stack of insulating layers 33 and conductive layers 34, 35_0 to 35_7, and 36 in the cell array region CA from the stack of insulating layers 33 and insulating layers 50 in the bit line relay region BHU. The top surface of the isolation region MPS is at the same height as the top surface of the memory pillars MP arranged in the cell array region CA. In other words, the height of the isolation region MPS from the semiconductor substrate surface is the same as the height of the memory pillars MP from the semiconductor substrate surface. The remaining structure is the same as that of the second embodiment.

[0177] 2.4 Variation 2

[0178] Second, use Figure 21 , a second variation of the second embodiment is described. Figure 21 1 is a plan view of the cell array region CA and the bit line relay region BHU in the semiconductor memory device according to the second modification.

[0179] like Figure 21As shown, a isolation region HRL is provided between the cell array region CA and the bit line relay region BHU. The isolation region HRL has a plate shape extending in the X and Z directions. The isolation region HRL is formed in the same process as the support pillars provided in the word line relay region WHU and comprises layers of the same material. The support pillars are provided in the word line relay region WHU to prevent the accumulated insulating layer 33 from collapsing. The isolation region HRL and the support pillars are formed, for example, from a silicon oxide layer.

[0180] The isolation region HRL separates the stacked structure comprising the plurality of insulating layers 33 and the plurality of conductive layers 34, 35_0 to 35_7, and 36 in the cell array region CA from the stacked structure comprising the plurality of insulating layers 33 and the plurality of insulating layers 50 in the bit line relay region BHU. The top surface of the isolation region HRL is at the same height as the top surface of the support pillars arranged in the word line relay region WHU. The remaining structure is the same as that of the second embodiment.

[0181] 2.5 Variation 3

[0182] Second, use Figure 22 , a third variation of the second embodiment is described. Figure 22 1 is a plan view of a cell array region CA and a bit line relay region BHU in a semiconductor memory device according to a third modification.

[0183] like Figure 23 As shown, a separation region HRS is provided between the cell array region CA and the bit line relay region BHU. The separation region HRS is composed of a plurality of pillars (hereinafter referred to as insulating pillars) continuously arranged in the X direction and made of an insulating material. Specifically, the separation region HRS is formed by a plurality of insulating pillars extending in the Z direction and arranged in a bead-like pattern in the X direction. The insulating pillars have a columnar shape extending in the Z direction. The separation region HRS is formed in the same process as the support pillars arranged in the word line relay region WHU and comprises layers of the same material. For example, the separation region HRS, including the insulating pillars, comprises a silicon oxide layer.

[0184] The isolation region HRS separates the stacked structure comprising the plurality of insulating layers 33 and the plurality of conductive layers 34, 35_0 to 35_7, and 36 in the cell array region CA from the stacked structure comprising the plurality of insulating layers 33 and the plurality of insulating layers 50 in the bit line relay region BHU. The top surface of the isolation region HRS is at the same height as the top surface of the support pillars disposed in the bit line relay region BHU. The remaining structures are the same as those of the second embodiment and the third variation.

[0185] 2.6 Effects of the Second Implementation

[0186] In the second embodiment, a separation region MPL, or MPS, HRL, or HRS is disposed between the laminated structure of the cell array region CA, where memory pillars MP are provided, and the laminated structure of the bit line relay region BHU, where contact plugs CP1 are provided. This separates the laminated structure of the cell array region CA from the laminated structure of the bit line relay region BHU.

[0187] By separating the laminated structure in the region where the memory pillars MP are provided from the laminated structure in the region where the contact plugs CP1 are provided, the laminated structure in the region where the contact plugs CP1 are provided can be configured as a laminated structure comprising an insulating layer (e.g., a silicon oxide layer) 33 and an insulating layer (e.g., a silicon nitride layer) 50. Consequently, the insulating layer 50 is disposed between the contact plugs CP1 and the conductive layers 35_0 to 35_7 and 36. As a result, the dielectric strength between the contact plugs CP1 penetrating the laminated structure and the conductive layers 35_0 to 35_7 and 36 can be improved, thereby enhancing the reliability of operations such as writing, reading, and erasing in the semiconductor memory device.

[0188] Furthermore, in the step of forming the storage pillars MP in the cell array region CA, a separation region MPL or MPS is formed between the cell array region CA and the bit line relay region BHU. Furthermore, in the step of forming the support pillars in the word line relay region WHU, a separation region HRL or HRS is formed between the cell array region CA and the bit line relay region BHU. Therefore, there is no need to newly provide the steps of forming the separation regions MPL or MPS, HRL, and HRS. Therefore, in the second embodiment, no new steps are added for manufacturing the semiconductor memory device, thereby suppressing an increase in manufacturing costs.

[0189] 3. Third Implementation Method

[0190] Next, a semiconductor memory device according to the third embodiment will be described. In the third embodiment, during the step of removing the plurality of insulating layers 50 and replacing them with conductive layers 35_0 to 35_7 and 36, insulating layer 50 remains near contact plug CP1 to improve the dielectric strength between the contact plug and the conductive layer. The circuit block structure of the third embodiment is the same as that of the first embodiment. The third embodiment will be described primarily regarding the differences from the first embodiment.

[0191] 3.1 Structure of Semiconductor Memory Device

[0192] Hereinafter, the structure of the semiconductor memory device according to the third embodiment will be described.

[0193] 3.1.1 Planar Structure of Semiconductor Memory Devices

[0194] Second, use Figure 23 , the planar structure of the semiconductor storage device of the third embodiment is described. Figure 23 FIG is a top view schematically showing a planar structure of a semiconductor memory device according to a third embodiment. Figure 4 In the planar structure of the first embodiment shown in FIG, no slit ST1 is provided between the cell array region CA and the bit line relay region BHU. Figure 4 The planar configuration shown is identical.

[0195] 3.1.2 Cross-sectional Structure of a Semiconductor Memory Device

[0196] Second, use Figure 24 , a cross-sectional structure of a semiconductor storage device according to a third embodiment is described. Figure 24 In the semiconductor memory device according to the third embodiment Figure 23 Cross-sectional view of line A-A'.

[0197] In the cross-sectional structure of the semiconductor memory device according to the third embodiment, Figure 5 In the cross-sectional structure of the first embodiment shown in FIG. Figure 24 As shown, the slit ST1 is not provided between the cell array region CA and the bit line relay region BHU.

[0198] Furthermore, the conductive layer extending from the cell array region extends beyond the boundary between the cell array region CA and the bit line relay region BHU and ends at the bit line relay region BHU. In other words, an insulating layer 50 is disposed between the contact plug CP1 and the conductive layers 35_0 to 35_7 and 36. The length of the insulating layer 50 in the Y direction is sufficient to improve the dielectric strength between the contact plug CP1 and the conductive layers 35_0 to 35_7 and 36. The remaining structure is the same as that of the first embodiment.

[0199] 3.2 Method for Manufacturing a Semiconductor Memory Device

[0200] Next, a method for manufacturing the semiconductor memory device according to the third embodiment will be described. Figure 25 is a cross-sectional view of the structure of the semiconductor memory device in the manufacturing step of the third embodiment, showing the structure of the semiconductor memory device along the Figure 23 The cross section along the line AA' (Y direction) in FIG.

[0201] After forming the memory pillars MP in the laminate and the conductive layers 32A, 32D, and 32C, the insulating layer (e.g., silicon nitride layer) 50 is replaced with the conductive layers (e.g., tungsten layers) 35_0 to 35_7 and 36. Specifically, the laminate formed by laminating the insulating layer 37, the plurality of insulating layers 33, the plurality of insulating layers 50, the conductive layer 34, the insulating layer 33, and the conductive layer 32 is formed, for example, Figure 25As shown in FIG5 , a groove 55 for the slit SLT is formed by RIE. Next, similarly to the first embodiment, the conductive layer 32B is connected to the memory pillar MP.

[0202] Then, the insulating layer 50 is removed using wet etching with a phosphoric acid solution and replaced with the conductive layers 35_0 to 35_7 and 36. During the step of removing the insulating layer 50, the wet etching conditions are used to control the length (or position) of the insulating layer 50 removed. Specifically, the step of removing the insulating layer 50 is controlled so that the insulating layer 50 within the cell array area CA is removed, leaving the insulating layer 50 within a specific distance from the contact plug CP1. The subsequent steps are the same as those of the manufacturing method of the first embodiment.

[0203] 3.3 Effects of the Third Implementation

[0204] In the third embodiment, in the step of removing the plurality of insulating layers 50 and replacing them with the conductive layers 35_0 to 35_7 and 36, the insulating layer 50 surrounding the contact plug CP1 is not removed but remains, and the insulating layer 50 surrounding the contact plug CP1 is not replaced with the conductive layers 35_0 to 35_7 and 36. Thus, the insulating layer 50 is disposed between the contact plug CP1 and the conductive layers 35_0 to 35_7 and 36. As a result, the dielectric strength between the contact plug CP1 and the conductive layers 35_0 to 35_7 and 36 can be improved, thereby improving the reliability of operations such as writing, reading, and erasing in the semiconductor memory device.

[0205] 4. Fourth Implementation Method

[0206] Next, a semiconductor memory device according to a fourth embodiment will be described. In the fourth embodiment, a layer made of the same material as that in the region where contact plug CP2 is formed is preformed in the region where contact plug CP1 is formed, and contact plugs CP1 and CP2 are formed simultaneously. The circuit block structure of the fourth embodiment is the same as that of the first embodiment. The fourth embodiment will be described primarily regarding differences from the first embodiment.

[0207] 4.1 Structure of Semiconductor Memory Device

[0208] The following describes the structure of the semiconductor memory device according to the fourth embodiment. Figure 4 The same as the first embodiment shown.

[0209] 4.1.1 Cross-sectional Structure of a Semiconductor Memory Device

[0210] Second, use Figure 26 , a cross-sectional structure of a semiconductor storage device according to a fourth embodiment is described. Figure 26yes Figure 4 A cross-sectional view of the cell array region CA, the bit line relay region BHU, and the contact region CRE along the Y direction. Figure 26 , the through holes V1, V2 and the conductive layer 39 are omitted.

[0211] like Figure 26 As shown, the cross-sectional structure of the cell array region CA is similar to Figure 5 The same as the first embodiment shown.

[0212] In the bit line relay region BHU, the structure of the contact plug CP1 is different from that of the first embodiment, but the other structures are the same. Figure 26 The illustrated contact plug CP1 extends in the Z direction, reaching the wiring layer D1 from the upper surface of the insulating layer 38. Specifically, the contact plug CP1 is provided so as to penetrate the insulating layers 38 and 37, the plurality of insulating layers 33, the plurality of insulating layers 50, the conductive layers 34 and 32, and the insulating layer 31 in the stacking direction, and is connected to the wiring layer D1.

[0213] Contact plug CP1 includes a plug portion CP1a located below conductive layer 36 (or on the substrate side) and a plug portion CP1b located above conductive layer 36 (or on the bit line side). The center positions of plug portion CP1a and plug portion CP1b in a direction perpendicular to the Z direction (on the XY plane) are not aligned. In other words, the center axis of plug portion CP1b is offset relative to the center axis of plug portion CP1a in a direction perpendicular to the Z direction. The boundary between plug portion CP1a and plug portion CP1b is not limited to that described above and can be varied in the Z direction.

[0214] In the contact region CRE, a peripheral circuit layer PE is provided on the semiconductor substrate 30 , and an insulating layer 37 is provided on the peripheral circuit layer PE. Furthermore, an insulating layer 38 is provided on the insulating layer 37 .

[0215] Contact plug CP2 extends in the Z direction, extending from the upper surface of insulating layer 38 to wiring layer D1. Specifically, contact plug CP1 is provided so as to penetrate insulating layers 38 and 37, multiple insulating layers 33, multiple insulating layers 50, conductive layers 34 and 32, and insulating layer 31 in the buildup direction, and is connected to wiring layer D1. Furthermore, contact plug CP2 is not divided into a plug portion CP1a and a plug portion CP1b, as is contact plug CP1.

[0216] 4.2 Method for Manufacturing a Semiconductor Memory Device

[0217] Next, a method for manufacturing the semiconductor memory device according to the fourth embodiment will be described. Figures 27 to 32 is a cross-sectional view of the structure of the semiconductor memory device in the manufacturing step of the fourth embodiment, showing Figure 4 FIG. 4 is a cross section of the cell array region CA, the bit line relay region BHU, and the contact region CRE along the Y direction.

[0218] First, after forming the storage pillar MP, as shown in FIG. Figure 27 and Figure 28 As shown, together with the slit ST1, an insulating layer 62 having the same shape as the contact plug CP1 (for example, a columnar body) is formed in the formation region of the contact plug CP1. Specifically, for example, by using the RIE method, as shown in FIG. Figure 27 As shown, a groove 54 for the slit ST1 extending in the X and Z directions is formed in the insulating layer 37, the plurality of insulating layers 33, and the plurality of insulating layers 50 between the cell array region CA and the bit line relay region BHU. Simultaneously with the formation of the groove 54 for the slit ST1, a hole 54A is formed in the region where the contact plug CP1 is to be formed.

[0219] Then, if Figure 28 As shown, an insulating material, such as a silicon oxide layer, is buried in the groove 54 and the hole 54A using, for example, CVD (or ALD). Thus, a slit ST1 is formed between the cell array region CA and the bit line relay region BHU, and an insulating layer 62 is formed in the hole 54A.

[0220] Secondly, if Figure 29 and Figure 30 As shown, the insulating layer (e.g., silicon nitride layer) 50 is replaced with conductive layers (e.g., tungsten layers) 35_0 to 35_7 and 36, and a slit SLT is formed separating the conductive layers 35_0 to 35_7 and 36. Furthermore, the conductive layer (source line SL) 32 is connected to the memory pillar MP. Specifically, a trench 55 for the slit SLT is formed in a laminate formed by laminating the insulating layer 37, multiple insulating layers 33, multiple insulating layers 50, the conductive layer 34, the insulating layer 33, and the conductive layer 32, for example, using RIE. Then, similar to the first embodiment, the conductive layer 32B is connected to the memory pillar MP. Furthermore, in the cell array area CA, the insulating layer 50 is removed by wet etching using a phosphoric acid solution and replaced with the conductive layers 35_0 to 35_7 and 36. Next, an insulating material, such as a silicon oxide layer, is buried in the trench 55 to form the slit SLT.

[0221] On the other hand, in the step of removing the insulating layer (silicon nitride layer) 50 in the bit line relay region BHU by wet etching using a phosphoric acid solution, the phosphoric acid solution is blocked by the slit ST1, and the insulating layer 50 in the bit line relay region BHU is not removed but remains. In other words, the stacked structure of the plurality of insulating layers 33 and the plurality of insulating layers 50 remains within the bit line relay region BHU.

[0222] Secondly, if Figure 31 and Figure 32 As shown in FIG, holes for contact plug CP1 and contact plug CP2 are formed. Specifically, as shown in FIG. Figure 31 As shown, a resist layer 63 having openings 63A and 63B is formed. Opening 63A is used to form a hole 64A for contact plug CP1 and is located above the region where contact plug CP1 is to be formed. Opening 63B is used to form a hole 64B for contact plug CP2 and is located above the region where contact plug CP2 is to be formed.

[0223] Then, for example, using the RIE method, Figure 32 As shown, in the bit line relay region BHU, a hole 64A for contact plug CP1 extending in the Z direction is formed in the insulating layers 38 and 37, the plurality of insulating layers 33, the plurality of insulating layers 50, and the insulating layer 51. Simultaneously with the formation of this hole 64A, a hole 64B for contact plug CP2 extending in the Z direction is formed in the insulating layers 38 and 37 in the contact region CRE.

[0224] Secondly, if Figure 26 As shown, insulating layer 53 and conductive layer 52 are formed in hole 64A for contact plug CP1 and hole 64B for contact plug CP2, and contact plug CP1 and contact plug CP2 are formed by simultaneous processing. Specifically, for example, using CVD (or ALD), insulating layer 53 is formed on the inner walls of holes 64A and 64B for contact plugs CP1 and CP2, and conductive layer 52 is buried within insulating layer 53. Thus, contact plug CP1 is formed in bit line relay region BHU, and contact plug CP2 is formed in contact region CRE. The above process completes the manufacturing of the semiconductor memory device according to the fourth embodiment.

[0225] 4.3 Effects of the Fourth Implementation

[0226] In the fourth embodiment, the contact plug CP1 provided in the region where the insulating layer (e.g., silicon oxide layer) 33 and the insulating layer (e.g., silicon nitride layer) 50 are stacked, and the contact plug CP2 provided in the region where the insulating layer (e.g., silicon oxide layer) 37 is stacked, can be formed simultaneously. This simplifies the manufacturing steps and reduces the manufacturing cost.

[0227] The effects of the fourth embodiment are described in detail below. For example, a three-dimensional stacked non-volatile semiconductor memory device may include contact plugs that penetrate a stacked structure formed by stacking an insulating layer (e.g., a silicon oxide layer) and an insulating layer (e.g., a silicon nitride layer) or a conductive layer (e.g., a metal layer), as well as contact plugs that penetrate only the insulating layer (e.g., a silicon oxide layer). These contact plugs, for example, connect upper wiring arranged above the stacked structure to lower wiring arranged below the stacked structure, or to a wiring layer of a peripheral circuit provided below the stacked structure. In such a structure, it may be difficult to simultaneously form contact plugs that penetrate the stacked structure and contact plugs that penetrate only the insulating layer, thereby increasing manufacturing costs.

[0228] Therefore, in the fourth embodiment, an insulating layer (silicon oxide layer) made of the same insulating material as that used in the region where the contact plug CP1 penetrating the laminate is formed is preformed at the location where the contact plug CP1 is formed. This allows the layers in the hole processing direction to be identical when forming the holes for contact plugs CP1 and CP2, allowing the holes for contact plugs CP1 and CP2 to be formed simultaneously in the same step. Furthermore, the holes for contact plugs CP1 and CP2 can also be filled with insulating material simultaneously in the same step. This simplifies the manufacturing process and reduces manufacturing costs. Other effects are the same as those of the first embodiment.

[0229] 5. Fifth Implementation Method

[0230] Next, a semiconductor memory device according to a fifth embodiment will be described. Figure 3 As shown, contact plug CP3 of contact region CRI and contact plug CP2 of contact region CRE are used as an example. The insulating layer 50 surrounding contact plug CP3 is replaced with the same insulating material as the insulating layer surrounding contact plug CP2 (e.g., a silicon oxide layer), and contact plugs CP2 and CP3 are formed by simultaneous processing. The circuit block structure of the fifth embodiment is the same as that of the first embodiment. In the fifth embodiment, the differences from the first embodiment are mainly described.

[0231] 5.1 Structure of Semiconductor Memory Devices

[0232] Next, the structure of the semiconductor memory device according to the fifth embodiment will be described.

[0233] 5.1.1 Planar Structure of Semiconductor Memory Devices

[0234] Figure 33 (a) is a plan view of the cell array region CA and the contact region CRI in the semiconductor memory device according to the fifth embodiment. Figure 33 (b) Yes Figure 33The enlarged view of the region R1 in (a) shows a cross section of the insulating column HRSa and the insulating layer 33 along the XY plane. Figure 33 (c) is an enlarged view of the region R1 , showing a cross section of the insulating column HRSa and the insulating layer 71 along the XY plane.

[0235] like Figure 33 As shown in (a), contact regions CRI are provided between the cell array regions CA in the X direction. Slits SLT are provided at both ends of the contact regions CRI and the cell array region CA in the Y direction. In the cell array region CA, memory pillars MP are arranged in a staggered pattern.

[0236] The contact region CRI is provided with a plurality of contact plugs CP3, a plurality of insulating pillars HRSa, and a slit ST4. The contact plugs CP3 connect the upper wiring (not shown) above the cell array region CA to the wiring layer D1 of the peripheral circuit layer. The insulating pillars HRSa have a columnar shape extending in the Z direction. The insulating pillars HRSa are formed in the same step as the support pillars HR arranged in the word line relay region WHU and are made of the same material. The insulating pillars HRSa include, for example, a silicon oxide layer. The slit ST4 is filled with an insulating layer containing an insulating material, such as at least one of a silicon oxide layer and an aluminum oxide layer.

[0237] The insulating pillars HRSa are arranged in a rosary-like pattern at the ends of the contact region CRI, surrounding the contact region CRI. Specifically, the insulating pillars HRSa are continuously arranged in the contact region CRI near the boundary between the contact region CRI and the cell array area CA. Furthermore, the insulating pillars HRSa are continuously arranged in the contact region CRI near the boundary between the contact region CRI and the slit SLT.

[0238] The insulating pillars HRSa, arranged to surround the contact region CRI, separate the area surrounded by the insulating pillars HRSa from the area not surrounded by the insulating pillars HRSa (main cell array region CA). The cell array region CA comprises a laminated structure composed of multiple insulating layers 33 and multiple conductive layers 34, 35_0 to 35_3, and 36. Within the contact region CRI, the area surrounded by the insulating pillars HRSa comprises a laminated structure composed of multiple insulating layers 33 and multiple insulating layers 71. The insulating layer 71 comprises, for example, a silicon oxide layer.

[0239] Contact plugs CP3 are arranged within contact region CRI. Insulation pillars HRSa are arranged around contact plugs CP3. The insulation pillars HRSa arranged around contact plugs CP3 function as support pillars to prevent the accumulated insulation layer 33 from collapsing. A slit ST4 is provided in the center of contact region CRI.

[0240] Figure 33(b) shows a cross section of the insulating column HRSa and the insulating layer 33 in the region R1 along the XY plane. The insulating column HRSa is covered with the insulating layer 33. In other words, the insulating layer 33 is arranged around the insulating column HRSa. Figure 33 (c) shows a cross section of the insulating pillar HRSa and the insulating layer 71 in the region R1 along the XY plane. The conductive layers 34, 35_0 to 35_3, and 36 are arranged on the cell array region CA side of the insulating pillar HRSa, and the insulating layer 71 is arranged on the contact region CRI side of the insulating pillar HRSa.

[0241] 5.1.2 Cross-sectional Structure of a Semiconductor Memory Device

[0242] Second, use Figure 34 , a cross-sectional structure of a semiconductor storage device according to a fifth embodiment is described. Figure 34 yes Figure 3 4 is a cross-sectional view of the contact region CRE, the word line relay region WHU, the cell array region CA, and the contact region CRI in FIG.

[0243] like Figure 34 As shown, a peripheral circuit layer PE is provided on a semiconductor substrate 30. The peripheral circuit layer PE includes a wiring layer D1. The wiring layer D1 is electrically connected to the peripheral circuits provided within the peripheral circuit layer PE. Furthermore, a conductive layer 32 is provided on the peripheral circuit layer PE. The conductive layer 32 functions as a source line SL. The conductive layer 32 is made of, for example, polysilicon or tungsten.

[0244] On the conductive layer 32, a laminate is provided, which is formed by alternating stacking of multiple insulating layers 33 and multiple conductive layers 34, 35_0, 35_1, 35_2, 35_3, and 36 in the Z direction. The conductive layers 34, 35_0 to 35_3, and 36 have a plate shape parallel to the XY plane (or the surface of the semiconductor substrate 30) and extend in the X direction. The conductive layer 34 functions as the selection gate line SGS. The conductive layers 35_0 to 35_3 function as word lines WL0 to WL3. The conductive layer 36 functions as the selection gate line SGD. The insulating layer 33 includes, for example, a silicon oxide layer. The conductive layers 34, 35_0 to 35_3, and 36 include, for example, tungsten (W) or polysilicon. Although four word lines WL are shown here, the number of word lines WL may be arbitrary.

[0245] Multiple pillar-shaped memory pillars MP are provided in a stacked structure comprising multiple insulating layers 33 and multiple conductive layers 34, 35_0 to 35_3, and 36. Each memory pillar MP extends in the Z direction. Each memory pillar MP is arranged to penetrate the insulating layers 33 and the conductive layers 34, 35_0 to 35_3, and 36 in the stacked structure, extending from the top surface of the topmost insulating layer 33 to the conductive layer 32. Specifically, the memory pillars MP are connected to the source line SL from the top surface of the insulating layer 33 via the select gate line SGD, multiple word lines WL0 to WL3, the select gate line SGS, and the multiple insulating layers 33.

[0246] In the bit line relay region BHU, the conductive layers 34, 35_0 to 35_3, and 36 each have a region (hereinafter referred to as a step region) sequentially provided in a stepwise manner in the X direction. The step regions of the conductive layers 34, 35_0 to 35_3, and 36 are electrically connected to the wiring layer (bit line BL) via contact plugs (not shown).

[0247] Multiple support pillars HR are provided in the bit line relay region BHU. The support pillars HR extend in the Z direction, from the topmost insulating layer 33 to the conductive layer 32. The support pillars HR are positioned in the word line relay region WHU to prevent the accumulated insulating layer 33 from collapsing. The support pillars HR are comprised of, for example, a silicon oxide layer.

[0248] In addition, if Figure 34 As shown in FIG. 1 , a plurality of insulating columns HRSa are provided in the contact region CRI. Figure 33 The insulating pillars HRSa extend in the Z direction, extending from the top insulating layer 33 to the conductive layer 32. Furthermore, a plurality of columnar contact plugs CP3 are provided in the contact region CRI. Each contact plug CP3 extends in the Z direction, extending from the top surface of the top insulating layer 33 to the wiring layer D1. Each contact plug CP3 is arranged so as to penetrate the laminated body of the plurality of insulating layers 33 and the plurality of insulating layers 71, and the conductive layer 32 in the stacking direction, and is connected to the wiring layer D1.

[0249] A plurality of columnar contact plugs CP2 are provided in the contact region CRE. Each contact plug CP2 extends in the Z direction and reaches from the upper surface of the insulating layer 33 to the wiring layer D1. Each contact plug CP2 is arranged to penetrate the insulating layer 33, the insulating layer 37, and the conductive layer 32 in the stacking direction and is connected to the wiring layer D1.

[0250] 5.2 Method for Manufacturing a Semiconductor Memory Device

[0251] Next, a method for manufacturing the semiconductor memory device according to the fifth embodiment will be described. Figures 35 to 46It is a diagram showing the structure of the semiconductor memory device in each manufacturing step according to the fifth embodiment. Figure 35 、 Figure 37 、 Figure 39 、 Figure 41 、 Figure 43 and Figure 45 is a top view showing the structure of a semiconductor memory device in each manufacturing step. Figure 36 、 Figure 38 、 Figure 40 、 Figure 42 、 Figure 44 and Figure 46 It is a cross-sectional view along the X direction of the structure in each manufacturing step.

[0252] First, if Figure 35 and Figure 36 As shown, a peripheral circuit layer PE and a conductive layer 32 are formed on a semiconductor substrate 30, and then a plurality of insulating layers 33 and a plurality of insulating layers 50 are stacked to form a stepped region and a storage column MP. Specifically, after forming a peripheral circuit layer PE including a wiring layer D1 on the semiconductor substrate 30, a conductive layer 32 is formed on the peripheral circuit layer PE, for example, by using a CVD (or ALD) method. Then, for example, by using a CVD (or ALD) method, a laminated body is formed on the conductive layer 32, in which a plurality of insulating layers 33 and a plurality of insulating layers 50 are alternately stacked. Then, by using a photolithography method, the insulating layers 33 and the insulating layers 50 of the laminated body are etched in a stepwise manner, as shown in FIG. Figure 36 As shown, a stepped region is formed in which the insulating layer 33 and the insulating layer 50 are sequentially extended in the X direction. Furthermore, a memory pillar MP extending in the Z direction is formed in the laminate of the insulating layer 33 and the insulating layer 50 .

[0253] Secondly, if Figure 37 and Figure 38 As shown in FIG. 1 , holes 72 for the support posts HR and the insulating posts HRSa are formed in the word line relay region WHU and the contact region CRI. Specifically, for example, by using RIE, as shown in FIG. Figure 38 As shown, holes 72 for the support posts HR and the insulating posts HRSa extending in the Z direction are formed in the laminate of the insulating layer 33 and the insulating layer 50 , or in the laminate and the insulating layer 37 .

[0254] Secondly, if Figure 39 and Figure 40 As shown in FIG. 7 , wet etching is used to make the insulating layer 50 retreat through the hole 72. Specifically, for example, wet etching using a phosphoric acid solution is used, as shown in FIG. Figure 40 As shown in FIG. 7 , a small amount of the insulating layer 50 is removed through the hole 72. In this wet etching, as shown in FIG. Figure 39 As shown in (c), the insulating layer 50 is etched until adjacent holes 72 are in contact with each other.

[0255] Secondly, if Figure 41 and Figure 42 As shown, support posts HR and insulating posts HRSa are formed simultaneously in word line relay region WHU and contact region CRI. Specifically, for example, an insulating material (e.g., a silicon oxide layer) is embedded in hole 72 using CVD (or ALD). This forms support posts HR in word line relay region WHU and insulating posts HRSa in contact region CRI.

[0256] Secondly, if Figure 43 and Figure 44 As shown, the insulating layer (e.g., silicon nitride layer) 50 is replaced with the conductive layers 34, 35_0 to 35_3, and 36. Specifically, a groove for the slit SLT is formed in the laminate of the plurality of insulating layers 33 and the plurality of insulating layers 50, for example, using the RIE method. The groove extends from the surface of the uppermost insulating layer 33 to the conductive layer 32. Next, in the cell array area CA and the word line relay area WHU, the insulating layer 50 is removed through the groove, for example, using wet etching using a phosphoric acid solution. Thus, a gap is formed between the insulating layers 33. Furthermore, the gap between the insulating layers 33 is filled with a conductive material, such as tungsten, using the CVD (or ALD) method, to form the conductive layers 35_0 to 35_7, and 36. Next, the insulating material, such as a silicon oxide layer, is buried in the groove, for example, using the CVD (or ALD) method. Thus, the slit SLT is formed.

[0257] On the other hand, in the area surrounded by the insulating pillars HRSa within the contact region CRI, during the wet etching using the phosphoric acid solution, the phosphoric acid solution is blocked by the insulating pillars HRSa and does not reach the insulating layer 50 in the area surrounded by the insulating pillars HRSa. Therefore, the insulating layer 50 in the area surrounded by the insulating pillars HRSa is not removed and remains as it is. That is, in the step of replacing the insulating layer 50 with the conductive layers 34, 35_0 to 35_3, and 36, as shown in FIG. Figure 43 (b) and Figure 43 As shown in (c), the insulating layer 50 in the area surrounded by the insulating posts HRSa within the contact region CRI is not replaced with a conductive layer, while the insulating layer 50 in the area not surrounded by the insulating posts HRSa is replaced with the conductive layers 34, 35_0 to 35_3, and 36. The stacked structure of the multiple insulating layers 33 and the multiple insulating layers 50 is maintained in the area surrounded by the insulating posts HRSa.

[0258] Secondly, if Figure 45 and Figure 46As shown, a slit ST4 is formed in the contact region CRI, and the insulating layer 50 in the area surrounded by the insulating pillars HRSa is replaced with the insulating layer 71. Specifically, in the area surrounded by the insulating pillars HRSa of the contact region CRI, a groove for the slit ST4 is formed, for example, using the RIE method. The groove for the slit ST4 is formed in the laminated body of the plurality of insulating layers 33 and the plurality of insulating layers 50, extending from the surface of the uppermost insulating layer 33 to the conductive layer 32. Next, the insulating layer 50 is removed through the groove for the slit ST4, for example, using wet etching using a phosphoric acid solution. Thus, a gap is formed between the insulating layers 33. Furthermore, an insulating material, for example, a silicon oxide layer, is buried in the gap between the insulating layers 33 using the CVD (or ALD) method to form the insulating layer 71. Thus, the area surrounded by the insulating pillars HRSa becomes a laminated body of the plurality of insulating layers 33 and the plurality of insulating layers 71. Next, for example, by using CVD (or ALD), an insulating material, for example, at least one of a silicon oxide layer and an aluminum oxide layer, is embedded in the groove for the slit ST4 , thereby forming the slit ST4 .

[0259] Secondly, if Figure 33 and Figure 34 As shown, contact plugs CP3 and CP2 are formed in contact region CRI and contact region CRE by simultaneous processing. Specifically, for example, using RIE, a hole for contact plug CP3 is formed in the area surrounded by insulating pillars HRSa in contact region CRI, and a hole for contact plug CP2 is formed in contact region CRE by simultaneous processing. In this case, the area surrounded by insulating pillars HRSa is formed by a laminate of multiple insulating layers 33 and multiple insulating layers 71, while the area within contact region CRE is formed by insulating layer 37. Since insulating layers 33, 71, and 37 are all, for example, silicon oxide layers, the holes can be easily processed using the same etching conditions and can be formed simultaneously. Next, using, for example, CVD (or ALD), a conductive material is embedded in the holes for contact plugs CP3 and CP2. Thus, contact plug CP3 is formed in contact region CRI, and contact plug CP2 is formed in contact region CRE.

[0260] 5.3 Effects of the Fifth Implementation

[0261] In the fifth embodiment, insulating pillars HRSa are arranged without gaps around the contact region CRI, or along the periphery of the contact region CRI, so as to surround the contact region CRI. Thus, the insulating pillars HRSa separate the insulating layer 50 in the cell array region CA and the word line relay region WHU from the insulating layer 50 in the contact region CRI. By isolating the insulating layer 50 in the contact region CRI and replacing the insulating layer 50 in the cell array region CA and the word line relay region WHU with a conductive layer, the insulating layer 50 in the contact region CRI is prevented from being replaced with a conductive layer.

[0262] Furthermore, by forming slits ST4 in the contact region CRI, the insulating layer 50 in the contact region CRI is replaced with an insulating layer (e.g., a silicon oxide layer) 71, thereby changing the layer structure of the contact region CRI to a stacked structure of the insulating layer 33 and the insulating layer 71. Thus, the layer material of the contact region CRI is the same insulating layer (e.g., a silicon oxide layer) as the layer material of the contact region CRE.

[0263] Thus, by making the layer material of the contact region CRI the insulating layer 71, the dielectric breakdown voltage between the contact plug CP3 and the conductive layers 34, 35_0 to 35_3, and 36 can be improved, thereby improving the reliability of operations such as writing, reading, and erasing in the semiconductor memory device.

[0264] Furthermore, by making the contact regions CRI and CRE of the same insulating layer (eg, silicon oxide), the contact plugs CP3 and CP2 can be easily formed simultaneously in the same step, thereby simplifying the manufacturing steps and reducing the manufacturing cost.

[0265] 6. Other variations, etc.

[0266] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the gist of the invention. These embodiments or variations thereof are intended to be within the scope and gist of the invention and are also intended to be within the scope of the invention set forth in the claims and their equivalents.

[0267] [Explanation of Symbols]

[0268] 10 NAND flash memory

[0269] 11 Memory Cell Array

[0270] 12-line decoder

[0271] 13 Driver

[0272] 14 Sense Amplifier

[0273] 15 Address register

[0274] 16 Instruction register

[0275] 17 Sequencer

[0276] 20 Controller

[0277] 30 semiconductor substrate

[0278] 32 conductive layer

[0279] 33 Insulation layer

[0280] 34, 35_0 to 35_7, 36 conductive layer

[0281] 37 Insulation layer

[0282] 50 insulation layer

[0283] 71 insulation layer

[0284] BHU bit line relay area

[0285] CA cell array area

[0286] CRE contact area

[0287] CRI contact area

[0288] WHU word line relay area

[0289] CC contact plug

[0290] CP1~CP3 contact plugs

[0291] HRL separation area

[0292] HRS separation area

[0293] HRSa Insulation Post

[0294] MP Storage Column

[0295] MPL separation area

[0296] MPS separation area

[0297] PE peripheral circuit layer

[0298] ST1~ST4 slits

[0299] SLT Slit

Claims

1. A semiconductor memory device comprising: a logic circuit disposed on the substrate; The first region is provided on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternately stacked in a first direction; a plurality of storage pillars extending in the first direction in the first region; a second region provided on the logic circuit and having the plurality of first insulating layers and the plurality of second insulating layers alternately stacked in the first direction; a contact plug extending in the first direction in the second region and connected to the logic circuit; a first separation region surrounding the second region and extending in the first direction; as well as a second separation region provided in the first region, extending in the first direction and a second direction intersecting the first direction and separating the conductive layer; and An upper surface of the first separation region is lower than an upper surface of the second separation region.

2. A semiconductor memory device comprising: a logic circuit disposed on the substrate; The first region is provided on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternately stacked in a first direction; a plurality of storage pillars extending in the first direction in the first region; a second region provided on the logic circuit and having the plurality of first insulating layers and the plurality of second insulating layers alternately stacked in the first direction; a contact plug extending in the first direction in the second region and connected to the logic circuit; a first separation region disposed between the first region and the second region and extending in the first direction; as well as a second separation region provided in the first region, extending in the first direction and a second direction intersecting the first direction and separating the conductive layer; and An upper surface of the first separation region is lower than an upper surface of the second separation region. 3 . The semiconductor memory device according to claim 1 , wherein the first isolation region has a plate shape extending in a second direction intersecting the first direction. 4 . The semiconductor memory device according to claim 1 , wherein the first isolation region includes a plurality of pillars continuously arranged in a second direction intersecting the first direction, and each of the pillars extends in the first direction. 5 . The semiconductor memory device according to claim 1 , wherein the first isolation region includes at least one of a silicon oxide layer and an aluminum oxide layer. 6 . The semiconductor memory device according to claim 1 , wherein the first isolation region includes the same film as that of the memory pillar. 7 . The semiconductor memory device according to claim 1 , wherein the first insulating layer comprises a silicon oxide layer, and the second insulating layer comprises a silicon nitride layer.

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