Semiconductor devices

Abstract

A semiconductor device is disclosed. The semiconductor device includes a stacked structure on a substrate. The stacked structure includes a stepped region and a central region located between the stepped regions, an upper insulating layer is located on the stacked structure, and a cover insulating layer is located on the stepped region of the stacked structure. The cover insulating layer includes a first upper end portion and a second upper end portion adjacent to the upper insulating layer. The upper insulating layer is located between the first upper end portion and the second upper end portion. The first upper end portion extends a first height relative to the substrate, and the first height is different from a second height of the second upper end portion relative to the substrate.

Description

[0001] This patent application claims the benefit of priority from Korean Patent Application No. 10-2018-0112457 filed on September 19, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device, and more particularly, to a planarization method of a cap insulating layer, a method of forming a semiconductor device using the planarization method, and a semiconductor device formed thereby. Background Art

[0003] In order to improve the integration of semiconductor devices, semiconductor devices including gates have been developed, which are stacked while being spaced apart from each other in a direction perpendicular to the upper surface of a semiconductor substrate. As the number of stacked gates increases, unexpected failures may occur in the process, making it difficult to improve the productivity of semiconductor devices. Summary of the invention

[0004] Aspects of the inventive concept are to provide a method of forming a semiconductor device capable of improving a planarization degree of a capping insulating layer surrounding a stack structure.

[0005] Aspects of the inventive concept are to provide a method capable of improving the integration degree of a semiconductor device.

[0006] Aspects of the inventive concept are to provide a method capable of improving productivity in manufacturing a semiconductor device.

[0007] Some embodiments of the present inventive concept provide a semiconductor device. The semiconductor device includes a stacked structure located on a substrate. The stacked structure includes: a step region and a central region located between the step regions, an upper insulating layer is located on the stacked structure, and a cover insulating layer is located on the step region of the stacked structure. The cover insulating layer includes a first upper end portion and a second upper end portion adjacent to the upper insulating layer. The upper insulating layer is located between the first upper end portion and the second upper end portion. The first upper end portion extends a first height relative to the substrate, and the first height is different from a second height of the second upper end portion relative to the substrate.

[0008] According to some embodiments of the present invention, a semiconductor device is provided. The semiconductor device includes stacked structures located on a substrate and separated from each other. Each stacked structure includes a central area and a stepped area surrounding the central area, an upper insulating layer is located on the stacked structure, and a cover insulating layer surrounds the upper insulating layer. The cover insulating layer is located on the stepped area of ​​the stacked structure and between the stacked structures. The cover insulating layer includes an upper end portion adjacent to the upper insulating layer and having a different height relative to the substrate.

[0009] According to some embodiments of the present invention, a semiconductor device is provided. The semiconductor device includes a separation structure located on a substrate and a protruding structure located between the separation structures. The protruding structure includes a stacked structure and an upper insulating layer located on the stacked structure. The stacked structure includes a step region and a central region located between the step regions, and a cover insulating layer is located on the step region and adjacent to the upper insulating layer. The cover insulating layer includes a first upper end portion and a second upper end portion, the first upper end portion and the second upper end portion are adjacent to the upper insulating layer and have different heights relative to the substrate.

[0010] According to some embodiments of the present invention, a method for forming a semiconductor device is provided. The method includes: forming a protruding structure on a substrate, wherein each protruding structure includes a molding structure, an upper insulating layer located on the molding structure, and a planarization stop layer located on the upper insulating layer; forming a covering insulating layer on the substrate having the protruding structure; forming a mask pattern having an opening on the covering insulating layer, wherein the opening overlaps the protruding structure; etching the covering insulating layer exposed by the opening; after etching the covering insulating layer, removing the mask pattern; after removing the mask pattern, performing a first planarization process for planarizing the covering insulating layer for the first time; after the first planarization process, performing a second planarization process for planarizing the covering insulating layer for the second time to form a planarized covering insulating layer; and removing the planarization stop layer of the protruding structure to expose the upper insulating layer. The planarized covering insulating layer has an upper end portion adjacent to the planarization stop layer, and the upper end portion includes a first upper end portion and a second upper end portion located at different height levels.

[0011] According to some embodiments of the present invention, a method for forming a semiconductor device is provided. The method includes: forming a protruding structure on a substrate, wherein each protruding structure includes a molding structure having a central area and a stepped area surrounding the central area, an upper insulating layer located on the central area of ​​the molding structure, and a planarization stop layer located on the upper insulating layer; forming a cover insulating layer on the substrate having the protruding structure; forming a mask pattern having an opening on the cover insulating layer, wherein the opening overlaps the central area of ​​the protruding structure; etching the cover insulating layer exposed by the opening; after etching the cover insulating layer, removing the mask pattern; after removing the mask pattern, performing a first planarization process for planarizing the cover insulating layer for the first time; after the first planarization process, performing a second planarization process for planarizing the cover insulating layer for the second time to form a planarized cover insulating layer; and removing the planarization stop layer of the protruding structure to expose the upper insulating layer. The opening has a size smaller than the size of the planarization stop layer of the protruding structure, and the opening includes openings having different widths or sizes from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1A and Figure 1B is a flowchart illustrating a method of forming a semiconductor device according to some embodiments of the inventive concept;

[0014] Figure 2 is a plan view illustrating a method of forming a semiconductor device according to some embodiments of the inventive concept;

[0015] Figure 3 yes Figure 2 a partial enlarged view of a portion of;

[0016] FIG. 4A to FIG. 15B is a view illustrating a method of forming a semiconductor device according to some embodiments of the inventive concept;

[0017] Fig.16 is a partially enlarged cross-sectional view showing a portion of a semiconductor device according to some embodiments of the inventive concept;

[0018] Fig.17 is a partially enlarged cross-sectional view showing a portion of a semiconductor device according to some embodiments of the inventive concept;

[0019] Fig.18 is a cross-sectional view illustrating a modified embodiment of a semiconductor device according to some embodiments of the inventive concept; and

[0020] Fig.19 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0021] It is noted that, although there is no specific description about different embodiments, the aspects of the inventive concept described about one embodiment can be incorporated into different embodiments. That is to say, all embodiments and / or the features of any embodiment can be combined in any manner and / or combination. These and other purposes and / or aspects of the inventive concept are explained in detail in the specification set forth below. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. When a statement such as "at least one (kind) of (one) ... " is after a column of elements, the entire column of elements is modified and the individual elements of the column are not modified. Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0022] In the following, reference will be made to Figures 1A to 19 Various embodiments of methods of forming a semiconductor device according to some embodiments of the inventive concept are described. Figure 1A and Figure 1B is a flowchart illustrating a method of forming a semiconductor device according to some embodiments of the inventive concept. Figure 2 is a plan view illustrating a method of forming a semiconductor device according to some embodiments of the inventive concept. Figure 3 yes Figure 2 A partial enlarged view of a portion (area 'A'). FIG. 4A to FIG. 15B are views illustrating a method of forming a semiconductor device according to some embodiments of the inventive concept. Fig.16 is a partially enlarged cross-sectional view illustrating a portion of a semiconductor device according to some embodiments of the inventive concept. Fig.17 is a partially enlarged cross-sectional view illustrating a portion of a semiconductor device according to some embodiments of the inventive concept. Fig.18 are cross-sectional views illustrating modified embodiments of semiconductor devices according to some embodiments of the inventive concept. Fig.19 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0023] exist FIG. 4A to FIG. 15B middle, Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 10A , Fig. 12A , Fig.13A and Fig.15A is shown along Figure 3 A cross-sectional view of the area cut by line II' in FIG. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 10B , Fig. 12B , Fig. 13B and 15B is shown along Figure 3 A cross-sectional view of the area cut by line II-II' in FIG. Fig. 9 is a partially enlarged cross-sectional view illustrating a modified embodiment of a method of forming a semiconductor device according to some embodiments of the inventive concept, Fig.14 is a partially enlarged plan view illustrating an example of a method of forming a semiconductor device according to some embodiments of the inventive concept.

[0024] Reference Figure 1A , Figure 2 , Figure 3 , Figure 4A and Figure 4B, a protruding structure PA may be formed on the substrate 10 (S5). The substrate 10 may be a semiconductor wafer. The substrate 10 may include a plurality of irradiation areas SA, through which light from an exposure device may be irradiated to perform an exposure process. Each irradiation area SA may include a plurality of chip areas CA. A protruding structure PA may be formed on the substrate 10. A protruding structure PA may be formed in each chip area CA.

[0025] The protruding structure PA formed on the substrate 10 may be arranged so that the distance in the first direction X is different from the distance in the second direction Y in one chip area CA. It will be understood that although the terms first, second, third, etc. may be used here to describe various elements, the elements should not be limited by these terms. Instead, these terms are only used to distinguish one element from another. Therefore, without departing from the scope of the inventive concept, the first element discussed may be referred to as the second element.

[0026] Each protruding structure PA may include a central region CR and a stepped region SR. The formation of the protruding structure PA may include: forming an interlayer insulating layer 14 and a gate layer 16 alternately and repeatedly stacked on the substrate 10; sequentially forming an upper insulating layer 18 and a planarization stop layer 20; and patterning the planarization stop layer 20, the upper insulating layer 18, the interlayer insulating layer 14, and the gate layer 16. The planarization stop layer 20 and the upper insulating layer 18 may remain in the central region CR. The interlayer insulating layer 14 and the gate layer 16 may be alternately and repeatedly stacked in the central region CR and extend into the step region SR to retain a shape having a step structure in the step region SR. The interlayer insulating layer 14 and the gate layer 16 may constitute each molding structure 12. Therefore, each protruding structure PA may include a molding structure 12 and an upper insulating layer 18 and a planarization stop layer 20 sequentially stacked on each molding structure 12.

[0027] The interlayer insulating layer 14 may be formed of silicon oxide.

[0028] In some embodiments, the gate layer 16 may be formed of an insulating material (eg, silicon nitride) having an etching selectivity with respect to the interlayer insulating layer 14 .

[0029] In some embodiments, the gate layer 16 may be formed of a conductive material having an etching selectivity relative to the interlayer insulating layer 14 (e.g., one or more of doped polysilicon, metal nitride (e.g., TiN), metal semiconductor compounds (e.g., TiSi, WSi, etc.), and metal (e.g., W) or a combination thereof).

[0030] A capping insulating layer 24 may be formed on the substrate having the protruding structure PA (S10). The capping insulating layer 24 may be formed of silicon oxide or porous oxide, and the capping insulating layer 24 has a density lower than that of the upper insulating layer 18. For example, the capping insulating layer 24 may be formed of a low-k dielectric. The capping insulating layer 24 may include an oxide formed by flowable CVD or spin-on glass (SOG), which has a higher deposition rate or a higher deposition rate than the upper insulating layer 18. The upper insulating layer 18 may be formed of a silicon-based oxide such as TEOS oxide.

[0031] The cover insulating layer 24 may be formed to have a curved shape by the step difference of the protruding structure PA. For example, the upper surface of the cover insulating layer 24 may include a protruding surface 24P protruding in an upward direction in the central region CR of the protruding structure PA, a recessed surface 24R provided on the substrate between the protruding structures PA, and an inclined surface 24S between the protruding surface 24P and the recessed surface 24R. The height of the recessed surface 24R of the upper surface of the cover insulating layer 24 may be higher than the height of the upper surface of the planarization stop layer 20 of the protruding structure PA.

[0032] In some embodiments, “height” or “height level” may be defined based on the upper surface 10s of the substrate 10. For example, the same height level may refer to being located at the same height from the upper surface 10s of the substrate 10 in the vertical direction Z. The vertical direction Z may be perpendicular to the upper surface 10s of the substrate 10.

[0033] The irradiation area SA may include a first irradiation area SA1 and a second irradiation area SA2 adjacent to each other. The plurality of chip areas CA in the first irradiation area SA1 may include a first chip area CA1 and a second chip area CA2 adjacent to each other in a first direction X. The plurality of chip areas CA in the first irradiation area SA1 may include a third chip area CA3 adjacent to the first chip area CA1 in a second direction Y. The first direction X and the second direction Y may be perpendicular to each other and may be parallel to the upper surface 10s of the substrate 10.

[0034] The first chip area CA1 may include a plurality of protrusion structures PA. For example, the first chip area CA1 may include first and second protrusion structures PA1 and PA2 adjacent to each other in the first direction X. The first chip area CA1 may be formed of first and second protrusion structures PA1 and PA2 adjacent to each other in the first direction X and third and fourth protrusion structures PA3 and PA4 adjacent to each other in the first direction X.

[0035] In some embodiments, a first distance L1 between the first and second protrusion structures PA1 and PA2 adjacent to each other in the first direction X may be greater than a second distance L2 between the first and third protrusion structures PA1 and PA3 adjacent to each other in the second direction Y.

[0036] In some embodiments, a third distance L3 between the second protruding structure PA2 in the first chip area CA1 and the protruding structure PA(PA5) in the second chip area CA2, which are adjacent to each other, may be smaller than a fourth distance L4 between the first protruding structure PA1 in the first irradiation area SA1 and the protruding structure PA(PA6) in the second irradiation area SA2, which are adjacent to each other.

[0037] In some embodiments, the third distance L3 between the second protruding structure PA2 in the first chip area CA1 and the protruding structure PA(PA5) in the second chip area CA2 adjacent to each other may be greater than the distances L1 and L2 between the protruding structures PA1, PA2, PA3, and PA4 adjacent to each other in the first chip area CA1. For example, the third distance L3 may be greater than each of the first distance L1 and the second distance L2.

[0038] Reference Figure 1A , Figure 2 , Figure 3 , Figure 5A and Figure 5B , a mask pattern 28 having openings 29 may be formed on the cover insulating layer 24 (S15). The mask 28 may be a photoresist pattern. The openings 29 may expose the cover insulating layer 24. The openings 29 may overlap the planarization stop layer 20 of the protruding structure PA. In some embodiments, each opening 29 may have a width narrower than the width of the planarization stop layer 20 or a size smaller than the size of the planarization stop layer 20.

[0039] As described above, the distances L1 , L2 , L3 , and L4 between the protrusion structures PA adjacent to each other in the first direction X or the second direction Y may be different.

[0040] The size of the opening 29 may be different according to the distance between the protruding structures PA adjacent to each other in the first direction X or the second direction Y. Alternatively, the spacing distance between the sidewall of the opening 29 and the virtual line extending from the side surface of the planarization stop layer 20 in the upward direction (i.e., in the vertical direction Z) may be determined according to the distance between the protruding structures PA adjacent to each other in the first direction X or the second direction Y. For example, when the spacing distance between the protruding structures PA adjacent to each other is relatively long, the distance between the sidewall of the opening 29 and the virtual line extending from the side surface of the planarization stop layer 20 in the upward direction Z may be relatively long. In some embodiments, when the spacing distance between the protruding structures PA adjacent to each other is relatively short, the distance between the sidewall of the opening 29 and the virtual line extending from the side surface of the planarization stop layer 20 in the upward direction Z may be relatively short. When the spacing distance between the protruding structures PA adjacent to each other is at a relatively medium length, the distance between the sidewall of the opening 29 and the virtual line extending from the side surface of the planarization stop layer 20 in the upward direction Z may be at a relatively medium length.

[0041] As described above, the distance between the sidewall of the opening 29 and the virtual line extending in the upward direction Z from the side surface of the planarization stop layer 20 may be determined according to the spacing distance between the protrusion structures PA adjacent to each other.

[0042] Some embodiments in which the distance between the sidewall of the opening 29 and an imaginary line extending in the upward direction Z from the side surface of the planarization stop layer 20 is determined according to the spacing distance between the protrusion structures PA adjacent to each other will be described below.

[0043] The opening 29 may include the first opening 29 a on the planarization-stop layer 20 a of the first protrusion structure PA1 described above.

[0044] The planarization stop layer 20a of the first protrusion structure PA1 may have a first side surface 20S1 and a second side surface 20S2 facing each other in the first direction X. The first side surface 20S1 of the planarization stop layer 20a of the first protrusion structure PA1 may face the protrusion structure PA in the second irradiation area SA2 that is spaced apart from the first protrusion structure PA1 by a fourth distance L4. The second side surface 20S2 of the planarization stop layer 20a of the first protrusion structure PA1 may face the second protrusion structure PA2 that is spaced apart from the first protrusion structure PA1 by a first distance L1. The first opening 29a may have a first side wall 29S1 and a second side wall 29S2 facing each other in the first direction X. The first side wall 29S1 of the first opening 29a may be adjacent to the first side surface 20S1, and / or the second side wall 29S2 may be adjacent to the second side surface 20S2.

[0045] The planarization-stop layer 20a of the first protrusion structure PA1 may have a third side surface 20S3 and a fourth side surface 20S4 facing each other in the second direction Y. The third side surface 20S3 of the planarization-stop layer 20a of the first protrusion structure PA1 may face a protrusion structure PA in another irradiation area SA that is spaced apart from the first protrusion structure PA1 by a fourth distance L4. The fourth side surface 20S4 of the planarization-stop layer 20a of the first protrusion structure PA1 may face a third protrusion structure PA3 that is spaced apart from the first protrusion structure PA1 by a second distance L2.

[0046] The first opening 29 a may have a third sidewall 29S3 and a fourth sidewall 29S4 facing each other in the second direction Y. In the first opening 29 a , the third sidewall 29S3 may be adjacent to the third side surface 20S3 , and the fourth sidewall 29S4 may be adjacent to the fourth side surface 20S4 .

[0047] A first distance D1 between an imaginary line extending from the first side surface 20S1 of the planarization stop layer 20a of the first protruding structure PA1 in the upward direction Z and the first sidewall 29S1 of the first opening 29a may be different from a second distance D2 between an imaginary line extending from the second side surface 20S2 of the planarization stop layer 20a of the first protruding structure PA1 in the upward direction Z and the second sidewall 29S2 of the first opening 29a. For example, the second distance D2 may be greater than the first distance D1.

[0048] A virtual line extending from the third side surface 20S3 of the planarization stop layer 20 a of the first protrusion structure PA1 in the upward direction Z and the third sidewall 29S3 of the first opening 29 a may be spaced apart from each other by a first distance D1 .

[0049] The fourth side surface 20S4 of the planarization stop layer 20a of the first protruding structure PA1 extending in the upward direction Z from the virtual line and the fourth side wall 29S4 of the first opening 29a may be separated from each other by a third distance D3 greater than the second distance D2. The sizes of the first distance to the third distance D1, D2 and D3 may be determined according to a predetermined rule. Therefore, the size and position of the first opening 29a may be determined. Similarly, the size and position of the second opening 29b and the third opening 29c may be determined. For example, when viewed in the first direction X, the third distance L3 between the protruding structure PA adjacent to the second protruding structure PA2 in the second chip area CA2 and the second protruding structure PA2 may be shorter than the fourth distance L4 between the protruding structure PA adjacent to the first protruding structure PA1 in the second irradiation area SA2 and the first protruding structure PA1. Therefore, the width W2 of the second opening 29b located on the second protruding structure PA2 in the first direction X may be smaller than the width W1 of the first opening 29a located on the first protruding structure PA1 in the first direction X.

[0050] Reference Figure 1A , Figure 2 , Figure 3 , Fig. 6A and Figure 6B , the capping insulating layer 24 exposed by the opening 29 may be etched (S20). An opening 32 of the capping insulating layer 24 corresponding to the opening 29 of the mask pattern 28 may be formed by etching the capping insulating layer 24. A first opening 32a, a second opening 32b, and a third opening 32c of the capping insulating layer 24 corresponding to the first opening 29a, the second opening 29b, and the third opening 29c of the mask pattern 28 may be formed.

[0051] In some embodiments, the planarization stop layer 20 may be exposed through the opening 32 of the capping insulation layer 24. A portion of the protruding surface 24P of the upper surface of the capping insulation layer 24 may remain.

[0052] In some embodiments, when the opening 32 capping the insulating layer 24 is formed, a relatively shallow trench 20 t may be formed in an upper portion of the planarization stop layer 20 adjacent to a sidewall of the opening 32 .

[0053] Subsequently, the mask pattern 28 may be removed ( S25 ).

[0054] Reference Figure 1A , Figure 2 , Figure 3 , Fig. 7A and Figure 7B , a first planarization process (S30) for planarizing the capping insulating layer 24 for the first time may be performed. The first planarization process may be a chemical mechanical polishing process. The first planarization process may reduce the thickness of the upper surface of the capping insulating layer 24. Figure 6B For example, the first planarization process can lower the protruding surface 24P of the upper surface of the capping insulating layer 24 to a level lower than the upper surface of the capping insulating layer 24. Figure 6B The level of the recessed surface 24R.

[0055] Reference Figure 1A , Figure 2 , Figure 3 , Fig. 8A and Figure 8B , a second planarization process (S35) for planarizing the capping insulating layer 24 for the second time may be performed. The second planarization process may be a chemical mechanical polishing process. The second planarization process may reduce the thickness of the upper surface of the capping insulating layer 24. Figure 6B For example, the second planarization process can reduce the upper surface of the capping insulating layer 24. Figure 6BThe recessed surface 24R of the planarization stop layer 20 is formed, and at the same time, a portion of the capping insulating layer 24 remaining on the upper surface of the planarization stop layer 20 is removed. Therefore, the capping insulating layer 24 can be planarized.

[0056] The capping insulating layer 24 may have an upper end portion 24T adjacent to the protrusion structure PA.

[0057] like Fig. 8A As shown in the cross-sectional view of FIG. 1 , in the first direction X, the upper end portion 24T of the cover insulating layer 24 may include a first upper end portion 24T1, a second upper end portion 24T2, a third upper end portion 24T3, and a fourth upper end portion 24T4, the first upper end portion 24T1 and the second upper end portion 24T2 are adjacent to the first upper insulating layer 18a of the first protruding structure PA1 and are opposite to each other, the third upper end portion 24T3 and the fourth upper end portion 24T4 are adjacent to the second upper insulating layer 18b of the second protruding structure PA2 and are opposite to each other. The second upper end portion 24T2 and the third upper end portion 24T3 may face each other.

[0058] In some embodiments, the second upper end portion 24T2 and the third upper end portion 24T3 , which may face each other, may be located at the same or similar height levels relative to each other.

[0059] In some embodiments, the first upper end portion 24T1 may be located at a level higher than that of the second upper end portion 24T2. The fourth upper end portion 24T4 may be located at a level higher than that of the third upper end portion 24T3. The fourth upper end portion 24T4 may be located at a level lower than that of the first upper end portion 24T1.

[0060] Therefore, among the first to fourth upper portions 24T1, 24T2, 24T3 and 24T4, the first upper portion 24T1 may be located at a relatively high level, the second upper portion 24T2 and the third upper portion 24T3 may be located at relatively low levels, and the fourth upper portion 24T4 may be located at a relatively middle level.

[0061] like Figure 8B As shown in the cross-sectional view of FIG. 2 , in the second direction Y, the upper end portion 24T of the cover insulating layer 24 may include a fifth upper end portion 24T5, a sixth upper end portion 24T6, a seventh upper end portion 24T7, and an eighth upper end portion 24T8, the fifth upper end portion 24T5 and the sixth upper end portion 24T6 are adjacent to the first upper insulating layer 18a of the first protruding structure PA1 and are opposite to each other, and the seventh upper end portion 24T7 and the eighth upper end portion 24T8 are adjacent to the third upper insulating layer 18c of the third protruding structure PA3 and are opposite to each other. The sixth upper end portion 24T6 and the seventh upper end portion 24T7 may face each other.

[0062] In some embodiments, the sixth upper end portion 24T6 and the seventh upper end portion 24T7 , which may face each other, may be located at the same height level with respect to each other.

[0063] In some embodiments, the fifth upper end portion 24T5 may be located at a level higher than those of the sixth upper end portion 24T6, the seventh upper end portion 24T7, and the eighth upper end portion 24T8. The eighth upper end portion 24T8 may be located at a level higher than that of the seventh upper end portion 24T7.

[0064] Therefore, among the fifth to eighth upper portions 24T5, 24T6, 24T7 and 24T8, the fifth upper portion 24T5 can be located at a relatively high level, the sixth upper portion 24T6 and the seventh upper portion 24T7 can be located at relatively low levels, and the eighth upper portion 24T8 can be located at a relatively middle level.

[0065] In some embodiments, the first upper end portion 24T1 and the fifth upper end portion 24T5 located in different irradiation regions and facing each other may be located at a level higher than the levels of the other upper end portions 24T2, 24T3, 24T4, 24T6, and 24T7 located in any one irradiation region. The fourth upper end portion 24T4 and the eighth upper end portion 24T8 facing the other chip region in any one irradiation region may be located at a level lower than the level of the first upper end portion 24T1 and the fifth upper end portion 24T5. The sixth upper end portion 24T6 and the seventh upper end portion 24T7 facing each other with a relatively short distance in any one chip region may be located at a level lower than the second upper end portion 24T2 and the third upper end portion 24T3 facing each other with a relatively long distance.

[0066] In some embodiments, the first to fourth upper end portions 24T1, 24T2, 24T3, and 24T4 and the fifth to eighth upper end portions 24T5, 24T6, 24T7, and 24T8 may be located at a level higher than that of the upper insulating layer 18, but the inventive concept is not limited thereto. At least one upper end portion located at a relatively low level among the first to fourth upper end portions 24T1, 24T2, 24T3, and 24T4 and the fifth to eighth upper end portions 24T5, 24T6, 24T7, and 24T8 may be located at a level lower than the upper surface of the upper insulating layer 18. Fig. 9 Such a modified embodiment is described. Fig. 9 24 is a partially enlarged cross-sectional view showing some embodiments in which the height level of the second upper end portion 24T2 may be different.

[0067] Reference Fig. 9, a second upper end portion ( Fig. 8A 24T2) in the figure may be modified to be another second upper end portion ( Fig. 9 As described above, by performing the over-planarization process, at least one upper end portion located at a relatively low level may be positioned at a level lower than the upper surface of the upper insulating layer 18, so that when a second planarization process may be performed in S35 to planarize the capping insulating layer 24 for the second time, the capping insulating layer 24 on the upper surface of the planarization stop layer 20 may not be retained, resulting in another second upper end portion 24T2′ being located at a level lower than the upper surface of the upper insulating layer 18.

[0068] Reference Figure 1A , Figure 2 , Figure 3 , Fig. 10A and Fig. 10B , you can remove Figure 8B Thus, the upper insulating layer 18 may be exposed.

[0069] The surface of the cover insulating layer 24 may be hardened to form the surface layer 24H. For example, the surface layer 24H may be formed by hardening the surface of the cover insulating layer 24 using an annealing process, and the annealing process may be performed in a humid atmosphere at a process temperature of about 500° C. to about 1000° C. for a process time of about 30 minutes to about 2 hours. When observed using a device such as a scanning electron microscope, the surface layer 24H may be viewed as a linear shape.

[0070] The surface of the upper insulating layer 18, which may be formed with an oxide denser than the capping insulating layer 24, may not be hardened by the annealing process, or may be hardened to have a thickness thinner than the surface layer 24H of the capping insulating layer 24. In some embodiments, the surface layer 24H of the capping insulating layer 24 may separate the capping insulating layer 24 from the upper insulating layer 18.

[0071] The surface layer 24H may be formed by hardening the surface of the capping insulating layer 24 and may be formed of a less dense oxide or a relatively porous oxide (eg, a low-k dielectric). The surface layer 24H may protect the capping insulating layer 24 from subsequent processes.

[0072] Reference Figure 1B , then a memory structure may be formed (S45). A method of forming such a memory structure will be described.

[0073] Reference Figure 1B , Figure 2 , Figure 3 , Fig.11Aand Fig. 11B , a first insulating layer 36 may be formed on the capping insulating layer 24. A memory vertical structure 40 may be formed on the substrate 10 passing through the central region CR of the protrusion structure PA.

[0074] Reference Figure 1B , Figure 2 , Figure 3 , Fig. 12A and Fig. 12B , a second insulating layer 56 may be formed covering the first insulating layer 36 and the memory vertical structure 40. The first insulating layer 36 and the second insulating layer 56 may be formed of silicon oxide.

[0075] A separation trench 57 passing through the protrusion structure PA may be formed on the substrate 10. The separation trench 57 may pass through the protrusion structure PA and extend in an upward direction, and may pass through the upper insulating layer 18, the cover insulating layer 24, and the first and second insulating layers 36 and 56 overlapping the protrusion structure PA.

[0076] The gate layer 16 may be exposed through the separation trench 57 .

[0077] Reference Figure 1B , Figure 2 , Figure 3 , Fig.13A and Fig. 13B , the gate layer 16 exposed by the separation trench 57 may be replaced by the gate pattern 60. Subsequently, a separation structure 66 filling the separation trench 57 may be formed.

[0078] Therefore, the above-mentioned protrusion structure PA can be modified into a protrusion structure PA' in which the gate layer 16 is replaced with the gate pattern 60. The protrusion structure PA' that can be modified as above can include the first to third protrusion structures PA1', PA2' and PA3' that can be modified at positions corresponding to the above-mentioned first to third protrusion structures PA1, PA2 and PA3. Likewise, the molding structure 12 can be replaced with a stacked structure 72. Therefore, each of the stacked structures 72 may include interlayer insulating layers 14 and gate patterns 60 that are alternately and repeatedly stacked.

[0079] In some embodiments, the gate layer 16 may remain in a portion of the step region SR located in the width direction of the separation structure 66 (e.g., in the second direction Y). Therefore, each of the stacked structures 72 may include the gate layer 16 that remains in a portion of the step region SR located in the width direction of the separation structure 66 (e.g., in the second direction Y) and faces the gate pattern 60.

[0080] Will refer to Fig.14 A plan view of the separation structure 66 is depicted. Fig.14is a plan view schematically showing the separation structure 66 and the memory vertical structure 40 together with any one of the protruding structures PA′.

[0081] Reference Fig.14 , the separation structure 66 may pass through the protrusion structure PA′. The memory vertical structure 40 may be formed in the center region CR of the protrusion structure PA′, and may be formed between the separation structures 66.

[0082] Next, refer to Figure 1B , Figure 2 , Figure 3 , Fig.15A and Fig. 15B , a wiring structure may be formed (S50). The formation of the wiring structure may include: forming a third insulating layer 74 on the second insulating layer 56; forming a gate contact structure 80 electrically connected to the gate pattern 60, the gate pattern 60 having a step structure in the step region SR located in the first direction X; forming a bit line contact structure 82 electrically connected to the memory vertical structure 40; and forming wirings 84 and 86 on the third insulating layer 74. The wirings 84 and 86 may include a gate connection wiring 84 electrically connected to the gate contact structure 80 and a bit line 86 electrically connected to the bit line contact structure 82. Then, an upper cover insulating layer 90 covering the wirings 84 and 86 may be formed on the third insulating layer 74.

[0083] Will refer to Fig.16 and Fig.17 Some embodiments of the above-described method of forming the memory vertical structure 40 , the gate pattern 60 , and the separation structure 66 are described. Fig.16 is a partially enlarged cross-sectional view showing a region including any one of the memory vertical structures 40, Fig.17 is a partially enlarged cross-sectional view showing a region including any one of the separation structures 66 .

[0084] Will refer to FIG. 11A to FIG. 17 Some embodiments of methods of forming any of the memory vertical structures 40 , the gate pattern 60 , and any of the separation structures 66 are described.

[0085] Reference FIG. 11A to FIG. 17 , the memory vertical structure 40 may be formed to include a dielectric structure 44 and a channel semiconductor layer 52. For example, Fig.11A and Fig. 11BAs described in the foregoing, the formation of the memory vertical structure 40 may include: forming a channel hole 40H passing through the central region CR of the protruding structure PA and exposing the substrate 10; performing an epitaxial process to form a semiconductor pattern 42 filling the lower region of the channel hole 40H of the substrate 10 exposed by the channel hole 40H; forming a dielectric structure 44 on the sidewall of the channel hole 40H; forming a channel semiconductor layer 52 contacting the semiconductor pattern 42 while covering the inner wall of the dielectric structure 44; forming a core pattern 53 partially filling the channel hole 40H; and forming a pad pattern 54 filling the remaining portion of the channel hole 40H. The pad pattern 54 may be formed on the core pattern 53 and contact the channel semiconductor layer 52.

[0086] The channel semiconductor layer 52 may be formed of polysilicon. The core pattern 53 may be formed of an insulating material such as silicon oxide. The pad pattern 54 may be formed of doped polysilicon (eg, polysilicon having N-type conductivity).

[0087] The dielectric structure 44 may include a tunnel insulating layer 50, a data storage layer 48, and a blocking insulating layer 46. The data storage layer 48 may be disposed between the tunnel insulating layer 50 and the blocking insulating layer 46. The tunnel insulating layer 50 may be disposed between the channel semiconductor layer 52 and the data storage layer 48. The blocking insulating layer 46 may be disposed between the data storage layer 48 and the gate pattern 60. The tunnel insulating layer 50 may include silicon oxide and / or silicon oxide doped with impurities. The blocking insulating layer 46 may include silicon oxide and / or a high-k dielectric.

[0088] The data storage layer 48 may store data in a nonvolatile memory device such as a flash memory device, etc. For example, the data storage layer 48 may be formed of a material such as silicon nitride, which may capture and retain electrons injected from the channel semiconductor layer 52 through the tunnel insulating layer 50, or erase the captured electrons in the data storage layer 48, according to operating conditions of the nonvolatile memory device such as a flash memory device.

[0089] like Fig. 12A and Fig. 12B As described in the above, the formation of the gate pattern 60 may include: forming a separation trench 57 to expose the gate layer ( Fig. 12A and Fig. 12B 16); etching the exposed gate layer ( Fig. 12A and Fig. 12B 16) to form a void space exposing the side surface of the memory vertical structure 40; forming a first material layer 62 covering and / or contacting the inner wall of the void space and a second material layer 64 filling the void space; and removing the first material layer 62 and the second material layer 64 remaining in the separation trench 57. The first material layer 62 may cover and / or contact the upper and lower surfaces of the second material layer 64, and may extend between the second material layer 64 and the memory vertical structure 40.

[0090] In some embodiments, the first material layer 62 can be formed of a dielectric, for example, a high-k dielectric (such as aluminum oxide), and the second material layer 64 can be formed of a conductive material (for example, any one or a combination of doped polysilicon, metal nitrides (for example, TiN, etc.) and metals (for example, W)).

[0091] In some embodiments, the first material layer 62 and the second material layer 64 may be formed of different conductive materials. For example, the first material layer 62 may be formed of metal nitride (eg, TiN), and the second material layer 64 may be formed of metal (eg, W).

[0092] The gate pattern 60 may include a lower gate pattern 60L, an intermediate gate pattern 60M on the lower gate pattern 60L, and an upper gate pattern 60U on the intermediate gate pattern 60M.

[0093] In some embodiments, the second material layer 64 of the lower gate pattern 60L may be a ground selection line of a NAND flash memory device, the second material layer 64 of the middle gate pattern 60M may be a word line of the NAND flash memory device, and the second material layer 64 of the upper gate pattern 60U may be a string selection line of the NAND flash memory device.

[0094] The data storage layer 48 may store data in a region facing the middle gate pattern 60M which may serve as a word line. The region capable of storing data in the data storage layer 48 in the memory vertical structure 40 may be arranged in a direction Z perpendicular to the upper surface of the substrate 10 and may include a memory cell.

[0095] The memory vertical structure 40 and the gate pattern 60 may be Figure 1B The memory structure of S45.

[0096] After forming the gate pattern 60, a separation structure 66 may be formed to fill the separation trench ( Fig. 12A and Fig. 12B 57 in). Each separation structure 66 may include a separation spacer 68 covering the side surface of each separation trench 57 and a separation core pattern 70 filling each separation trench 57. In some embodiments, the separation spacer 68 may be formed of an insulating material such as silicon oxide, and the separation core pattern 70 may be formed of any one of doped polysilicon, metal nitride (e.g., TiN, etc.), metal (e.g., W), or a combination thereof.

[0097] In some embodiments, the separate spacers 68 and the separate core patterns 70 may be formed of an insulating material.

[0098] As mentioned above Fig. 9As described above, the second upper end portion 24T2' that can be modified may be located at a level lower than the upper surface of the upper insulating layer 18. As described above, with respect to the substrate having the second upper end portion 24T2' that can be modified, it is possible to refer to FIG. 10A to FIG. 17 The method described is to perform a semiconductor process to form a semiconductor device having a Fig.18 1 , the semiconductor device of the second upper end portion 24T2′ is shown located at a level lower than the upper surface of the upper insulating layer 18. As described above, the third upper end portion 24T3′ may be located at the same height level as the height level of the second upper end portion 24T2′, and thus may be located at a height level lower than the upper surface of the upper insulating layer 18.

[0099] Reference Figure 1B , Figure 2 , Figure 3 and Fig.19 , the semiconductor chip CH can be separated (S55). Figure 2 As shown in , the separation of the semiconductor chip CH may include cutting the chip areas CA to separate the chip areas CA from each other. Therefore, each separated chip area CA may be a semiconductor chip CH. Therefore, the semiconductor chip CH may include a protruding structure PA' formed on the substrate 10. Each protruding structure PA' may include a central area CR and a step area SR of a step structure surrounding the central area CR.

[0100] A product 100 may be formed using the semiconductor chip CH (S60). The product 100 may include a semiconductor chip CH disposed on a substrate 95. In some embodiments, when the product 100 is a semiconductor device such as a semiconductor package, the substrate 95 may be a printed circuit board. In another embodiment, the product 100 may be an electronic device including a semiconductor device having the semiconductor chip CH.

[0101] Therefore, it is possible to provide Figures 1A to 19 The semiconductor device formed by the method for forming a semiconductor device described herein. Fig.15A , Fig. 15B , Fig.16 , Fig.17 and Fig.19 The structure of the semiconductor device formed by the above method is described. When explaining the structure of such a semiconductor device, the above reference will be omitted. Figures 1A to 19 The content described is duplicated or can be referenced from Figures 1A to 19 The content of the description leads to the content.

[0102] Reference Fig.14 , Fig.15A , Fig. 15B , Fig.16 , Fig.17 and Fig.19 , the protrusion structures PA′ may be disposed on the substrate 10 . Each of the protrusion structures PA′ may include a stack structure 72 and an upper insulating layer 18 on the stack structure 72 .

[0103] Each protruding structure PA' may include a central region CR and a stepped region SR surrounding the central region CR. Each stacked structure 72 may be regarded as including a central region CR and a stepped region SR surrounding the central region CR in a manner similar to the protruding structure PA'.

[0104] Each stacked structure 72 may include an interlayer insulating layer 14 and a gate pattern 60, which are alternately and repeatedly stacked in the central region CR and extend into the step region SR to form a step structure in the step region SR. The interlayer insulating layer 14 and the gate pattern 60 may have a step structure in the step region SR. The upper insulating layer 18 of the protruding structure PA' may be located in the central region CR and may be disposed on the stacked structure 72.

[0105] The capping insulating layer 24 may surround the upper insulating layer 18 , cover the step regions SR of the stack structures 72 , and fill between the stack structures 72 .

[0106] The cover insulating layer 24 may include a surface layer 24H formed in the surface of the cover insulating layer 24. The surface layer 24H may be formed by hardening the surface of the cover insulating layer 24, and thus may be harder and / or denser than other portions of the cover insulating layer 24. Other portions of the cover insulating layer 24 may be referred to as a "main portion." Therefore, the surface layer 24H of the cover insulating layer 24 may be disposed on an upper surface of the main portion of the cover insulating layer 24.

[0107] The capping insulating layer 24 may include an upper end portion 24T adjacent to the upper insulating layer 18 and located at a different height level.

[0108] As the upper insulating layer 18 is closer to the cover insulating layer 24, the cover insulating layer 24 may include a portion whose height increases in the direction Z perpendicular to the upper surface 10s of the substrate 10. For example, as the cover insulating layer 24 is closer to the upper insulating layer 18, the upper end portion 24T of the cover insulating layer 24 may be an upper end portion of a portion whose height increases in the direction Z perpendicular to the upper surface 10s of the substrate 10. For example, the cover insulating layer 24 may include an upper surface 24U, an inclined surface 24I, and an upper end portion 24T. The height of the upper end portion 24T of the cover insulating layer 24 may be higher than the height of the upper surface 24U of the cover insulating layer 24 relative to the substrate 10. The inclined surface 24I of the cover insulating layer 24 may extend from the upper surface 24U of the cover insulating layer 24 to the upper end portion 24T of the cover insulating layer 24.

[0109] The stack structure 72 may include a first stack structure 72a and a second stack structure 72b adjacent to each other in the first direction X. The upper insulating layer 18 may include a first upper insulating layer 18a overlapping a central region CR of the first stack structure 72a and a second upper insulating layer 18b overlapping a central region CR of the second stack structure 72b.

[0110] The upper end portion 24T of the capping insulating layer 24 may include a first upper end portion 24T1 and a second upper end portion 24T2 adjacent to the first upper insulating layer 18a. The first upper insulating layer 18a may be located between the first upper end portion 24T1 and the second upper end portion 24T2.

[0111] The second upper end portion 24T2 may be located between the first upper insulating layer 18a and the second upper insulating layer 18b, and may be adjacent to the first upper insulating layer 18a. A height level of the second upper end portion 24T2 may be lower than a height level of the first upper end portion 24T1.

[0112] The capping insulating layer 24 may further include a third upper end portion 24T3 and a fourth upper end portion 24T4 adjacent to the second upper insulating layer 18b. The second upper insulating layer 18b may be located between the third upper end portion 24T3 and the fourth upper end portion 24T4, and the third upper end portion 24T3 may be located between the first upper insulating layer 18a and the second upper insulating layer 18b and may be adjacent to the second upper insulating layer 18b. The height of the third upper end portion 24T3 and the height of the fourth upper end portion 24T4 may be different from each other. The second upper end portion 24T2 and the third upper end portion 24T3 may face each other and may be located at substantially the same height relative to each other. The fourth upper end portion 24T4 may be located at a height higher than the heights of the second upper end portion 24T2 and the third upper end portion 24T3, and may be located at a height lower than the height of the first upper end portion 24T1.

[0113] The memory vertical structure 40 may extend in the vertical direction Z perpendicular to the upper surface 10s of the substrate 10 and have a side surface facing the gate pattern 60 in the central region CR of the stack structure 72 of the protrusion structure PA'. Since the memory vertical structure 40 has been described above in the formation method, its detailed description will be omitted.

[0114] The separation structure 66 may extend in a direction Z perpendicular to the upper surface 10s of the substrate 10. The separation structure 66 may pass through the protrusion structure PA'. Each protrusion structure PA' located between the separation structures 66 may include a central region CR between step regions SR spaced apart from each other. The stacked structure 72 of the protrusion structure PA' and the upper insulating layer 18 may be located between the separation structures 66.

[0115] In some embodiments, the upper end portion 24T may be located at a level higher than that of the upper surface of the upper insulating layer 18 , but the inventive concept is not limited thereto. Fig.18 , one upper end portion 24T may be located at a level higher than the level of the upper surface of the upper insulating layer 18, and the other upper end portion 24T may be located at a level lower than the upper surface of the upper insulating layer 18. Among the upper end portions 24T, the second upper end portion 24T2 and the third upper end portion 24T3 may be located at a level lower than the upper surface of the upper insulating layer 18, and the first upper end portion 24T1 and the fourth upper end portion 24T4 may be located at a level higher than the level of the upper surface of the upper insulating layer 18.

[0116] The flattening degree of the cover insulating layer 24 can be improved by flattening the cover insulating layer 24 using the above method. For example, in the cover insulating layer 24, the flattening degree of the portion other than the protruding structure PA can be improved. Therefore, the overall flattening degree of the planarized cover insulating layer 24 can be improved. A subsequent photolithography process (for example, a process for forming a channel hole ( ) filled with the memory vertical structure 40) using the substrate including the cover insulating layer 24 to improve the flattening degree can be performed. Fig.16 The lithography process 40H) in or the lithography process for forming the separation trench 57) is performed without defects or with minimal defects.

[0117] As described above, since the flattening degree of the cover insulating layer 24 can be improved, the number of stacked gate patterns 60 of the protruding structure PA' can be increased to improve the integration of the semiconductor device. For example, even when the height difference between the upper surface and the lower surface of the protruding structure PA' is increased by increasing the number of stacked gate patterns 60 in the protruding structure PA', a semiconductor device with minimized defects can be formed by providing a method for flattening the cover insulating layer 24. Therefore, the integration of the semiconductor device, the yield and productivity when manufacturing the semiconductor device can be improved.

[0118] According to some embodiments of the present inventive concept, a method of forming a semiconductor device can improve the planarization degree of a capping insulating layer filled between stacked structures. When using this method, the integration of the semiconductor device can be improved, and the productivity when manufacturing the semiconductor device can be improved.

[0119] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A stacking structure, located on a substrate, the stacking structure comprising a stepped region and a central region located between the stepped regions; an upper insulating layer, located on the stacked structure; as well as a covering insulating layer, located on the step region of the stacked structure, wherein the cover insulating layer includes a first upper end portion and a second upper end portion adjacent to the upper insulating layer and opposite to each other, wherein the upper insulating layer is located between the first upper end portion and the second upper end portion, and The first upper portion extends to a first height relative to the base, and the first height is different from a second height of the second upper portion relative to the base.

2. The semiconductor device according to claim 1, wherein The cover insulating layer further includes a surface layer on an upper surface of a main portion of the cover insulating layer.

3. The semiconductor device according to claim 1, wherein At least one of the first height of the first upper end portion and the second height of the second upper end portion is higher than a third height of an upper surface of the upper insulating layer relative to the substrate.

4. The semiconductor device according to claim 1, wherein The first height of the first upper end portion is higher than a third height of an upper surface of the upper insulating layer relative to the substrate, and the second height of the second upper end portion is lower than the third height of the upper surface of the upper insulating layer.

5. The semiconductor device according to claim 1, further comprising: A memory vertical structure extending in a direction perpendicular to the upper surface of the substrate, The stacked structure includes interlayer insulating layers and gate patterns that are alternately stacked, and The memory vertical structure has a side surface facing the gate pattern.

6. A semiconductor device, comprising: stacked structures, located on the substrate and spaced apart from each other, each of the stacked structures comprising a central region and a stepped region surrounding the central region; an upper insulating layer, located on the stacked structure; as well as a covering insulating layer surrounding a side surface of the upper insulating layer, wherein the cover insulating layer is located on the step region of each of the stacked structures and between the stacked structures, wherein the cover insulating layer includes an upper end portion adjacent to the upper insulating layer, wherein the upper end portion of the cover insulating layer includes a first upper end portion and a second upper end portion adjacent to the first upper insulating layer of the upper insulating layer and opposite to each other, and wherein the first upper end portion and the second upper end portion have different heights relative to the substrate, and The first upper insulating layer is located between the first upper end portion and the second upper end portion of the cover insulating layer.

7. The semiconductor device according to claim 6, in, The stack structure includes a first stack structure and a second stack structure adjacent to the first stack structure in a first direction, The upper insulating layer includes the first upper insulating layer overlapping with the first central region of the first stacked structure and the second upper insulating layer overlapping with the second central region of the second stacked structure.

8. The semiconductor device according to claim 7, in, The second upper end portion is located between the first upper insulating layer and the second upper insulating layer and is adjacent to the first upper insulating layer, and A second height of the second upper end portion relative to the substrate is lower than a first height of the first upper end portion relative to the substrate.

9. The semiconductor device according to claim 8, in, The cover insulating layer further includes a third upper end portion and a fourth upper end portion adjacent to the second upper insulating layer, wherein the second upper insulating layer is located between the third upper end portion and the fourth upper end portion, wherein the third upper end portion is adjacent to the second upper insulating layer between the first upper insulating layer and the second upper insulating layer, and Wherein, a third height of the third upper end portion relative to the substrate is different from a fourth height of the fourth upper end portion relative to the substrate.

10. The semiconductor device according to claim 9, wherein: The second height of the second upper end portion is equal to the third height of the third upper end portion.

11. The semiconductor device according to claim 9, wherein The fourth height of the fourth upper end portion is higher than the second height of the second upper end portion and the third height of the third upper end portion, and is lower than the first height of the first upper end portion.

12. The semiconductor device according to claim 6, further comprising a memory vertical structure located on the substrate, in, Each of the stacked structures includes an interlayer insulating layer and a gate pattern, the interlayer insulating layer and the gate pattern are alternately stacked in the central region and extend into the step region to provide a step structure in the step region, and The memory vertical structure extends in a direction perpendicular to an upper surface of the substrate and has a side surface facing the gate pattern.

13. The semiconductor device according to claim 12, wherein: The cover insulating layer further includes an upper surface and an inclined surface, wherein the height of the upper end portion of the cover insulating layer is higher than the height of the upper surface of the cover insulating layer relative to the substrate, and wherein the inclined surface of the cover insulating layer extends from the upper surface of the cover insulating layer to the upper end portion of the cover insulating layer.

14. The semiconductor device according to claim 6, wherein: The cover insulating layer includes a surface layer on an upper surface of a main portion of the cover insulating layer.

15. The semiconductor device according to claim 14, wherein: The surface layer comprises a hardened surface of the cover insulating layer, and The surface layer of the cover insulating layer has a higher hardness or density than other portions of the cover insulating layer.

16. A semiconductor device, comprising: a separation structure, located on a substrate; a protruding structure located between the separation structures, wherein the protruding structure includes a stacked structure and an upper insulating layer located on the stacked structure, and wherein the stacked structure includes a stepped region and a central region located between the stepped regions; and a covering insulating layer, located on the step region and adjacent to the upper insulating layer, wherein the cover insulating layer includes a first upper end portion and a second upper end portion, the first upper end portion and the second upper end portion are adjacent to the upper insulating layer and opposite to each other, and have different heights relative to the substrate, and Wherein, the upper insulating layer is located between the first upper end portion and the second upper end portion.

17. The semiconductor device according to claim 16, in, The cover insulating layer includes a portion whose height in a direction perpendicular to an upper surface of the substrate increases as the cover insulating layer gets closer to the upper insulating layer.

18. The semiconductor device according to claim 16, wherein: The capping insulating layer includes a porous oxide or an oxide having a lower material density than that of the upper insulating layer.

19. The semiconductor device according to claim 16, wherein: The cover insulating layer includes a surface layer on an upper surface of a main portion of the cover insulating layer.

20. The semiconductor device according to claim 16, further comprising: A memory vertical structure extending in a direction perpendicular to the upper surface of the substrate, The stacked structure includes interlayer insulating layers and gate patterns that are alternately stacked, and The memory vertical structure has a side surface facing the gate pattern.

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