Semiconductor structure, semiconductor structure preparation method and use thereof

Abstract

The present invention provides a semiconductor structure, a method for fabricating the semiconductor structure, and its use. The method comprises providing a substrate having at least one first metal structure embedded therein; the top surface of the first metal structure being coplanar with the top surface of the substrate; forming an interlayer dielectric layer on the substrate; forming at least one trench in the interlayer dielectric layer, the trench exposing the top surface of the first metal structure; forming a diffusion barrier layer on the sidewalls of the trench; and forming a second metal structure in the trench having the diffusion barrier layer formed therein, the second metal structure directly bonding to the first metal structure to achieve electrical connection. By removing the diffusion barrier layer at the bottom, the present invention not only reduces interconnect contact resistance and RC delay, but also protects the interlayer dielectric layer and improves via filling quality. Furthermore, an insulating material can be used as the diffusion barrier layer, improving the electrical stability and reliability of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure, a method for preparing the semiconductor structure and applications thereof. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits is getting smaller and smaller, and interconnect resistance has become one of the important factors affecting the electrical performance and reliability of semiconductor devices. The delay of the resistance and capacitance (RC) of the back-end interconnection has shown a significant increase, affecting the performance of semiconductor devices. In order to reduce RC delay, on the one hand, the metal wire has evolved from the original metal aluminum interconnection to metal copper interconnection to reduce the wire resistance R, and on the other hand, the interlayer dielectric material uses Low-k materials with a lower dielectric constant k to reduce the parasitic capacitance C. For example, the existing back-end process often uses metal Cu interconnection with Low-K material interlayer dielectric.

[0003] The byproducts of conventional copper dry etching are not easily volatile. The Damascene process was introduced to fabricate copper interconnects. Its basic process involves etching a via or trench, then filling it with a barrier layer, a copper seed layer, copper electroplating, and CMP, thus avoiding copper etching issues. Later, the dual Damascene process was developed, forming vias and trenches within a dielectric layer. This process also requires filling it with a barrier layer, a copper seed layer, copper electroplating, and CMP.

[0004] Copper easily diffuses into dielectric materials, causing device performance degradation or even failure. Therefore, a copper diffusion barrier must be prepared before copper electroplating. The resistivity of currently commonly used diffusion barrier materials is much higher than that of copper, which increases the interconnect resistance and affects the electrical performance and reliability of semiconductor devices. Moreover, according to the resistance formula R = ρL / S (ρ is the resistivity of the diffusion barrier material, and L is the thickness of the diffusion barrier material), the thicker the diffusion barrier, the greater the resistance value, and the greater the impact on the electrical performance and reliability of semiconductor devices. In addition, in theory, the thinner the diffusion barrier, the lower its resistance value. However, the thinner the diffusion barrier is filled, the following problems arise: ① Localized uneven filling leads to poor barrier effect; ② The large number of defects inside the diffusion barrier and near the Cu contact interface causes its resistivity to increase sharply.

[0005] In addition, Ar ion etching is currently used to thin the barrier layer to reduce resistance. However, high-energy Ar bombardment has low material selectivity and can easily cause: 1) local defects (bombardment and sputtering) on the sidewalls and steps (dual damascene structure) of the diffusion barrier layer, leading to Cu diffusion and reduced device stability; 2) damage to the mechanically poor low-k interlayer dielectric material, even causing stress deformation, which affects subsequent Cu filling and affects the electrical performance stability and reliability of the device.

[0006] Therefore, finding a semiconductor structure and a method for preparing the semiconductor structure that can reduce the metal interconnect contact resistance in the semiconductor structure has become an important technical problem that those skilled in the art need to solve urgently. Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor structure, a method for preparing a semiconductor structure and its use, which are used to solve the problem of poor electrical stability and reliability of semiconductor devices caused by the large contact resistance of the metal interconnect structure in the prior art.

[0008] To achieve the above-mentioned and other related purposes, the present invention provides a method for preparing a semiconductor structure, comprising:

[0009] Providing a substrate, wherein at least one first metal structure is embedded in the substrate; the top surface of the first metal structure and the top surface of the substrate are in the same plane;

[0010] forming an interlayer dielectric layer on the substrate;

[0011] forming at least one trench in the interlayer dielectric layer, wherein the trench exposes a top surface of the first metal structure;

[0012] forming a diffusion barrier layer on the sidewalls of the trench; and

[0013] A second metal structure is formed in the trench with the diffusion barrier layer formed on the sidewall thereof, and the second metal structure is directly bonded to the first metal structure to achieve electrical connection.

[0014] As an improvement to the semiconductor structure manufacturing method of the present invention, the step of forming the diffusion barrier layer on the trench sidewall includes:

[0015] forming a diffusion barrier layer material on an inner wall of the trench;

[0016] The diffusion barrier layer material at the bottom of the trench is removed to expose the top surface of the first metal structure.

[0017] As an improvement to the semiconductor structure manufacturing method of the present invention, a first stop layer is further formed between the substrate and the interlayer dielectric layer, and a second stop layer is further formed on the interlayer dielectric layer; the step of forming the trench includes:

[0018] At least one trench is formed in the second stop layer, the interlayer dielectric layer, and the first stop layer, wherein the trench exposes a top surface of the first metal structure.

[0019] As an improvement to the semiconductor structure manufacturing method of the present invention, the step of forming the diffusion barrier layer on the trench sidewall includes:

[0020] forming a diffusion barrier layer material on an inner wall of the trench;

[0021] The diffusion barrier layer material at the bottom of the trench is removed by etching using the second stop layer as a mask to expose the top surface of the first metal structure.

[0022] As an improvement to the semiconductor structure fabrication method of the present invention, the step of forming the diffusion barrier layer on the sidewall of the trench includes:

[0023] forming a diffusion barrier layer material on an inner wall of the trench;

[0024] Filling a sacrificial layer in the trench formed with the diffusion barrier layer material, wherein the top surface of the sacrificial layer is higher than the top surface height of the diffusion barrier layer material;

[0025] A patterned first photoresist layer is formed on the sacrificial layer, wherein the patterned first photoresist layer has at least one second opening, and the second opening serves as a window for subsequently etching the diffusion barrier layer material located at the bottom of the trench;

[0026] Using the patterned first photoresist layer as a mask, the sacrificial layer and the diffusion barrier layer are sequentially etched downward to expose the top surface of the first metal structure;

[0027] The remaining patterned first photoresist layer and the remaining sacrificial layer are removed.

[0028] As an improvement to the semiconductor structure fabrication method of the present invention, a first stop layer is further formed between the substrate and the interlayer dielectric layer, and a second stop layer is further formed on the interlayer dielectric layer; the fabrication method further comprises:

[0029] forming at least one trench in the second stop layer and the interlayer dielectric layer, wherein the trench exposes the first stop layer;

[0030] forming a diffusion barrier layer material on an inner wall of the trench;

[0031] removing the diffusion barrier layer material at the bottom of the trench to form the diffusion barrier layer on the sidewall of the trench and expose the first stop layer;

[0032] removing the exposed portion of the first stop layer to form a first opening in the first stop layer, wherein the first opening exposes the top surface of the first metal structure; and

[0033] The second metal structure is formed in the trench with the diffusion barrier layer formed on the sidewall and in the first opening. The second metal structure is directly bonded to the first metal structure through the first opening to achieve electrical connection.

[0034] As an improvement to the semiconductor structure preparation method of the present invention, the preparation method further comprises:

[0035] After forming a diffusion barrier layer material on the inner wall of the trench, the diffusion barrier layer material and the first stop layer are sequentially etched downward using the second stop layer and the diffusion barrier layer material on the surface thereof as masks to form the first opening in the first stop layer, wherein the first opening exposes the top surface of the first metal structure;

[0036] The second metal structure is formed in the trench with the diffusion barrier layer formed on the sidewall and in the first opening. The second metal structure is joined to the first metal structure through the first opening to achieve electrical connection.

[0037] As an improvement to the semiconductor structure preparation method of the present invention, the preparation method further comprises:

[0038] Filling the trench having the diffusion barrier layer material formed on the inner wall with a sacrificial layer, wherein the top surface of the sacrificial layer is higher than the top surface height of the diffusion barrier layer material;

[0039] A patterned first photoresist layer is formed on the sacrificial layer, wherein the patterned first photoresist layer has at least one second opening, and the second opening serves as a window for subsequently etching the diffusion barrier layer material located at the bottom of the trench;

[0040] Using the patterned first photoresist layer as a mask, sequentially etching downward the sacrificial layer and the diffusion barrier layer material until the first stop layer is exposed;

[0041] removing the remaining patterned first photoresist layer and the remaining sacrificial layer to expose the diffusion barrier layer material on the second stop layer, and etching downward the first stop layer using the second stop layer and the diffusion barrier layer material on the surface thereof as a mask to form the first opening in the first stop layer, wherein the first opening exposes the top surface of the first metal structure;

[0042] A second metal structure is formed in the trench where the diffusion barrier layer is formed and in the first opening. The second metal structure is directly bonded to the first metal structure through the first opening to achieve electrical connection.

[0043] As an improvement to the semiconductor structure preparation method of the present invention, the preparation method further comprises:

[0044] Filling a sacrificial layer in the groove having the diffusion barrier layer material formed on the inner wall, wherein the top surface of the sacrificial layer is higher than the top surface height of the diffusion barrier layer material;

[0045] A patterned first photoresist layer is formed on the sacrificial layer, wherein the patterned first photoresist layer has at least one second opening, and the second opening serves as a window for subsequently etching the diffusion barrier layer material located at the bottom of the trench;

[0046] Using the patterned first photoresist layer as a mask, the sacrificial layer, the diffusion barrier layer material, and the first stop layer are sequentially etched downward to form the first opening in the first stop layer, wherein the first opening exposes the top surface of the first metal structure;

[0047] removing the remaining patterned first photoresist layer and the remaining sacrificial layer;

[0048] A second metal structure is formed in the trench with the diffusion barrier layer formed on the sidewall thereof, and the second metal structure is joined to the first metal structure through the first opening to achieve electrical connection.

[0049] As an improvement to the semiconductor structure preparation method of the present invention, the thickness of the second stop layer is greater than that of the first stop layer; the thickness of the second stop layer is 200% to 250% of the thickness of the first stop layer.

[0050] As an improvement to the semiconductor structure preparation method of the present invention, the sacrificial layer includes a mask layer and an anti-reflection layer located on the sacrificial layer.

[0051] As an improvement to the semiconductor structure preparation method of the present invention, the method of etching the diffusion barrier layer material includes using a traditional dry etching process or an atomic layer etching process.

[0052] As an improvement to the above-mentioned semiconductor structure preparation method of the present invention, the diffusion barrier layer material includes a conductive diffusion barrier layer material or an insulating diffusion barrier layer material; the conductive diffusion barrier layer material includes one of titanium nitride, tantalum, tungsten nitride, tantalum nitride and ruthenium; the insulating diffusion barrier layer material includes one of silicon nitride and silicon oxynitride.

[0053] As an improvement to the semiconductor structure fabrication method of the present invention, the step of forming the second metal structure in the trench having the diffusion barrier layer formed therein includes:

[0054] filling a second metal material in the trench where the diffusion barrier layer is formed;

[0055] A planarization process is performed on the structure filled with the second metal material to form the second metal structure in the trench where the diffusion barrier layer is formed.

[0056] As an improvement to the semiconductor structure manufacturing method of the present invention, the step of filling the trench having the diffusion barrier layer formed therein with a second metal material includes:

[0057] forming a seed layer on an inner surface of the trench where the diffusion barrier layer is formed;

[0058] filling the second metal material in the trench where the seed layer is formed;

[0059] A planarization process is performed on the structure filled with the second metal material to form the second metal structure in the trench where the diffusion barrier layer is formed.

[0060] As an improvement to the semiconductor structure preparation method of the present invention, the step of removing the remaining patterned first photoresist layer and the remaining sacrificial layer and the step of forming the second metal structure also includes a step of removing the residue and oxide layer on the exposed top surface of the first metal structure.

[0061] To achieve the above-mentioned and other related objectives, the present invention further provides a semiconductor structure comprising:

[0062] a substrate, wherein at least one first metal structure is embedded on a surface of the substrate;

[0063] an interlayer dielectric layer formed on the substrate, wherein at least one trench is formed in the interlayer dielectric layer, and the trench exposes a top surface of the first metal structure;

[0064] a diffusion barrier layer formed on the sidewalls of the trench; and

[0065] A second metal structure is filled in the trench where the diffusion barrier layer is formed, and the second metal structure is directly bonded to the first metal structure to achieve electrical connection.

[0066] As an improvement to the above-mentioned semiconductor structure of the present invention, the semiconductor structure further includes:

[0067] a first stop layer located between the substrate and the interlayer dielectric layer;

[0068] a second stop layer located above the interlayer dielectric layer;

[0069] The trench is formed in the second stop layer, the interlayer dielectric layer and the first stop layer, and exposes the top surface of the first metal structure.

[0070] As an improvement to the above-mentioned semiconductor structure of the present invention, the semiconductor structure further includes:

[0071] a first stop layer located between the substrate and the interlayer dielectric layer, the first stop layer having at least one first opening;

[0072] a second stop layer located above the interlayer dielectric layer;

[0073] The trench is formed in the second stop layer and the interlayer dielectric layer, and the trench exposes the first opening and a portion of the first stop layer located around the first opening;

[0074] The bottom of the diffusion barrier layer is bonded to a portion of the surface of the first stop layer exposed by the trench;

[0075] The second metal structure is filled in the trench where the diffusion barrier layer is formed and in the first opening. The second metal structure is directly bonded to the first metal structure through the first opening to achieve electrical connection.

[0076] As an improvement to the above semiconductor structure of the present invention, the top surface of the second stop layer, the top surface of the diffusion barrier layer, and the top surface of the first metal structure are formed on the same polishing plane.

[0077] As an improvement to the above semiconductor structure of the present invention, the second metal structure includes a main body and a seed layer, and the seed layer is coated on the outer surface of the main body excluding the upper surface.

[0078] As an improvement to the semiconductor structure of the present invention, the substrate includes a third stop layer and an underlying dielectric layer located on the third stop layer; at least one first metal structure is embedded in the underlying dielectric layer and the third stop layer.

[0079] As an improvement to the above-mentioned semiconductor structure of the present invention, the diffusion barrier layer material includes a conductive diffusion barrier layer material or an insulating diffusion barrier layer material; the conductive diffusion barrier layer material includes one of titanium nitride, tantalum, tungsten nitride, tantalum nitride and ruthenium; the insulating diffusion barrier layer material includes one of silicon nitride and silicon oxynitride.

[0080] To achieve the above-mentioned object and other related objects, the present invention also provides the use of the above-mentioned semiconductor structure preparation method, which is applied to single damascene process and dual damascene process.

[0081] By using the present invention, the diffusion barrier layer at the contact part of the metal interconnect structure is removed by etching, which can reduce the interconnection contact resistance between the upper and lower metal structures, thereby reducing RC delay, improving the speed of semiconductor devices and ensuring device reliability;

[0082] By utilizing the present invention, the diffusion barrier material at the bottom of the Damascus structure is removed while protecting the interlayer dielectric layer, thereby improving the through-hole filling quality and thus improving the electrical performance stability and device reliability of the semiconductor device.

[0083] By utilizing the present invention, since the diffusion barrier layer between the first metal structure and the second metal structure is removed, the first metal structure and the second metal structure can be directly joined to achieve electrical connection. When selecting the material of the diffusion barrier layer, it is only necessary to consider its ability to block the diffusion of the second metal material (such as Cu) without considering its conductive properties. Therefore, an insulating material with better ability to block the diffusion of the second metal material (such as Cu) can be selected for the diffusion barrier layer, thereby further improving the electrical performance stability and device reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] Figure 1 Shown is a flow chart of a method for preparing a semiconductor structure according to the present invention.

[0085] Figures 2a-2g It shows a schematic structural diagram of preparing trench A and trench B in the semiconductor structure preparation method of the present invention.

[0086] Figure 3 Shown is a structural schematic diagram of a substrate in the semiconductor structure preparation method of the present invention.

[0087] Figures 4a-4d It is a structural schematic diagram of a first embodiment of a method for manufacturing a semiconductor structure according to the present invention.

[0088] Figures 5a-5f It is a structural schematic diagram of a second embodiment of the method for manufacturing a semiconductor structure of the present invention.

[0089] Figures 6a-6f It is a schematic structural diagram of a third embodiment of the method for manufacturing a semiconductor structure according to the present invention.

[0090] Figures 7a-7c It is a schematic structural diagram of a fourth embodiment of the method for preparing a semiconductor structure according to the present invention.

[0091] Figures 8a-8f FIG. 1 is a schematic structural diagram of a fifth embodiment of a method for fabricating a semiconductor structure according to the present invention.

[0092] Figures 9a-9f It is a structural schematic diagram of a sixth embodiment of the method for manufacturing a semiconductor structure according to the present invention.

[0093] Figure 10-12 Schematic diagrams showing three types of defects when the diffusion barrier layer is thinned using an ion thinning process in the present invention.

[0094] Component number description

[0095] 1 substrate

[0096] 11 First Metal Structure

[0097] 12 Third stop layer

[0098] 13 Bottom dielectric layer

[0099] 2 First stop layer

[0100] 3 interlayer dielectric layer

[0101] 31 Deformation part

[0102] 4 Second stop layer

[0103] 5 Diffusion barrier

[0104] 51 Defect Department

[0105] 50 Diffusion barrier material

[0106] 6 Second Metal Structure

[0107] 61 seed layer

[0108] 62 Main body

[0109] 71 First Sacrificial Layer

[0110] 72 Second Sacrificial Layer

[0111] 81 first anti-reflection layer

[0112] 82 second anti-reflection layer

[0113] 91 third photoresist layer

[0114] 92 second photoresist layer

[0115] 93 first photoresist layer DETAILED DESCRIPTION

[0116] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0117] See also Figures 1-12It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0118] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0119] Figure 1 1 is a flow chart of a method for preparing a semiconductor structure according to the present invention, wherein the method comprises the following steps:

[0120] Execute step S10, as Figure 2a As shown, a substrate 1 is provided, in which at least one first metal structure 11 is embedded; the top surface of the first metal structure 11 is coplanar with the top surface of the substrate 1. For example, the substrate 1 may be a general semiconductor structure after completing the front-end of line (FEOL) process, and the first metal structure 11 includes an electrical connection terminal (e.g., a gate terminal of a transistor device) for electrical connection to the outside, or a contact portion formed on the electrical connection terminal (e.g., a contact portion formed on the source / drain terminal of a transistor device).

[0121] In one embodiment, if Figure 3 As shown, the substrate 1 also includes a third stop layer 12 and an underlying dielectric layer 13 located on the third stop layer 12 ; at least one first metal structure 11 is embedded in the underlying dielectric layer 13 and the third stop layer 12 .

[0122] Those skilled in the art can obtain the image 2 or the image 3 in a variety of ways through the front-end process. Figure 3 The substrate 1 shown here. Here, the specific production of the substrate 1 is not repeated.

[0123] like Figures 2a-2g As shown, execute step S20, as shown Figures 2a-2g As shown, an interlayer dielectric layer 3 is formed on the substrate 1, and then step S30 is performed to form at least one trench in the interlayer dielectric layer 3, wherein the trench exposes the top surface of the first metal structure 11. The trench includes Figure 2b As shown in the figure, a type A groove (hereinafter referred to as groove A) is formed by a one-step photolithography process and Figure 2gThe type B trench (hereinafter referred to as trench B) with a step shape is formed by two or more steps of photolithography process.

[0124] The steps of forming the trench A include:

[0125] like Figure 2a-2b As shown, first, a first stop layer 2, an interlayer dielectric layer 3, a second stop layer 4, and a third photoresist layer 91 are sequentially formed on the substrate 1. Next, the third photoresist layer 91 is patterned to form an opening therein. Next, the second stop layer 4 and the interlayer dielectric layer 3 are sequentially etched downward using the patterned third photoresist layer 91 as a mask to form a trench A therein. It should be noted that the first stop layer 2 below the trench A will be opened in a subsequent step to form a first opening, thereby exposing the top surface of the first metal structure 11 below the first stop layer 2.

[0126] The first stop layer 2 and the second stop layer 4 can be made of, for example, silicon nitride (Si3N4) or silicon carbide. Of course, other suitable materials can also be used, without limitation. As an example, silicon nitride (Si3N4) can be used.

[0127] In order to reduce the distributed capacitance between layers and the delay time of signal transmission, the interlayer dielectric layer 3 can adopt low-k dielectric material (low-k material). Low-k dielectric material refers to a dielectric material with a dielectric constant lower than SiO2, and its dielectric constant range is between the dielectric constant of air and the dielectric constant of SiO2. The low-k dielectric materials that can be used include but are not limited to SiF, SiOC, polyparaphenylene dimethyl ether, HSQ and dry gel. For low-k dielectrics, not only is its k value required to be as low as possible, but it should also meet the following conditions: good thermal stability, high mechanical strength, high thermal conductivity, good dimensional stability, easy patterning and corrosion, and compatible with IC processes, such as post-step cleaning, etching, CMP, heat treatment and other processes.

[0128] It should be noted that in order to effectively reduce line distortion and increased surface roughness of the patterned photoresist layer caused by factors such as light reflection and standing waves during the photolithography process, an anti-reflection layer (not shown) may be formed between the second stop layer 4 and the third photoresist layer 91. In one embodiment, the second stop layer 4 may also serve as an anti-reflection layer.

[0129] like Figures 2a-2g As shown, the steps of forming the trench B include, first, Figure 2a and 2b As shown, the step of forming the trench A is performed; secondly, as shown Figure 2cAs shown, the surface of the structure with the groove A (the surface of the second stop layer 4) and the groove A are filled with a first sacrificial layer 71 material, and a planarization process (such as chemical mechanical polishing CMP) is performed to form a first sacrificial layer 71; again, as shown Figure 2d As shown, a second photoresist layer 92 is formed on the first sacrificial layer 71, and the second photoresist layer 92 is patterned to form an opening in the second photoresist layer 92. The size of the opening in the second photoresist layer 92 is larger than the size of the groove A and its projection includes the groove A. Then, as shown in FIG. Figure 2e and 2f As shown, the second sacrificial layer 72, the second stop layer 4 and a portion of the thickness of the interlayer dielectric layer 3 are sequentially etched downwards using the patterned second photoresist layer 92 as a mask; finally, as shown Figure 2g As shown, excess second photoresist layer 92 material and excess first sacrificial layer 71 material are removed to form a stepped trench B. It should be noted that the first stop layer 2 below the trench B will also be opened in a subsequent step to form a first opening to expose the top surface of the first metal structure 11 below the first stop layer 2.

[0130] It should be noted that if Figure 2c As shown, in order to effectively reduce the problems of line deformation and increased surface roughness of the patterned photoresist layer caused by factors such as light reflection and standing waves in the photolithography process, a first anti-reflection layer 81 is further formed between the first sacrificial layer 71 and the second photoresist layer 92.

[0131] It should be noted that other non-photolithography processes such as implantation and laser etching may also be used to prepare the groove structure, without limitation thereto.

[0132] Step S40 is executed to form a diffusion barrier layer 5 on the sidewall of the trench. According to the order of forming the first opening in the first stop layer 2 and the diffusion barrier layer 5, there are two implementation methods.

[0133] In the first embodiment, first, open Figure 2b / Figure 2g A portion of the first stop layer 2 below the middle trench A / trench B is used to form a first opening in the first stop layer 2. The first opening and the trench A / trench B together serve as a groove for forming a diffusion barrier layer 5 to expose the top surface of the first metal structure 11 below the first stop layer 2. Then, a diffusion barrier layer material 50 is formed on the inner wall of the trench. Finally, the diffusion barrier layer material 50 located at the bottom of the trench is removed to reveal the top surface of the first metal structure 11.

[0134] In one embodiment, the step of forming the diffusion barrier layer 5 on the sidewall of the trench includes: first, opening Figure 2bThe first stop layer 2 portion below the trench A is formed to form a first opening in the first stop layer 2. The first opening and the trench A serve together as a trench for forming the diffusion barrier layer 5 to expose the first metal structure 11 below the first stop layer 2, forming a structure as shown in FIG. Figure 4a The structure shown; secondly, Figure 4b As shown, Figure 4a The inner wall of the trench forms a diffusion barrier material 50; again, as Figure 4c As shown, the diffusion barrier layer material 50 at the bottom of the trench is etched away using the second stop layer 4 as a mask, exposing the top surface of the first metal structure 11. To prevent the second stop layer 4 from being etched through, thereby exposing and damaging the underlying interlayer dielectric layer 3, the thickness of the second stop layer 4 is greater than that of the first stop layer 2; the thickness of the second stop layer 4 is 200% to 250% of the thickness of the first stop layer 2.

[0135] In another embodiment, the step of forming the diffusion barrier layer 5 on the sidewall of the trench includes: first, opening the first stop layer 2 below the trench B in FIG. 2g to form a first opening in the first stop layer 2, wherein the first opening and the trench B together serve as a trench for forming the diffusion barrier layer 5 to expose the first metal structure 11 below the first stop layer 2, forming a first metal structure 11 below the first stop layer 2. Figure 5a The structure shown; secondly, Figure 5b As shown in Figure 5a The inner wall of the trench is shown to form a diffusion barrier material 50; again, as shown Figure 5c As shown, a second sacrificial layer 72 is filled in the trench formed with the diffusion barrier material 50, and the top surface of the second sacrificial layer 72 is higher than the top surface height of the diffusion barrier material 50; Figure 5c As shown, a patterned first photoresist layer 93 is formed on the second sacrificial layer 72. The patterned first photoresist layer 93 has at least one second opening. The second opening serves as a window for subsequently etching the diffusion barrier layer material 50 at the bottom of the trench. Figure 5d As shown, the second sacrificial layer 72 and the diffusion barrier layer material 50 are sequentially etched downward using the patterned photoresist layer as a mask to expose the top surface of the first metal structure 11; finally, as shown Figure 5fAs shown, the remaining patterned photoresist layer and the remaining second sacrificial layer 72 are removed. Since oxygen plasma is generally used to remove the remaining patterned photoresist layer and the remaining second sacrificial layer 72, the top surface of the first metal structure 11 exposed at the bottom of the trench will be oxidized, and residues will remain. Therefore, before forming the second metal structure 6, it is necessary to remove the residues and the oxide layer on the top surface of the exposed first metal structure 11. As an example, Ar plasma bombardment can be used to remove the surface residues and the oxide layer on the top surface of the first metal structure 11. Of course, other suitable plasma treatments can also be used, and are not limited to this. At the same time, H2 is introduced to prevent the top surface of the first metal structure 11 from being oxidized.

[0136] In another embodiment, the step of forming the diffusion barrier layer 5 on the sidewall of the trench includes: first, opening the first stop layer 2 below the trench A in FIG. 2 b to form a first opening in the first stop layer 2, the first opening and the trench A together serving as a trench for forming the diffusion barrier layer 5 to expose the first metal structure 11 below the first stop layer 2, forming a first metal structure 11 below the first stop layer 2. Figure 6a The structure shown; secondly, Figure 6b As shown in Figure 6a The inner wall of the trench is shown to form a diffusion barrier material 50; again, as shown Figure 6b As shown, a second sacrificial layer 72 is filled in the trench formed with the diffusion barrier material 50, and the top surface of the second sacrificial layer 72 is higher than the top surface height of the diffusion barrier material 50; Figure 6b As shown, a patterned first photoresist layer 93 is formed on the second sacrificial layer 72. The patterned first photoresist layer 93 has at least one second opening. The second opening serves as a window for subsequently etching the diffusion barrier layer material 50 at the bottom of the trench. Figure 6d As shown, the second sacrificial layer 72 and the diffusion barrier layer material 50 are sequentially etched downward using the patterned photoresist layer as a mask to expose the top surface of the first metal structure 11; finally, as shown Figure 6f As shown, the remaining patterned photoresist layer and the remaining second sacrificial layer 72 are removed. Since oxygen plasma is generally used to remove the remaining patterned photoresist layer and the remaining second sacrificial layer 72, the top surface of the first metal structure 11 exposed at the bottom of the trench will be oxidized, and residues will remain. Therefore, before forming the second metal structure 6, it is necessary to remove the residues and the oxide layer on the top surface of the exposed first metal structure 11. As an example, Ar plasma bombardment can be used to remove the surface residues and the oxide layer on the top surface of the first metal structure 11. Of course, other suitable plasma treatments can also be used, and are not limited to this. At the same time, H2 is introduced to prevent the top surface of the first metal structure 11 from being oxidized.

[0137] It should be noted that if Figure 6c As shown, in order to effectively reduce the problems of line deformation and increased surface roughness of the patterned photoresist layer caused by factors such as light reflection and standing waves in the photolithography process, which affect the accurate transfer of the pattern, a second anti-reflection layer 82 can be formed between the second sacrificial layer 72 and the first photoresist layer 93.

[0138] In the first embodiment, it is necessary to etch open the first stop layer 2 first. During the etching process of the first stop layer 2, this may cause damage and deformation of the interlayer dielectric layer 3 exposed by the groove, affecting the subsequent filling of the second metal structure, and further affecting the electrical performance stability and reliability of the finally formed device.

[0139] To this end, the present invention discloses another embodiment, comprising the following steps: first, as Figure 2b As shown in FIG. 2g, the first trench A / trench B serves as a trench for forming a diffusion barrier layer 5, and a diffusion barrier material 50 is formed on the inner wall of trench A / trench B. Next, the diffusion barrier material 50 at the bottom of trench A / trench B is removed to form the diffusion barrier layer 5 on the sidewalls of trench A / trench B, exposing the first stop layer 2. Finally, the exposed portion of the first stop layer 2 is removed to form a first opening in the first stop layer 2, exposing the top surface of the first metal structure 11. This embodiment, utilizing the protection of the diffusion barrier layer, can prevent damage and deformation of the interlayer dielectric layer 3 when opening the first stop layer 2.

[0140] In one embodiment, the step of forming the diffusion barrier layer 5 on the sidewall of the trench includes: first, Figure 7a As shown, in Figure 2b The inner wall of the middle trench A forms a diffusion barrier material 50; secondly, as Figure 7b As shown, after forming a diffusion barrier material 50 on the inner wall of the trench A, the diffusion barrier material 50 at the bottom of the trench A and the first stop layer 2 are sequentially etched downward using the second stop layer 4 and the diffusion barrier material 50 on its surface as a mask, thereby forming a first opening in the first stop layer 2. The first opening exposes the top surface of the first metal structure 11. To prevent the second stop layer 4 from being etched through, thereby exposing and damaging the underlying interlayer dielectric layer 3, the thickness of the second stop layer 4 is greater than that of the first stop layer 2; the thickness of the second stop layer 4 is 200% to 250% of the thickness of the first stop layer 2.

[0141] In another embodiment, the step of forming the diffusion barrier layer 5 on the sidewall of the trench includes: first, Figure 8a As shown, in Figure 2b The inner wall of the middle trench A forms a diffusion barrier material 50; secondly, as Figure 8b As shown, a second sacrificial layer 72 is filled in the groove A with the diffusion barrier layer material 50 formed on the inner wall, and the top surface of the second sacrificial layer 72 is higher than the top surface height of the diffusion barrier layer material 50; again, as shown Figure 8b As shown, a patterned first photoresist layer 93 is formed on the second sacrificial layer 72. The patterned first photoresist layer 93 has at least one second opening, and the second opening serves as a window for subsequently etching the diffusion barrier layer material 50 at the bottom of the trench A. Figure 8c As shown, the second sacrificial layer 72 and the diffusion barrier layer material 50 are sequentially etched downward using the patterned photoresist layer as a mask until the first stop layer 2 is exposed; then, as shown Figure 8d As shown, the remaining patterned photoresist layer and the remaining second sacrificial layer 72 are removed to expose the diffusion barrier layer material 50 located on the second stop layer 4; finally, as shown in Figure 8e, the first stop layer 2 is etched downward using the second stop layer 4 and the diffusion barrier layer material 50 located on its surface as a mask to form the first opening in the first stop layer 2, and the first opening reveals the top surface of the first metal structure 11. In order to prevent the second stop layer 4 from being etched through, thereby exposing and damaging the interlayer dielectric layer 3 below it, the thickness of the second stop layer 4 is greater than the thickness of the first stop layer 2; the thickness of the second stop layer 4 is 200% to 250% of the thickness of the first stop layer 2.

[0142] In another embodiment, the step of forming the diffusion barrier layer 5 on the sidewall of the trench includes: first, Figure 9a As shown, in Figure 2g The inner wall of the trench B of the structure shown is formed with a diffusion barrier material 50; secondly, as shown in FIG. Figure 9b As shown, a second sacrificial layer 72 is filled in the groove B with the diffusion barrier layer material 50 formed on the inner wall. The top surface of the second sacrificial layer 72 is higher than the top surface height of the diffusion barrier layer material 50. Again, as shown Figure 9b As shown, a patterned first photoresist layer 93 is formed on the second sacrificial layer 72. The patterned first photoresist layer 93 has at least one second opening, and the second opening serves as a window for subsequently etching the diffusion barrier layer material 50 at the bottom of the trench B. Figure 9c 9d, the second sacrificial layer 72, the diffusion barrier layer material 50 and the first stop layer 2 are sequentially etched downward using the patterned first photoresist layer 93 as a mask to form the first opening in the first stop layer 2, wherein the first opening exposes the top surface of the first metal structure 11; finally, as shown in Figure 9e As shown, the remaining patterned first photoresist layer 93 and the remaining second sacrificial layer 72 are removed. Since oxygen plasma is generally used to remove the remaining patterned first photoresist layer 93 and the remaining second sacrificial layer 72, the top surface of the first metal structure 11 exposed at the bottom of the first opening will be oxidized, and residues will remain. Therefore, before forming the second metal structure 6, it is necessary to remove the residues and the oxide layer on the exposed top surface of the first metal structure 11. As an example, Ar plasma bombardment can be used to remove the surface residues and the oxide layer on the top surface of the first metal structure 11. Of course, other suitable plasma treatments can also be used, and are not limited to this. H2 is also introduced to prevent oxidation of the top surface of the first metal structure 11.

[0143] It should be noted that in order to effectively reduce the problems of line deformation and increased surface roughness of the patterned photoresist layer caused by factors such as light reflection and standing waves in the photolithography process, which affect the transfer of the pattern, a second anti-reflection layer 82 can be formed between the second sacrificial layer 72 and the second photoresist layer 92.

[0144] It should be noted that the method for forming the diffusion barrier layer 5 on the inner wall of the trench may adopt physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable processes, but is not limited thereto.

[0145] It should be noted that the method of etching the diffusion barrier layer material 50 includes using a traditional dry etching process or an atomic layer etching process, and other processes such as laser thinning that can achieve this purpose may also be used, without limitation.

[0146] It should be noted that since the bottom portion of the diffusion barrier layer material 50 can be removed, the barrier layer material selection only needs to consider its ability to block the diffusion of the second metal material (e.g., copper), without considering its conductive properties. Therefore, the diffusion barrier layer material 50 can be either a conductive diffusion barrier material 50 or an insulating diffusion barrier material 50 that has a better ability to block the diffusion of the second metal material (e.g., copper). The conductive diffusion barrier layer material 50 includes one of titanium nitride, tungsten nitride, tantalum, tantalum nitride, and ruthenium; the insulating diffusion barrier layer material 50 includes one of silicon nitride and silicon oxynitride.

[0147] It should be noted that the method of the present invention can be used to remove the diffusion barrier layer 5 at the bottom, which can avoid the situation where the high-energy Ar bombardment will have poor selectivity for the material when the diffusion barrier layer 5 at the bottom is thinned and removed by the ion thinning process, resulting in local defects on the sidewalls of the diffusion barrier layer 5 and the interlayer dielectric layer 3, thereby affecting the electrical stability and reliability of the device. Common defects of using the ion thinning process to remove the diffusion barrier layer 5 at the bottom include Figure 10-12As shown, for example Figure 10-11 As shown in FIG. 1 , a defect 51 is generated at the sidewall or step of the diffusion barrier layer 5, causing diffusion of metal (eg, Cu), or as shown in FIG. Figure 12 As shown, a deformed portion 31 is generated in the interlayer dielectric layer 3 , which affects the subsequent filling of the second metal structure 6 , thereby affecting the electrical stability and reliability of the device.

[0148] Execute step S50 to form a second metal structure 6 in the trench having the diffusion barrier layer 5 formed on the sidewall. The second metal structure 6 is directly bonded to the first metal structure 11 to achieve electrical connection. The second metal structure 6 may include interconnecting wires or conductive plugs.

[0149] The step of forming the second metal structure 6 in the trench (trench A / trench B and the first opening) with the diffusion barrier layer 5 formed on the sidewall in step S40 includes: filling the trench (trench A / trench B and the first opening) with the diffusion barrier layer 5 formed with a second metal material; performing a planarization process on the structure filled with the second metal material to form the second metal structure 6 in the trench (trench A / trench B and the first opening) with the diffusion barrier layer 5 formed, and forming the following steps: Figure 4d , Figure 5f , Figure 6f , Figure 7c , Figure 8f and Figure 9f One of the structures shown.

[0150] The step of filling the second metal material in the trench (trench A / trench B and the first opening) with the diffusion barrier layer 5 formed on the sidewall in step S40 further includes: forming a seed layer 61 on the inner surface of the trench (trench A / trench B and the first opening) with the diffusion barrier layer 5 formed; filling the second metal material in the trench (trench A / trench B and the first opening) with the seed layer 61 formed; and flattening the structure filled with the second metal material to form a second metal structure 6 in the trench with the diffusion barrier layer 5 formed, the second metal structure 6 including a main body 62 and a seed layer 61, the seed layer 61 being coated on the outer surface of the main body 62 excluding the upper surface, forming a structure as shown in FIG. Figure 4d , Figure 5f , Figure 6f , Figure 7c , Figure 8f and Figure 9f One of the structures shown.

[0151] The material of the second metal structure 6 may include, but is not limited to, metals such as Cu or Al.

[0152] It should be noted that the semiconductor structure preparation method of the present invention is also applicable to be repeated multiple times to form a three-layer or even more metal interconnection structure.

[0153] It should be noted that the semiconductor structure preparation method of the present invention can be used for the back-end copper interconnection process of dynamic random access memory to reduce the contact resistance of the copper interconnection.

[0154] It should be noted that the semiconductor structure preparation method is applicable to single damascene process and dual damascene process.

[0155] like Figure 4d , 5f, 6f, 7c, 8f or 9f, the present invention also provides a semiconductor structure prepared using the above-mentioned semiconductor structure preparation method, comprising: a substrate 1, wherein at least one first metal structure 11 is embedded in the surface of the substrate 1; an interlayer dielectric layer 3 formed on the substrate 1, wherein at least one trench is formed in the interlayer dielectric layer 3, wherein the trench exposes the top surface of the first metal structure 11; a diffusion barrier layer 5 formed on the sidewall of the trench; and a second metal structure 6 filling the trench in which the diffusion barrier layer 5 is formed, wherein the second metal structure 6 is directly bonded to the first metal structure 11 to achieve electrical connection. The second metal structure 6 includes a main body 62 and a seed layer 61, wherein the seed layer 61 is disposed on the outer surface of the main body 62, excluding the upper surface.

[0156] like Figure 4d , as shown in 5f or 6f, the semiconductor structure also includes a first stop layer 2 located between the substrate 1 and the interlayer dielectric layer 3; a second stop layer 4 located above the interlayer dielectric layer 3; the groove is formed in the second stop layer 4, the interlayer dielectric layer 3 and the first stop layer 2, and the top surface of the first metal structure 11 is exposed.

[0157] like Figure 7c8f or 9f, the semiconductor structure further includes: a first stop layer 2 located between the substrate 1 and the interlayer dielectric layer 3, the first stop layer 2 having at least one first opening; a second stop layer 4 located above the interlayer dielectric layer 3; a trench formed in the second stop layer 4 and the interlayer dielectric layer 3, the trench exposing the first opening and a portion of the first stop layer 2 located around the first opening; a bottom portion of the diffusion barrier layer 5 adjoining the portion of the surface of the first stop layer 2 exposed by the trench; and a second metal structure 6 filled in the trench and the first opening formed with the diffusion barrier layer 5, the second metal structure 6 directly adjoining the first metal structure 11 through the first opening to achieve electrical connection. The top surfaces of the second stop layer 4, the diffusion barrier layer 5, and the first metal structure 11 are formed on the same polished surface.

[0158] like Figure 3 As shown, the substrate 1 also includes a third stop layer 12 and an underlying dielectric layer 13 located on the third stop layer 12 ; at least one first metal structure 11 is embedded in the underlying dielectric layer 13 and the third stop layer 12 .

[0159] It should be noted that since the bottom portion of the diffusion barrier layer material 50 can be removed, the barrier layer material selection only needs to consider its ability to block the diffusion of the second metal material (e.g., copper), without considering its conductive properties. Therefore, the diffusion barrier layer material 50 can be either a conductive diffusion barrier material 50 or an insulating diffusion barrier material 50 that has a better ability to block the diffusion of the second metal material (e.g., copper). The conductive diffusion barrier layer material 50 includes one of titanium nitride, tungsten nitride, tantalum, tantalum nitride, and ruthenium; the insulating diffusion barrier layer material 50 includes one of silicon nitride and silicon oxynitride.

[0160] The concept of the present invention will be further described below with specific embodiments. It should be noted that in embodiments 1-7, the substrate 1 has been described as an example using the structure shown in FIG. 2 . Of course, the substrate 1 may also be described as Figure 3 The structure shown.

[0161] Example 1

[0162] like Figure 2a-2b , as shown in 4a-4d, this embodiment provides a method for preparing a semiconductor structure, which specifically includes the following steps.

[0163] First, if Figure 2aAs shown, a substrate 1 is provided, which includes a bottom dielectric layer 13 and a first metal structure 11, wherein the first metal structure 11 is embedded in the bottom dielectric layer 13, and the top surface of the first metal structure 11 is in the same plane as the top surface of the bottom dielectric layer 13; a first stop layer 2, an interlayer dielectric layer 3, a second stop layer 4, and a third photoresist layer 91 are formed on the substrate 1 from bottom to top; as an example, the thickness of the first stop layer 2 is between 40-70nm, the thickness of the interlayer dielectric layer 3 is between 250nm-300nm, and the thickness of the second stop layer 4 is 200% to 250% of the thickness of the first stop layer 2, so as to prevent the second stop layer 4 from being etched through when the second stop layer 4 is used as a mask to remove the bottom of the first stop layer 2 and the diffusion barrier layer 5, thereby exposing and damaging the interlayer dielectric layer 3 below it.

[0164] Secondly, if Figure 2b As shown, the second stop layer 4 and the interlayer dielectric layer 3 are sequentially etched downward using a photolithography process, and the etching stops at the surface of the first stop layer 2 to form at least one trench A in the second stop layer 4 and the interlayer dielectric layer 3 .

[0165] Again, as Figure 4a As shown, the first stop layer 2 is etched using the etched second stop layer 4 as a mask to form a through hole (first opening) in the first stop layer 2, exposing the top surface of the first metal structure 11, and the through hole and the trench A serve as grooves for forming the diffusion barrier layer 5.

[0166] From then on, Figure 4b As shown, a diffusion barrier layer material 50 is formed on the inner wall of the trench by using PVD, CVD or ALD process. The diffusion barrier layer material 50 can be selected from one of Si3N4, WN, TiN, Ta, TaN, and Ru, for example, Ta can be selected.

[0167] Then, if Figure 4c As shown, the diffusion barrier layer 5 at the bottom of the trench (trench A and the first opening) is removed by conventional dry etching or atomic layer etching ALE process, and the diffusion barrier layer 5 on the sidewall of the trench (trench A and the first opening) is retained.

[0168] As an example, for example, when the barrier layer is Ta, the atomic layer etching ALE method is used to precisely control the dimensional accuracy. The atomic layer etching process steps for removing the bottom of the diffusion barrier layer 5 include: placing the structure formed with the diffusion barrier layer material 50 in an atomic layer etching chamber; introducing Cl2 into the atomic layer etching chamber, and the etching gas molecules Cl2 are adsorbed on the surface of the diffusion barrier layer material 50, and Cl2 reacts with the diffusion barrier layer material 50 to generate a compound; using a vacuum pump to remove excess Cl2; irradiating the atomic layer etching chamber with an Ar atomic beam, and using the Ar atomic beam to decompose the compound generated by the reaction adsorbed on the surface of the diffusion barrier layer material 50; and using a vacuum pump to remove the compound. The chamber temperature is 50°C to 150°C, the chamber pressure is 0.3mtorr to 0.5mtorr, and the irradiation dose of the Ar atomic beam is 7×10 15 atom / cm 2 to 8×10 15 atom / cm 2 The above process is repeated until the diffusion barrier layer material 50 at the bottom of the trench is completely removed, exposing the top surface of the first metal structure 11 .

[0169] The reaction equation of Ta and Cl2 is: Ta+Cl2→TaCl x +Cl *

[0170] Finally, if Figure 4d As shown, a Cu seed layer 61 is deposited on the inner wall of the trench (trench A and the first opening) where the diffusion barrier layer 5 is formed, and Cu is electroplated to form a Cu-filled through-hole structure (second metal structure 6). Of course, chemical plating and other feasible processes can also be used to form the second metal structure 6, without limitation. The chemical mechanical polishing (CMP) process stops at layer 230 to form the following. Figure 4d In the structure shown, the sidewalls of the second metal structure 6 are in contact with the diffusion barrier layer 5 .

[0171] Example 2

[0172] like Figures 2a-2g , as shown in 5a-5f, this embodiment provides a method for preparing a semiconductor structure, which specifically includes the following steps.

[0173] First, provide Figure 2g For the structure shown, please refer to the above description for the detailed formation process, which will not be repeated here. The thickness of the interlayer dielectric layer 3 can be 500-550nm.

[0174] Secondly, if Figure 5a As shown, open Figure 2gThe first stop layer 2 is partially below the trench B to form a first opening in the first stop layer 2 . The first opening and the trench B together serve as a trench for forming the diffusion barrier layer 5 to expose the first metal structure 11 below the first stop layer 2 .

[0175] Again, as Figure 5b As shown, PVD, CVD or ALD process is used in Figure 5a A layer of diffusion barrier material 50 is formed on the inner wall of the trench (trench B and the first opening) shown. The diffusion barrier material 50 can be selected from one of Si3N4, WN, TiN, Ta, TaN, and Ru, for example, Ta.

[0176] From then on, Figure 5c As shown, a second sacrificial layer 72 is filled in the grooves (trench B and the first opening) in which the diffusion barrier layer material 50 is formed, and the top surface of the second sacrificial layer 72 is higher than the top surface height of the diffusion barrier layer material 50; a patterned first photoresist layer 93 is formed on the second sacrificial layer 72, and the patterned first photoresist layer 93 has at least one second opening, which serves as a window for subsequent etching of the diffusion barrier layer material 50 located at the bottom of the grooves (trench B and the first opening).

[0177] Then, if Figure 5d As shown, the second sacrificial layer 72 and the diffusion barrier layer material 50 are sequentially etched downward using the patterned photoresist layer as a mask, exposing the top surface of the first metal structure 11. As an example, the second anti-reflective layer 82 is etched first (the etching gas includes CF4), followed by the second sacrificial layer 72 (the etching gas includes CO), and finally the diffusion barrier layer material 50Ta is etched. As an example, the diffusion barrier layer material 50Ta can be etched using a conventional RIE method, such as a BCl3 / Cl2 etching gas, which generates TaCl5 and is then extracted, with the chemical formula being Ta+Cl2→TaCl5+Cl*. It should be noted that the diffusion barrier layer material 50Ta can also be removed using the ALE method (Cl2 / Ar) described in Example 1.

[0178] Then, if Figure 5eAs shown, the remaining patterned photoresist layer and the remaining second sacrificial layer 72 are removed. Since oxygen plasma is generally used to remove the remaining patterned photoresist layer and the remaining second sacrificial layer 72, the top surface of the first metal structure 11 (such as Cu or Al) exposed at the bottom of the trench (trench B and the first opening) will be oxidized, and residues will remain. Therefore, before forming the second metal structure 6, it is necessary to remove the residues and the oxide layer on the top surface of the exposed first metal structure 11. As an example, Ar plasma bombardment can be used to remove the surface residues and the oxide layer on the top surface of the first metal structure 11. Of course, other suitable plasma treatments can also be used, and are not limited to this. At the same time, H2 is introduced to prevent the top surface of the first metal structure 11 from being oxidized.

[0179] Finally, if Figure 5f , a second metal structure 6 is formed in the trench (trench B and the first opening) where the diffusion barrier layer 5 is formed. As an example, a Cu seed layer 61 is deposited on the inner wall of the trench where the diffusion barrier layer 5 is formed, and Cu is electroplated to form a Cu-filled through-hole structure. Of course, chemical plating and other feasible processes can also be used to form the second metal structure 6, without limitation. The chemical mechanical polishing (CMP) process stops at layer 230 to form a Cu-filled through-hole structure. Figure 5f In the structure shown, the sidewalls of the second metal structure 6 are in contact with the diffusion barrier layer 5 .

[0180] Example 3

[0181] like Figure 2a-2b , as shown in 6a-6f, this embodiment provides a method for preparing a semiconductor structure, which specifically includes the following steps.

[0182] First, provide Figure 2b For the structure shown, please refer to the previous description for the detailed formation process, which will not be repeated here.

[0183] Secondly, if Figure 6a As shown, open Figure 2b The first stop layer 2 is partially below the trench A to form a first opening in the first stop layer 2 . The first opening and the trench A together serve as a trench for forming the diffusion barrier layer 5 to expose the first metal structure 11 below the first stop layer 2 .

[0184] Again, as Figure 6b As shown, PVD, CVD or ALD process is used in Figure 6a A layer of diffusion barrier material 50 is formed on the inner wall of the trench (trench A and the first opening) shown. The diffusion barrier material 50 can be selected from one of Si3N4, WN, TiN, Ta, TaN, and Ru, for example, Ta.

[0185] From then on, Figure 6c As shown, a second sacrificial layer 72 is filled in the grooves (grooves A and the first opening) in which the diffusion barrier layer material 50 is formed, and the top surface of the second sacrificial layer 72 is higher than the top surface height of the diffusion barrier layer material 50; a patterned first photoresist layer 93 is formed on the second sacrificial layer 72, and the patterned first photoresist layer 93 has at least one second opening, which serves as a window for subsequent etching of the diffusion barrier layer material 50 located at the bottom of the grooves (grooves A and the first opening).

[0186] Then, if Figure 6d As shown, the second sacrificial layer 72 and the diffusion barrier layer material 50 are sequentially etched downward using the patterned photoresist layer as a mask to expose the top surface of the first metal structure 11. As an example, the second anti-reflective coating is etched first (the etching gas includes CF4), then the amorphous carbon second sacrificial layer 72 is etched (the etching gas includes CO), and finally the diffusion barrier layer material 50Ta is etched. As an example, the diffusion barrier layer material 50Ta is etched using a conventional RIE method, such as a BCl3 / Cl2 etching gas. TaCl5 is generated and then extracted, with the chemical formula being Ta+Cl2→TaCl5+Cl*. It should be noted that the diffusion barrier layer material 50Ta can also be removed using the ALE method (Cl2 / Ar) described in Example 1.

[0187] Then, if Figure 6e As shown, the remaining patterned photoresist layer and the remaining second sacrificial layer 72 are removed. Since oxygen plasma is generally used to remove the remaining patterned photoresist layer and the remaining second sacrificial layer 72, the top surface of the first metal structure 11 (such as Cu or Al) exposed at the bottom of the trench (trench A and the first opening) will be oxidized, and residues will remain. Therefore, before forming the second metal structure 6, it is necessary to remove the residues and the oxide layer on the top surface of the exposed first metal structure 11. As an example, Ar plasma bombardment can be used to remove the surface residues and the oxide layer on the top surface of the first metal structure 11. Of course, other suitable plasma treatments can also be used, and are not limited to this. At the same time, H2 is introduced to prevent the top surface of the first metal structure 11 from being oxidized.

[0188] Finally, if Figure 6f , a second metal structure 6 is formed in the trench (trench A and the first opening) where the diffusion barrier layer 5 is formed. As an example, a Cu seed layer 61 is deposited on the inner wall of the trench (trench A and the first opening) where the diffusion barrier layer 5 is formed, and Cu is electroplated to form a Cu-filled through-hole structure (second metal structure 6). Of course, chemical plating and other feasible processes can also be used to form the second metal structure 6, and the present invention is not limited thereto; the chemical mechanical polishing (CMP) process stops at the 230th layer to form the following. Figure 6f In the structure shown, the sidewalls of the second metal structure 6 are in contact with the diffusion barrier layer 5 .

[0189] Example 4

[0190] like Figure 2a-2b , as shown in 7a-7c, this embodiment provides a method for preparing a semiconductor structure, which specifically includes the following steps.

[0191] First, provide Figure 2b For the structure shown, please refer to the description above for the detailed formation process, which will not be repeated here. The thickness of the second stop layer 4 is 200% to 250% of the thickness of the first stop layer 2. This is to prevent the second stop layer 4 from being etched through when the second stop layer 4 is used as a mask to remove the bottom of the first stop layer 2 and the diffusion barrier layer 5, thereby exposing and damaging the interlayer dielectric layer 3 below it.

[0192] Secondly, if Figure 7a As shown, in Figure 2b A layer of diffusion barrier material 50 is formed on the inner wall of the trench A shown in the figure. The diffusion barrier material 50 can be selected from one of Si3N4, WN, TiN, Ta, TaN, and Ru, for example, Ta can be selected.

[0193] Again, as Figure 7b As shown, the diffusion barrier layer material 50 and the first stop layer 2 at the bottom of the groove A are etched downward in sequence using the etched second stop layer 4 and the diffusion barrier layer material 50 on its surface as masks to form the first opening in the first stop layer 2, and the first opening exposes the top surface of the first metal structure 11.

[0194] As an example, the first stop layer 2 may be made of Si3N4, and the diffusion barrier layer 5 may be made of Ta. Conventional dry etching or ALE is used to remove the diffusion barrier material 50 and the first stop layer 2 at the bottom of the trench A in one etching step, leaving only the diffusion barrier material 50 on the sidewalls of the trench A. Simultaneously, at least one first opening is formed in the first stop layer 2. For example, a mixed gas of CF4 and CH2F2 may be used to etch the diffusion barrier material 50 and the first stop layer 2. The etching selectivity can be adjusted by adjusting the amount of CH2F2: F* + Ta → TaF5, F* + Si3N4 → SiF4.

[0195] Finally, if Figure 7cAs shown, a second metal structure 6 is formed in the trench (trench A and the first opening) where the diffusion barrier layer 5 is formed. As an example, a Cu seed layer 61 is deposited on the inner wall of the trench (trench A and the first opening) where the diffusion barrier layer 5 is formed, and Cu is electroplated to form a Cu-filled through-hole structure (second metal structure 6). Of course, chemical plating and other feasible processes can also be used to form the second metal structure 6, without limitation. The chemical mechanical polishing (CMP) process stops at layer 230 to form the following. Figure 7c In the structure shown, the sidewall of the second metal structure 6 is located at the first stop layer 2 and is in direct contact with the first stop layer 2 , and the portion above the first stop layer 2 is in contact with the diffusion barrier layer 5 .

[0196] Example 5

[0197] like Figure 2a-2b , as shown in 8a-8f, this embodiment provides a method for preparing a semiconductor structure, which specifically includes the following steps.

[0198] First, provide Figure 2b The detailed formation process of the structure shown is described above and will not be repeated here. The thickness of the first stop layer 2 is between 40 and 70 nm; the thickness of the interlayer dielectric layer 3 is between 250 and 300 nm; and the thickness of the second stop layer 4 is 200% to 250% of the thickness of the first stop layer 2. This is to prevent etching through the second stop layer 4 when the second stop layer 4 is used as a mask to remove the bottom of the first stop layer 2 and the diffusion barrier layer 5, thereby exposing and damaging the underlying interlayer dielectric layer 3.

[0199] like Figure 8a As shown, in Figure 2b The inner wall of the trench A of the structure shown is formed with a diffusion barrier layer material 50; the diffusion barrier layer material 50 can also be selected from one of Si3N4, WN, TiN, Ta, TaN, and Ru, for example, Ta can be selected.

[0200] Secondly, if Figure 8b As shown, a second sacrificial layer 72 is filled in the groove A whose inner wall is formed with the diffusion barrier layer material 50, and the top surface of the second sacrificial layer 72 is higher than the top surface height of the diffusion barrier layer material 50; a patterned first photoresist layer 93 is formed on the second sacrificial layer 72, and the patterned first photoresist layer 93 has at least one second opening, and the second opening serves as a window for subsequent etching of the diffusion barrier layer material 50 located at the bottom of the groove A.

[0201] Again, as Figure 8cAs shown, the second sacrificial layer 72 and the diffusion barrier layer material 50 are sequentially etched downward using the patterned photoresist layer as a mask until the first stop layer 2 is exposed. As an example, the second anti-reflective coating (etching gas includes CF4), the second sacrificial layer 72 (etching gas includes CO), and the diffusion barrier layer material 50Ta are sequentially etched. As an example, conventional RIE etching of the diffusion barrier layer material 50Ta can be performed, using a BCl3 / Cl2 etching gas, which generates TaCl5 that is then extracted, with the chemical formula being Ta+Cl2→TaCl5+Cl*. It should be noted that the diffusion barrier layer material 50Ta can also be removed using the ALE (Cl2 / Ar) method described in Example 1.

[0202] From then on, Figure 8d As shown, the remaining patterned photoresist layer and the remaining second sacrificial layer 72 are removed to expose the diffusion barrier layer material 50 located on the second stop layer 4 .

[0203] Then, if Figure 8e As shown, the first stop layer 2 is etched downward using the second stop layer 4 and the diffusion barrier layer material 50 located on its surface as a mask to form a first opening in the first stop layer 2. The first opening exposes the top surface of the first metal structure 11. As an example, Si3N4 can be selected as the material for the first stop layer 2. A mixed gas of CF4 and CH2F2 is used to etch the diffusion barrier layer material 50 and the first stop layer 2. By adjusting the amount of CH2F2, the etching selectivity ratio of Si3N4 to Ta is adjusted, so that only Si3N4 is etched, while Ta is not etched or the etching rate is very low.

[0204] Finally, if Figure 8f As shown, a second metal structure 6 is formed in the trench (trench A and the first opening) where the diffusion barrier layer 5 is formed. As an example, a Cu seed layer 61 is deposited on the inner wall of the trench (trench A and the first opening) where the diffusion barrier layer 5 is formed, and Cu is electroplated to form a Cu-filled through-hole structure (second metal structure 6). Of course, chemical plating and other feasible processes can also be used to form the second metal structure 6, without limitation. The chemical mechanical polishing (CMP) process stops at layer 230 to form the following. Figure 7c In the structure shown, the sidewall of the second metal structure 6 is located at the first stop layer 2 and is in direct contact with the first stop layer 2 , and the portion above the first stop layer 2 is in contact with the diffusion barrier layer 5 .

[0205] Example 6

[0206] like Figures 2a-2g , as shown in 9a-8f, this embodiment provides a method for preparing a semiconductor structure, which specifically includes the following steps.

[0207] First, provide Figure 2g For the structure shown, please refer to the above description for the detailed formation process, which will not be repeated here. The thickness of the interlayer dielectric layer 3 can be 500-550nm.

[0208] Secondly, if Figure 9a As shown, in Figure 2g The inner wall of the trench B in the structure shown is formed with a diffusion barrier layer material 50 ; the diffusion barrier layer material 50 may also be selected from one of Si 3 N 4 , WN, TiN, Ta, TaN, and Ru, for example, Ta may be selected.

[0209] Again, as Figure 9b As shown, a second sacrificial layer 72 is filled in the groove B whose inner wall is formed with the diffusion barrier layer material 50, and the top surface of the second sacrificial layer 72 is higher than the top surface height of the diffusion barrier layer material 50; a patterned first photoresist layer 93 is formed on the second sacrificial layer 72, and the patterned first photoresist layer 93 has at least one second opening, and the second opening serves as a window for subsequent etching of the diffusion barrier layer material 50 located at the bottom of the groove B.

[0210] From then on, Figure 9c 9d, the second sacrificial layer 72, the diffusion barrier layer material 50 and the first stop layer 2 are etched downward in sequence using the patterned first photoresist layer 93 as a mask to form the first opening in the first stop layer 2, and the first opening exposes the top surface of the first metal structure 11.

[0211] As an example, when the diffusion barrier layer 5 is made of Ta and the first stop layer 2 is made of Si3N4, a mixed gas of CF4 and CH2F2 can be used to etch the diffusion barrier layer material 50 and the first stop layer 2 in one step. By adjusting the amount of CH2F2, the etching selectivity can be adjusted. F*+Ta→TaF5, F*+Si3N4→SiF4.

[0212] Finally, if Figure 9e As shown, the remaining patterned first photoresist layer 93 and the remaining second sacrificial layer 72 are removed.

[0213] Since oxygen plasma is generally used to remove the remaining patterned first photoresist layer 93 and the remaining second sacrificial layer 72, the top surface of the first metal structure 11 exposed at the bottom of the first opening will be oxidized, and residues will remain. Therefore, before forming the second metal structure 6, it is necessary to remove the residues and the oxide layer on the top surface of the exposed first metal structure 11. As an example, Ar plasma bombardment can be used to remove the surface residues and the oxide layer on the top surface of the first metal structure 11. Of course, other suitable plasmas can also be used for treatment, and the present invention is not limited thereto. At the same time, H2 is introduced to prevent the top surface of the first metal structure 11 from being oxidized. The process parameters are as follows: chamber pressure 20-100 mTorr, RF bias 10-100 W, and etching gas H2 / Ar can be used.

[0214] Examples 7-12

[0215] Examples 7-12 correspond to Examples 1-6 respectively, and the preparation process is basically the same, except that the conductive diffusion barrier layer 5 is replaced by an insulating diffusion barrier layer 5.

[0216] As an example, the material of the diffusion barrier layer 5 may be silicon nitride or silicon oxynitride. Of course, other suitable insulating materials may also be used, without limitation thereto.

[0217] In summary, the present invention provides a semiconductor structure, a method for preparing a semiconductor structure, and uses thereof. The preparation method includes providing a substrate, wherein at least one first metal structure is embedded in the substrate; the top surface of the first metal structure and the top surface of the substrate are in the same plane; forming an interlayer dielectric layer on the substrate; forming at least one trench in the interlayer dielectric layer, wherein the trench exposes the top surface of the first metal structure; forming a diffusion barrier layer on the sidewall of the trench; and forming a second metal structure in the trench having the diffusion barrier layer formed therein, wherein the second metal structure is directly bonded to the first metal structure to achieve electrical connection. The present invention uses etching to remove the diffusion barrier layer at the contact point of the metal interconnect structure, reducing the interconnect contact resistance between the upper and lower metal structures, thereby reducing RC delay, improving the speed of the semiconductor device, and ensuring device reliability. By removing the diffusion barrier material at the bottom of the Damascene structure while protecting the interlayer dielectric layer, the present invention improves the quality of via filling, thereby improving the electrical stability and device reliability of the semiconductor device. By removing the diffusion barrier layer between the first and second metal structures, the first and second metal structures can be directly bonded to achieve electrical connection. Therefore, the selection of the diffusion barrier material only needs to consider its ability to block the diffusion of the second metal material (e.g., Cu), without considering its conductive properties. Therefore, an insulating material with better ability to block the diffusion of the second metal material (e.g., Cu) can be selected for the diffusion barrier layer, further improving the electrical stability and device reliability of the semiconductor device. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial application value. The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate having at least one first metal structure embedded therein; The top surface of the first metal structure and the top surface of the substrate are in the same plane; forming an interlayer dielectric layer on the substrate; A first stop layer is formed between the substrate and the interlayer dielectric layer, and a second stop layer is formed on the interlayer dielectric layer; The preparation method further comprises: forming at least one trench in the second stop layer and the interlayer dielectric layer, wherein the trench exposes a top surface of the first stop layer; forming a diffusion barrier layer material on an inner wall of the trench; removing the diffusion barrier layer material at the bottom of the trench to form the diffusion barrier layer on the sidewall of the trench and expose the first stop layer; removing the exposed portion of the first stop layer to form a first opening in the first stop layer, wherein the first opening exposes the top surface of the first metal structure; as well as forming a second metal structure in the trench having the diffusion barrier layer formed on its sidewalls and in the first opening, wherein the second metal structure is directly bonded to the first metal structure to achieve electrical connection; The thickness of the second stop layer is greater than that of the first stop layer.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The preparation method further comprises: Filling the trench having the diffusion barrier layer material formed on the inner wall with a sacrificial layer, wherein the top surface of the sacrificial layer is higher than the top surface height of the diffusion barrier layer material; A patterned first photoresist layer is formed on the sacrificial layer, wherein the patterned first photoresist layer has at least one second opening, and the second opening serves as a window for subsequently etching the diffusion barrier layer material located at the bottom of the trench; Using the patterned first photoresist layer as a mask, sequentially etching downward the sacrificial layer and the diffusion barrier layer material until the first stop layer is exposed; The remaining patterned first photoresist layer and the remaining sacrificial layer are removed to expose the diffusion barrier layer material located on the second stop layer, and the first stop layer is etched downward using the second stop layer and the diffusion barrier layer material located on its surface as a mask to form the first opening in the first stop layer.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The preparation method further comprises: Filling a sacrificial layer in the groove having the diffusion barrier layer material formed on the inner wall, wherein the top surface of the sacrificial layer is higher than the top surface height of the diffusion barrier layer material; A patterned first photoresist layer is formed on the sacrificial layer, wherein the patterned first photoresist layer has at least one second opening, and the second opening serves as a window for subsequently etching the diffusion barrier layer material located at the bottom of the trench; Using the patterned first photoresist layer as a mask, the sacrificial layer, the diffusion barrier layer material, and the first stop layer are sequentially etched downward to form the first opening in the first stop layer, wherein the first opening exposes the top surface of the first metal structure; removing the remaining patterned first photoresist layer and the remaining sacrificial layer; A second metal structure is formed in the trench having the diffusion barrier layer formed on its sidewalls, and the second metal structure is joined to the first metal structure through the first opening to achieve electrical connection.

4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, wherein: The diffusion barrier layer material includes a conductive diffusion barrier layer material or an insulating diffusion barrier layer material; the conductive diffusion barrier layer material includes one of titanium nitride, tantalum, tungsten nitride, tantalum nitride and ruthenium; the insulating diffusion barrier layer material includes one of silicon nitride and silicon oxynitride.

5. The method for preparing a semiconductor structure according to claim 2 or 3, wherein: Between the step of removing the remaining patterned first photoresist layer and the remaining sacrificial layer and the step of forming the second metal structure, there is also a step of removing the residue and the oxide layer on the exposed top surface of the first metal structure.

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