Method for forming semiconductor device

Abstract

A method for forming a semiconductor device includes forming a fin protruding above a substrate, forming a gate structure above the fin, forming a groove in the fin adjacent to the gate structure; and forming a source / drain region in the groove, the source / drain region including a first film layer, a second film layer, and a third film layer. Forming the source / drain region includes: performing a first epitaxial process under a first process condition to form a first film layer in the groove, the first film layer extending along the surface of the fin exposed by the groove, performing a second epitaxial process under a second process condition to form a second film layer on the first film layer; and performing a third epitaxial process under a third process condition to form a third film layer on the second film layer, the third film layer filling the groove. The first process condition, the second process condition, and the third process condition are different.

Description

Technical Field

[0001] The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a semiconductor device including a fin field-effect transistor (FinFET). Background Art

[0002] The semiconductor industry has experienced rapid growth due to continued improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, improvements in integration density come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.

[0003] Fin-shaped field effect transistor devices have become commonly used in integrated circuits. Fin-shaped field effect transistor devices have a three-dimensional structure, which includes a semiconductor fin protruding from a substrate. A gate structure surrounds the semiconductor fin, which is used to control the flow of charge carriers in a conductive channel of the fin-shaped field effect transistor device. For example, in a tri-gate fin-shaped field effect transistor device, the gate structure surrounds three sides of the semiconductor fin, thereby forming a conductive channel on three sides of the semiconductor fin. Summary of the invention

[0004] An embodiment of the present invention includes a method for forming a semiconductor device, including: forming a fin protruding above a substrate, forming a gate structure above the fin, forming a groove in the fin adjacent to the gate structure; and forming a source / drain region in the groove, the source / drain region including a first film layer, a second film layer, and a third film layer. Forming the source / drain region includes: performing a first epitaxial process under a first process condition to form a first film layer in the groove, the first film layer extending along the surface of the fin exposed by the groove, performing a second epitaxial process under a second process condition to form a second film layer on the first film layer; and performing a third epitaxial process under a third process condition to form a third film layer on the second film layer, the third film layer filling the groove. The first process condition, the second process condition, and the third process condition are different. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The following will be described in detail with reference to the accompanying drawings. It should be noted that the various characteristic components are not drawn to scale and are only used for illustration. In fact, the size of the components may be enlarged or reduced to clearly show the technical features of the embodiments of the present invention.

[0006] Figure 1 is a perspective view illustrating a FinFET device according to some embodiments.

[0007] Figures 2 to 9 , FIG. 10A to FIG. 10C , Fig.11A , Fig. 11B , Fig.12 , Fig.13 , Fig.14A ,and Fig. 14B are cross-sectional views of a FinFET device at various stages of fabrication according to some embodiments.

[0008] Fig.15 is a cross-sectional view illustrating a fin field effect transistor device according to some embodiments.

[0009] Fig.16 is a flow chart showing a method of manufacturing a semiconductor device according to some embodiments.

[0010] Description of reference numerals:

[0011] 30~Fin Field Effect Transistor

[0012] 50~Substrate

[0013] 52~Pad oxide layer

[0014] 56~Pad nitride layer

[0015] 58~Mask

[0016] 61~Groove

[0017] 62~Isolated Area

[0018] 64, 64A, 64B~Semiconductor fins

[0019] 64S~Sidewall

[0020] 64L~lower surface

[0021] 64U~Top surface

[0022] 65~Lightly doped drain region

[0023] 66~Gate dielectric

[0024] 68~Gate

[0025] 70~Mask

[0026] 75, 75A, 75B, 75C ~ Virtual gate structure

[0027] 80~Source / drain region

[0028] 80A, 80B, 80C~film layer

[0029] 86~Groove

[0030] 87~Gate spacer

[0031] 87'~Spacer

[0032] 89~Contact etch stop layer

[0033] 90~First interlayer dielectric layer

[0034] 91~Contact opening

[0035] 92~Second interlayer dielectric layer

[0036] 93~Contact opening

[0037] 94~Gate dielectric layer

[0038] 95~Silicide region

[0039] 95U~Upper surface

[0040] 96~Barrier Layer

[0041] 97, 97A, 97B, 97C ~ Replacement gate

[0042] 98~Seed layer

[0043] 99~Gate electrode

[0044] 100, 100A~Fin Field Effect Transistor

[0045] 101~Barrier Layer

[0046] 102, 102A, 102B~contact

[0047] 103~Seed layer

[0048] 105~Conductive materials

[0049] 1000~Method

[0050] 1010, 1020, 1030, 1040 ~ Steps

[0051] AA, BB, CC ~ Section

[0052] D~Depth

[0053] T1, T2, T3, T4, T5, T6, T7, T8, T9~Thickness

[0054] W - Distance

[0055] TH~Thickness DETAILED DESCRIPTION

[0056] The following disclosure provides many different embodiments or examples to implement the different features of the present disclosure. The following disclosure describes specific examples of various components and their arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the present invention describes a first characteristic component formed on or above a second characteristic component, it means that it may include an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and may also include an embodiment in which an additional characteristic component is formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact.

[0057] In addition, spatially relative terms may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These spatially relative terms are used to facilitate the description of the relationship between one (or some) elements or features and another (or some) elements or features in the drawings. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the orientation after the rotation.

[0058] The present invention is discussed in the context of forming a fin field effect transistor device, and in particular, forming a source / drain region of the fin field effect transistor device. Although the present invention is discussed using a fin field effect transistor device as an example, the method of the present invention can also be used for other types of devices, such as planar devices.

[0059] Figure 1 A perspective view of an example fin field effect transistor 30 is shown. The fin field effect transistor 30 includes a substrate 50 and a fin 64 protruding above the substrate 50. An isolation region 62 is formed on opposite sides of the fin 64, and the fin 64 protrudes above the isolation region 62. A gate dielectric 66 is located along the sidewalls and top surface of the fin 64, and a gate 68 is located on the gate dielectric 66. A source / drain region 80 is in the fin 64 and is located on opposite sides of the gate dielectric 66 and the gate 68. Figure 1 The reference cross sections used in the subsequent figures are further shown. Cross section BB is along the longitudinal axis of the gate 68 of the fin field effect transistor 30. Cross section AA is perpendicular to cross section BB and along the longitudinal axis of the fin 64 and in the direction of current flow, for example, between the source / drain regions 80. Cross section CC is parallel to cross section BB and crosses the source / drain regions 80. For clarity, the subsequent figures refer to these cross sections.

[0060] No. 2 to Fig. 9 , FIG. 10A to FIG. 10C , Fig.11A , Fig. 11B , Fig.12 , Fig.13 , Fig.14A ,and Fig. 14B FIG. 1 is a cross-sectional view of the FinFET device 100 at various stages of fabrication according to some embodiments. Figure 1 FIG. 2-5 shows a cross-sectional view of the FinFET device 100 along the cross section BB. Figures 6 to 9 and Fig. 10A A cross-sectional view of the fin field effect transistor device 100 along the cross section AA is shown. Fig. 10B and Fig. 10C A cross-sectional view of the FinFET device 100 along the cross-section CC is shown. Fig.11A , Fig.12 , Fig.13 ,and Fig.14A A cross-sectional view of the fin field effect transistor device 100 along the cross-sectional plane AA is shown, and Fig. 11B and Fig. 14B A cross-sectional view of the fin field effect transistor device 100 along the cross-sectional plane BB is shown.

[0061] Figure 2 A cross-sectional view of substrate 50 is shown. Substrate 50 may be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate thereof, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Generally, a SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates may be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors include silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors include SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof.

[0062] See also Figure 3 , patterned by photolithography and etching techniques, for example Figure 2. For example, a mask layer such as a pad oxide layer 52 and an overlying pad nitride layer 56 are formed on the substrate 50. The pad oxide layer 52 may be, for example, a thin film including silicon oxide formed using a thermal oxidation process. The pad oxide layer 52 may serve as an adhesion layer between the substrate 50 and the overlying pad nitride layer 56. In some embodiments, the pad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof, and may be formed using, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0063] The mask layer may be patterned using photolithography techniques. Generally, photolithography techniques use deposition, irradiation (exposure), and development of a photoresist material (not shown) to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, during subsequent process steps such as etching. In this example, a photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 to form a Figure 3 The patterned mask 58 is shown in FIG.

[0064] Then, the exposed portion of the substrate 50 is patterned using the patterned mask 58 to form a groove 61, so that Figure 3 As shown, semiconductor fins 64 (e.g., 64A and 64B) are defined between adjacent trenches 61. In some embodiments, a recess is etched in the substrate 50 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), a similar method, or a combination thereof to form the semiconductor fins 64. The etching may be anisotropic. In some embodiments, the trenches 61 may be parallel strips to each other (as viewed from above) and closely spaced from each other. In some embodiments, the trenches 61 may be continuous and surround the semiconductor fins 64. Hereinafter, the semiconductor fins 64 may also be referred to as fins 64.

[0065] The fins 64 may be patterned in any suitable manner. For example, one or more photolithography processes, including double patterning or multiple patterning processes, may be used to pattern the fins 64. In general, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, smaller intercepts than would be achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned on a substrate using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0066] Figure 4 An insulating material is shown formed between adjacent semiconductor fins 64 to form an isolation region 62. The insulating material may be an oxide such as silicon oxide, nitride, the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., depositing a chemical vapor deposition-based material in a remote plasma system and then curing it to convert it to another material, such as an oxide), the like, or a combination thereof. Other insulating materials and / or other formation processes may be used. In the embodiment shown, the insulating material is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process may be performed. A planarization process such as chemical mechanical polishing (CMP) may remove any excess insulating material and form a coplanar top surface of the isolation region 62 and a top surface of the semiconductor fin 64 (not shown). The patterned mask 58 may also be removed by a planarization process (see Figure 3 ).

[0067] In some embodiments, the isolation region 62 includes a liner, such as an oxide liner (not shown), at the interface between the isolation region 62 and the substrate 50 / semiconductor fin 64. In some embodiments, the oxide liner is formed to reduce crystal defects at the interface between the substrate 50 and the isolation region 62. Similarly, the oxide liner can also be used to reduce crystal defects at the interface between the semiconductor fin 64 and the isolation region 62. The oxide liner (e.g., silicon oxide) can be a thermal oxide formed by thermally oxidizing a surface layer of the substrate 50, but other suitable methods can also be used to form the oxide liner.

[0068] Next, the isolation region 62 is etched back to form a shallow trench isolation (STI) region 62. The isolation region 62 is etched back so that the upper portion of the semiconductor fin 64 protrudes between adjacent shallow trench isolation regions 62. The top surface of the shallow trench isolation region 62 may have a flat surface (as shown), a convex surface, a concave surface (e.g., a dish shape), or a combination thereof. By suitable etching, the top surface of the shallow trench isolation region 62 may be formed to be flat, protruding, and / or concave. The isolation region 62 may be etched back using an acceptable etching process, such as an etching process that is selective to the material of the isolation region 62. For example, dry etching or wet etching using dilute hydrofluoric (dHF) may be performed to etch back the isolation region 62.

[0069] Figures 2 to 4 An embodiment of forming fins 64 is shown, but fins may be formed by various different processes. For example, the top of substrate 50 may be replaced with a suitable material, such as an epitaxial material suitable for a predetermined type (e.g., N-type or P-type) of the semiconductor element to be formed. Thereafter, substrate 50 having the epitaxial material on the top is patterned to form semiconductor fins 64 including the epitaxial material.

[0070] As another example, a dielectric layer may be formed on the top surface of the substrate; a trench may be etched through the dielectric layer; a homoepitaxial structure may be epitaxially grown in the trench; and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form a fin.

[0071] In another embodiment, a dielectric layer may be formed on the top surface of the substrate; a trench may be etched through the dielectric layer; a homoepitaxial structure may be epitaxially grown in the trench using a material different from that of the substrate; and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form a fin.

[0072] In some embodiments of growing epitaxial materials or structures (e.g., heteroepitaxial structures or homoepitaxial structures), the growing material or structure may be doped in situ as it grows, although both in situ and ion doping may be used, which may avoid prior or subsequent implantation. Further, it may be beneficial to epitaxially grow a different material in the NMOS region than in the PMOS region. In various embodiments, the fins 64 may include silicon germanium (SiGe). x Ge 1-x, x can be between 0 and 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, or the like. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0073] Figure 5 A dummy gate structure 75 is shown formed over the semiconductor fin 64. A mask 70 may be formed over the dummy gate structure 75. To form the dummy gate structure 75, a dielectric layer is formed over the semiconductor fin 64. The dielectric layer may be, for example, silicon oxide, silicon nitride, multiple layers thereof, or the like, and the dielectric layer may be deposited or thermally grown.

[0074] A gate layer is formed on the dielectric layer, and a mask layer is formed on the gate layer. The gate layer may be deposited on the dielectric layer and then planarized, for example, by chemical mechanical polishing. A mask layer may be deposited on the gate layer. The gate layer may be formed, for example, of polysilicon, although other materials may also be used. The mask layer may be formed, for example, of silicon nitride or the like.

[0075] After forming film layers (e.g., dielectric layer, gate layer, and mask layer), the mask layer may be patterned using acceptable photolithography and etching techniques to form a mask 70. Next, the pattern of mask 70 may be transferred to the gate layer and the dielectric layer using acceptable etching techniques to form a gate 68 and a gate dielectric 66, respectively. The gate 68 and the gate dielectric 66 cover each channel region of the semiconductor fin 64. The gate 68 may also have a length direction substantially perpendicular to the length direction of each semiconductor fin 64.

[0076] exist Figure 5 In the example of FIG. 5 , gate dielectric 66 is shown formed over fin 64 (e.g., over the top surface and sidewalls of fin 64) and over shallow trench isolation region 62. In other embodiments, gate dielectric 66 may be formed of a material such as thermally oxidized fin 64, and thus may be formed over fin 64 instead of shallow trench isolation region 62. These and other variations are fully intended to be within the scope of embodiments of the present invention.

[0077] Figure 6 to Figure 1 0 and Fig.11A FIG. 4 shows a cross-sectional view of the fin field effect transistor device 100 in a further process along the cross section AA (along the longitudinal axis of the fin 64 ). Figure 6 to Figure 1 0 and Fig.11AIn the embodiment of the present invention, three dummy gate structures 75 (eg, 75A, 75B, and 75C) are formed on the fin 64. One skilled in the art will appreciate that more or less than three dummy gate structures may be formed on the fin 64, and these and other variations are fully intended to be within the scope of the present invention.

[0078] like Figure 6 As shown, a lightly doped drain (LDD) region 65 is formed in the fin 64. The lightly doped drain region 65 may be formed by a plasma doping process. The plasma doping process may include forming and patterning a mask such as a photoresist to cover the fin field effect transistor region to be protected from the plasma doping process. The plasma doping process may implant N-type or P-type impurities in the fin 64 to form the lightly doped drain region 65. For example, a P-type impurity such as boron may be implanted in the fin 64 to form a lightly doped drain region 65 for a P-type device. As another example, an N-type impurity such as phosphorus may be implanted in the fin 64 to form a lightly doped drain region 65 for an N-type device. In some embodiments, the lightly doped drain region 65 abuts the channel region of the fin field effect transistor device 100. A portion of the lightly doped drain region 65 may extend under the gate 68 and into the channel region of the fin field effect transistor device 100. Figure 6 A non-limiting example of a lightly doped drain region 65 is shown. Other forms, shapes, and methods of forming the lightly doped drain region 65 are also possible and are fully intended to be included within the scope of the embodiments of the present invention. For example, the lightly doped drain region 65 can be formed after forming the gate spacer 87. In some embodiments, the lightly doped drain region 65 is omitted. For simplicity, the lightly doped drain region 65 is not shown in subsequent figures, and it is understood that the lightly doped drain region 65 can be formed in the fin 64.

[0079] Still see Figure 6 , after forming the lightly doped drain region 65, a gate spacer 87 is formed on the gate structure. The gate spacer 87 may include a first gate spacer and a second gate spacer (not shown separately). For example, the first gate spacer may be a gate sealing spacer formed on opposite sidewalls of the gate 68 and on opposite sidewalls of the gate dielectric 66. A second gate spacer is formed on the first gate spacer. The first gate spacer may be formed of a nitride such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof, and may be formed using, for example, thermal oxidation, chemical vapor deposition, or other suitable deposition processes. The second gate spacer may be formed of silicon nitride, silicon carbonitride, a combination thereof, or the like, using a suitable deposition method. The gate spacer 87 may, for example, have a thickness between about 20 nm and about 35 nm.

[0080] In an exemplary embodiment, the gate spacer is formed by first conformally depositing a first gate spacer layer on the fin field effect transistor device 100, and then conformally depositing a second gate spacer layer on the deposited first gate spacer. Next, an anisotropic etching process, such as a dry etching process, is performed to remove a first portion of the second gate spacer layer located on the upper surface of the fin field effect transistor device 100 (e.g., the upper surface of the mask 70), while retaining a second portion of the second gate spacer layer located along the sidewall of the gate structure. After the anisotropic etching process, the remaining second portion of the second gate spacer layer forms a second gate spacer. The anisotropic etching process also removes a portion of the first gate spacer layer located outside the sidewall of the second gate spacer, and the remaining portion of the first gate spacer layer forms the first gate spacer.

[0081] like Figure 6 The shapes and formation methods of the gate spacers 87 shown in FIG. 8 are non-limiting examples, and other shapes and formation methods are possible. These and other variations are fully intended to be included within the scope of embodiments of the present invention.

[0082] Then, if Figure 7 As shown, a recess 86 is formed in the fin 64 adjacent to the dummy gate structure 75, for example, between adjacent dummy gate structures 75 and / or next to the dummy gate structure 75. In some embodiments, the recess 86 is formed using the dummy gate structure 75 as an etching mask, for example, by an anisotropic etching process, but other suitable etching processes may also be used. The recess 86 exposes the sidewall 64S and the lower surface 64L of the fin 64, and therefore, the sidewall 64S and the lower surface 64L may also be referred to as the surface of the fin 64 exposed by the recess 86. The depth D of the recess 86 measured between the upper surface 64U of the fin 64 and the lower surface 64L of the fin 64 may be between about 35nm and about 60nm.

[0083] Then, if Figure 8 As shown, source / drain regions 80 are formed (see Fig. 10A ) is formed in the recess 86. The film layer 80A includes an epitaxial semiconductor material suitable for the type of device to be formed (e.g., N-type or P-type). In the illustrated embodiment, the fin field effect transistor device 100 is an N-type fin field effect transistor device, and the film layer includes silicon phosphorous (SiP), silicon arsenic (SiAs), or the like. In this discussion, impurities such as phosphorous (P) and arsenic (As) are referred to as dopants in the epitaxial material of the source / drain region 80.

[0084] like Figure 8As shown, the film layer 80A physically contacts and extends along the sidewall 64S and the lower surface 64L of the fin 64, and extends continuously from the upper surface 64U of the fin 64 to the lower surface 64L at the bottom of the groove 86. In the embodiment shown, the thickness of the film layer 80A is non-uniform. In particular, the bottom of the film layer 80A (e.g., the portion along the lower surface 64L of the fin 64) is thicker than the sidewall portion of the film layer 80A (e.g., the portion along the sidewall 64S of the fin 64). For example, the thickness T1 of the bottom of the film layer 80A is between about 1nm and about 8nm. The thickness T2 of the sidewall portion of the film layer 80A is between about 1nm and about 5nm. In the embodiment shown, the concentration of dopants (e.g., P or As) in the film layer 80A is between about 5e20 / cm 3 to about 2e21 / cm 3 .

[0085] In some embodiments, a suitable method such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or similar methods or a combination thereof is used to epitaxially grow a material in the recess 86 to form the film layer 80A. The process conditions of the epitaxial process are adjusted to achieve a target dopant concentration and / or control the profile of the formed epitaxial material (e.g., the film layer 80A).

[0086] In some embodiments, the epitaxial process is performed at a temperature between about 450° C. and about 800° C. and a pressure between about 5 Torr and about 600 Torr. The epitaxial process is performed using a process gas including a silicon-containing gas and a dopant gas. The silicon-containing gas may be silane (SiH4), dichlorosilane (DCS), disilane (DS), trichlorosilane (TCS), a combination thereof, or the like. The dopant gas may be phosphine (PH3), arsine (AsH3), liquid arsine, a combination thereof, or the like. In some embodiments, in addition to the silicon-containing gas and the dopant gas, the process gas also includes an etching gas such as hydrogen chloride (HCl) to achieve selective epitaxial growth, so that after the epitaxial process is completed, the epitaxial material of the film layer 80A is formed on the semiconductor material (e.g., on the sidewalls 64S and the lower surface 64L of the fin 64), and is not formed on, for example, a dielectric material such as the gate spacer 87.

[0087] In some embodiments, during the epitaxial process of forming the film layer 80A, the flow rate of the silicon-containing gas is between about 10 standard cubic centimeters per minute (sccm) and about 900 sccm, the flow rate of the dopant gas is between about 50 sccm and about 400 sccm, and the flow rate of the etching gas is between about 40 sccm and about 1000 sccm. The mixing ratio (e.g., the ratio of the flow rates) of different process gases (e.g., the silicon-containing gas, the dopant gas, and the etching gas) is adjusted to achieve the target dopant concentration of the film layer 80A. For example, during the epitaxial process of forming the film layer 80A, the mixing ratio of the silicon-containing gas, the dopant gas, and the etching gas is about 7:2:1, wherein the mixing ratio of 7:2:1 means that the flow rate of the silicon-containing gas is seven times that of the etching gas, and the flow rate of the dopant gas is twice that of the etching gas.

[0088] Then, if Fig. 9 As shown, source / drain regions 80 are formed (see Fig. 10A ) is formed above the film layer 80A in the recess 86. The film layer 80B partially fills the recess 86, so that after the film layer 80B is formed, the recess 86 becomes shallower. The film layer 80B includes the same epitaxial material (e.g., SiP or SiAs) as the film layer 80A, but with a different (e.g., higher) dopant concentration. In addition, as described below, the profile (e.g., size and / or shape) of the film layer 80B can be different from that of the film layer 80A.

[0089] like Fig. 9 As shown, the film layer 80B is in physical contact with and extends along the film layer 80A, and extends continuously from the upper surface 64U of the fin 64 to the bottom of the (now shallower) groove 86. In the embodiment shown, the thickness of the film layer 80B is non-uniform. In particular, the bottom of the film layer 80B is thicker than the sidewall portion. For example, the thickness T3 of the bottom of the film layer 80B (e.g., at the bottom portion of the groove 86) is between about 15nm and about 48nm. The thickness T4 of the sidewall portion of the film layer 80B (e.g., along the sidewall 64S) is between about 3nm and about 30nm. In the embodiment shown, the concentration of dopants (e.g., P or As) in the film layer 80B is between about 2e21 / cm 3 to about 3.5e21 / cm 3 In other words, the doping concentration of the film layer 80B is higher than the doping concentration of the film layer 80A.

[0090] In some embodiments, film layer 80B is formed on film layer 80A using epitaxially grown material, for example using the same or similar epitaxial process as film layer 80A, but adjusting the process conditions of the epitaxial process to achieve a target dopant concentration and / or control the profile of the formed epitaxial material (e.g., film layer 80B). For example, the epitaxial process for forming film layer 80B may be performed in the same process chamber using the same process gases as the epitaxial process for forming film layer 80A, but adjusting the process conditions such as the temperature of the process chamber, the pressure of the process chamber, the flow rate of the process gas, and / or the mixing ratio of the process gas. In some embodiments, an epitaxial process is first performed to form film layer 80A (using the process conditions selected for film layer 80A), and once the target dimensions (e.g., thickness) of film layer 80A are achieved, the process conditions of the epitaxial process for film layer 80B are adjusted, and the epitaxial process is continued to form film layer 80B. Similarly, once the target dimensions of film layer 80B are achieved, the process conditions of the epitaxial process are adjusted to the (subsequently formed) film layer 80C of the source / drain region 80 (see Fig. 10A ), and the epitaxial process is continued to form the film layer 80C. Therefore, by adjusting the process conditions at different stages of the epitaxial process, the film layers 80A, 80B, and 80C can be formed sequentially in the same process chamber using the same epitaxial process. In other words, the epitaxial process for forming the film layer 80A, the epitaxial process for forming 80B, and the epitaxial process for forming 80C can be three different stages of a single (continuous) epitaxial process, each stage having different process conditions.

[0091] In some embodiments, the epitaxial process for forming the film layer 80B is performed at a temperature between about 400° C. and about 800° C. and a pressure between about 5 Torr and about 600 Torr. The epitaxial process is performed using a silicon-containing gas and a dopant gas. The silicon-containing gas may be silane (SiH4), dichlorosilane (DCS), disilane (DS), trichlorosilane (TCS), a combination thereof, or the like. The dopant gas may be phosphine (PH3), arsine (AsH3), liquid arsine, a combination thereof, or the like. In some embodiments, in addition to the silicon-containing gas and the dopant gas used in the epitaxial process, an etching gas such as hydrogen chloride (HCl) is used to achieve selective epitaxial growth. In the embodiment shown, the silicon-containing gas, the dopant gas, and the etching gas are the same as the process gases used to form the film layer 80A in the epitaxial process.

[0092] In some embodiments, during the epitaxial process to form the film layer 80B, the flow rate of the silicon-containing gas is between about 10 sccm and about 900 sccm, the flow rate of the dopant gas is between about 50 sccm and about 400 sccm, and the flow rate of the etching gas is between about 40 sccm and about 1000 sccm. The mixing ratio of the different process gases is adjusted to achieve the target dopant concentration of the film layer 80B. In one embodiment, during the epitaxial process to form the film layer 80B, the mixing ratio of the silicon-containing gas, the dopant gas, and the etching gas is about 11:3:1.

[0093] Then, if Fig. 10A As shown, a film layer 80C that forms the source / drain region 80 is above the film layer 80B. The film layer 80C fills the recess 86 and extends above the upper surface 64U of the fin 64. The film layer 80C includes the same epitaxial material (e.g., SiP or SiAs) as the film layers 80A and 80B, but with a different (e.g., higher) dopant concentration. In addition, as described below, the profile (e.g., size and / or shape) of the film layer 80C can be different from that of the film layers 80A and 80B. In the illustrated embodiment, the film layers 80A, 80B, and 80C form the source / drain region 80 of the fin field effect transistor device 100.

[0094] like Fig. 10A As shown, the film layer 80C has a lower portion extending below the upper surface 64U of the fin 64 by a distance T6. In one embodiment, the distance T6 between the lowermost surface of the film layer 80C and the upper surface 64U of the fin 64 is between about 5nm and about 10nm. In addition, the film layer 80C has an upper portion extending above the upper surface 64U of the fin 64 by a distance T5. The upper portion of the film layer 80C may physically contact the gate spacer 87 adjacent to the film layer 80C. In one embodiment, the distance T5 measured between the upper surface (e.g., the uppermost surface) of the film layer 80C and the upper surface 64U of the fin 64 is between about 3nm and about 5nm. In some embodiments, the distance T7 measured between the upper surface of the film layer 80C and the lowermost surface of the film layer 80C is between about 5nm and about 15nm. Fig. 10A In the example of FIG. 5 , the upper portion of the film layer 80C has a rectangular cross-section, while the lower portion of the film layer 80C has a tapered profile, with the distance W between the opposite sidewalls of the lower portion decreasing as the lower portion extends toward the substrate 50. Other profiles of the film layer 80C are also possible and are fully intended to be included within the scope of the embodiments of the present invention. In the illustrated embodiment, the concentration of the dopant (e.g., P or As) in the film layer 80C is between about 3.5e21 / cm 3 to about 5e21 / cm 3 In other words, the doping concentration of the film layer 80C is higher than the doping concentration of the film layer 80B, and the doping concentration of the film layer 80B is higher than the doping concentration of the film layer 80A.

[0095] In some embodiments, film layer 80C is formed on film layer 80B by epitaxially growing material, for example using the same or similar epitaxial process as film layers 80A and 80B, but as described above, the process conditions of the epitaxial process are adjusted to achieve a target dopant concentration and / or to control the profile of the formed epitaxial material (e.g., film layer 80C).

[0096] In some embodiments, the epitaxial process for forming the film layer 80C is performed at a temperature between about 400° C. and about 800° C. and a pressure between about 5 Torr and about 650 Torr. The epitaxial process is performed using a silicon-containing gas and a dopant gas. The silicon-containing gas may be silane (SiH4), dichlorosilane (DCS), disilane (DS), trichlorosilane (TCS), a combination thereof, or the like. The dopant gas may be phosphine (PH3), arsine (AsH3), liquid arsine, a combination thereof, or the like. In some embodiments, in addition to the silicon-containing gas and the dopant gas used in the epitaxial process, an etching gas such as hydrogen chloride (HCl) is used to achieve selective epitaxial growth. In the embodiment shown, the silicon-containing gas, the dopant gas, and the etching gas are the same as the process gases used to form the film layer 80A in the epitaxial process.

[0097] In some embodiments, during the epitaxial process to form the film layer 80C, the flow rate of the silicon-containing gas is between about 10 sccm and about 900 sccm, the flow rate of the dopant gas is between about 50 sccm and about 400 sccm, and the flow rate of the etching gas is between about 40 sccm and about 1000 sccm. The mixing ratio of the different process gases is adjusted to achieve the target dopant concentration of the film layer 80C. In one embodiment, during the epitaxial process to form the film layer 80C, the mixing ratio of the silicon-containing gas, the dopant gas, and the etching gas is about 15:6:1.

[0098] like Fig. 10B As shown, the epitaxial source / drain regions 80 (e.g., 80A, 80B, and 80C, not shown separately) may have surfaces that protrude from corresponding surfaces of the fins 64 (e.g., protrude over portions of the fins 64 that are not recessed), and may have facets. The source / drain regions 80 adjacent to the fins 64 may merge to form a continuous epitaxial source / drain region 80. Fig. 10B Also shown are spacers 87' on opposite sidewalls of the source / drain region 80. The spacers 87' may have the same shape as the gate spacers 87 (see FIG. Fig. 10A) and can be formed in the same process step as the gate spacer 87. In some embodiments, the source / drain regions 80 adjacent to the fin 64 are not fused together and separate source / drain regions 80 are maintained (see Fig. 10C ).

[0099] After forming the epitaxial source / drain regions 80, an optional implantation process is performed to implant dopants in the source / drain regions 80. In the illustrated embodiment, since the dopant concentration of the film layers (e.g., 80A, 80B, 80C) of the source / drain regions 80 is within the target dopant concentration range after forming the source / drain regions 80 using the above process steps, the implantation process is omitted. Next, an annealing process is performed to activate the dopants in the source / drain regions 80.

[0100] like Figure 8 , Fig. 9 ,and Fig. 10A The illustrated embodiment of the present invention provides many advantages with the multi-layer source / drain region 80 and the multi-step formation method. The film layer 80C has a temperature between about 3.5e21 / cm 3 to about 5e21 / cm 3 The high concentration of dopants (e.g., P or As) may be orders of magnitude (e.g., ten, one hundred, or more) greater than the dopant concentration in the source / drain regions of the prior art transistor elements. Prior to the present invention, the transistor element having such a high dopant concentration (e.g., between about 3.5e21 / cm 3 to about 5e21 / cm 3 ) may have a lower activation rate in the source / drain region, and the selective epitaxial growth of the source / drain region 80 may be difficult to achieve such a high dopant concentration. Therefore, without the embodiments of the present invention, the high dopant concentration in the source / drain region (e.g., between about 3.5e21 / cm 3 to about 5e21 / cm 3 ) may not be achievable or practical. However, due to the structure of the source / drain region 80 and the formation method used to form the source / drain region 80, the source / drain region 80 of the embodiment of the present invention has a high activation rate and excellent selective epitaxial growth properties. The increased carrier mobility of the source / drain region 80 of the embodiment of the present invention shows (e.g., reflects) a high activation rate. For example, before the annealing process, the carrier mobility of the source / drain region 80 including the SiP can be between about 50cm 2 / (VS) to about 70cm 2 / (VS), and after the annealing process, the carrier mobility of the source / drain region 80 may be between about 55 cm 2 / (VS) to about 80cm 2Therefore, the embodiment of the present invention allows the source / drain region 80 to have a high doping concentration, a high activation rate, and a selective epitaxial property, which can improve the performance of the fin field effect transistor device 100.

[0101] In addition, since the lower portion of the film layer 80C extends below the upper surface 64U of the fin 64 (see FIG. 10A ), during the annealing process for activating the dopants in the source / drain region 80, some dopants (such as P or As) are driven into the channel region 64C (see FIG. 10A ). Fig. 10A ), thereby advantageously reducing the channel resistance R of the fin field effect transistor device 100 ch For example, R ch The resistance R of the channel is reduced by about 0.13 KΩ to 0.15 KΩ. Recall that each layer 80A and 80B has a non-uniform thickness, with the sidewall portion being thinner than the bottom. The thinner sidewalls can advantageously facilitate thermal driving of dopants from layer 80C into channel region 64C. It should be noted that when thermally driving dopants into the channel region, the channel resistance R ch , but if not properly handled, heat drive-in may adversely affect the leakage current of the fin field effect transistor device 100. This may be another reason why previous transistor devices cannot use such high doping concentrations in the source / drain region, and why previous transistor devices may not have a high doping concentration source / drain region portion extending so deep (e.g., 5nm to 10nm) below the upper surface 64U of the fin 64. The source / drain region 80 and its structure and method of the embodiment of the present invention minimize or reduce the performance loss due to heat driving dopants into the channel region, making the performance loss negligible. For example, it has been confirmed that the drain-induced barrier lowering (DIBL) caused by heat drive-in is only 2mV. Therefore, the fin field effect transistor device 100 of the embodiment of the present invention reduces the channel resistance R ch , with negligible performance loss.

[0102] In addition, the upper portion of the film layer 80C extends above the upper surface 64U of the fin 64, increasing the volume of the epitaxial source / drain region 80. The increased volume of the film layer 80C and the subsequently formed source / drain contacts (see Fig.14A The lower energy barrier between the film layer 102B) and the film layer 80C (due to the high dopant concentration of the film layer 80C) advantageously reduces the contact resistance R of the formed fin field effect transistor device 100. p .

[0103] Then, if Fig.11A As shown, a contact etch stop layer (CESL) 89 is formed at Fig. 10AThe contact etch stop layer 89 serves as an etch stop layer in subsequent etching processes and may include a suitable material such as silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, or the like, and may be formed by a suitable formation method such as chemical vapor deposition, physical vapor deposition, a combination thereof, or the like.

[0104] Next, a first interlayer dielectric (ILD) layer 90 is formed on the contact etch stop layer 89 and on the dummy gate structures 75 (e.g., 75A, 75B, and 75C). In some embodiments, the first interlayer dielectric layer 90 is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and can be deposited in any suitable manner, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, or flowable chemical vapor deposition. A planarization process such as a chemical mechanical polishing process can be performed to remove the mask 70 and remove the portion of the contact etch stop layer 89 located on the gate 68. After the planarization process, the top surface of the first interlayer dielectric layer 90 is flush with the top surface of the gate 68.

[0105] Fig. 11B Show Fig.11A The fin field effect transistor device 100 shown in FIG. 1 is a cross-sectional view along the cross-sectional plane BB. Fig. 11B As shown in FIG. 1 , gate 68 is located above fin 64A and fin 64B and extends continuously from fin 64A to fin 64B. A gate spacer 87 is formed between gate 68 and first interlayer dielectric layer 90. An embodiment of a gate-last process (sometimes referred to as a replacement gate process) is then performed to replace gate 68 and gate dielectric 66 with an active gate (sometimes also referred to as a replacement gate or metal gate) and an active gate dielectric material. In some embodiments, the active gate can be a metal gate. Therefore, in the gate-last process, gate 68 and gate dielectric 66 are considered as dummy gate structures.

[0106] According to some embodiments, Fig.12 , Fig.13 ,and Fig.14A FIG. 2 shows a cross-sectional view of the fin field effect transistor device 100 along the cross section AA during a subsequent process. Fig.12, the dummy gate structures 75A, 75B, and 75C are replaced with active gate structures 97A, 97B, and 97C, respectively. According to some embodiments, to form active gate structure 97 (e.g., 97A, 97B, or 97C), gate 68 and gate dielectric 66 directly below gate 68 are removed in an etching step, so that recesses (not shown) are formed between gate spacers 87. Each recess exposes a channel region of a corresponding fin 64. When removing the dummy gate, dummy gate dielectric layer 66 may be used as an etch stop layer when etching dummy gate 68. After removing dummy gate 68, dummy gate dielectric layer 66 may be removed.

[0107] Next, a gate dielectric layer 94, a barrier layer 96, a seed layer 98, and a gate electrode 99 are formed in the recess of the replacement gate 97. The gate dielectric layer 94 is conformally deposited in the recess, such as on the top surface and sidewalls of the fin 64, on the sidewalls of the gate spacer 87, and on the top surface of the first interlayer dielectric layer 90 (not shown). According to some embodiments, the gate dielectric layer 94 includes silicon oxide, silicon nitride, or a multilayer thereof. In other embodiments, the gate dielectric layer 94 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 94 may have a dielectric constant greater than about 7.0 and may include metal oxides or silicides of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric layer 94 may include molecular beam deposition (MBD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition, and the like.

[0108] Next, a barrier layer 96 is conformally formed over the gate dielectric layer 94. The barrier layer 96 may include a conductive material such as titanium nitride, but other materials such as tantalum nitride, titanium, tantalum, or the like may be used instead. The barrier layer 96 may be formed using a chemical vapor deposition process such as plasma enhanced chemical vapor deposition. However, other alternative processes such as sputtering, metal organic chemical vapor deposition, or atomic layer deposition may also be used instead.

[0109] Although not shown in Fig.12In some embodiments, a work function layer such as a P-type work function layer or an N-type work function layer may be formed on the barrier layer 96 in the recess before forming the seed layer 98. Exemplary P-type work function metals that may be included in the gate structure of the P-type device include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function metals, or combinations thereof. Exemplary N-type work function metals that may be included in the gate structure of the N-type device include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function metals, or combinations thereof. The work function value is related to the material composition of the work function layer, and thus the material of the work function layer is selected to adjust its work function value so as to achieve a target threshold voltage Vt in the formed device. The work function layer may be deposited by chemical vapor deposition, physical vapor deposition (PVD), and / or other suitable processes.

[0110] Next, a seed layer 98 is conformally formed on the barrier layer 96. The seed layer 98 may include copper, titanium, tantalum, titanium nitride, tantalum nitride, the like, or a combination thereof, and may be deposited by atomic layer deposition, sputtering, physical vapor deposition, or the like. In some embodiments, the seed layer may be a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. For example, the seed layer 98 includes a titanium layer and a copper layer on the titanium layer.

[0111] Next, a gate electrode 99 is deposited on the seed layer 98 and fills the rest of the groove. The gate electrode 99 may be made of a metal-containing material such as Cu, Al, W, the like, a combination thereof, or a multilayer thereof, and may be formed by, for example, electroplating, chemical plating, or other suitable methods. After the gate electrode 99 is formed, a planarization process such as chemical mechanical polishing may be performed to remove the gate dielectric layer 94, the barrier layer 96, the work function layer (if formed), the seed layer 98, and the excess portion of the gate electrode 99, the excess portion of which is located above the upper surface of the first interlayer dielectric layer 90. The remaining portions of the resulting gate dielectric layer 94, the barrier layer 96, the work function layer (if formed), the seed layer 98, and the gate electrode 99 thus form the replacement gate 97 of the resulting fin field effect transistor device 100.

[0112] See next Fig.13, a second interlayer dielectric layer 92 is formed on the first interlayer dielectric layer 90. A contact opening 93 is formed through the second interlayer dielectric layer 92 to expose the replacement gate 97 (e.g., 97A, 97B, and 97C). Similarly, a contact opening 91 is formed through the first interlayer dielectric layer 90 and the second interlayer dielectric layer 92 to expose the source / drain region 80.

[0113] In one embodiment, the second interlayer dielectric layer 92 is a flowable film layer formed by a flowable chemical vapor deposition method. In some embodiments, the second interlayer dielectric layer 92 is formed of a dielectric material such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and can be deposited by any suitable method, such as chemical vapor deposition and plasma enhanced chemical vapor deposition. Contact openings 91 and 93 can be formed using photolithography and etching. The etching process etches through the contact etch stop layer 89 to expose the film layer 80C of the source / drain region 80. The etching process may over-etch, and thus the contact opening 91 may extend into the film layer 80C, and the bottom of the contact opening 91 may be flush with the upper surface 64U of the fin 64 (e.g., at the same level, or having the same distance as the substrate), or lower than (e.g., closer to the substrate) the upper surface 64U of the fin 64.

[0114] Since the film layer 80C extends above the upper surface 64U of the fin 64, even if the etching process is over-etched to remove the contact etch stop layer 89, the remaining portion of the film layer 80C still has contact with the subsequently formed source / drain contacts (see, for example, Fig.14A The large volume of the connection 102B) in the fin field effect transistor device 100 helps to reduce the contact resistance R p If the upper portion of the film layer 80C does not extend above the upper surface 64U of the fin 64 , the volume of the remaining portion of the film layer 80C after over-etching may be too small, and the contact resistance R of the fin field effect transistor device 100 may be too small. p The tolerance of the contact etch stop layer 89 to over-etching illustrates another advantage of embodiments of the present invention.

[0115] After forming the contact opening 93, a silicide region 95 is formed on the film layer 80C. In some embodiments, the silicide region 95 is first deposited with a metal that can react with a semiconductor material (e.g., silicon, germanium) to form a silicide or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof on the exposed portion of the film layer 80C of the epitaxial source / drain region 80, and then a thermal annealing process is performed to form the silicide region 95. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the region 95 is referred to as a silicide region, the region 95 may also be a germanide region, or a silicon-germanide region (e.g., a region including silicide and germanide). In one embodiment, the silicide region 95 includes TiSi and has a thickness TH between about 2 nm and about 10 nm.

[0116] Then, in Fig.14A In the embodiment shown, contacts 102 (e.g., 102A, 102B, which may also be referred to as contact plugs) are formed in contact openings 91 and 93. In the illustrated embodiment, each contact 102 includes a barrier layer 101, a seed layer 103, and a conductive material 105, and is electrically coupled to an underlying conductive component (e.g., a replacement gate 97 or a silicide region 95). Contact 102A electrically coupled to replacement gate 97 may be referred to as a gate contact, and contact 102B electrically coupled to silicide region 95 may be referred to as a source / drain contact. The materials and formation methods of barrier layer 101, seed layer 103, and conductive material 105 may be the same or similar to those used to form barrier layer 96, seed layer 98, and gate electrode 99 of replacement gate 97, respectively, and thus the details are not repeated. In one embodiment, the conductive material 105 of the source / drain contact 102B is tungsten (W), and the height of the source / drain contact 102B is between about 5 nm and about 15 nm. Fig.14A In the figure, for illustration, all the contacts 102 are shown in the same cross section. This is of course an example and not a limitation. The contacts 102 may be in different cross sections.

[0117] Fig. 14B Show Fig.14A The FinFET device 100 is shown along the cross section BB. Fig. 14B A contact 102 is shown on each fin 64A and 64B. The contact 102 is electrically connected to the replacement gate 97. The number and location of the contacts 102 are for illustrative purposes only and are not limiting. Other numbers and other locations are possible and are fully intended to be within the scope of the embodiments of the present invention.

[0118] According to some embodiments, Fig.15 FIG. 4 is a cross-sectional view of a fin field effect transistor device 100A. Fig.14A The fin field effect transistor 100 in FIG. 1 is similar to the fin field effect transistor 100 in FIG. 1 , but the film layers 80B / 80C of the source / drain regions 80 thereof have different shapes and / or sizes. The different shapes and / or sizes of the film layers 80B / 80C may be attributed to the variation in the process conditions of the epitaxial process for forming the film layers 80B / 80C. Fig.15 and Fig.14A In the present invention, unless otherwise specified, the same or similar reference numerals refer to the same or similar components formed by the same or similar processes using the same or similar materials, and thus the details will not be repeated.

[0119] exist Fig.15 In the embodiment, the film layer 80A has Fig.14A For example, the film layer 80A has a non-uniform thickness, wherein the bottom of the film layer 80A (e.g., the portion along the lower surface 64L of the fin 64) is thicker than the sidewall portion of the film layer 80A (e.g., the portion along the sidewall 64S of the fin 64). In the illustrated embodiment, the concentration of dopants (e.g., P or As) in the film layer 80A is between about 5e20 / cm 3 to about 2e21 / cm 3 .

[0120] Fig.15 The middle film layers 80B and 80C and Fig.14A The film layers 80B and 80C in the embodiment have different shapes and / or sizes. For example, Fig.15 The film layer 80B in the embodiment has a substantially flat upper surface, and the film layer 80B exposes (e.g., does not cover) the upper sidewall portion of the film layer 80A. The thickness T8 of the film layer 80B (e.g., measured between the upper and lower surfaces of the film layer 80B) can be between about 15 nm and about 48 nm. In the embodiment shown, the concentration of the dopant (e.g., P or As) in the film layer 80B is between about 2e21 / cm 3 to about 3.5e21 / cm 3 .

[0121] Fig.15 The film layer 80C in the groove 86 (see Fig. 9 ). The upper surface of the film layer 80C extends above the upper surface 64U of the fin 64. The thickness T9 of the film layer 80C may be between about 5 nm and about 35 nm. In the illustrated embodiment, the concentration of dopants (e.g., P or As) in the film layer 80C is between about 3.5e21 / cm 3 to about 5e21 / cm 3 In other words, the doping concentration of the film layer 80C is greater than that of the film layer 80B, and the doping concentration of the film layer 80B is greater than that of the film layer 80A. Fig.14A and Fig.15 The profiles of the film layers 80A / 80B / 80C shown in the figure are merely examples, and other profiles are possible and are fully intended to be included within the scope of the embodiments of the present invention.

[0122] exist Fig.15 In the etching process, the contact opening 91 is formed (see Fig.13 ) may be an over-etch, and the contact opening 91 may enter the membrane layer 80C. As a result, the upper surface 95U of the silicide region 95 may be flush with the upper surface 64U of the fin 64. In other embodiments, the upper surface 95U of the silicide region 95 may be lower than the upper surface 64U of the fin 64 (e.g., closer to the substrate 50).

[0123] According to some embodiments, Fig.16 1 is a flow chart showing a method 1000 of forming a semiconductor device. It should be understood that Fig.16 The embodiment method shown in is only one example of many possible embodiment methods. Those skilled in the art can recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, and repeated. Fig.16 The different steps shown in .

[0124] See also Fig.16 In step 1010, a fin is formed to protrude above the substrate. In step 1020, a gate structure is formed on the fin. In step 1030, a groove is formed in the fin adjacent to the gate structure. In step 1040, a source / drain region is formed in the groove, the source / drain region includes a first film layer, a second film layer, and a third film layer, wherein forming the source / drain region includes: performing a first epitaxial process under a first process condition to form a first film layer in the groove, the first film layer extending along the surface of the fin exposed by the groove; performing a second epitaxial process under a second process condition to form a second film layer on the first film layer; and performing a third epitaxial process under a third process condition to form a third film layer on the second film layer, the third film layer filling the groove, wherein the first process condition, the second process condition, and the third process condition are different.

[0125] Embodiments of the present invention can achieve advantages. For example, the source / drain region 80 of the embodiment of the present invention has a high dopant concentration, a high activation rate, and good selective epitaxial growth properties. The multi-layer structure and different dopant concentrations of the film layers (e.g., 80A / 80B / 80C) of the source / drain region 80, as well as other factors, allow the fin field effect transistor device 100 to reduce the channel resistance due to thermal driving of dopants into the channel region, with negligible performance loss. Due to the large volume and high dopant concentration of the film layer 80C, for example, the contact resistance of the fin field effect transistor device 100 is also reduced. The reduced channel resistance and contact resistance improve the electrical performance of the fin field effect transistor device 100.

[0126] In one embodiment, a method for forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure above the fin; forming a recess in the fin adjacent to the gate structure; and forming a source / drain region in the recess, the source / drain region including a first film layer, a second film layer, and a third film layer, wherein forming the source / drain region includes: performing a first epitaxial process under a first process condition to form a first film layer in the recess, the first film layer extending along a surface of the fin exposed by the recess; performing a second epitaxial process under a second process condition to form a second film layer on the first film layer; and performing a third epitaxial process under a third process condition to form a third film layer on the second film layer, the third film layer filling the recess, wherein the first process condition, the second process condition, and the third process condition are different. In one embodiment, the first film layer, the second film layer, and the third film layer are formed of the same epitaxial material including a semiconductor material and a dopant, wherein a first dopant concentration of the first film layer, a second dopant concentration of the second film layer, and a third dopant concentration of the third film layer are different. In one embodiment, the epitaxial material is silicon phosphorous (SiP) or silicon arsenic (SiAs). In one embodiment, the third doping concentration is higher than the second doping concentration, and the second doping concentration is higher than the first doping concentration. In one embodiment, the first doping concentration is between about 5e20 / cm 3 to about 2e21 / cm 3 The second dopant concentration is between about 2e21 / cm 3 to about 3.5e21 / cm 3 and the third doping concentration is between about 3.5e21 / cm 3 to about 5e21 / cm 3In one embodiment, a first film layer is formed to have a non-uniform thickness, wherein a first sidewall portion of the first film layer is thinner than a first bottom portion of the first film layer, wherein a second film layer is formed to have a non-uniform thickness, wherein a second sidewall portion of the second film layer is thinner than a second bottom portion of the second film layer. In one embodiment, a third film layer is formed to have a lower portion extending below an upper surface of the fin, and an upper portion extending above an upper surface of the fin. In one embodiment, the first epitaxial process, the second epitaxial process, and the third epitaxial process are performed using the same process gas but process gases of different mixing ratios, wherein the process gas includes a silicon-containing gas, a dopant gas, and an etching gas. In one embodiment, the process gas mixing ratio of each of the first epitaxial process, the second epitaxial process, and the third epitaxial process is adjusted to achieve different dopant concentrations of the first film layer, the second film layer, and the third film layer. In one embodiment, the first epitaxial process, the second epitaxial process, and the third epitaxial process are performed in the same process chamber, and are three stages of a single continuous epitaxial process. In one embodiment, the method also includes forming a dielectric layer over the source / drain region and around the gate structure; replacing the gate structure with a replacement gate; forming a third film layer with an opening in the dielectric layer to expose the source / drain region, wherein the bottom of the opening is flush with the upper surface of the fin; and forming a contact in the opening, the contact electrically coupled to the source / drain region.

[0127] In one embodiment, a method for forming a semiconductor device includes forming a gate structure on a fin; forming a groove in the fin, the groove being adjacent to a channel region of the fin; forming a first epitaxial layer in the groove, the first epitaxial layer having a first dopant concentration; forming a second epitaxial layer in the groove on the first epitaxial layer, the second epitaxial layer having a second dopant concentration higher than the first dopant concentration; and forming a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a third dopant concentration higher than the second dopant concentration. In one embodiment, the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are formed of the same epitaxial material, silicon phosphorous (SiP) or silicon arsenic (SiAs). In one embodiment, the dopant of the same epitaxial material is phosphorus or arsenic, and the third dopant concentration is between about 3.5e21 / cm 3 to about 5e21 / cm 3 In one embodiment, the third epitaxial layer is formed to have a top portion extending above the upper surface of the fin, and a lower portion extending below the upper surface of the fin. In one embodiment, the top portion of the third epitaxial layer extends about 3 nm to about 5 nm above the upper surface of the fin, and the lower portion extends about 5 nm to about 10 nm below the upper surface of the fin.

[0128] In one embodiment, a semiconductor device includes a fin protruding above a substrate; a gate structure located above the fin; and a source / drain region adjacent to the gate structure, wherein the source / drain region includes a first film layer extending along the sidewall and lower surface of the fin exposed by a groove in the fin, the first film layer being located below the upper surface of the fin, the first film layer comprising an epitaxial material with a first doping concentration; a second film layer being located above the first film layer and below the upper surface of the fin, the second film layer comprising an epitaxial material with a second doping concentration higher than the first doping concentration; and a third film layer being located above the second film layer and filling the groove, the third film layer comprising an epitaxial material with a third doping concentration higher than the second doping concentration. In one embodiment, a first thickness of the first film layer measured at the sidewall of the fin is less than a second thickness of the first film layer measured at the lower surface of the fin, wherein a third thickness of the second film layer measured at the sidewall of the fin is less than a fourth thickness of the second film layer measured at the lower surface of the fin. In one embodiment, the third film layer has an upper portion located above the upper surface of the fin and a lower portion located below the upper surface of the fin, wherein the distance between the opposite sidewalls of the lower portion decreases as the lower portion extends toward the lower surface of the fin. In one embodiment, the epitaxial material is silicon phosphorus or silicon arsenic, and the third dopant concentration is between about 3.5e21 / cm 3 to about 5e21 / cm 3 .

[0129] The foregoing text summarizes the characteristic components of many embodiments, so that those skilled in the art can preferably understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the inventive concept and scope of the embodiments of the present invention. Without departing from the inventive concept and scope of the embodiments of the present invention, various changes, substitutions or modifications may be made to the embodiments of the present invention, so the scope of protection of the present invention shall be subject to those defined by the claims. In addition, although the present invention has been disclosed as above with several preferred embodiments, it is not intended to limit the present invention, and not all advantages have been described in detail herein.

Claims

1. A method for forming a semiconductor device, comprising: forming a fin protruding above a substrate; forming a gate structure on the fin; forming a groove in the fin adjacent to the gate structure; as well as A source / drain region is formed in the groove, wherein the source / drain region includes a first film layer, a second film layer, and a third film layer, wherein forming the source / drain region includes: Performing a first epitaxial process under a first process condition to form the first film layer in the groove, wherein the first film layer extends along the surface of the fin exposed by the groove; Performing a second epitaxial process under second process conditions to form the second film layer on the first film layer; and A third epitaxial process is performed under third process conditions to form the third film layer on the second film layer, and the third film layer fills the groove, wherein the first process conditions, the second process conditions, and the third process conditions are different, wherein the first epitaxial process, the second epitaxial process, and the third epitaxial process are performed using the same process gas but different mixing ratios of the process gas, wherein the process gas includes a silicon-containing gas, a dopant gas, and an etching gas.

2. The method for forming a semiconductor device as described in claim 1, wherein the first film layer, the second film layer, and the third film layer are formed by the same epitaxial material including semiconductor material and dopants, wherein a first dopant concentration of the first film layer, a second dopant concentration of the second film layer, and a third dopant concentration of the third film layer are different. 3 . The method for forming a semiconductor device as claimed in claim 2 , wherein the epitaxial material is silicon phosphorus or silicon arsenic. 4 . The method for forming a semiconductor device as claimed in claim 2 , wherein the third doping concentration is higher than the second doping concentration, and the second doping concentration is higher than the first doping concentration.

5. The method for forming a semiconductor device as claimed in claim 4, wherein the first dopant concentration is between 5e20 / cm 3 to 2e21 / cm 3 The second doping concentration is between 2e21 / cm 3 to 3.5e21 / cm 3 and the third doping concentration is between 3.5e21 / cm 3 To 5e21 / cm 3 between.

6. A method for forming a semiconductor device as described in claim 4, wherein the first film layer is formed to have an uneven thickness, and a first sidewall portion of the first film layer is thinner than a first bottom portion of the first film layer, and wherein the second film layer is formed to have an uneven thickness, and a second sidewall portion of the second film layer is thinner than a second bottom portion of the second film layer. 7 . The method for forming a semiconductor device as claimed in claim 6 , wherein the third film layer is formed to have a lower portion extending below an upper surface of the fin and an upper portion extending above the upper surface of the fin.

8. The method for forming a semiconductor device as described in claim 1, wherein the mixing ratio of process gases of each of the first epitaxial process, the second epitaxial process, and the third epitaxial process is adjusted to achieve different doping concentrations of the first film layer, the second film layer, and the third film layer. 9 . The method for forming a semiconductor device as claimed in claim 8 , wherein the first epitaxial process, the second epitaxial process, and the third epitaxial process are performed in the same process chamber and are three stages of a single continuous epitaxial process.

10. The method for forming a semiconductor device according to claim 1, further comprising: forming a dielectric layer on the source / drain region and around the gate structure; replacing the gate structure with a replacement gate; forming an opening in the dielectric layer to expose the third film layer of the source / drain region, wherein the bottom of the opening is flush with the upper surface of the fin; as well as A contact is formed in the opening, the contact being electrically coupled to the source / drain region.

11. A method for forming a semiconductor device, comprising: forming a gate structure on a fin; forming a groove in the fin, the groove being adjacent to a channel region of the fin; Forming a first epitaxial layer in the groove, the first epitaxial layer contacts the sidewall and bottom surface of the groove and extends along the sidewall and bottom surface of the groove, the first epitaxial layer having a first doping concentration greater than zero; forming a second epitaxial layer on the first epitaxial layer in the recess and contacting the first epitaxial layer, the second epitaxial layer having a second doping concentration higher than the first doping concentration; and A third epitaxial layer is formed on the second epitaxial layer and contacts the second epitaxial layer, wherein the lower surface of the third epitaxial layer extends below the upper surface of the fin, the upper surface of the third epitaxial layer extends above the upper surface of the fin, and the third epitaxial layer has a third doping concentration higher than the second doping concentration. 12 . The method for forming a semiconductor device as claimed in claim 11 , wherein the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are formed of the same epitaxial material, silicon phosphorus or silicon arsenic.

13. The method for forming a semiconductor device as claimed in claim 12, wherein the dopant of the same epitaxial material is phosphorus or arsenic, and the third dopant concentration is between 3.5e21 / cm 3 To 5e21 / cm 3 between. 14 . The method for forming a semiconductor device as claimed in claim 11 , wherein an upper surface of the third epitaxial layer extends 3 nm to 5 nm above an upper surface of the fin, and a lower surface extends 5 nm to 10 nm below an upper surface of the fin. 15 . The method for forming a semiconductor device as claimed in claim 11 , wherein the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are formed by using the same process gas but different mixing ratios of the process gas. 16 . The method for forming a semiconductor device as claimed in claim 15 , wherein the process gas comprises a silicon-containing gas, a dopant gas and an etching gas.

17. The method for forming a semiconductor device according to claim 11, further comprising: forming a dielectric layer on the third epitaxial layer and around the gate structure; replacing the gate structure with a replacement gate; forming an opening in the dielectric layer to expose the third epitaxial layer, wherein a bottom of the opening is flush with an upper surface of the fin; and A contact is formed in the opening, and the contact is electrically coupled to the third epitaxial layer.

18. A semiconductor device comprising: A fin protrudes from a substrate; A gate structure is located on the fin; as well as A source / drain region is adjacent to the gate structure, wherein the source / drain region includes: A first film layer extends along the sidewall and the lower surface of the fin exposed by a groove in the fin, the first film layer is located below the upper surface of the fin, and the first film layer includes an epitaxial material with a first doping concentration; A second film layer is located on the first film layer and below the upper surface of the fin, the second film layer comprising the epitaxial material with a second doping concentration higher than the first doping concentration; and A third film layer is located on the second film layer and fills the groove, the third film layer includes the epitaxial material with a third doping concentration higher than the second doping concentration, wherein the epitaxial material is silicon phosphorus or silicon arsenic, and the third doping concentration is between 3.5e21 / cm 3 To 5e21 / cm 3 .

19. A semiconductor device as described in claim 18, wherein a first thickness of the first film layer measured from the side wall of the fin is less than a second thickness of the first film layer measured from the bottom surface of the fin, and wherein a third thickness of the second film layer measured from the side wall of the fin is less than a fourth thickness of the second film layer measured from the bottom surface of the fin.

20. The semiconductor device of claim 19, wherein the third film layer has an upper portion located above the upper surface of the fin, and a lower portion located below the upper surface of the fin, wherein a distance between opposite side walls of the lower portion decreases as the lower portion extends toward the lower surface of the fin.

Images