Semiconductor device

Abstract

Provided is a semiconductor device and a method for manufacturing the same. The semiconductor device includes a gate stack and source / drain regions. The gate stack is located above an active region. The source / drain regions are located in the active region and adjacent to the gate stack, and include: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer. The first semiconductor layer has a first germanium concentration. The second semiconductor layer is located above the first semiconductor layer and has a second germanium concentration greater than the first germanium concentration. The third semiconductor layer is located above the second semiconductor layer and has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer is located above the third semiconductor layer and has a fourth germanium concentration less than the third germanium concentration.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device including source / drain regions having semiconductor layers with different germanium concentrations and a method of manufacturing the same. Background Art

[0002] Semiconductor devices are used in various electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layer materials over a semiconductor substrate and patterning the various material layers using photolithography processes to form circuit elements and components on the semiconductor substrate.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a specific area. However, as the minimum feature size is reduced, additional problems arise that need to be solved. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor device, including: a gate stack and source / drain regions. The gate stack is located over an active region. The source / drain regions are located in the active region and adjacent to the gate stack. The source / drain regions include: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer. The first semiconductor layer has a first germanium concentration. The second semiconductor layer is located over the first semiconductor layer, where the second semiconductor layer has a second germanium concentration, and the second germanium concentration is greater than the first germanium concentration. The third semiconductor layer is located over the second semiconductor layer, where the third semiconductor layer has a third germanium concentration, and the third germanium concentration is greater than the second germanium concentration. The fourth semiconductor layer is located over the third semiconductor layer, where the fourth semiconductor layer has a fourth germanium concentration, and the fourth germanium concentration is less than the third germanium concentration.

[0005] An embodiment of the present disclosure provides a semiconductor device, including: a gate stack, an epitaxial source / drain region, and a contact plug. The foregoing gate stack is located above the active region. The foregoing epitaxial source / drain region is located in the foregoing active region and adjacent to the foregoing gate stack. The foregoing epitaxial source / drain region includes silicon germanium and includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer. The foregoing first semiconductor layer has a first boron concentration. The foregoing second semiconductor layer is located above the foregoing first semiconductor layer, wherein the foregoing second semiconductor layer has a second boron concentration, and the foregoing second boron concentration is greater than the foregoing first boron concentration. The foregoing third semiconductor layer is located above the foregoing second semiconductor layer, wherein the foregoing third semiconductor layer has a third boron concentration, and the foregoing third boron concentration is greater than the foregoing second boron concentration. The foregoing fourth semiconductor layer is located above the foregoing third semiconductor layer, wherein the foregoing fourth semiconductor layer has a fourth boron concentration, and the foregoing fourth boron concentration is less than the foregoing third boron concentration. The foregoing contact plug is located above the foregoing epitaxial source / drain region, wherein the foregoing contact plug extends through the foregoing fourth semiconductor layer and extends into the foregoing third semiconductor layer.

[0006] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including: forming a gate stack above an active region; forming an opening in the foregoing active region and adjacent to the foregoing gate stack; and forming a source / drain region in the foregoing opening. Forming the foregoing source / drain region includes: epitaxially growing a first semiconductor layer along the bottom and sidewalls of the foregoing opening, wherein the foregoing first semiconductor layer has a first germanium concentration; epitaxially growing a second semiconductor layer above the foregoing first semiconductor layer, wherein the foregoing second semiconductor layer has a second germanium concentration, and the foregoing second germanium concentration is greater than the foregoing first germanium concentration; epitaxially growing a third semiconductor layer above the foregoing second semiconductor layer, wherein the foregoing third semiconductor layer has a third germanium concentration, and the foregoing third germanium concentration is greater than the foregoing second germanium concentration; and epitaxially growing a fourth semiconductor layer above the foregoing third semiconductor layer, wherein the foregoing fourth semiconductor layer has a fourth germanium concentration, and the foregoing fourth germanium concentration is less than the foregoing third germanium concentration. Description of the Drawings

[0007] The concepts of the embodiments of the present disclosure can be better understood according to the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to the standard practice in the industry, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clear illustration.

[0008] Figure 1 A perspective view of a fin field-effect transistor (FinFET) according to some embodiments is shown.

[0009] Figure 2 、3 、4, 5, 6, 7, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11B, 11C, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 15C, 16A, 16B, 17A, and 17B illustrate cross-sectional views of intermediate stages of manufacturing a fin field-effect transistor according to some embodiments.

[0010] Figure 18 Illustrates a cross-sectional view of a fin field-effect transistor according to some embodiments.

[0011] Figure 19 Illustrates a cross-sectional view of a fin field-effect transistor according to some embodiments.

[0012] Figure 20 Illustrates a cross-sectional view of a fin field-effect transistor according to some embodiments.

[0013] Figure 21 Illustrates a flowchart of a method of forming a semiconductor device according to some embodiments.

[0014]

Symbol Description

[0015] 50 Substrate

[0016] 50N, 50P Regions

[0017] 51 Separation Line

[0018] 52 Fin

[0019] 54 Insulating Material

[0020] 56 Isolation Region (Shallow Trench Isolation Region)

[0021] 58 Channel Region

[0022] 60Dummy Dielectric Layer

[0023] 62Dummy Gate Layer

[0024] 64 Mask Layer

[0025] 72Dummy Gate

[0026] 74 Mask

[0027] 80 Gate Sealing Spacer

[0028] 82 Source / Drain Region (Epitaxial Source / Drain Region)

[0029] 82A First Layer

[0030] 82B Second Layer

[0031] 82C Third Layer

[0032] 82D Fourth layer

[0033] 86 Gate spacer

[0034] 86A, 86B layers

[0035] 87 Contact etch stop layer

[0036] 88 First interlayer dielectric layer

[0037] 89 Region

[0038] 90 Depression

[0039] 92 Gate dielectric layer

[0040] 94 Gate electrode

[0041] 94A Buffer layer

[0042] 94B Work function tuning layer

[0043] 94C Filling material

[0044] 96 Gate mask

[0045] 108 Second interlayer dielectric layer

[0046] 110 Gate contact

[0047] 112 Source / drain contact

[0048] 114 Silicide layer

[0049] 2100 Method

[0050] 2101, 2103, 2105, 2107 Steps

[0051] A-A, B-B, C-C Cross sections (reference cross sections)

[0052] W1, W2, W3 Widths Detailed implementation mode

[0053] The following disclosure provides many different embodiments or examples for implementing different features of the embodiments of the present disclosure. Specific examples of components and configurations are described below to simplify the description of the embodiments of the present disclosure. Of course, these specific examples are only illustrative and not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that the first feature is formed on or above the second feature, which means that it may include embodiments in which the first feature and the second feature are in direct contact, and may also include embodiments in which additional features are formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse the same reference numerals and / or symbols in various examples. These repetitions themselves are not used to specify the relationship between different embodiments and / or structures discussed.

[0054] In addition, spatially relative terms may be used herein. For example, "under", "below", "lower", "above", "higher" and similar terms are used to facilitate the description of the relationship between one element or feature shown in the drawings and another (some) element or feature. In addition to the orientation shown in the drawings, these spatially relative terms are intended to include different orientations of the device in use or operation. The device may be turned in different orientations (rotated 90 degrees or other orientations), and the spatially relative terms used herein may be interpreted in the same way accordingly.

[0055] Embodiments will be described below in conjunction with a specific background, that is, the source / drain regions of semiconductor devices and methods for manufacturing the same. The various embodiments presented in the present disclosure are described in the context of fin field-effect transistor devices formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments consider aspects for planar transistor devices, multi-gate transistor devices, two-dimensional (2D) transistor devices, surround-gate transistor devices, nanowire transistor devices, or other similar devices. For example, the various embodiments described in the present disclosure allow the formation of silicon germanium (Si x Ge 1-x , where x may range from 0 to 1) source / drain regions, which include multiple layers with different germanium and dopant (such as boron) concentrations. The various embodiments described in the present disclosure further allow reducing the source / drain impedance of semiconductor devices and improving the stability of the interface between the contacts and each source / drain region.

[0056] Figure 1A perspective view of a fin field-effect transistor (FinFET) according to some embodiments is shown. The fin field-effect transistor includes fins 52 located on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and the fins 52 protrude therefrom between adjacent isolation regions 56. Although the isolation regions 56 are illustrated as being separate from the substrate 50, the term "substrate" as used in this disclosure can be used to refer to a semiconductor substrate or a semiconductor substrate including isolation regions. Additionally, although the fins 52 are illustrated as being of the same and continuous material as the substrate 50, the fins 52 and / or the substrate 50 can include a single material or multiple materials. In this document, a fin 52 refers to the portion extending between adjacent isolation regions 56.

[0057] A gate dielectric layer 92 is along the sidewalls of the fin 52 and above the top surface of the fin 52, and a gate electrode 94 is located above the gate dielectric layer 92. Source / drain regions 82 are disposed on opposite sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1 Reference cross-sections for subsequent figures are further shown. Cross-section A-A is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current between the source / drain regions 82 of the fin field-effect transistor. Cross-section B-B is perpendicular to cross-section A-A and along the longitudinal axis of the fin 52 and in the direction of current, for example, between the source / drain regions 82 of the fin field-effect transistor. Cross-section C-C is parallel to cross-section A-A and extends through the source / drain regions 82 of the fin field-effect transistor. For clarity, the subsequent figures are related to these reference cross-sections.

[0058] Figure 2 、 3 、4, 5, 6, 7, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11B, 11C, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 15C, 16A, 16B, 17A, and 17B show cross-sectional views of intermediate stages of manufacturing a fin field-effect transistor according to some embodiments. Figures 2 to 7 Shown Figure 1 is the reference cross-section A-A shown in Figure 8A 、 9A 、10A, 12A, 13A, 14A, 15A, 16A, and 17A are shown along Figure 1 the reference cross-section A-A shown in Figure 8B 、 9B 、10B, 11B, 12B, 13B, 14B, 15B, 15C, 16B, and 17B are shown along Figure 1 a similar cross-section B-B shown in Figure 10C 、 10Dand 11C are shown along the reference cross-section C-C shown in Figure 1 , except for the plurality of fins / finned field-effect transistors. Figure 1 In and

[0059] , a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or other similar dopable (e.g., using p-type or n-type dopants) or undoped substrates. The substrate 50 may be a wafer (e.g., a silicon wafer). Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or other similar layers. Other substrates (e.g., multi-layer substrates or gradient substrates) may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP)), or a combination of the foregoing.

[0059] In Figure 2 , a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or other similar dopable (e.g., using p-type or n-type dopants) or undoped substrates. The substrate 50 may be a wafer (e.g., a silicon wafer). Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or other similar layers. Other substrates (e.g., multi-layer substrates or gradient substrates) may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP)), or a combination of the foregoing. Figure 2 In Figure 2 , a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or other similar dopable (e.g., using p-type or n-type dopants) or undoped substrates. The substrate 50 may be a wafer (e.g., a silicon wafer). Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or other similar layers. Other substrates (e.g., multi-layer substrates or gradient substrates) may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP)), or a combination of the foregoing.

[0060] The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form n-type devices (such as n-type metal-oxide-semiconductor (NMOS) transistors, n-type finned field-effect transistors). The region 50P can be used to form p-type devices (such as p-type metal-oxide-semiconductor (PMOS) transistors, p-type finned field-effect transistors). The region 50N can be physically separated from the region 50P (separated by a dividing line 51 as shown in the figure), and any number of device features (such as other active devices, doped regions, isolation structures, etc.) can be provided between the region 50N and the region 50P.

[0061] In Figure 3 , Figure 3In [description], fins 52 are formed in substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 can be formed in the substrate 50 by etching trenches in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), other similar etching processes, or a combination of the foregoing. The etching can be anisotropic.

[0062] The fins can be patterned in any suitable manner. For example, the fins can be patterned using one or more lithography processes, including double patterning processes or multiple patterning processes. Generally, double patterning processes or multiple patterning processes combine lithography processes and self-alignment processes, allowing the generation of patterns, for example, having pitches smaller than those obtainable using other single, direct lithography processes. For example, in one embodiment, a sacrificial layer is formed and patterned over the substrate using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. Then, the sacrificial layer is removed, and the remaining spacer can be used to pattern the fins.

[0063] In Figure 4 In [description], an insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide (such as silicon oxide), a nitride, other similar compounds, or a combination of the foregoing, and the insulating material 54 can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD, such as material deposition based on chemical vapor deposition in a remote plasma system and then cured to convert it into another material, such as an oxide), other similar means, or a combination of the foregoing. Any acceptable process can be used to form other insulating materials. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by a flowable CVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is depicted as a single layer, some embodiments can use multiple layers. For example, in some embodiments, a liner (not shown) can be formed along the surface of the substrate 50 and the fins 52 first. Then, the filling material as described above can be formed over the liner.

[0064] In Figure 5In [the process], a removal process is applied to the insulating material 54 to remove the excess insulating material 54 above the fin 52. In some embodiments, a planarization process (such as chemical mechanical polish; CMP), a re-etch process, a combination of the foregoing, or other similar processes may be used. After the planarization process is completed, the planarization process exposes the fin 52 such that the top surface of the fin 52 is flush with the top surface of the insulating material 54.

[0065] In Figure 6 [the process], the insulating material 54 is recessed to form a Shallow Trench Isolation (STI) region 56. The insulating material 54 is recessed such that the upper portions of the fins 52 in the regions 50N and 50P protrude between adjacent shallow trench isolation regions 56. In addition, the top surface of the shallow trench isolation region 56 may have a flat surface, a convex surface, a concave surface (such as a depression), or a combination of the foregoing as shown. The top surface of the shallow trench isolation region 56 may be formed to be flat, convex, and / or concave through appropriate etching. An acceptable etching process, such as an etching process selective to the material of the insulating material 54 (such as etching the material of the insulating material 54 at a faster rate compared to the material of the fin 52), may be used to recess the shallow trench isolation region 56. For example, dilute hydrofluoric (dHF) may be used to chemically remove the oxide with a suitable etching process.

[0066] Regarding Figures 2 to 6 The described process is only an example of how the fin 52 may be formed. In some embodiments, the fin may be formed through an epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure may be epitaxially grown in the trenches, and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form a fin. Additionally, in some embodiments, the homoepitaxial structure may be used for the fin 52. For example, Figure 5The fin 52 is recessed, and a material different from the fin 52 can grow epitaxially above the recessed fin 52. In this embodiment, the fin 52 includes a recessed material and an epitaxially grown material disposed above the recessed material. In yet another embodiment, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can be grown epitaxially in the trenches using a material different from the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments of growing a homoepitaxial or heteroepitaxial structure, although in situ and implantation doping can be used together, the epitaxially grown material can be doped in situ during growth, which can omit the previous and subsequent implantation processes.

[0067] Additionally, it is advantageous to grow epitaxially a material different from the region 50P (such as a p-type metal oxide semiconductor region) in the region 50N (such as an n-type metal oxide semiconductor region). In various embodiments, the upper portion of the fin 52 can be formed of silicon germanium (Si x Ge 1-x , where x can range from 0 to 1), silicon carbide, pure or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, or other similar materials. For example, available materials for forming group III-V compound semiconductors include indium arsenide (InAs), aluminum arsenide (AlAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium antimonide (GaSb), aluminum antimonide (AlSb), aluminum phosphide (AlP), gallium phosphide (GaP), and other similar materials, but not limited thereto.

[0068] Additionally, in Figure 6In [the figure], appropriate wells (not shown) can be formed in the fin 52 and / or the substrate 50. In some embodiments, a p-well can be formed in the region 50N, and an n-well can be formed in the region 50P. In some embodiments, a p-well or an n-well can be formed in the regions 50N and 50P. In embodiments with different well patterns, a photoresist or other mask (not shown) can be used to achieve different implantation steps for the regions 50N and 50P. For example, a photoresist can be formed over the fin 52 and the shallow trench isolation 56 in the region 50N. The photoresist is patterned to expose the region 50P (e.g., a p-type metal oxide semiconductor region) of the substrate 50. The photoresist can be formed by spin-on technology and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the region 50P, and the photoresist can act as a mask to generally prevent the n-type impurity from being implanted into the region 50N (e.g., an n-type metal oxide semiconductor region). The n-type impurity can be phosphorus, arsenic, antimony, or other similar substances, and is implanted into the region at a concentration equal to or less than 10 18 cm -3 in, for example, a concentration range between about 10 17 cm -3 and about 10 18 cm -3 . After the implantation, the photoresist is removed through, for example, an acceptable ashing process.

[0069] After implanting the region 50P, a photoresist is formed over the fin 52 and the shallow trench isolation 56 in the region 50P. The photoresist is patterned to expose the region 50N (e.g., an n-type metal oxide semiconductor region) of the substrate 50. The photoresist can be formed by spin-on technology and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implantation is performed in the region 50N, and the photoresist can act as a mask to generally prevent the p-type impurity from being implanted into the region 50P (e.g., a p-type metal oxide semiconductor region). The p-type impurity can be boron, boron difluoride, indium, or other similar substances, and is implanted into the region at a concentration equal to or less than 10 18 cm -3 in, for example, a concentration range between about 10 17 cm -3 and about 10 18 cm -3 . After the implantation, the photoresist is removed through, for example, an acceptable ashing process.

[0070] After implantation in regions 50N and 50P, annealing may be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, although in-situ and implant doping may be used together, the growth material of the epitaxial fins may be doped in-situ during growth, which may omit the implantation process.

[0071] In Figure 7 a dummy dielectric layer 60 is formed on fin 52. For example, the dummy dielectric layer 60 may be silicon oxide, silicon nitride, a combination of the foregoing, or other similar materials, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed above the dummy dielectric layer 60, and a mask layer 64 is formed above the dummy gate layer 62. The dummy gate layer 62 may be deposited above the dummy dielectric layer 60 and planarized (e.g., by chemical mechanical polishing). The mask layer 64 may be deposited above the dummy gate layer 62. The dummy gate layer 62 may be a conductive material and may be selected from the group including amorphous silicon, polycrystalline-silicon / polysilicon, poly-crystalline silicon-germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 may be deposited by physical vapor deposition (PVD), chemical vapor deposition, sputter deposition, or other techniques known in the art for depositing conductive materials. The dummy gate layer 62 may be made of other materials having a high etch selectivity compared to the etched isolation region. The mask layer 64 may include, for example, silicon nitride, silicon oxynitride, or other similar materials. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed over the entire regions 50N and 50P. It should be noted that the shown dummy dielectric layer 60 covering only the fin 52 is for illustrative purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited such that the dummy dielectric layer 60 covers the shallow trench isolation region 56 and extends between the dummy gate layer 62 and the shallow trench isolation region 56.

[0072] Figure 8A 、 8B Figures 9A, 9B, 10A, 10B, 10C, 10D, 11B, 11C, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 15C, 16A, 16B, 17A, and 17B illustrate various additional steps in manufacturing an exemplary device. Figure 8A 、 8B, 9A, 9B, 10A, 10B, 10C, 10D, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 15C, 16A, 16B, 17A, and 17B illustrate features in one of region 50N and region 50P. For example, Figure 8A , 8B , the structures shown in 9A, 9B, 10A, 10B, 10C, 10D, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 15C, 16A, 16B, 17A, and 17B can be applied to region 50N and region 50P. The structural differences (if any) in region 50N and region 50P will be described below in conjunction with the respective drawings in words. Figure 11B , 11C illustrates features in region 50P.

[0073] In Figure 8A , 8B , the mask layer 64 (see Figure 7 ) can be patterned using acceptable lithography and etching techniques to form mask 74. Then, the pattern of mask 74 can be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of mask 74 can also be transferred to the dummy dielectric layer 60 through acceptable etching techniques to form dummy gate 72. Dummy gate 72 covers each channel region 58 of fin 52. The pattern of mask 74 can be used to physically separate each of the dummy gates 72 from adjacent dummy gates. Dummy gate 72 can also have a longitudinal direction that is generally perpendicular to the longitudinal direction of each epitaxial fin 52. Dummy gate 72 is a sacrificial gate and will be replaced by a replacement gate later, which will be described in more detail below. Therefore, dummy gate 72 can also be referred to as a sacrificial gate. In other embodiments, dummy gate 72 is not replaced and remains in the final structure of the formed fin field-effect transistor device.

[0074] Additionally, in Figure 8A , 8BIn [the structure], a gate-sealing spacer 80 can be formed on the exposed surfaces of the dummy gate 72, the mask 74, and / or the fin 52. Anisotropic etching can be performed after thermal oxidation or deposition to form the gate-sealing spacer 80. After forming the gate-sealing spacer 80, doping of a lightly doped source / drain (LDD) region (not explicitly shown) can be carried out. In embodiments with different device configurations, similar to the implantation described in FIG. 6 above, a mask (such as a photoresist) can be formed over the region 50N, exposing the region 50P. Impurities of an appropriate type (such as p-type) can be implanted into the fins 52 in the region 50P, and then the photoresist can be removed. Next, a mask (such as a photoresist) can be formed over the region 50P, exposing the region 50N. Impurities of an appropriate type (such as n-type) can be implanted into the fins 52 in the region 50N, and then the photoresist can be removed. The n-type impurities can be any of the above-described n-type impurities, and the p-type impurities can be any of the above-described p-type impurities. The lightly doped source / drain region can have an impurity concentration between about 10 15 cm -3 and about 10 16 cm -3 . An annealing process can be used to activate the implanted impurities.

[0075] In Figure 9A , 9B , a gate spacer 86 is formed along the sidewalls of the dummy gate 72 and the mask 74 on the gate-sealing spacer 80. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon nitride, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxynitride (SiOCN), a combination of the foregoing, or other similar compounds. In some embodiments, the gate spacer 86 can include multiple layers (such as shown in Figure 11B , 11C ), and the foregoing layers include different materials.

[0076] In Figure 10A , 10B , an epitaxial source / drain region 82 is formed in the fin 52 to apply stress in each channel region 58, thereby improving the performance of the device. The epitaxial source / drain region 82 is formed in the fin 52 such that each dummy gate 72 is disposed between each adjacent pair of the epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain region 82 can extend into the fin 52 or penetrate the fin 52. In some embodiments, the gate spacer 86 is used to separate the epitaxial source / drain region 82 from the dummy gate 72 by an appropriate lateral distance such that the epitaxial source / drain region 82 does not form a short circuit with the subsequently formed gate of the fin field-effect transistor.

[0077] An epitaxial source / drain region 82 in region 50N (e.g., an n-type metal oxide semiconductor region) can be formed by masking region 50P (e.g., a p-type metal oxide semiconductor region) and etching the source / drain regions of fins 52 in region 50N to form a recess in fins 52. Then, the epitaxial source / drain region 82 in region 50N is epitaxially grown in the recess. The epitaxial source / drain region 82 can include any acceptable material, such as a material suitable for an n-type fin field effect transistor. For example, if fin 52 is silicon, the epitaxial source / drain region 82 in region 50N can include a material that applies tensile strain to channel region 58, such as silicon, silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon phosphide (SiP), or other similar materials. The epitaxial source / drain region 82 in region 50N can have a surface rising from each surface of fin 52 and can have a facet.

[0078] An epitaxial source / drain region 82 in region 50P (e.g., a p-type metal oxide semiconductor region) can be formed by masking region 50N (e.g., an n-type metal oxide semiconductor region) and etching the source / drain regions of fins 52 in region 50P to form a recess in fins 52. Then, the epitaxial source / drain region 82 in region 50P is epitaxially grown in the recess. The epitaxial source / drain region 82 can include any acceptable material, such as a material suitable for a p-type fin field effect transistor. For example, if fin 52 is silicon, the epitaxial source / drain region 82 in region 50P can include a material that applies compressive strain to channel region 58, such as silicon germanium, silicon germanium boron (SiGeB), germanium (Ge), germanium tin (GeSn), or other similar materials. The epitaxial source / drain region 82 in region 50P can have a surface rising from each surface of fin 52 and can have a facet.

[0079] Similar to the above process for forming lightly doped source / drain regions, the epitaxial source / drain region 82 and / or fin 52 can be implanted with dopants to form the source / drain regions, followed by an annealing process. The source / drain regions can have an impurity concentration between about 10 19 cm -3 and about 10 21 cm -3 . The n-type and / or p-type impurities for the source / drain regions can be any of the above impurities. In some embodiments, the epitaxial source / drain region 82 can be in-situ doped during growth.

[0080] After performing an epitaxial process for forming the epitaxial source / drain regions 82 in the regions 50N and 50P, the upper surface of the epitaxial source / drain regions has end faces that laterally extend outward beyond the sidewalls of the fins 52. In some embodiments, these end faces cause adjacent epitaxial source / drain regions 82 of the same fin field-effect transistor to merge into one body, as Figure 10C shown. In other embodiments, as Figure 10D shown, after the epitaxial process is completed, the adjacent epitaxial source / drain regions 82 remain separate.

[0081] In Figure 11B , 11C , detailed structures in the region 50P are shown respectively according to some embodiments, such as Figure 10B , 10C shown. The gate spacers 86 may include multiple layers, such as layers 86A, 86B. In some embodiments, the anisotropic etching process described with reference to Figure 9A , 9B does not completely remove the horizontal portions of the layers 86A, 86B from the isolation region 56 between the fins 52. In this embodiment, the isolation region 56 between the fins 52 is covered by the non-removed horizontal portions of the layers 86A, 86B.

[0082] Additionally, in Figure 11B , 11C , the epitaxial source / drain regions 82 in the region 50P include silicon germanium (Si x Ge 1-x doped with boron (B), where x can range from 0 to 1). In some embodiments, each of the epitaxial source / drain regions 82 includes a first layer 82A, a second layer 82B, a third layer 82C, and a fourth layer 82D. The second layer 82B may also be referred to as a diffusion barrier layer. The third layer 82C may also be referred to as a high-concentration layer. The fourth layer 82D may also be referred to as a cap layer or a protective layer. In some embodiments, the thickness of the fourth layer 82D is less than about 5 nm.

[0083] In some embodiments, the first layer 82A has non-connected portions corresponding to each of the fins 52. In some embodiments, the first layer 82A has a germanium concentration ranging from about 0 atomic percent (at%) to about 40 atomic percent. In some embodiments, the first layer 82A has a boron concentration ranging from about 10 19 atoms per cubic centimeter to about 10 21 atoms per cubic centimeter. In some embodiments, the second layer 82B has a non-planar top surface. In some embodiments, the second layer 82B has a germanium concentration ranging from about 20 atomic percent to about 80 atomic percent. In some embodiments, the second layer 82B has a concentration ranging from about 10 20from about 5×10 atoms per cubic centimeter to about 5×10 atoms per cubic centimeter of boron concentration. In some embodiments, the third layer 82C is a continuous layer lining the outer surface of the second layer 82B. In some embodiments, a portion of the third layer 82C extends into the second layer 82B such that a portion of the third layer 82C is inserted between portions of the second layer 82B. In some embodiments, the third layer 82C has a germanium concentration between about 20 atomic percent and about 100 atomic percent. In some embodiments, the third layer 82C has a boron concentration between about 5×10 atoms per cubic centimeter and about 10 atoms per cubic centimeter. 21 from about 5×10 atoms per cubic centimeter to about 10 atoms per cubic centimeter of boron concentration. In some embodiments, the fourth layer 82D is a continuous layer lining the outer surface of the third layer 82C. In some embodiments, the fourth layer 82D has a germanium concentration between about 0 atomic percent and about 40 atomic percent. In some embodiments, the fourth layer 82D has a boron concentration between about 5×10 atoms per cubic centimeter and about 10 atoms per cubic centimeter. 20 from about 5×10 atoms per cubic centimeter to about 10 atoms per cubic centimeter of boron concentration. 22 In some embodiments, the germanium concentration of the second layer 82B is greater than the germanium concentration of the first layer 82A. In some embodiments, the boron concentration of the second layer 82B is greater than the boron concentration of the first layer 82A. In some embodiments, the germanium concentration of the third layer 82C is greater than the germanium concentration of the second layer 82B. In some embodiments, the boron concentration of the third layer 82C is greater than the boron concentration of the second layer 82B. In some embodiments, the germanium concentration of the fourth layer 82D is less than the germanium concentration of the third layer 82C. In some embodiments, the boron concentration of the fourth layer 82D is less than the boron concentration of the third layer 82C. 19 from about 5×10 atoms per cubic centimeter to about 10 atoms per cubic centimeter of boron concentration. 21 of boron concentration.

[0084] In some embodiments, the germanium concentration of the second layer 82B is greater than the germanium concentration of the first layer 82A. In some embodiments, the boron concentration of the second layer 82B is greater than the boron concentration of the first layer 82A. In some embodiments, the germanium concentration of the third layer 82C is greater than the germanium concentration of the second layer 82B. In some embodiments, the boron concentration of the third layer 82C is greater than the boron concentration of the second layer 82B. In some embodiments, the germanium concentration of the fourth layer 82D is less than the germanium concentration of the third layer 82C. In some embodiments, the boron concentration of the fourth layer 82D is less than the boron concentration of the third layer 82C.

[0085] In some embodiments, a metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), a combination of the foregoing, or other similar processes are used to epitaxially grow the epitaxial source / drain regions 82. In some embodiments in which the epitaxial source / drain regions 82 are formed of boron-doped silicon germanium, the epitaxial growth process uses a suitable silicon precursor, a suitable germanium precursor, and a suitable boron precursor. The boron precursor provides a boron source for in-situ doping of the epitaxial source / drain regions 82 during the epitaxial growth process. In some embodiments, a suitable silicon precursor may be silane (SiH4), dichlorosilane (DCS), disilane (Si2H6), a combination of the foregoing, or other similar compounds. In some embodiments, a suitable germanium precursor may be germane (GeH4), digermane (Ge2H6), a combination of the foregoing, or other similar compounds. In some embodiments, a suitable boron precursor may be diborane (B2H6) or other similar compounds. In some embodiments, the flow rate of the silicon precursor is between about 0 standard cubic centimeter per minute (sccm) and about 1000 sccm. In some embodiments, the flow rate of the germanium precursor is between about 0 sccm and about 1000 sccm. In some embodiments, the flow rate of the boron precursor is between about 0 sccm and about 500 sccm. In some embodiments, the epitaxial growth process is performed at a temperature between about 400 °C and about 800 °C. In some embodiments, the epitaxial growth process is carried out at a pressure between about 0.1 Torr and 300 Torr.

[0086] In some embodiments, the first layer 82A, the second layer 82B, the third layer 82C, and the fourth layer 82D can be epitaxially grown by changing the temperatures and flow rates of, for example, a silicon precursor, a germanium precursor, and a boron precursor to obtain desired concentrations of germanium and boron within the first layer 82A, the second layer 82B, the third layer 82C, and the fourth layer 82D. In some embodiments, the epitaxial growth process for forming the first layer 82A is carried out at a temperature between about 400°C and about 800°C, wherein the flow rate ratio of the germanium precursor to the silicon precursor is between about 1 and about 4, and the flow rate ratio of the boron precursor to the silicon precursor is between about 0.1 and about 1. In some embodiments, the epitaxial growth process for forming the second layer 82B is carried out at a temperature between about 400°C and about 800°C, wherein the flow rate ratio of the germanium precursor to the silicon precursor is between about 1 and about 25, and the flow rate ratio of the boron precursor to the silicon precursor is between about 0.1 and about 5. In some embodiments, the epitaxial growth process for forming the third layer 82C is carried out at a temperature between about 400°C and about 800°C, wherein the flow rate ratio of the germanium precursor to the silicon precursor is between about 10 and about 40, and the flow rate ratio of the boron precursor to the silicon precursor is between about 1 and about 10. In some embodiments, the epitaxial growth process for forming the fourth layer 82D is carried out at a temperature between about 400°C and about 800°C, wherein the flow rate ratio of the germanium precursor to the silicon precursor is between about 1 and about 4, and the flow rate ratio of the boron precursor to the silicon precursor is between about 0.1 and about 1.

[0087] In Figure 12A , 12B the first interlayer dielectric (ILD) 88 is deposited on Figure 10A , 10BAbove the structure shown. The first interlayer dielectric layer 88 can be formed of a dielectric material and deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or other similar materials. Other insulating materials can be formed by any acceptable process that may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first interlayer dielectric layer 88 and the epitaxial source / drain regions 82, the mask 74, and the gate spacers 86. The contact etch stop layer 87 can include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or other similar materials, which have an etching rate different from that of the material of the overlying first interlayer dielectric layer 88.

[0088] In Figure 13A , 13B , a planarization process (such as chemical mechanical polishing) can be performed to make the top surface of the first interlayer dielectric layer 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 on the dummy gate 72 and portions of the gate seal spacers 80 and the gate spacers 86 that are laterally recessed along the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate seal spacers 80, the gate spacers 86, and the first interlayer dielectric layer 88 are flush. In this way, the top surface of the dummy gate 72 is exposed through the first interlayer dielectric layer 88. In some embodiments, the mask 74 can be retained when the planarization process makes the top surface of the first interlayer dielectric layer 88 flush with the top surface of the mask 74.

[0089] In Figure 14A , 14BIn one or more etching steps, dummy gate 72 and mask 74 (if present) are removed, thereby forming recess 90. A portion of dummy dielectric layer 60 in recess 90 may also be removed. In some embodiments, only dummy gate 72 is removed, while dummy dielectric layer 60 is retained and exposed in recess 90. In some embodiments, dummy dielectric layer 60 is removed from recess 90 in a first region (e.g., a core logic region) of the die and dummy dielectric layer 60 in recess 90 in a second region (e.g., an input / output region) of the die is retained. In some embodiments, dummy gate 72 is removed through an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches dummy gate 72 without etching first interlayer dielectric 88 or gate spacer 86. Each recess 90 exposes channel region 58 of each fin 52. Each channel region 58 is disposed between an adjacent pair of epitaxial source / drain regions 82. During removal, when etching dummy gate 72, dummy dielectric layer 60 can be used as an etch stop layer. Then, after removing dummy gate 72, dummy dielectric layer 60 can be selectively removed.

[0090] In Figure 15A , 15B a gate dielectric layer 92 and a gate electrode 94 are formed for replacing the gate. Figure 15C Illustrates Figure 15B a detailed view of region 89. Gate dielectric layer 92 is conformally deposited in recess 90 (see Figure 14A , 14B ), for example, on the top surface and sidewalls of fins 52 and on the sidewalls of gate seal spacer 80 / gate spacer 86. Gate dielectric layer 92 may also be formed on the top surface of first interlayer dielectric 88. In some embodiments, gate dielectric layer 92 includes silicon oxide, silicon nitride, or a multi-layer of the foregoing. In some embodiments, gate dielectric layer 92 includes a high dielectric constant (high-k) dielectric material, and in these embodiments, gate dielectric layer 92 may have a dielectric constant value (k value) greater than about 7.0. Gate dielectric layer 92 may include a metal oxide or a silicate of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), and combinations of the foregoing. The method of forming gate dielectric layer 92 may include molecular beam deposition (MBD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), and other similar processes. In embodiments where a portion of dummy dielectric layer 60 is retained in recess 90, gate dielectric layer 92 includes the material of dummy dielectric layer 60 (e.g., silicon dioxide (SiO2)).

[0091] Gate electrode 94 is deposited on gate dielectric layer 92 respectively and fills the remaining portion of recess 90 (see Figure 14A and 14B)。For example, although a single-layer gate electrode 94 is illustrated in FIG. 15B, the gate electrode 94 may include any number of liner layers 94A, any number of work function tuning layers 94B, and fill material 94C, as Figure 15C shown. The liner layer 94A may include titanium nitride (TiN), titanium oxide (TiO), tantalum nitride (TaN), tantalum carbide (TaC), combinations of the foregoing, multilayers of the foregoing, or other similar materials. In region 50N, the work function tuning layer 94B may include titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum aluminum carbide (TaAlC), manganese (Mn), zirconium (Zr), combinations of the foregoing, multilayers of the foregoing, or other similar materials. In region 50P, the work function tuning layer 94B may include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), combinations of the foregoing, multilayers of the foregoing, or other similar materials. The fill material 94C may include cobalt (Co), ruthenium (Ru), aluminum (Al), silver (Ag), gold (Au), tungsten (W), nickel (Ni), titanium (Ti), copper (Cu), manganese (Mn), palladium (Pd), rhenium (Re), iridium (Ir), platinum (Pt), zirconium (Zr), alloys of the foregoing, combinations of the foregoing, multilayers of the foregoing, or other similar materials. After filling the gate electrode 94, a planarization process (e.g., chemical mechanical polishing) may be performed to remove the excess portions of the gate dielectric layer 92 and the material of the gate electrode 94, where the foregoing excess portions are above the top surface of the first interlayer dielectric layer 88. Accordingly, the remaining portions of the materials of the gate electrode 94 and the gate dielectric layer 92 form the replacement gate of the resulting fin field effect transistor. The gate electrode 94 and the gate dielectric layer 92 may be collectively referred to as a "gate stack". The gate and the gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0092] The formation of the gate dielectric layer 92 in region 50N and region 50P may be performed simultaneously such that the gate dielectric layer 92 in each region is formed of the same material. The formation of the gate electrode 94 may also be performed simultaneously such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region may be formed through different processes such that the gate dielectric layer 92 may be different materials, and / or the gate electrode 94 in each region may be formed through different processes such that the gate electrode 94 may be different materials. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0093] In Figure 16A 、16B In 16B , a second interlayer dielectric layer 108 is deposited over the first interlayer dielectric layer 88. In some embodiments, the second interlayer dielectric layer 108 is a flowable thin film formed by a flowable chemical vapor deposition process. In some embodiments, the second interlayer dielectric layer 108 is formed of a dielectric material (such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or other similar materials), and can be deposited by any suitable method (such as chemical vapor deposition and plasma-enhanced chemical vapor deposition). In some embodiments, prior to forming the second interlayer dielectric layer 108, the gate stack (including the gate dielectric layer 92 and the corresponding overlying gate electrode 94) is recessed such that a recess is formed between directly above the gate stack and opposing portions of the gate spacers 86, as Figure 16A shown in 16B . The gate mask 96 includes one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or other similar materials) filled in the grooves, and then a planarization process is performed to remove the excess portion of the dielectric material extending above the first interlayer dielectric layer 88. The subsequently formed gate contact 110 (see Figure 17A shown in 17B ) penetrates the gate mask 96 to contact the top surface of the recessed gate electrode 94.

[0094] In Figure 17A shown in 17BIn accordance with some embodiments, gate contacts 110 and source / drain contacts 112 are formed to penetrate through the second interlayer dielectric layer 108 and the first interlayer dielectric layer 88. Openings for the source / drain contacts 112 are formed through the first interlayer dielectric layer 88 and the second interlayer dielectric layer 108, and openings for the gate contacts 110 are formed through the second interlayer dielectric layer 108 and the gate mask 96. Acceptable lithography and etching techniques can be used to form the openings. After forming the openings for the source / drain contacts 112, a silicide layer 114 is formed through the openings for the source / drain contacts 112. In some embodiments, a metal material is deposited in the openings for the source / drain contacts 112. The metal material can include titanium (Ti), cobalt (Co), nickel (Ni), cobalt nickel (NiCo), platinum (Pt), platinum nickel (NiPt), iridium (Ir), platinum iridium (PtIr), erbium (Er), ytterbium (Yb), palladium (Pd), rhodium (Rh), niobium (Nb), combinations of the foregoing, or other similar materials, and can be formed using physical vapor deposition, sputtering, or other processes. Subsequently, an annealing process is performed to form the silicide layer 114. In some embodiments where the epitaxial source / drain region 82 includes silicon, the annealing process causes the metal material to react with the silicon to form a silicide of the metal material at the interface between the metal material and the epitaxial source / drain region 82. After forming the silicide layer 114, an appropriate removal process is used to remove the unreacted portion of the metal layer. Subsequently, a liner (such as a diffusion barrier layer, a seed layer, or other similar layers) and a conductive material are formed in the openings for the source / drain contacts 112 and the openings for the gate contacts 110. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, or other similar materials. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or other similar materials. A planarization process (such as chemical mechanical polishing) can be performed to remove excess material from the surface of the second interlayer dielectric layer 108. The remaining liner and conductive material form the source / drain contacts 112 and the gate contacts 110 in the openings. The source / drain contacts 112 are physically and electrically coupled to the epitaxial source / drain region 82. The gate contacts 110 are physically and electrically coupled to the gate electrode 94. The source / drain contacts 112 and the gate contacts 110 can be formed in different processes, or can be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contacts 112 and the gate contacts 110 can be formed in different cross-sections, which can avoid short-circuiting of the contacts.

[0095] In Figure 18 is shown in detail in region 50P in accordance with some embodiments respectively in Figure 17A and 17B the structures shown in Figure 18 is along Figure 1It is illustrated by the reference cross-section C-C shown in [the figure]. In some embodiments, openings are formed for the source / drain contacts 112 such that the openings extend into the respective epitaxial source / drain regions 82. In some embodiments, each opening extends through the fourth layer 82D and exposes the third layer 82C of each epitaxial source / drain region 82. In other embodiments, each opening may partially extend into the third layer 82C of each epitaxial source / drain region 82. In some embodiments, the source / drain contacts 112 are electrically coupled to the third layer 82C through the silicide layer 114. Since the third layer 82C is a layer with a high concentration of germanium and boron, the impedance of the epitaxial source / drain region 82 is reduced. The width W1 of the source / drain contact 112 at the interface between the source / drain contact 112 and each epitaxial source / drain region 82 may be approximately equal to the pitch of the fins 52. In some embodiments, the width W1 is between about 20 nm and about 60 nm.

[0096] Figure 19 A cross-sectional view of a fin field-effect transistor according to some embodiments is shown. Figure 19 is taken along Figure 1 the reference cross-section C-C shown in [the figure], except for multi-fin / fin field-effect transistors. Figure 19 The structure shown is similar to Figure 18 the structure shown, where similar features are denoted by similar reference numerals and the similar features will not be repeated in this disclosure. In some embodiments, the structure shown in Figure 2 , 3 , 4, 5, 6, 7, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11B, 11C, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 15C, 16A, 16B, 17A and 17B can be formed using the process steps described above with reference to Figure 19 the structure shown, and will not be repeated in this disclosure. In the illustrated embodiment, the width W2 of the source / drain contact 112 at the interface between the source / drain contact 112 and each epitaxial source / drain region 82 may be less than the pitch of the fins 52. In some embodiments, the width W2 is between about 5 nm and about 20 nm.

[0097] Figure 20 A cross-sectional view of a fin field-effect transistor according to some embodiments is shown. Figure 20 is taken along Figure 1 the reference cross-section C-C shown in [the figure], except for multi-fin / fin field-effect transistors. Figure 20 The structure shown is similar to Figure 18The structures shown are similar, where similar features are denoted by similar reference numerals, and the similar features will not be described repeatedly in this disclosure. In some embodiments, the processes described above with reference to FIGS. 2, 3, 4, 5, 6, 7, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11B, 11C, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 15C, 16A, 16B, 17A, and 17B can be used to form Figure 20 the structure shown, and it will not be described repeatedly in this disclosure. In the embodiment shown, the width W3 of the source / drain contact 112 at the interface between the source / drain contact 112 and each epitaxial source / drain region 82 can be greater than the pitch of the fins 52. In some embodiments, the width W3 is between about 60 nm and about 100 nm.

[0098] Figure 21 FIG. 2100 is a flow chart illustrating a method 2100 of forming a semiconductor device according to some embodiments. Method 2100 begins at step 2101, where a sacrificial gate (e.g., Figure 8A and 8B the dummy gate 72 shown in FIGS.) is formed over an active region (e.g., Figure 8A and 8B as described above with reference to Figure 2 , 3 , 4, 5, 6, 7, 8A, and 8B. In step 2103, an epitaxial source / drain region (e.g., Figure 11B and 11C the epitaxial source / drain region 82 shown in FIGS.) is formed in the active region, as described above with reference to Figure 9A , 9B , 10A, 10B, 10C, 10D, 11B, and 11C. In step 2105, the sacrificial gate is replaced with a replacement gate (e.g., Figure 15A , 15B and the gate electrode 94 and the gate dielectric layer 92 shown in 15C), as described above with reference to Figure 12A , 12B , 13A, 13B, 14A, 14B, 15A, 15B, 15C. In step 2107, contact plugs (e.g., Figure 17A and 17B the source / drain contact 112 and the gate contact 110 shown in FIGS.) are formed, as described above with reference to Figure 16A , 16B , 17A, and 17B.

[0099] According to some embodiments, a semiconductor device includes: a gate stack and source / drain regions. The aforementioned gate stack is located above an active region. The aforementioned source / drain regions are located in the aforementioned active region and adjacent to the aforementioned gate stack, and the aforementioned source / drain regions include: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer. The aforementioned first semiconductor layer has a first germanium concentration. The aforementioned second semiconductor layer is located above the aforementioned first semiconductor layer, wherein the aforementioned second semiconductor layer has a second germanium concentration, and the aforementioned second germanium concentration is greater than the aforementioned first germanium concentration. The aforementioned third semiconductor layer is located above the aforementioned second semiconductor layer, wherein the aforementioned third semiconductor layer has a third germanium concentration, and the aforementioned third germanium concentration is greater than the aforementioned second germanium concentration. The aforementioned fourth semiconductor layer is located above the aforementioned third semiconductor layer, wherein the aforementioned fourth semiconductor layer has a fourth germanium concentration, and the aforementioned fourth germanium concentration is less than the aforementioned third germanium concentration.

[0100] In some embodiments, the aforementioned source / drain regions include silicon.

[0101] In some embodiments, the aforementioned first semiconductor layer has a first boron concentration.

[0102] In some embodiments, the aforementioned second semiconductor layer has a second boron concentration, and the aforementioned second boron concentration is greater than the aforementioned first boron concentration.

[0103] In some embodiments, the aforementioned third semiconductor layer has a third boron concentration, and the aforementioned third boron concentration is greater than the aforementioned second boron concentration.

[0104] In some embodiments, the aforementioned fourth semiconductor layer has a fourth boron concentration, and the aforementioned fourth boron concentration is less than the aforementioned third boron concentration.

[0105] In some embodiments, the aforementioned semiconductor device further includes a contact plug electrically coupled to the aforementioned source / drain regions, the aforementioned contact plug extending through the aforementioned fourth semiconductor layer and extending into the aforementioned third semiconductor layer.

[0106] In some embodiments, the aforementioned first semiconductor layer includes a plurality of non-connected portions.

[0107] In some embodiments, the aforementioned second semiconductor layer includes a continuous layer extending between adjacent non-connected portions of the aforementioned first semiconductor layer.

[0108] In some embodiments, a portion of the aforementioned third semiconductor layer is inserted between a plurality of portions of the aforementioned second semiconductor layer.

[0109] According to other embodiments, a semiconductor device includes: a gate stack, an epitaxial source / drain region, and a contact plug. The aforementioned gate stack is located above the active region. The aforementioned epitaxial source / drain region is located in the aforementioned active region and adjacent to the aforementioned gate stack. The aforementioned epitaxial source / drain region includes silicon germanium and includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer. The aforementioned first semiconductor layer has a first boron concentration. The aforementioned second semiconductor layer is located above the aforementioned first semiconductor layer, wherein the aforementioned second semiconductor layer has a second boron concentration, and the aforementioned second boron concentration is greater than the aforementioned first boron concentration. The aforementioned third semiconductor layer is located above the aforementioned second semiconductor layer, wherein the aforementioned third semiconductor layer has a third boron concentration, and the aforementioned third boron concentration is greater than the aforementioned second boron concentration. The aforementioned fourth semiconductor layer is located above the aforementioned third semiconductor layer, wherein the aforementioned fourth semiconductor layer has a fourth boron concentration, and the aforementioned fourth boron concentration is less than the aforementioned third boron concentration. The aforementioned contact plug is located above the aforementioned epitaxial source / drain region, wherein the aforementioned contact plug extends through the aforementioned fourth semiconductor layer and extends into the aforementioned third semiconductor layer.

[0110] In some embodiments, the aforementioned first semiconductor layer has a first germanium concentration.

[0111] In some embodiments, the aforementioned second semiconductor layer has a second germanium concentration, and the aforementioned second germanium concentration is greater than the aforementioned first germanium concentration.

[0112] In some embodiments, the aforementioned third semiconductor layer has a third germanium concentration, and the aforementioned third germanium concentration is greater than the aforementioned second germanium concentration.

[0113] In some embodiments, the aforementioned fourth semiconductor layer has a fourth germanium concentration, and the aforementioned fourth germanium concentration is less than the aforementioned third germanium concentration.

[0114] In some embodiments, the aforementioned semiconductor device further includes a silicide layer located between the aforementioned contact plug and the aforementioned third semiconductor layer, and the topmost surface of the aforementioned silicide layer is located below the topmost surface of the aforementioned third semiconductor layer.

[0115] According to some other embodiments, a method of manufacturing a semiconductor device includes: forming a gate stack over an active region; forming an opening in the active region and adjacent to the gate stack; and forming source / drain regions in the opening. Forming the source / drain regions includes: epitaxially growing a first semiconductor layer along a bottom and sidewalls of the opening, wherein the first semiconductor layer has a first germanium concentration; epitaxially growing a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a second germanium concentration, and the second germanium concentration is greater than the first germanium concentration; epitaxially growing a third semiconductor layer over the second semiconductor layer, wherein the third semiconductor layer has a third germanium concentration, and the third germanium concentration is greater than the second germanium concentration; and epitaxially growing a fourth semiconductor layer over the third semiconductor layer, wherein the fourth semiconductor layer has a fourth germanium concentration, and the fourth germanium concentration is less than the third germanium concentration.

[0116] In some embodiments, epitaxially growing the first semiconductor layer further includes in-situ doping the first semiconductor layer with boron, and the first semiconductor layer has a first boron concentration.

[0117] In some embodiments, epitaxially growing the second semiconductor layer further includes in-situ doping the second semiconductor layer with boron, the second semiconductor layer has a second boron concentration, and the second boron concentration is greater than the first boron concentration.

[0118] In some embodiments, epitaxially growing the third semiconductor layer further includes in-situ doping the third semiconductor layer with boron, the third semiconductor layer has a third boron concentration, and the third boron concentration is greater than the second boron concentration.

[0119] In some embodiments, epitaxially growing the fourth semiconductor layer further includes in-situ doping the fourth semiconductor layer with boron, the fourth semiconductor layer has a fourth boron concentration, and the fourth boron concentration is less than the third boron concentration.

[0120] In some embodiments, the method of manufacturing the semiconductor device further includes forming a contact plug over the source / drain regions, wherein the contact plug extends through the fourth semiconductor layer and extends into the third semiconductor layer.

[0121] In some embodiments, the method of manufacturing the semiconductor device further includes forming a silicide layer over the third semiconductor layer, physically contacting the third semiconductor layer, and the silicide layer is inserted between the contact plug and the third semiconductor layer before forming the contact plug.

[0122] The foregoing has outlined features of many embodiments so that those of ordinary skill in the art to which this disclosure pertains can better understand the various embodiments of this disclosure. Those of ordinary skill in the art to which this disclosure pertains should understand that other processes and structures can be readily designed or changed based on the embodiments of this disclosure to achieve the same purposes and / or attain the same advantages as the embodiments introduced herein. Those of ordinary skill in the art to which this disclosure pertains should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure. Various changes, substitutions, and alterations can be made to the embodiments of this disclosure without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A gate stack located above an active region; And A source / drain region located in the active region and adjacent to the gate stack, the source / drain region comprising: A first semiconductor layer having a first germanium concentration, wherein the first semiconductor layer has a first boron concentration; A second semiconductor layer located above the first semiconductor layer, wherein the second semiconductor layer has a second germanium concentration, and the second germanium concentration is greater than the first germanium concentration, wherein the second semiconductor layer has a second boron concentration, and the second boron concentration is greater than the first boron concentration; A third semiconductor layer located above the second semiconductor layer, wherein the third semiconductor layer has a third germanium concentration, and the third germanium concentration is greater than the second germanium concentration; and A fourth semiconductor layer located above the third semiconductor layer, wherein the fourth semiconductor layer has a fourth germanium concentration, and the fourth germanium concentration is less than the third germanium concentration.

2. The semiconductor device according to claim 1, wherein the first germanium concentration ranges from 0 atomic percent to 40 atomic percent.

3. The semiconductor device according to claim 1, wherein the second germanium concentration ranges from 20 atomic percent to 80 atomic percent.

4. The semiconductor device according to claim 1, wherein the third semiconductor layer has a third boron concentration, and the third boron concentration is greater than the second boron concentration.

5. The semiconductor device according to claim 4, wherein the fourth semiconductor layer has a fourth boron concentration, and the fourth boron concentration is less than the third boron concentration.

6. The semiconductor device according to claim 1, wherein the first semiconductor layer comprises a plurality of non-connected portions.

7. The semiconductor device according to claim 6, wherein the second semiconductor layer comprises a continuous layer extending between adjacent non-connected portions of the first semiconductor layer.

8. The semiconductor device according to claim 7, wherein a portion of the third semiconductor layer is inserted between a plurality of portions of the second semiconductor layer.

9. A semiconductor device, comprising: A gate stack located above an active region; An epitaxial source / drain region located in the active region and adjacent to the gate stack, the epitaxial source / drain region comprising silicon germanium, and comprising: A first semiconductor layer having a first boron concentration; A second semiconductor layer located above the first semiconductor layer, wherein the second semiconductor layer has a second boron concentration, and the second boron concentration is greater than the first boron concentration; A third semiconductor layer located above the second semiconductor layer, wherein the third semiconductor layer has a third boron concentration, and the third boron concentration is greater than the second boron concentration; and A fourth semiconductor layer located above the third semiconductor layer, wherein the fourth semiconductor layer has a fourth boron concentration, and the fourth boron concentration is less than the third boron concentration; and A contact plug located above the epitaxial source / drain region, wherein the contact plug extends through the fourth semiconductor layer and extends into the third semiconductor layer.

10. The semiconductor device according to claim 9, wherein the first semiconductor layer has a first germanium concentration.

11. The semiconductor device as claimed in claim 10, wherein the second semiconductor layer has a second germanium concentration, and the second germanium concentration is greater than the first germanium concentration.

12. The semiconductor device as claimed in claim 11, wherein the third semiconductor layer has a third germanium concentration, and the third germanium concentration is greater than the second germanium concentration.

13. The semiconductor device as claimed in claim 12, wherein the fourth semiconductor layer has a fourth germanium concentration, and the fourth germanium concentration is less than the third germanium concentration.

14. A method of manufacturing a semiconductor device, comprising: forming a gate stack over an active region; forming an opening in the active region adjacent to the gate stack; forming a source / drain region in the opening, and forming the source / drain region includes: epitaxially growing a first semiconductor layer along a bottom and a plurality of sidewalls of the opening, wherein the first semiconductor layer has a first germanium concentration; epitaxially growing a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a second germanium concentration, and the second germanium concentration is greater than the first germanium concentration; epitaxially growing a third semiconductor layer over the second semiconductor layer, wherein the third semiconductor layer has a third germanium concentration, and the third germanium concentration is greater than the second germanium concentration; and epitaxially growing a fourth semiconductor layer over the third semiconductor layer, wherein the fourth semiconductor layer has a fourth germanium concentration, and the fourth germanium concentration is less than the third germanium concentration; and forming a contact plug over the source / drain region, wherein the contact plug extends through the fourth semiconductor layer and extends into the third semiconductor layer.

15. The method of manufacturing a semiconductor device as claimed in claim 14, wherein epitaxially growing the first semiconductor layer further includes in-situ doping the first semiconductor layer with boron, and the first semiconductor layer has a first boron concentration.

16. The method of manufacturing a semiconductor device according to claim 15, wherein, Epitaxially growing the second semiconductor layer further includes in-situ doping the second semiconductor layer with boron, the second semiconductor layer has a second boron concentration, and the second boron concentration is greater than the first boron concentration.

17. The method of manufacturing a semiconductor device as claimed in claim 16, wherein epitaxially growing the third semiconductor layer further includes in-situ doping the third semiconductor layer with boron, the third semiconductor layer has a third boron concentration, and the third boron concentration is greater than the second boron concentration.

18. The method of manufacturing a semiconductor device as claimed in claim 17, wherein epitaxially growing the fourth semiconductor layer further includes in-situ doping the fourth semiconductor layer with boron, the fourth semiconductor layer has a fourth boron concentration, and the fourth boron concentration is less than the third boron concentration.

19. The method of manufacturing a semiconductor device as claimed in claim 14, further comprising forming a silicide layer over the third semiconductor layer before forming the contact plug, physically contacting the third semiconductor layer, and the silicide layer is inserted between the contact plug and the third semiconductor layer.

20. The method of manufacturing a semiconductor device as claimed in claim 14, wherein a portion of the contact plug extends below a top surface of the second semiconductor layer.

21. A semiconductor device, comprising: A source / drain region, located in an active region of a substrate, the source / drain region comprising: A first semiconductor layer, having a first germanium concentration, wherein the first semiconductor layer comprises a plurality of non-connected portions; A second semiconductor layer, located above the first semiconductor layer, wherein the second semiconductor layer has a second germanium concentration, and the second germanium concentration is greater than the first germanium concentration, wherein the second semiconductor layer comprises a continuous layer extending between adjacent non-connected portions of the first semiconductor layer; A third semiconductor layer, located above the second semiconductor layer, wherein the third semiconductor layer has a third germanium concentration, and the third germanium concentration is greater than the second germanium concentration; and A fourth semiconductor layer, located above the third semiconductor layer, wherein the fourth semiconductor layer has a fourth germanium concentration, and the fourth germanium concentration is less than the third germanium concentration.

22. The semiconductor device according to claim 21, wherein the first semiconductor layer has a first boron concentration.

23. The semiconductor device according to claim 22, wherein the second semiconductor layer has a second boron concentration, and the second boron concentration is greater than the first boron concentration.

24. The semiconductor device according to claim 23, wherein the third semiconductor layer has a third boron concentration, and the third boron concentration is greater than the second boron concentration.

25. The semiconductor device according to claim 24, wherein the fourth semiconductor layer has a fourth boron concentration, and the fourth boron concentration is less than the third boron concentration.

26. The semiconductor device according to claim 21, wherein a portion of the third semiconductor layer is inserted between portions of the second semiconductor layer.

27. The semiconductor device according to claim 21, further comprising a plurality of spacers disposed along each of the plurality of non-connected portions of the first semiconductor layer.

28. A semiconductor device, comprising: An epitaxial source / drain region, located in an active region of a substrate, the epitaxial source / drain region comprising silicon germanium, and comprising: A first semiconductor layer, having a first boron concentration; A second semiconductor layer, located above the first semiconductor layer, wherein the second semiconductor layer has a second boron concentration, and the second boron concentration is greater than the first boron concentration; A third semiconductor layer, located above the second semiconductor layer, wherein the third semiconductor layer has a third boron concentration, and the third boron concentration is greater than the second boron concentration; and A fourth semiconductor layer, located above the third semiconductor layer, wherein the fourth semiconductor layer has a fourth boron concentration, and the fourth boron concentration is less than the third boron concentration.

29. The semiconductor device according to claim 28, wherein the first semiconductor layer has a first germanium concentration.

30. The semiconductor device according to claim 29, wherein the second semiconductor layer has a second germanium concentration, and the second germanium concentration is greater than the first germanium concentration.

31. The semiconductor device according to claim 30, wherein the third semiconductor layer has a third germanium concentration, and the third germanium concentration is greater than the second germanium concentration.

32. The semiconductor device according to claim 31, wherein the fourth semiconductor layer has a fourth germanium concentration, and the fourth germanium concentration is less than the third germanium concentration.

33. The semiconductor device according to claim 28, wherein the first semiconductor layer includes a first portion and a second portion not connected to the first portion.

34. The semiconductor device according to claim 33, further comprising a spacer structure extending from a first sidewall of the first portion of the first semiconductor layer to a second sidewall of the second portion of the first semiconductor layer.

35. A method of manufacturing a semiconductor device, comprising: forming a gate stack over an active region of a substrate; forming an opening in the active region and adjacent to the gate stack; and forming a source / drain region in the opening, the source / drain region including silicon germanium, and forming the source / drain region includes: epitaxially growing a first semiconductor layer along a bottom and a plurality of sidewalls of the opening, wherein the first semiconductor layer has a first boron concentration; epitaxially growing a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer has a second boron concentration, and the second boron concentration is greater than the first boron concentration; epitaxially growing a third semiconductor layer over the second semiconductor layer, wherein the third semiconductor layer has a third boron concentration, and the third boron concentration is greater than the second boron concentration; and epitaxially growing a fourth semiconductor layer over the third semiconductor layer, wherein the fourth semiconductor layer has a fourth boron concentration, and the fourth boron concentration is less than the third boron concentration.

36. The method of manufacturing a semiconductor device according to claim 35, wherein the first semiconductor layer has a first germanium concentration.

37. The method of manufacturing a semiconductor device according to claim 36, wherein the second semiconductor layer has a second germanium concentration, and the second germanium concentration is greater than the first germanium concentration.

38. The method of manufacturing a semiconductor device according to claim 37, wherein the third semiconductor layer has a third germanium concentration, and the third germanium concentration is greater than the second germanium concentration.

39. The method of manufacturing a semiconductor device according to claim 38, wherein the fourth semiconductor layer has a fourth germanium concentration, and the fourth germanium concentration is less than the third germanium concentration.

40. The method of manufacturing a semiconductor device according to claim 35, wherein the first semiconductor layer includes a first portion and a second portion not connected to the first portion.

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