image sensor

Abstract

An image sensor includes a semiconductor substrate having a first surface and a second surface opposite the first surface; a photoelectric conversion layer in the semiconductor substrate; a transistor on the first surface of the semiconductor substrate; a first interlayer insulating layer on the transistor; a first lower pad electrode and a second lower pad electrode on the first interlayer insulating layer, the second lower pad electrode spaced apart from the first lower pad electrode; a molded insulating layer on the first lower pad electrode and the second lower pad electrode; a first lower electrode and a second lower electrode in the molded insulating layer; a dielectric layer on the first lower electrode and the second lower electrode; an upper electrode on the dielectric layer; and an upper pad electrode connected to the upper electrode and including a conductive material different from the first lower pad electrode and the second lower pad electrode. The first lower electrode is on the first lower pad electrode, and the second lower electrode is on the second lower pad electrode.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0118218, filed on October 4, 2018, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The exemplary embodiments of this disclosure relate to image sensors, and more specifically, to an image sensor capable of operating in a global shutter mode. Background Technology

[0004] An image sensor is a semiconductor device used to convert optical images into electrical signals. With the development of the computer and communications industries, there is a strong demand for high-performance image sensors in various devices such as digital cameras, camcorders, personal communication systems (PCS), gaming devices, security cameras, and / or medical miniature cameras. Image sensors for realizing 3D and color images have been developed. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, an image sensor may include: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a photoelectric conversion layer in the semiconductor substrate; a transistor on the first surface of the semiconductor substrate; a first interlayer insulating layer on the transistor; a first lower pad electrode and a second lower pad electrode on the first interlayer insulating layer, the second lower pad electrode being spaced apart from the first lower pad electrode; a molded insulating layer on the first lower pad electrode and the second lower pad electrode; the first lower electrode and the second lower electrode in the molded insulating layer; a dielectric layer on the first lower electrode and the second lower electrode; an upper electrode on the dielectric layer; and an upper pad electrode connected to the upper electrode. The first lower electrode may be on the first lower pad electrode. The second lower electrode may be on the second lower pad electrode. The upper pad electrode may include a conductive material different from the first lower pad electrode and the second lower pad electrode.

[0006] According to an exemplary embodiment of the present invention, an image sensor may include: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a photoelectric conversion layer in the semiconductor substrate; a transistor on the first surface of the semiconductor substrate; a first interlayer insulating layer on the transistor; a first wiring comprising a first metal material on the first interlayer insulating layer and connected to the transistor; a molded insulating layer on the first wiring; a capacitor in the molded insulating layer and connected to the transistor; a second interlayer insulating layer on the capacitor; and a second wiring comprising a second metal material on the second interlayer insulating layer and connected to the first wiring and the capacitor. The second metal material of the second wiring may have a resistivity lower than that of the first metal material of the first wiring.

[0007] According to example embodiments of the present inventive concept, an image sensor can include: a semiconductor substrate having a first surface and a second surface opposite the first surface; a pixel separation structure in the semiconductor substrate and defining a plurality of pixel regions; a photoelectric conversion layer in the semiconductor substrate in each of the plurality of pixel regions; a transistor on the first surface of the semiconductor substrate; a first interlayer insulating layer on the transistor; and a first capacitor and a second capacitor on the first interlayer insulating layer and overlapping the photoelectric conversion layer in each of the plurality of pixel regions. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram of an image processing device according to some embodiments of the present inventive concept.

[0009] Figure 2 is a block diagram of an image sensor according to some embodiments of the present inventive concept.

[0010] Figure 3 is a schematic block diagram of a pixel array of an image sensor according to some embodiments of the present inventive concept.

[0011] Figure 4A 、 Figure 4B and Figure 4C are circuit diagrams showing a unit pixel of a pixel array according to some embodiments of the present inventive concept.

[0012] Figure 5 is a plan view of an image sensor according to some embodiments of the present inventive concept.

[0013] Figure 6A and Figure 6B are cross-sectional views taken along lines I-I' and II-II' of Figure 5 respectively, showing an image sensor according to some embodiments of the present inventive concept.

[0014] Figure 7 is an enlarged view of portion A of Figure 6A .

[0015] Figure 8A and Figure 8B are cross-sectional views taken along lines I-I' and II-II' of Figure 5 respectively, showing an image sensor according to some embodiments of the present inventive concept.

[0016] Figure 9 is a cross-sectional view taken along line I-I' of Figure 5 showing an image sensor according to some embodiments of the present inventive concept.

[0017] Figure 10A is a plan view of an image sensor according to some embodiments of the inventive concept.

[0018] Figure 10B is a cross-sectional view taken along line III-III' of Figure 10A

[0019] Figures 11 to 18 is a cross-sectional view taken along line I-I' of Figure 5 DETAILED DESCRIPTION

[0020] The inventive concept will now be described more fully with reference to the accompanying drawings, showing example embodiments of the inventive concept. Like reference numerals can be used to refer to like elements throughout this embodiment. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be noted that aspects described with respect to one embodiment can be incorporated into different embodiments although not specifically described with respect to each. That is, features of all embodiments and / or any embodiment can be combined in any way and / or combination.

[0021] Figure 1 is a block diagram of an image processing apparatus according to some embodiments of the inventive concept.

[0022] Referring to Figure 1 , the image processing apparatus 1000 can include an image sensor 110, an image signal processing unit (ISP) 120, a display apparatus 130, and a storage apparatus 140.

[0023] The image processing apparatus 1000 can be any type of electronic apparatus configured to acquire an external image, such as a smart phone or a digital camera.

[0024] The image sensor 110 can convert an image of an external object into an electrical signal or a data signal. The image sensor 110 can include a plurality of pixels. Each pixel can receive light reflected from an external object and can convert the received light into an electrical image signal or a photoelectric signal.

[0025] The image signal processing unit 120 can perform signal processing on frame data (e.g., image data or photoelectric data) FR received from the image sensor 110 and can output corrected image data IMG. For example, the image signal processing unit 120 can generate the image data IMG by performing signal processing operations such as color interpolation, color correction, gamma correction, color space conversion, and / or edge correction on the received frame data FR.

[0026] ​​The display apparatus 130 can output the image data IMG from the image signal processing unit 120 so that a user can perform an inspection. The display apparatus 130 can include one or more displays such as a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, and an electrowetting display panel. The display apparatus 130 can output the image data IMG through the display panel.

[0027] The storage apparatus 140 can be configured to store the image data IMG output from the image signal processing unit 120. The storage apparatus 140 can include a volatile memory such as SRAM, DRAM, synchronous DRAM, a non-volatile memory such as ROM, EPROM, EEPROM, a flash memory apparatus, PRAM, MRAM, RRAM, and / or FRAM.

[0028] Figure 2 is a block diagram of an image sensor according to some embodiments of the inventive concept.

[0029] Referring to Figure 2 , the image sensor 110 can include a pixel array 10, a row decoder 20, a row driver 30, a column decoder 40, a timing generator 50, a correlated double sampler (CDS) 60, an analog-to-digital converter (ADC) 70, and an input / output (I / O) buffer 80.

[0030] The pixel array 10 can include a plurality of unit pixels arranged in rows and columns and can convert light incident on the unit pixels into an electrical signal. The pixel array 10 can be driven by a plurality of driving signals (e.g., a selection signal, a reset signal, and a charge transfer signal) provided from the row decoder 20.

[0031] The row decoder 20 can provide the driving signals to each of the unit pixels. The electrical signal converted in the pixel array 10 in response to the driving signals can be provided to the correlated double sampler 60.

[0032] The row driver 30 can provide a plurality of driving signals for driving a plurality of unit pixels to the pixel array 10 based on a result of decoding in the row decoder 20. When the unit pixels are arranged in rows and columns, the driving signals can be provided to each of the unit pixels.

[0033] The timing generator 50 can control the row decoder 20 and the column decoder 40, the correlated double sampler 60, the analog-to-digital converter 70, and the input / output buffer 80, and can supply a control signal such as a clock signal or a timing control signal used for operations of driving them. The timing generator 50 can include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, and a communication interface circuit.

[0034] The correlated double sampler 60 can receive, hold, and sample the electrical signal generated from the pixel array 10. The correlated double sampler 60 can double sample the signal level by sampling a specific noise level and an electrical signal level, and can output the difference level corresponding to the difference between the noise level and the electrical signal level.

[0035] The analog-to-digital converter 70 can convert the analog signal corresponding to the difference level output from the correlated dual sampler 60 into a digital signal, and can output a digital signal.

[0036] The input / output buffer 80 can latch the digital signal output from the analog-to-digital converter 70, and the latched signal can be sequentially output to the image signal processing unit based on the decoding result in the column decoder 40.

[0037] Figure 3 This is a schematic block diagram of a pixel array of an image sensor according to some embodiments of the present invention.

[0038] Reference Figure 3 The pixel array 10 may include multiple unit pixels P arranged in two dimensions along multiple rows and multiple columns, multiple drive signal lines SL, and multiple output lines Vout.

[0039] An electrical signal can be generated in each of the unit pixels P by incident light. The unit pixel P can be driven by a drive signal sent through a drive signal line SL connected to the unit pixel P.

[0040] The drive signal line SL can be in the row direction ( Figure 3 The signal line SL extends horizontally in the block diagram so that unit pixels P in the same row can be driven substantially simultaneously. In some embodiments, the drive signal line SL may include a transfer signal line, a reset signal line, a sampling signal line, a calibration signal line, a precharge signal line, and a selection signal line. The transfer signal line, reset signal line, and selection signal line may be connected together to unit pixels P in the same row. The output line Vout may extend in the column direction (in the horizontal direction of the block diagram) to allow for the driving of unit pixels P in the same row. Figure 3 The unit pixels P that extend vertically in the block diagram and can be connected together to the same column.

[0041] Each of the unit pixels P may include a photoelectric conversion device and a plurality of metal-oxide-semiconductor (MOS) transistors constituting readout and sampling circuits.

[0042] The photoelectric conversion device of a unit pixel P can generate photoelectric charge in proportion to the amount of light incident from the outside. The generated photoelectric charge can be converted into a voltage in proportion to the amount of generated photoelectric charge, and the voltage can be stored. Therefore, in some embodiments, in each of the unit pixels P, the generated photoelectric charge can be converted into a voltage in proportion to the amount of generated photoelectric charge, and the voltage can be stored.

[0043] The unit pixel P can include a sampling circuit configured to hold and sample photoelectric charges generated from the photoelectric conversion device. Accordingly, the image sensor according to an example embodiment can be configured to operate in a global shutter mode. When the image sensor operates, all the unit pixels P are exposed at substantially the same time, so that photoelectric charges are stored in each of the unit pixels P at substantially the same time, and pixel signals can be sequentially outputted row by row.

[0044] In some embodiments, the unit pixels P can have the same circuit configuration, and these embodiments will be described in more detail with reference to Figure 4A 、 Figure 4B and Figure 4C .

[0045] Figure 4A 、 Figure 4B and Figure 4C are circuit diagrams showing a unit pixel of a pixel array according to example embodiments of the inventive concept.

[0046] With reference to Figure 4A , the image sensor according to an example embodiment can have an in-pixel correlated double sampling structure.

[0047] Each of the unit pixels P can include a photoelectric conversion device PD, a transfer transistor TX, a reset transistor RX, a first source follower transistor SF1, a pre-charge transistor PC, a sampling transistor SAM, a calibration transistor CAL, a second source follower transistor SF2, a selection transistor SEL, a first capacitor C1, and a second capacitor C2.

[0048] The transfer transistor TX can be connected between the photoelectric conversion device PD and a charge detection node (i.e., a floating diffusion region) FD. The transfer transistor TX can transfer the charge accumulated in the photoelectric conversion device PD to the charge detection node FD. The transfer transistor TX can operate in response to a charge transfer signal input to a transfer gate electrode.

[0049] The photoelectric conversion device PD can generate photoelectric charges in proportion to an amount of light incident from the outside and can accumulate the photoelectric charges. The photoelectric conversion device PD can include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0050] The charge detection node FD can receive the charge generated from the photoelectric conversion device PD and can cumulatively store the charge. A potential of a gate electrode of the first source follower transistor SF1 can vary based on an amount of the photoelectric charges accumulated in the charge detection node FD.

[0051] The reset transistor RX can periodically reset the photoelectric charge accumulated in the charge detection node FD. The reset transistor RX can operate in response to a reset signal input to a gate electrode thereof. A drain of the reset transistor RX can be connected to the charge detection node FD. A source of the reset transistor RX can be connected to a power supply voltage Vpix. When the reset transistor RX is turned on, the power supply voltage Vpix connected to the source of the reset transistor RX can be applied to the charge detection node FD. In other words, when the reset transistor RX is turned on, the photoelectric charge accumulated in the charge detection node FD can be discharged so that the charge detection node can be reset.

[0052] The first source follower transistor SF1 can be a source follower buffer amplifier for generating a source-drain current in proportion to an amount of photoelectric charge input to a gate electrode thereof.

[0053] A drain of the first source follower transistor SF1 can be connected to the power supply voltage Vpix. A source of the first source follower transistor SF1 can be connected to a source of the pre-charge transistor PC and a source of the sampling transistor SAM.

[0054] The sampling transistor SAM can be connected between the source of the first source follower transistor SF1 and a first node n1.

[0055] First electrodes of the first capacitor C1 and the second capacitor C2 can be connected to the first node n1. A capacitor voltage Vc can be applied to a second electrode of the first capacitor C1, and a second electrode of the second capacitor C2 can be connected to a second node n2.

[0056] A drain of the calibration transistor CAL can be connected to the power supply voltage Vpix. A source of the calibration transistor CAL can be connected to the second node n2. The calibration transistor CAL can calibrate the second node n2.

[0057] A gate electrode of the second source follower transistor SF2 can be connected to the second node n2. A drain of the second source follower transistor SF2 can be connected to the power supply voltage Vpix. A source of the second source follower transistor SF2 can be connected to a drain of the selection transistor SEL.

[0058] The second source follower transistor SF2 can amplify a change in potential in the second node n2 and can output a pixel signal to an output line Vout through the selection transistor SEL.

[0059] The operation of the unit pixel P can include a reset phase of resetting the photoelectric conversion device PD and the charge detection node FD, an optical accumulation phase of accumulating photoelectric charge in the photoelectric conversion device PD, and a sampling phase of outputting the accumulated photoelectric charge as a pixel signal. The sampling phase can include a reset signal sampling phase and an image signal sampling phase.

[0060] In the reset phase, the reset transistor RX and the transfer transistor TX can be turned on. Thus, the pixel power voltage Vpix can be applied to the charge detection node FD, so that the charge can be discharged from the photoelectric conversion device PD and the charge detection node FD to reset the photoelectric conversion device PD and the charge detection node FD.

[0061] After the photoelectric conversion device PD and the charge detection node FD are reset, in a time interval from the transfer transistor TX being turned off until the transfer transistor TX is turned on (for example, during a photoelectric conversion time), photoelectric charges can be generated and accumulated in the photoelectric conversion device PD.

[0062] After the optical accumulation phase, the charge detection node FD can be reset to the pixel power voltage Vpix. The reset signal can include a noise component. The reset signal including the noise component can be amplified in the first source follower transistor SF1.

[0063] In the reset signal sampling phase, the sampling transistor SAM can be turned on, and the first capacitor C1 and the second capacitor C2 can sample the reset signal.

[0064] At the start of the reset signal sampling phase, the first capacitor C1 and the second capacitor C2 can erase their previously sampled voltages and can be pre-charged, so that the first source follower transistor SF1 can sample a new voltage. Such a pre-charging operation can be performed using the pre-charging transistor PC. In the reset signal sampling phase, the calibration transistor CAL can be turned off.

[0065] After the reset signal sampling phase, the transfer transistor TX can be turned on again, and the image signal detected in the charge detection node FD can not include noise.

[0066] In the image signal sampling phase, the sampling transistor SAM can be turned on, and the first capacitor C1 and the second capacitor C2 can sample the image signal. Here, the voltage of the first capacitor C1 can be a voltage value proportional to the amount of charge transferred by the transfer transistor TX. Thus, the value of the voltage across the first capacitor C1 can be a new voltage value different from the previous reset signal.

[0067] In the image signal sampling phase, the second node n2 of the second capacitor C2 can be floating, and the amount of charge of the second capacitor C2 can be maintained as the amount of charge in the previous reset signal sampling phase. The second node n2 of the second capacitor C2 can drop from the calibrated voltage (for example, Vpix) by the same range as the voltage drop on the first node n1 of the second capacitor C2.

[0068] Since the second node n2 of the second capacitor C2 can be calibrated to a calibrated voltage (e.g., Vpix) in the reset signal sampling phase, a noise component can not be included. Thus, the pixel signal Vout can be sent to an analog-to-digital converter without a noise component.

[0069] In the image signal sampling phase, the second capacitor C2 can be charged to a voltage corresponding to a difference between an image signal generated from the pixel P and a voltage charged in the reset signal sampling phase (e.g., the reset signal Vres).

[0070] In each of the pixels P, the image signal level of a certain noise level and the image can be double-sampled, and thus, a pixel signal Vout corresponding to a difference between the noise level and the image signal level can be output from each of the pixels P. In other words, in each of the pixels P, a voltage proportional to a difference between a potential of the charge detection node FD in a reset state and a potential of the charge detection node FD based on a photocharge generated by the image signal can be generated.

[0071] According to an example embodiment of Figure 4B , a unit pixel P can include first and second photoelectric conversion devices PD1 and PD2 and first and second charge transfer transistors TX1 and TX2. The first and second transfer transistors TX1 and TX2 can share a charge detection node FD. The first and second transfer transistors TX1 and TX2 can operate in response to a charge transfer signal.

[0072] According to an example embodiment of Figure 4C , a unit pixel P can include first, second, third, and fourth photoelectric conversion devices PD1, PD2, PD3, and PD4 and first, second, third, and fourth charge transfer transistors TX1, TX2, TX3, and TX4. The first to fourth charge transfer transistors TX1, TX2, TX3, and TX4 can share a charge detection node FD. The first, second, third, and fourth charge transfer transistors TX1, TX2, TX3, and TX4 can operate individually in response to a charge transfer signal.

[0073] Figure 5 is a plan view of an image sensor according to some embodiments of the inventive concept. Figure 6A and Figure 6B are cross-sectional views taken along lines I-I' and II-II' of Figure 5 , respectively, showing an image sensor according to some embodiments of the inventive concept. Figure 7 is a magnified view of part A of Figure 6A .

[0074] Referring to Figure 5 , Figure 6A and Figure 6B , an image sensor according to example embodiments can include a photoelectric conversion layer 100, an integrated circuit layer 200, and a light transmission layer 300. As shown in Figure 6A and Figure 6B , the photoelectric conversion layer 100 can be disposed between the integrated circuit layer 200 and the light transmission layer 300 in a vertical direction.

[0075] The photoelectric conversion layer 100 can include a semiconductor substrate 101, a pixel separation structure 103 defining a pixel region PR, and a photoelectric conversion region 111 in the semiconductor substrate 101.

[0076] The semiconductor substrate 101 can have a first surface (or front surface) 101a and a second surface (or back surface) 101b opposite to each other. The semiconductor substrate 101 can be a substrate in which an epitaxial layer of a first conductive type is formed on a bulk silicon substrate of the first conductive type (e.g., p-type). In some embodiments, the semiconductor substrate 101 can be a substrate in which the bulk silicon substrate can be removed and the p-type epitaxial layer can be retained during fabrication of the image sensor. In some embodiments, the semiconductor substrate 101 can be a bulk semiconductor substrate including a well of the first conductive type.

[0077] The pixel separation structure 103 can be disposed in the semiconductor substrate 101 and can define a plurality of pixel regions PR arranged in a matrix form along a first direction D1 and a second direction D2. In a plan view, the pixel separation structure 103 can at least partially surround each of the pixel regions PR. The pixel separation structure 103 can include a first portion extending in parallel along the first direction D1 and a second portion crossing the first portion and extending in parallel along the second direction D2.

[0078] The pixel separation structure 103 can be formed of an insulating material having a refractive index lower than that of the semiconductor substrate (e.g., silicon substrate) 101, and can include one or more insulating layers. For example, the pixel separation structure 103 can include a silicon oxide layer, a silicon nitride layer, an undoped polysilicon layer, air, or a combination thereof. In some embodiments, the pixel separation structure 103 can be an impurity region formed by doping a first conductive type impurity into the first conductive type semiconductor substrate 101.

[0079] The pixel separation structure 103 can penetrate (or extend through) the semiconductor substrate 101. A vertical thickness of the pixel separation structure 103 can be substantially the same as a vertical thickness of the semiconductor substrate 101. In some embodiments, in a cross-sectional view, the vertical thickness of the pixel separation structure 103 can be smaller than the vertical thickness of the semiconductor substrate 101.

[0080] The isolation structure 105 can penetrate the semiconductor substrate 101 in each pixel region PR and can define a light-receiving region R1 and a light-blocking region R2. Each pixel region PR can include the light-receiving region R1 and the light-blocking region R2. The isolation structure 105 can extend in the first direction D1 or the second direction D2.

[0081] The isolation structure 105 can have substantially the same structure as the pixel separation structure 103. The isolation structure 105 can be formed of an insulating material having a refractive index lower than that of the semiconductor substrate (e.g., a silicon substrate) 101 and can include one or more insulating layers.

[0082] The photoelectric conversion region 111 can be provided in the light-receiving region R1 of each pixel region PR. The photoelectric conversion region 111 can be formed by implanting an impurity having a second conductivity type opposite to the first conductivity type of the semiconductor substrate 101 in the semiconductor substrate 101.

[0083] A photodiode can be formed at a junction of the semiconductor substrate 101 of the first conductivity type and the photoelectric conversion region 111 of the second conductivity type. Light incident from the outside can be converted into an electric signal in the photoelectric conversion region 111.

[0084] The device insulating layer 107 can be provided adjacent to the first surface 101a of the semiconductor substrate 101 and can define an active region.

[0085] The integrated circuit layer 200 can be provided on the first surface 101a of the semiconductor substrate 101. The integrated circuit layer 200 can include a readout circuit and a sampling circuit electrically connected to the photoelectric conversion region 111. As described with reference to Figure 3 the integrated circuit layer 200 can include a reset transistor RX, a first source follower transistor SF1 and a second source follower transistor SF2, a sampling transistor SAM, a precharge transistor PC, a calibration transistor CAL, a selection transistor SEL, and a first capacitor C1 and a second capacitor C2.

[0086] As an example, the transfer transistor TX, the reset transistor RX, and the first follower transistor SF1 can be provided in the light-receiving region R1, and the sampling transistor SAM, the precharge transistor PC, the calibration transistor CAL, the selection transistor SEL, and the second source follower transistor SF2 can be provided in the light-blocking region R2.

[0087] In each pixel region PR, the transfer gate electrode TG and the gate electrode GE of the MOS transistor described with reference to Figure 3 may be provided on the first surface 101a of the semiconductor substrate 101.

[0088] A portion of the transfer gate TG can be provided in the semiconductor substrate 101, and a gate insulating layer can be interposed between the transfer gate electrode TG and the semiconductor substrate 101.

[0089] The gate electrodes TG and GE of the transistor can include one or more materials, such as doped polysilicon, metal silicide (such as cobalt silicide), metal nitride (such as titanium nitride), and metal (such as tungsten, copper, or aluminum). The gate insulating layer can include one or more materials, such as silicon oxide, silicon nitride, insulating metal oxide, and / or insulating metal nitride.

[0090] The floating diffusion region FD can be provided on one side of the transfer gate electrode TG in the semiconductor substrate 101. Referring to FIG. 1, the floating diffusion region FD can be provided on the side of the transfer gate electrode TG in the semiconductor substrate 101. Figure 3 The source / drain impurity region 101sd of the MOS transistor can be provided in the semiconductor substrate 101.

[0091] The floating diffusion region FD and the source / drain impurity region 101sd can be formed by implanting an impurity having a conductivity type opposite to that of the semiconductor substrate 101. For example, the floating diffusion region FD and the source / drain impurity region 101sd can be n-type impurity regions.

[0092] The first interlayer insulating layer 210 can at least partially cover the first surface 101a of the semiconductor substrate 101 and can at least partially cover the MOS transistor. The first wiring 211 can be provided on the first interlayer insulating layer 210. The first wiring 211 can be electrically connected to the MOS transistor through the first contact plug CP1.

[0093] The second interlayer insulating layer 220 can be provided on the first interlayer insulating layer 210 and can at least partially cover the first wiring 211. For example, the first interlayer insulating layer 210 and the second interlayer insulating layer 220 can include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0094] The first lower pad electrode 222a and the second lower pad electrode 222b and the second wiring 221 can be provided on the second interlayer insulating layer 220. The first lower pad electrode 222a and the second lower pad electrode 222b can be spaced apart from each other in each pixel region PR. The first lower pad electrode 222a and the second lower pad electrode 222b can each have a plate shape. In a plan view, the first lower pad electrode 222a and the second lower pad electrode 222b can overlap the photoelectric conversion region 111.

[0095] The second wiring 221 can be selectively connected to some of the first wirings 211 through the second contact plugs CP2. The second lower pad electrode 222b can be connected to the first wiring 211 through any of the second contact plugs CP2. The second lower pad electrode 222b can be electrically connected to the gate electrode of the second source follower transistor and the source / drain impurity region 101sd of the calibration transistor through the first contact plug CP1 and the second contact plug CP2 and the first wiring 211.

[0096] The second wiring 221 and the first lower pad electrode 222a and the second lower pad electrode 222b can include a first metal material, for example, a metal such as tungsten or titanium and / or an electrically conductive metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride.

[0097] The first lower pad electrode 222a and the second lower pad electrode 222b, which are in a plate shape, can reflect light incident through the semiconductor substrate 101 so that the reflected light can be incident on the photoelectric conversion region 111 again.

[0098] The molded insulating layer 230 can be disposed on the second interlayer insulating layer 220 to at least partially cover the second wiring 221 and the first lower pad electrode 222a and the second lower pad electrode 222b.

[0099] The molded insulating layer 230 can have a plurality of openings exposing the first lower pad electrode 222a and the second lower pad electrode 222b. The molded insulating layer 230 can include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0100] Lower electrodes 231a and 231b can be disposed in the openings, respectively. In some embodiments, the lower electrodes 231a and 231b include a plurality of first lower electrodes 231a located on the first lower pad electrode 222a and a plurality of second lower electrodes 231b located on the second lower pad electrode 222b.

[0101] The first lower electrodes 231a can be arranged on the first lower pad electrode 222a along both the first direction D1 and the second direction D2. Adjacent first lower electrodes 231a and adjacent second lower electrodes 231b can be arranged to be offset with respect to each other. The first lower electrodes 231a can be arranged on the first lower pad electrode 222a in a zigzag pattern or a honeycomb shape. The second lower electrodes 231b can be arranged on the second lower pad electrode 222b in a zigzag pattern or a honeycomb shape. For example, centers of at least three adjacent first lower electrodes 231a arranged in the first direction D1 or the second direction D2 can be arranged at the same interval, and centers of at least three adjacent second lower electrodes 231b arranged in the first direction D1 or the second direction D2 can be arranged at the same interval.

[0102] Since the first lower electrodes 231a and the second lower electrodes 231b are arranged in a zigzag pattern or a honeycomb shape, a diameter of each of the first lower electrodes 231a and the second lower electrodes 231b can increase, and an integration density of the first lower electrodes 231a and the second lower electrodes 231b can increase. In some embodiments, the first lower electrodes 231a and the second lower electrodes 231b can be arranged in a matrix form at a predetermined interval along the first direction and the second direction.

[0103] As an example, each of the first lower electrodes 231a and the second lower electrodes 231b can at least partially cover an inner surface of each of the openings, and can have a cup shape. Each of the first lower electrodes 231a and the second lower electrodes 231b can have a cylindrical shape having a bottom portion for defining a blank space and a sidewall portion extending vertically from the bottom portion. An upper surface of the first lower electrodes 231a and the second lower electrodes 231b can be substantially coplanar with an upper surface of the molded insulating layer 230.

[0104] The dielectric pattern 233 and the upper electrode 235 can be sequentially disposed on the molded insulating layer 230 to conformally at least partially cover the first lower electrodes 231a and the second lower electrodes 231b. The dielectric pattern 233 can be formed to have a substantially uniform thickness to at least partially cover inner surfaces of the first lower electrodes 231a and the second lower electrodes 231b. The upper electrode 235 can be located on the dielectric pattern 233 to at least partially cover the first lower electrodes 231a and the second lower electrodes 231b.

[0105] The upper electrode 235 can at least partially cover a surface of the dielectric pattern 233 with a substantially uniform thickness. As an example, referring to Figure 7 The upper electrode 235 can define a gap region G in the openings of the molded insulating layer 230.

[0106] The first lower electrodes 231a and the second lower electrodes 231b and the upper electrode 235 can include a refractory metal (e.g., cobalt, titanium, nickel, tungsten, or molybdenum) and / or a metal nitride (e.g., titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, or tungsten nitride).

[0107] For example, the dielectric pattern 233 can include a metal oxide such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, or TiO2, a dielectric material having a perovskite structure such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, or PLZT, or a combination thereof. The dielectric pattern 233 can be monolithic or can include one or more layers.

[0108] An upper pad electrode 237 can be disposed on the upper electrode 235. The upper pad electrode 237 can include a doped semiconductor material or a conductive material different from that of the upper electrode 235. For example, the upper pad electrode 237 can include polysilicon and / or silicon germanium doped with an impurity, and / or a metal such as tungsten, copper, aluminum, titanium, and / or tantalum.

[0109] In a plan view, the upper pad electrode 237 can overlap one or both of the first lower pad electrode 222a and the second lower pad electrode 222b. The thickness of the upper pad electrode 237 can be greater than that of each of the first lower pad electrode 222a and the second lower pad electrode 222b. The upper pad electrode 237 can directly contact a portion of the upper electrode 235 on the molded insulating layer 230, and can be spaced apart from (or not contact) other portions of the upper electrode 235 on the inner surfaces of the openings of the molded insulating layer 230, as shown. Figure 7

[0110] In some embodiments, the upper pad electrode 237, the first lower pad electrode 222a, and the first lower electrode 231a, the dielectric pattern 233, and the upper electrode 235 therebetween can constitute a first capacitor (see C1 of FIG. 1B). The upper pad electrode 237, the second lower pad electrode 222b, and the second lower electrode 231b, the dielectric pattern 233, and the upper electrode 235 therebetween can constitute a second capacitor (see C2 of FIG. 1B). The upper pad electrode 237 can be commonly connected to the first capacitor and the second capacitor (see C1 and C2 of FIG. 1B). Figure 3 Figure 3 Figure 3

[0111] According to example embodiments, since the first lower electrode 231a and the second lower electrode 231b have a relatively high aspect ratio and a cylindrical shape, the surface area of the first lower electrode 231a and the second lower electrode 231b can increase. In addition, since the first lower electrode 231a and the second lower electrode 231b are arranged in a zigzag pattern, the number of the first lower electrode 231a and the second lower electrode 231b arranged on the first lower pad electrode 222a and the second lower pad electrode 222b can increase. Accordingly, the capacitance of the first capacitor and the second capacitor (see C1 and C2 of FIG. 1B) can increase. Thus, during a global shutter operation, charge loss and noise generation can be reduced or prevented, so that shutter efficiency can be improved. Figure 3

[0112] ​​​​​A third interlayer insulating layer 240 can be disposed on the molding insulating layer 230 to at least partially cover the upper pad electrodes 237. A plurality of upper contact plugs TCP can penetrate the third interlayer insulating layer 240 to connect to the upper pad electrodes 237. A lower contact plug BCP can penetrate the third interlayer insulating layer 240 and the molding insulating layer 230 to connect to the first lower pad electrode 222a. A third contact plug CP3 can penetrate the third interlayer insulating layer 240 and the molding insulating layer 230 to connect to at least one of the second wires 221.

[0113] The upper contact plugs TCP, the lower contact plug BCP, and the third contact plug CP3 can include the same metal and can include a barrier metal layer and a metal layer as shown. Figure 7 The upper contact plugs TCP, the lower contact plug BCP, and the third contact plug CP3 can include the same first metal material as the first wires 211 and the second wires 221. For example, the first metal material can include a metal such as tungsten, titanium, and / or tantalum and / or a conductive metal nitride such as titanium nitride, tantalum nitride, and / or tungsten nitride.

[0114] The third wires 241 can be disposed on the third interlayer insulating layer 240 and can be connected to at least one of the second wires 221 through the third contact plug CP3. One of the third wires 241 can be connected to the upper pad electrodes 237 through the plurality of upper contact plugs TCP. At least one of the third wires 241 can have a linear type extending in a direction substantially parallel to the first surface 101a of the semiconductor substrate 101 and can be connected to the lower contact plug BCP.

[0115] A fourth interlayer insulating layer 250 can be disposed on the third interlayer insulating layer 240 to at least partially cover the third wires 241. A fourth wire 251 can be disposed on the fourth interlayer insulating layer 250. At least one of the fourth wires 251 can have a linear shape crossing the third wires 241.

[0116] In some embodiments, the third wires 241 and the fourth wires 251 above an upper surface of the third interlayer insulating layer 240 can include a second metal material different from the first wires 211 and the second wires 221 below the upper surface of the third interlayer insulating layer 240. The second metal material can have a lower resistivity than the first metal material. For example, the second metal material can include copper or a copper alloy. The copper alloy can include a small amount of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Mg, Al, and / or Zr mixed in copper. The third wires 241 and the fourth wires 251 can each include a barrier metal layer and a metal layer.

[0117] Some of the third wirings 241 may intersect with multiple pixel regions PR and may include power supply lines for applying power supply voltage and capacitor voltage. Since the third wirings 241 are formed of a second metallic material with low resistivity, signal delay can be reduced.

[0118] The fifth interlayer insulation layer 260 may be disposed on the fourth interlayer insulation layer 250 to at least partially cover the fourth wiring 251.

[0119] The light-transmitting layer 300 may be disposed on the second surface 101b of the semiconductor substrate 101. The light-transmitting layer 300 may include a planarization insulating layer 310, a light-blocking pattern 315, a filter layer 320, and a microlens ML.

[0120] The planarization insulating layer 310 may at least partially cover the second surface 101b of the semiconductor substrate 101. The planarization insulating layer 310 may be formed of an insulating material having a reflectivity different from that of the semiconductor substrate 101. For example, the planarization insulating layer 310 may be formed of an insulating material having a reflectivity lower than that of silicon. The planarization insulating layer 310 may have a reflectivity of about 1.4 to 4.0.

[0121] A light-blocking pattern 315 may be disposed on the planarization insulating layer 310 in the light-blocking region R2. The light-blocking pattern 315 may reflect or block light incident on the second surface 101b of the semiconductor substrate 101. For light incident on the light-blocking region R2 of each pixel PR, the light-blocking pattern 315 may prevent the generation of photoelectric charges in the semiconductor substrate 101 and may block light incident on the sampling circuit formed on the first surface 101a of the semiconductor substrate 101. For example, the light-blocking pattern 315 may be formed of a metal such as tungsten or aluminum. A buffer insulating layer 317 may be disposed on the planarization insulating layer 310 to at least partially cover the light-blocking pattern 315.

[0122] A filter layer 320 may be disposed on the second surface 101b of the semiconductor substrate 101 in the light receiving region R1. The filter layer 320 may transmit light of a specific wavelength band from externally incident light. The filter layer 320 may include a color filter and / or an infrared filter.

[0123] Microlenses ML, each corresponding to the photoelectric conversion region 111, can be disposed on the filter layer 320. The microlenses ML can be arranged in two dimensions along intersecting first directions D1 and second directions D2. The microlenses ML can have a convex shape and a predetermined radius of curvature. The microlenses ML can alter the path of light incident on the image sensor, thus focusing the light. The microlenses ML can be formed of a light-transmitting resin.

[0124] Figure 8A and Figure 8B They are respectively along Figure 5The cross-sectional views taken by lines I-I' and II-II' illustrate an image sensor according to some embodiments of the concept of the present invention. Descriptions of elements identical to those in the above embodiments will be brief or omitted.

[0125] Reference Figure 8A and Figure 8B The first lower electrode 231a and the second lower electrode 231b may have a cylindrical shape. The upper surfaces of the first lower electrode 231a and the second lower electrode 231b may be substantially coplanar with each other. The first lower electrode 231a and the second lower electrode 231b may have a substantially uniform upper width.

[0126] Since the capacitance of a capacitor is proportional to the surface area of ​​the first lower electrode 231a and the second lower electrode 231b, the height of the first lower electrode 231a and the second lower electrode 231b can be increased to increase the surface area of ​​the first lower electrode 231a and the second lower electrode 231b formed in a limited area. For example, the aspect ratio (height to width ratio) of the first lower electrode 231a and the second lower electrode 231b can be increased.

[0127] The first lower electrode 231a and the second lower electrode 231b, which are cylindrical, can be arranged in a zigzag pattern or a honeycomb shape as described above.

[0128] In some embodiments, the molded insulating layer 230 described above may be omitted, and the dielectric pattern 233 may at least partially cover the outer walls of the first lower electrode 231a and the second lower electrode 231b with a substantially uniform thickness. The dielectric pattern 233 may at least partially cover the first lower pad electrode 222a and the second lower pad electrode 222b between the respective electrodes of the first lower electrode 231a and the second lower electrode 231b.

[0129] The upper electrode 235 may at least partially cover the plurality of first lower electrodes 231a and the plurality of second lower electrodes 231b on the dielectric pattern 233 and may at least partially fill the space between the corresponding electrodes of the first lower electrodes 231a and the second lower electrodes 231b. The upper pad electrode 237 may be formed of a conductive material different from the conductive material of the upper electrode 235 and may be disposed on the upper electrode 235.

[0130] Figure 9 It is along Figure 5 The image is shown as a cross-sectional view taken along line I-I', illustrating an image sensor according to some embodiments of the invention. Descriptions of elements identical to those in the above embodiments will be brief or omitted.

[0131] Reference Figure 9The molded insulating layer 230 may at least partially cover the first lower pad electrode 222a and the second lower pad electrode 222b. The first lower electrode 231a and the second lower electrode 231b, which have a cylindrical shape, may be disposed in the molded insulating layer 230. The upper surface of the molded insulating layer 230 may be positioned at a level lower than the upper surfaces of the first lower electrode 231a and the second lower electrode 231b.

[0132] The dielectric pattern 233 can conformally cover the upper portions of the first lower electrode 231a and the second lower electrode 231b that protrude above the upper surface of the molded insulating layer 230, and can cover the upper surface of the molded insulating layer 230 between the corresponding electrodes of the first lower electrode 231a and the second lower electrode 231b.

[0133] The upper electrode 235 may cover a plurality of first lower electrodes 231a and second lower electrodes 231b on the dielectric pattern 233, and may at least partially fill the space between corresponding electrodes in the first lower electrodes 231a and second lower electrodes 231b. The upper pad electrode 237 may be formed of a conductive material different from the conductive material of the upper electrode 235 and may be disposed on the upper electrode 235.

[0134] Figure 10A This is a plan view of an image sensor according to some embodiments of the present invention. Figure 10B It is along Figure 10A A cross-sectional view taken from line III-III'. Descriptions of elements identical to those in the above embodiments will be brief or omitted.

[0135] Reference Figure 10A and Figure 10B The first lower electrode 231a can be disposed on the first lower pad electrode 222a, and the second lower electrode 231b can be disposed on the second lower pad electrode 222b.

[0136] The dielectric pattern 233 and the upper electrode 235 may cover at least partially the first lower electrode 231a and the second lower electrode 231b with substantially uniform thickness.

[0137] A first upper pad electrode 237a and a second upper pad electrode 237b spaced apart may be disposed on the upper electrode 235. As an example, in a plan view, the first upper pad electrode 237a may overlap with the first lower pad electrode 222a, and in a plan view, the second upper pad electrode 237b may overlap with the second lower pad electrode 222b.

[0138] The spaced-apart first upper pad electrode 237a and second upper pad electrode 237b can be electrically connected via the upper contact plug TCP and the fourth wiring 251.

[0139] Figures 11 to 18This is a diagram illustrating a method for manufacturing an image sensor according to some embodiments of the concept of the present invention, and is along... Figure 5 A cross-sectional view taken from line I-I'.

[0140] Reference Figure 11 A semiconductor substrate 101 of a first conductivity type (e.g., p-type) may be provided. The semiconductor substrate 101 may have a first surface 101a and a second surface 101b opposite to each other. The semiconductor substrate 101 may be a substrate on which an epitaxial layer of the first conductivity type is formed on a bulk silicon substrate of the first conductivity type (e.g., p-type). In some embodiments, the semiconductor substrate 101 may be a bulk semiconductor substrate including a well of the first conductivity type.

[0141] A pixel separation structure 103 defining a pixel region PR and an isolation structure 105 defining a light receiving region R1 and a light blocking region R2 in each pixel region PR can be formed in a semiconductor substrate 101.

[0142] The pixel separation structure 103 and isolation structure 105 can be formed by the following steps: patterning the first surface 101a and / or the second surface 101b of the semiconductor substrate 101 to form deep trenches, and then filling the deep trenches with an insulating material. Multiple pixel regions PR can be arranged in a matrix along the first direction D1 and the second direction D2.

[0143] A photoelectric conversion region 111 can be formed in the semiconductor substrate 101 of the light-receiving region R1. The photoelectric conversion region 111 can be formed by the following steps: forming a mask with openings corresponding to the light-receiving regions R1 of each pixel PR on the first surface 101a of the semiconductor substrate 101, and using the mask to dope the semiconductor substrate 101 with an impurity of a second conductivity type (e.g., n-type) different from the first conductivity type. The mask can be removed after the photoelectric conversion region 111 is formed. Before or after the formation of the photoelectric conversion region 111, a well region of the first conductivity type can be formed adjacent to the first surface 101a of the semiconductor substrate 101.

[0144] In each pixel region PR, a device insulating layer 107 adjacent to the first surface 101a of the semiconductor substrate 101 can be formed in the semiconductor substrate 101 to define an active region. The device insulating layer 107 can be formed by the following steps: patterning the first surface 101a of the semiconductor substrate 101 to form shallow trenches, and then depositing insulating material in the shallow trenches.

[0145] Reference Figure 12 MOS transistors constituting unit pixels can be formed on the first surface 101a of the semiconductor substrate 101.

[0146] The gate electrodes TG and GE of a MOS transistor can be formed on the first surface 101a of the semiconductor substrate 101. The gate electrodes TG and GE can be formed by the following steps: patterning the first surface 101a of the semiconductor substrate 101 to form a gate recess region in each pixel region PR; forming a gate insulating layer to conformally cover the first surface 101a of the semiconductor substrate 101 and the inner surface of the gate recess region; forming a gate conductive layer to at least partially fill the gate recess region; and patterning the gate conductive layer. The transfer gate TG in the gate electrode can be formed in the recess region formed by patterning the first surface 101a of the semiconductor substrate 101.

[0147] After forming the gate electrodes TG and GE, a floating diffusion region FD and a source / drain impurity region 101sd can be formed on one side of the gate electrodes TG and GE in the semiconductor substrate 101. The floating diffusion region FD and the source / drain impurity region 101sd can be formed by implanting impurities of a second conductivity type.

[0148] A first interlayer insulating layer 210 may be formed on a first surface 101a of a semiconductor substrate 101. The first interlayer insulating layer 210 may at least partially cover the gate electrodes TG and GE of a MOS transistor. A first contact plug CP1 connected to the MOS transistor may be formed in the first interlayer insulating layer 210. A first wiring 211 may be formed on the first interlayer insulating layer 210 to connect to the first contact plug CP1.

[0149] A second interlayer insulating layer 220 may be formed on the first interlayer insulating layer 210 to at least partially cover the first wiring 211. A second wiring 221, a first lower pad electrode 222a, and a second lower pad electrode 222b may be formed on the second interlayer insulating layer 220. A second contact plug CP2 may be formed in the second interlayer insulating layer 220. The second wiring 221 may be selectively connected to some of the first wiring 211 via the second contact plug CP2. The second lower pad electrode 222b may be connected to the first wiring 211 via any of the second contact plugs CP2. The second lower pad electrode 222b may be electrically connected to the gate electrode and the source / drain impurity region 101sd via the first contact plug CP1, the second contact plug CP2, and the first wiring 211.

[0150] The second wiring 221 and the first lower pad electrode 222a and the second lower pad electrode 222b can be formed by depositing a metal layer on the second interlayer insulating layer 220 and then patterning the metal layer.

[0151] Reference Figure 13 A molded insulating layer 230 can be formed on the second interlayer insulating layer 220 to at least partially cover the second wiring 221 and the first lower pad electrode 222a and the second lower pad electrode 222b.

[0152] The molding insulating layer 230 may be formed of silicon oxide. In some embodiments, an etch stop layer having etch selectivity relative to the molding insulating layer 230 may be formed prior to the formation of the molding insulating layer 230.

[0153] When forming the first lower electrode 231a and the second lower electrode 231b, the heights of the first lower electrode 231a and the second lower electrode 231b can be varied based on the thickness of the molded insulating layer 230. The capacitance of the first capacitor and the second capacitor can be adjusted based on the height and number of the first lower electrode 231a and the second lower electrode 231b. As the height of the first lower electrode 231a and the second lower electrode 231b increases, the capacitance of the capacitor can increase. Therefore, the molded insulating layer 230 can be formed to a desired thickness to increase the capacitance of the capacitor to a desired value.

[0154] After the molding insulating layer 230 is formed, a process for forming lower electrode holes can be performed. The lower electrode holes can be formed by the following steps: forming a mask pattern on the molding insulating layer 230, and using the mask pattern as an etching mask to anisotropically etch the molding insulating layer 230 to expose the first lower pad electrode 222a and the second lower pad electrode 222b. The lower electrode holes can be arranged in a zigzag pattern or a honeycomb shape.

[0155] After depositing the lower electrode layer to conformally at least partially cover the surface of the molded insulating layer 230 having lower electrode holes, the lower electrode layer can be planarized to expose the upper surface of the molded insulating layer 230, so that a first lower electrode 231a and a second lower electrode 231b can be formed in the lower electrode holes, respectively.

[0156] Each of the first lower electrode 231a and the second lower electrode 231b may have a cylindrical shape, having a bottom portion that contacts a corresponding one of the first lower pad electrode 222a and the second lower pad electrode 222b, and sidewall portions extending from both ends of the bottom portion.

[0157] Reference Figure 14 A dielectric layer and an upper electrode layer can be formed on the first lower electrode 231a and the second lower electrode 231b.

[0158] Film deposition techniques with high-step coverage, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, can be used to form the dielectric layer and the top electrode layer.

[0159] The dielectric layer and the upper electrode layer may at least partially cover the surfaces of the first lower electrode 231a and the second lower electrode 231b in the lower electrode hole, and may extend to the upper surface of the molded insulating layer 230. The upper electrode layer may define a gap region in the lower electrode hole (see reference). Figure 7(G). In some embodiments, the upper electrode layer may completely fill the lower electrode hole having a first lower electrode 231a and a second lower electrode 231b and a dielectric layer.

[0160] An upper pad conductive layer can be formed on the upper electrode layer, and the upper pad conductive layer can be patterned to form the upper pad electrode 237. The upper pad conductive layer can be formed by depositing a conductive material different from that of the upper electrode layer. For example, the upper pad conductive layer can be a doped silicon-germanium layer.

[0161] After the upper pad electrode 237 is formed, the upper electrode layer and the dielectric layer can be etched sequentially to form the dielectric pattern 233 and the upper electrode 235.

[0162] Reference Figure 15 A third interlayer insulating layer 240 may be formed on the molded insulating layer 230 to at least partially cover the pad electrode 237.

[0163] It can essentially form a third contact plug CP3 and a lower contact plug BCP that penetrate the third interlayer insulation layer 240 and the molded insulation layer 230, as well as an upper contact plug TCP that penetrates the third interlayer insulation layer 240 simultaneously.

[0164] Forming the third contact plug CP3, the lower contact plug BCP, and the upper contact plug TCP may include the following steps: forming a mask pattern on the third interlayer insulating layer 240; anisotropically etching the third interlayer insulating layer 240 and the molding insulating layer 230 to form a first contact hole exposing the second wiring 221, a second contact hole exposing the first lower pad electrode 222a, and a third contact hole exposing the upper pad electrode 237; and at least partially filling the first, second, and third contact holes with a conductive material. The upper pad electrode 237 may suppress or prevent etching of the upper electrode 235 during the formation of the first to third contact holes. When the third contact hole is formed, a portion of the upper surface of the upper pad electrode 237 may be recessed.

[0165] Filling at least partially the first to third contact holes with a conductive material may include sequentially depositing a barrier metal layer and a metal layer in the first, second, and third contact holes and planarizing the barrier metal layer and the metal layer to expose the upper surface of the third interlayer insulation layer 240.

[0166] For example, the third contact plug CP3, the lower contact plug BCP, and the upper contact plug TCP may be made of aluminum, tungsten, titanium, molybdenum, tantalum, titanium nitride, tantalum nitride, zirconium nitride, tungsten nitride, or combinations thereof.

[0167] Reference Figure 16A third wiring 241 may be formed on the third interlayer insulating layer 240, and a fourth interlayer insulating layer 250 may be formed on the third interlayer insulating layer 240 to at least partially cover the third wiring 241. The third wiring 241 may be formed of a metallic material having a resistivity lower than that of the third contact plug CP3, the lower contact plug BCP, and the upper contact plug TCP. The third wiring 241 may be formed in the fourth interlayer insulating layer 250 by depositing a metal layer and patterning the metal layer or by performing a damascene process.

[0168] The third wiring 241 may have a linear or strip shape. One of the third wirings 241 may be connected to the upper pad electrode 237 via a lower contact plug TCP. The other of the third wirings 241 may be connected to the first lower pad electrode 222a via a lower contact plug BCP.

[0169] A fourth wiring 251 may be formed on the fourth interlayer insulating layer 250, and a fifth interlayer insulating layer 260 may be formed on the fourth interlayer insulating layer 250 to at least partially cover the fourth wiring 251. The fourth wiring 251 may include the same metallic material as the third wiring 241.

[0170] Reference Figure 17 A thinning process can be performed to remove a portion of the semiconductor substrate 101 to reduce the vertical thickness of the semiconductor substrate 101. The thinning process may include grinding or polishing the second surface 101b of the semiconductor substrate 101 and isotropically or anisotropically etching the resulting structure. The top and bottom of the semiconductor substrate 101 may be reversed to make the semiconductor substrate 101 thinner (to perform the thinning process). A portion of the semiconductor substrate 101 may be removed by a grinding or polishing process, and then isotropic and / or anisotropic etching processes may be performed to remove surface defects in the semiconductor substrate 101.

[0171] When a thinning process is performed on the second surface 101b of the semiconductor substrate 101, the surfaces of the pixel separator structure 103 and the isolation structure 105 can be exposed. The exposed surfaces of the pixel separator structure 103 and the isolation structure 105 can be substantially coplanar with the second surface 101b of the semiconductor substrate 101.

[0172] A planarization insulating layer 310 may be formed on a second surface 101b of the semiconductor substrate 101. The planarization insulating layer 310 may at least partially cover the surfaces of the pixel separation structure 103 and the insulating structure 105. The planarization insulating layer 310 may be formed by depositing a metal oxide such as aluminum oxide and / or hafnium oxide.

[0173] A light-blocking pattern 315 can be formed on the planarized insulating layer 310 in the light-blocking region R2. The light-blocking pattern 315 can be formed by depositing a metal layer and then patterning the metal layer.

[0174] Reference Figure 18 A buffer insulating layer 317 can be formed to at least partially cover the light blocking pattern 315 and expose the planarized insulating layer 310 in the light receiving region R1.

[0175] A filter layer 320 may be formed on the planarized insulating layer 310 corresponding to each light-receiving region R1. The filter layer 320 may include a blue, green, or red filter or an infrared filter. A microlens ML may be formed on the filter layer 320 in the light-receiving region R1.

[0176] According to the example embodiment, shutter efficiency can be enhanced during global shutter speed because the capacitance of the capacitor on the photoelectric conversion device can be increased.

[0177] The optical signal generated from the photoelectric conversion device can be stored in a capacitor until it is output as an image signal. Therefore, the loss of photoelectric charge or the generation of noise can be reduced before the pixel signal is output from the unit pixel.

[0178] Because the capacitor is placed on the photoelectric conversion device, the area ratio (i.e., fill factor) of the photoelectric conversion device in each unit pixel can be increased.

[0179] Furthermore, even if the unit size of the unit pixel is reduced, the aspect ratio and surface area of ​​the lower electrode can be increased, so that the capacitance of the capacitor can be maintained at the desired value.

[0180] Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. An image sensor, comprising: A semiconductor substrate having a first surface and a second surface opposite to the first surface; Photoelectric conversion layer in a semiconductor substrate; A transistor on the first surface of a semiconductor substrate; The first interlayer insulating layer on the transistor; A first lower pad electrode and a second lower pad electrode on a first interlayer insulating layer, wherein the second lower pad electrode is spaced apart from the first lower pad electrode; Molded insulating layer on the first and second lower pad electrodes; Multiple first lower electrodes in a molded insulating layer, the multiple first lower electrodes on a first lower pad electrode; Multiple second lower electrodes in a molded insulating layer, the multiple second lower electrodes on the second lower pad electrode; Dielectric layer on the first and second lower electrodes; The top electrode on the dielectric layer; as well as The upper pad electrode is connected to the upper electrode. In the planar view, the first lower pad electrode and the second lower pad electrode overlap with the photoelectric conversion layer. In the plan view, the first lower electrode is arranged in a zigzag pattern on the first lower pad electrode, and... In the plan view, the second lower electrode is arranged on the second lower pad electrode in a zigzag pattern.

2. The image sensor according to claim 1, wherein, The upper pad electrode comprises a different conductive material than the first lower pad electrode and the second lower pad electrode, and the upper pad electrode comprises a different conductive material than the upper electrode.

3. The image sensor according to claim 1, wherein, The upper pad electrode contains doped semiconductor material.

4. The image sensor according to claim 1, wherein, The upper pad electrode is thicker than each of the first and second lower pad electrodes.

5. The image sensor according to claim 1, further comprising: A second interlayer insulating layer on the molded insulating layer and on the upper pad electrode; Multiple upper contact plugs extend through the second interlayer insulation layer and connect to the upper pad electrode; as well as The lower contact plug extends through the second interlayer insulation layer and the molded insulation layer and connects to the first lower pad electrode; The plurality of upper contact plugs comprise the same first metal material as the lower contact plugs.

6. The image sensor according to claim 5, further comprising: Multiple wires on the second interlayer insulation layer, The plurality of wires are connected to the transistor, the plurality of upper contact plugs and lower contact plugs, and include a second metal material having a resistivity lower than that of the first metal material.

7. The image sensor according to claim 1, wherein, Each of the first and second lower electrodes includes a bottom portion and a sidewall portion for defining a blank space, the sidewall portion extending from the bottom portion, and The dielectric layer and the upper electrode extend along the inner surfaces of the first and second lower electrodes.

8. The image sensor according to claim 7, wherein, The upper pad electrode contacts the portion of the upper electrode on the molded insulating layer.

9. The image sensor according to claim 1, wherein, Each of the first and second lower electrodes has a cylindrical shape, and The dielectric layer and the upper electrode extend along the outer surfaces of the first and second lower electrodes.

10. The image sensor according to claim 1, wherein, In the planar view, the first lower pad electrode and the second lower pad electrode overlap with the photoelectric conversion layer.

11. The image sensor according to claim 1, wherein, One of the first and second lower pad electrodes is connected to the transistor.

12. The image sensor according to claim 1, further comprising: A pixel separation structure in a semiconductor substrate, which defines a pixel region; as well as An isolation structure in a semiconductor substrate within a pixel region, defining a light-receiving region and a light-blocking region. The photoelectric conversion layer is located in the light receiving region.

13. The image sensor according to claim 1, further comprising: Microlenses on the second surface of a semiconductor substrate; as well as A filter between a microlens and a semiconductor substrate.

14. An image sensor, comprising: A semiconductor substrate having a first surface and a second surface opposite to the first surface; Photoelectric conversion layer in a semiconductor substrate; A transistor on the first surface of a semiconductor substrate; The first interlayer insulating layer on the transistor; A first wiring comprising a first metallic material on a first interlayer insulating layer, the first wiring being connected to a transistor; Molded insulation layer on the first wiring; A capacitor in a molded insulating layer, which is connected to a transistor; The second interlayer insulation layer on the capacitor; as well as A second wiring comprising a second metallic material is provided on the second interlayer insulation layer. This second wiring is connected to the first wiring and the capacitor. The second metal material of the second wiring has a resistivity lower than that of the first metal material of the first wiring. The first wiring includes a first lower pad electrode and a second lower pad electrode spaced apart from the first lower pad electrode. In the planar view, the first lower pad electrode and the second lower pad electrode overlap with the photoelectric conversion layer. Among them, capacitors include: Multiple first lower electrodes on the first lower pad electrode; Multiple second lower electrodes on the second lower pad electrode; The upper electrode on the first lower electrode and the second lower electrode; and A dielectric layer between the upper electrode and the first lower electrode, and between the upper electrode and the second lower electrode.

15. The image sensor of claim 14, further comprising: The upper pad electrode that contacts the upper electrode includes a doped semiconductor material.

16. The image sensor of claim 15, further comprising: A lower contact plug in the molded insulating layer and the second interlayer insulating layer connects the first lower pad electrode to a second wiring in the second wiring; as well as An upper contact plug in the second interlayer insulation layer connects the upper pad electrode to another second wiring in the second wiring. The upper contact plug is made of the same metal material as the lower contact plug.

17. The image sensor according to claim 15, wherein, The second lower pad electrode is connected to a first wiring via a contact plug in the first interlayer insulation layer.

18. An image sensor, comprising: A semiconductor substrate having a first surface and a second surface opposite to the first surface; A pixel separation structure in a semiconductor substrate, which defines multiple pixel regions; A photoelectric conversion layer in a semiconductor substrate in each of the plurality of pixel regions; A transistor on the first surface of a semiconductor substrate; The first interlayer insulating layer on the transistor; as well as A first capacitor and a second capacitor on a first interlayer insulating layer in each of the plurality of pixel regions, the first capacitor and the second capacitor overlapping with the photoelectric conversion layer in each of the plurality of pixel regions in a planar view. The first capacitor includes multiple first lower electrodes. The second capacitor includes multiple second lower electrodes. In the plan view, the first lower electrode is arranged in a zigzag pattern, and The second lower electrode is arranged in a zigzag pattern in the plan view.

19. The image sensor according to claim 18, wherein, The first capacitor further includes a first lower pad electrode on a first interlayer insulating layer in each of the plurality of pixel regions, an upper electrode on the plurality of first lower electrodes, and a dielectric layer between the upper electrode and the plurality of first lower electrodes. The second capacitor further includes a second lower pad electrode on a first interlayer insulating layer in each of the plurality of pixel regions, an upper electrode on the plurality of second lower electrodes, and a dielectric layer between the upper electrode and the plurality of second lower electrodes.

20. The image sensor of claim 19, further comprising: A first wiring on the first interlayer insulating layer, the first wiring being connected to the transistor; A second interlayer insulating layer on the first capacitor and the second capacitor; as well as The second wiring on the second interlayer insulation layer The first lower pad electrode is connected to a second wiring in the second wiring via an upper contact plug extending through the second interlayer insulation layer. The second lower pad electrode is connected to a first wiring in the first wiring via a lower contact plug that extends through the first interlayer insulation layer.

21. The image sensor according to claim 20, wherein, The second wiring includes a second metallic material having a resistivity that is less than that of the first metallic material of the first wiring.

Images