Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same. The semiconductor device according to an exemplary embodiment of the present invention includes: an n-type epitaxial layer disposed on a first surface of a substrate; a p-type region disposed on the n-type epitaxial layer; an n+-type region disposed on the p-type region; a gate disposed on the n-type epitaxial layer; an oxide film disposed on the gate; a source electrode disposed on the oxide film and the n+-type region; and a drain electrode disposed on a second surface of the substrate. The gate includes a PN junction portion.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2018 - 0118905, filed with the Korean Intellectual Property Office on October 5, 2018, which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor device and a method of manufacturing the same. Background Art

[0004] Power semiconductor devices particularly require a low on - resistance or a low saturation voltage in order to generate a very large current in the conducting state and reduce power loss. Further, power semiconductor devices mainly need to have a characteristic, that is, a high breakdown voltage characteristic, through which the power semiconductor device can resist the reverse high voltage applied across the PN - junction at both ends of the power semiconductor device in the off - state or when the switch is turned off.

[0005] The metal - oxide - semiconductor field - effect transistor (MOSFET) in a power semiconductor device is the most commonly used transistor in digital circuits and analog circuits.

[0006] Meanwhile, in order to reduce the on - resistance and increase the current density, a trench - gate MOSFET in which the JFET region of a planar - gate MOSFET is removed has been studied.

[0007] In the case of a trench - gate MOSFET, after forming a trench, a gate insulating layer is formed on the lateral surface and the bottom surface of the trench. In this case, the electric field is concentrated on the gate insulating layer disposed at the corner of the trench, such that the gate insulating layer may break during the operation of the semiconductor device.

[0008] The above information disclosed in this background art section is only for enhancing the understanding of the background of the present invention, and thus, the above information may include information that does not constitute the prior art known to those of ordinary skill in the art in this country. Summary of the Invention

[0009] The completed present invention is directed to relaxing the electric field concentrated on the gate insulating layer in a trench - gate metal - oxide - semiconductor field - effect transistor (MOSFET). Exemplary embodiments of the present invention provide a semiconductor device. An n - type epitaxial layer is disposed on a first surface of a substrate. A p - type region is disposed on the n - type epitaxial layer. An n + - type region is disposed on the p - type region. A gate is disposed on the n - type epitaxial layer. An oxide film is disposed on the gate. A source electrode is disposed on the oxide film and the n + - type region. A drain electrode is disposed on a second surface of the substrate. The gate includes a PN - junction portion.

[0010] The gate may include a first gate and a second gate disposed on the first gate. The first gate may include n-type polysilicon, and the second gate may include p-type polysilicon.

[0011] The first gate may be in contact with the second gate, and a PN junction portion may be disposed in the surface where the first gate contacts the second gate.

[0012] The boundary of the lateral surface of the first gate may be the same as the boundary of the lateral surface of the second gate.

[0013] The second gate may cover the lateral surface of the first gate.

[0014] The semiconductor device may further include: a trench disposed in the n-type layer; and a gate insulating layer disposed in the trench, wherein the first gate may be in contact with the gate insulating layer disposed in the lower surface of the trench.

[0015] The extension line of the upper surface of the first gate may be disposed lower than the lower surface of the p-type region.

[0016] The first gate may be disposed to extend from the lateral surface of the trench to the lower surface.

[0017] The first gate may be in contact with the gate insulating layer disposed in the lower surface and the lateral surface of the trench.

[0018] The semiconductor device may further include a p+-type region disposed on the p-type region and spaced apart from the lateral surface of the trench.

[0019] The substrate may be an n+-type silicon carbide substrate.

[0020] Another exemplary embodiment of the present invention provides a method of manufacturing a semiconductor device, the method including: sequentially forming an n-type epitaxial layer, a p-type region, and an n+-type region on a first surface of a substrate; forming a trench by etching the n-type epitaxial layer, the p-type region, and the n+-type region; forming a gate insulating layer in the trench; forming a gate on the gate insulating layer; forming an oxide film on the gate; forming a source electrode disposed on the oxide film and the n+-type region; and forming a drain electrode disposed on a second surface of the substrate, wherein the gate includes a PN junction portion.

[0021] Forming the gate may include: forming a gate material layer on the gate insulating layer; forming a first gate by etching the gate material layer; and forming a second gate on the first gate.

[0022] According to an exemplary embodiment of the present invention, the gate disposed in the trench includes a PN junction portion so that the electric field concentrated on the gate insulating layer can be relaxed.

[0023] Therefore, the breakdown voltage of the semiconductor device can be increased.

[0024] Furthermore, according to the relaxation of the electric field concentrated in the gate insulating layer, the durability of the gate insulating layer can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a diagram schematically showing an example of a cross-section of a semiconductor device according to an exemplary embodiment of the present invention.

[0026] Figure 2 is schematically showing Figure 1 a diagram of the off state of the semiconductor device.

[0027] Figure 3 is schematically showing Figure 1 a diagram of the on state of the semiconductor device.

[0028] Figures 4 to 8 is schematically showing an example of a method of manufacturing Figure 1 the semiconductor device.

[0029] Figure 9 is a diagram schematically showing an example of a cross-section of a semiconductor device according to another exemplary embodiment of the present invention.

[0030] Figure 10 is schematically showing an example of a method of manufacturing Figure 9 the semiconductor device.

[0031] Figure 11 is a diagram schematically showing an example of a cross-section of a semiconductor device according to another exemplary embodiment of the present invention.

[0032] Figure 12 is a diagram schematically showing an example of a cross-section of a semiconductor device according to another exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0033] In the following detailed description, only some exemplary embodiments of the present invention are shown and described simply by way of illustration. As those skilled in the art will recognize, all can be modified in various different ways without departing from the spirit or scope of the present invention.

[0034] The drawings and the description are to be regarded as illustrative in nature and not restrictive, and throughout the specification, the same reference numerals represent the same elements.

[0035] In addition, for purposes of understanding and ease of description, the dimensions and thicknesses of each configuration shown in the drawings are arbitrarily shown, but the present invention is not limited thereto. In the drawings, for clarity, the thicknesses of layers, films, panels, regions, etc. are exaggerated. In the drawings, for purposes of understanding and ease of description, the thicknesses of some layers and regions are exaggerated.

[0036] Further, it should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be an intervening element. In contrast, when an element is referred to as being "directly on" another element, there is no intervening element. Further, "on" or "above" in the portions used as references means placed on or below the portion used as a reference, but does not necessarily mean placed "on" or "above" in a direction opposite to the direction of gravity.

[0037] In addition, unless explicitly described to the contrary, the word "comprising" and variations such as "comprises" or "containing" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0038] Further, throughout this specification, "in a plane" means the case where the target portion is viewed from the top side, and "cross-sectional view" means the case where the cross-section of the target portion obtained by vertically cutting the target portion is viewed from the side.

[0039] Figure 1 is a diagram schematically showing an example of a cross-section of a semiconductor device according to an exemplary embodiment of the present invention.

[0040] Reference Figure 1 , a semiconductor device according to an exemplary embodiment of the present invention includes a substrate 100, an n-type layer 200, a p-type region 300, a trench 350, an n+-type region 400, a gate 600, a p+-type region 700, a source electrode 900, and a drain electrode 950.

[0041] The substrate 100 can be an n+-type silicon carbide substrate.

[0042] The n-type layer 200 is disposed on a first surface of the substrate 100, and the p-type region 300 is disposed on the n-type layer 200. The n+-type region 400 and the p+-type region 700 are disposed on the p-type region 300. Herein, the thickness of the p+-type region 700 can be greater than the thickness of the n+-type region 400.

[0043] The trench 350 passes through the p-type region 300 and the n+-type region and is disposed in the n-type layer 200. Accordingly, the p-type region 300 and the n+-type region are disposed on lateral surfaces of the trench 350. The p+-type region 700 is spaced apart from the lateral surface of the trench 350, and the n+-type region is disposed between the lateral surface of the p+-type region 700 and the lateral surface of the trench 350.

[0044] The gate insulating layer 500 is disposed within the trench 350. The gate insulating layer 500 may include silicon dioxide (SiO2).

[0045] The gate 600 is disposed on the gate insulating layer 500. The trench 350 may be filled with the gate 600, and a portion of the gate 600 may protrude outside the trench 350.

[0046] The gate 600 includes a first gate 610 and a second gate 620. The first gate 610 is in contact with the gate insulating layer 500 disposed in the lower surface of the trench 350, and the second gate 620 is disposed on the first gate 610 and in contact with the first gate 610. A portion of the second gate 620 may protrude outside the trench 350. In this case, the extension line of the upper surface of the first gate 610 may be disposed lower than the lower surface of the p-type region 300 so as not to affect the threshold voltage determined by the p-type region 300, the gate insulating layer 500, and the second gate 620.

[0047] The first gate 610 includes n-type polysilicon, and the second gate 620 includes p-type polysilicon. Thus, the gate 600 includes a PN junction portion J. The PN junction portion J is disposed within the trench 350 and is formed in the surface where the first gate 610 and the second gate 620 are in contact.

[0048] The oxide film 800 is disposed on the gate 600. The oxide film 800 covers the lateral surfaces of the protruding gate 600. That is, the oxide film 800 is disposed on the second gate 620 and covers the lateral surfaces of the second gate 620. The oxide film 800 may include silicon dioxide (SiO2).

[0049] The source electrode 900 is disposed on the n+-type region 400, the p+-type region 700, and the oxide film 800, and the drain electrode 950 is disposed on the second surface of the substrate 100. Herein, the second surface of the substrate 100 represents the surface opposite to the first surface of the substrate 100. The source electrode 900 and the drain electrode 950 may include ohmic metal.

[0050] As described above, the gate 600 within the trench 350 includes a PN junction portion J so that the electric field is distributed to the gate insulating layer 500 and the PN junction portion J of the gate 600 in the off state of the semiconductor device. Therefore, the electric field applied to the gate insulating layer 500 is relaxed, so that the breakdown voltage of the semiconductor device can be increased. Further, according to the relaxation of the electric field applied to the gate insulating layer 500, the durability of the gate insulating layer 500 can be improved.

[0051] Then, reference will be made to Figure 2 and Figure 3 describe Figure 1 the operation of the semiconductor device described above.

[0052] Figure 2 And Figure 3 schematically shows Figure 1 the operation of a semiconductor device.

[0053] Figure 2 schematically shows Figure 1 the off state of a semiconductor device. Figure 3 schematically shows Figure 1 the on state of a semiconductor device.

[0054] Under the conditions described below, the off state of the semiconductor device is formed.

[0055] V GS < V TH V DS ≥ 0V

[0056] Under the conditions described below, the on state of the semiconductor device is formed.

[0057] V GS ≥ V TH V DS > 0V

[0058] In this document, V TH is the threshold voltage of the MOSFET, and V GS is V G - V S V DS is V D - V S V G is the voltage applied to the gate, V D is the voltage applied to the drain electrode, and V S is the voltage applied to the source electrode.

[0059] Refer to Figure 2 , in the turn-off of the semiconductor device, a depletion layer 50 is formed to almost cover the n-type layer 200 to block the current path. The depletion layer 50 surrounds the lower surface and corners of the trench 350. In the off state of the semiconductor device, an electric field is generated in the gate 600 and the p-type region 300 by the voltage applied to the drain electrode 950, and the PN junction portion J existing in the gate 600 distributes the electric field so that a low electric field is applied to the gate insulating layer 500.

[0060] As described above, the relaxation of the electric field applied to the gate insulating layer 500 enables improvement of the breakdown voltage of the semiconductor device. Further, according to the relaxation of the electric field applied to the gate insulating layer 500 at a voltage lower than the breakdown voltage, the durability of the gate insulating layer 500 can be improved.

[0061] Reference Figure 3 In the on-state of the semiconductor device, a depletion layer 50 is formed in the n-type layer 200 disposed below the p-type region 300. The depletion layer 50 is not formed in the n-type layer 200 adjacent to the lateral surface of the trench 350, and a channel is formed in the p-type region 300 adjacent to the lateral surface of the trench 350 to form a current path. That is, in the on-state of the semiconductor device, electrons (e-) emitted from the source electrode 900 move through the n+-type region 400, the p-type region 300, and the n-type layer 200 to the drain electrode 950.

[0062] Then, a comparison between the characteristics of the semiconductor device according to the present exemplary embodiment and the characteristics of a general semiconductor device will be described with reference to Table 1.

[0063] Table 1 shows the simulation results of the semiconductor device according to the present exemplary embodiment and a general semiconductor device.

[0064] Comparative Example 1 is a general trench gate MOSFET device in which the gate does not include a PN junction portion. Example 1 is a semiconductor device according to Figure 1 the

[0065] In Table 1, the breakdown voltages of the semiconductor device according to Example 1 and the semiconductor device according to Comparative Example 1 are compared at almost the same current density.

[0066] (Table 1)

[0067]

[0068] Referring to Table 1, the breakdown voltage of the semiconductor device according to Comparative Example 1 is shown as 858 V, and the breakdown voltage of the semiconductor device according to Example 1 is shown as 1230 V. That is, it can be seen that the breakdown voltage of the semiconductor device according to Example 1 is increased by 43.4% compared to the breakdown voltage of the semiconductor device according to Comparative Example 1.

[0069] Then, a method of manufacturing the Figures 4 to 8 and Figure 1 semiconductor device will be described with reference to Figure 1 the

[0070] Figures 4 to 8 FIG. Figure 1 is a diagram schematically showing an example of a method of manufacturing the

[0071] Reference Figure 4 FIG., a substrate 100 is prepared, and an n-type layer 200 is formed on the first surface of the substrate 100. The n-type layer 200 may be formed on the first surface of the substrate 100 by epitaxial growth. Herein, the substrate 100 may be an n+-type silicon carbide substrate.

[0072] Reference Figure 5 , a p-type region 300 is formed on the n-type layer 200, and an n+-type region 400 is formed on the p-type region 300. The p-type region 300 can be formed by implanting p ions such as boron (B), aluminum (Al), gallium (Ga), and indium (In) into the n-type layer 200, and the n+-type region 400 can be formed by implanting n ions such as nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb) into the p-type region 300.

[0073] However, the present invention is not limited thereto, and the p-type region 300 is formed on the n-type layer 200 by epitaxial growth, and the n+-type region 400 can also be formed on the p-type region 300 by epitaxial growth.

[0074] Reference Figure 6 , a trench 350 is formed by etching the n+-type region 400, the p-type region 300, and the n-type layer 200. The trench 350 passes through the p-type region 300 and the n+-type region and is formed in the n-type layer 200.

[0075] Next, a gate insulating layer 500 is formed in the trench 350, and a first gate material layer 610a is formed on the gate insulating layer 500. The trench 350 is filled with the first gate material layer 610a, and the first gate material layer 610a may include n-type polysilicon.

[0076] Reference Figure 7 , a first gate 610 is formed by etching a part of the first gate material layer 610a. The first gate 610 is formed on the gate insulating layer 500 disposed on the lower surface of the trench 350. In this case, the extension line of the upper surface of the first gate electrode 610 may be disposed lower than the lower surface of the p-type region 300.

[0077] Reference Figure 8 , a gate 600 is formed by forming a second gate 620 on the first gate 610. The second gate 620 is in contact with the first gate 610 and includes p-type polysilicon. Therefore, the gate 600 includes a PN junction portion J. The PN junction portion J is disposed in the trench 350 and is formed in the surface where the first gate 610 and the second gate 620 are in contact. The trench 350 may be filled with the gate 600, and a part of the gate 600 may protrude to the outside of the trench 350.

[0078] Next, p ions such as boron (B), aluminum (Al), gallium (Ga), and indium (In) are implanted into the n+-type region 400 and the p-type region 300 to form a p+-type region 700. The p+-type region 700 is spaced apart from the lateral surface of the trench 350. The concentration of p ions contained in the p+-type region 700 is higher than the concentration of p ions contained in the p-type region 300.

[0079] Next, an oxide film is formed on the gate 600. The oxide film 800 may cover the lateral surfaces of the protruding gate 600.

[0080] Reference Figure 1 , a source electrode 900 is formed on the n+-type region 400, the p+-type region 700, and the oxide film 800, and a drain electrode 950 is formed on the second surface of the substrate 100.

[0081] Then, reference Figures 9 to 11 will describe a semiconductor device according to another exemplary embodiment of the present invention.

[0082] Figure 9 is a diagram schematically showing an example of a cross-section of a semiconductor device according to another exemplary embodiment of the present invention.

[0083] Reference Figure 9 , the semiconductor device is different from the semiconductor device of Figure 1 only in the structure of the gate 600, and the remaining structures are the same as those of the semiconductor device of Figure 1 . Therefore, the description of the same structures will be omitted.

[0084] A gate insulating layer 500 is disposed in the trench 350, and a gate 600 is disposed on the gate insulating layer 500. The trench 350 may be filled with the gate 600, and a part of the gate 600 may protrude to the outside of the trench 350.

[0085] The gate 600 includes a first gate 610 and a second gate 620. The first gate 610 is disposed to extend from the lateral surface to the lower surface of the trench 350, and the second gate 620 is disposed on and in contact with the first gate 610. A part of the second gate 620 may protrude to the outside of the trench 350. In this case, the first gate 610 is in contact with the gate insulating layer 500 disposed on the lower surface and the lateral surface of the trench 350. Further, a part of the first gate 610 and the second gate 620 may protrude to the outside of the trench 350.

[0086] The first gate 610 includes n-type polysilicon, and the second gate 620 includes p-type polysilicon. Thus, the gate 600 includes a PN junction portion J. The PN junction portion J is disposed in the trench 350 and is formed in the surface where the first gate 610 and the second gate 620 are in contact.

[0087] Then, a comparison between the characteristics of the semiconductor device according to this exemplary embodiment and the characteristics of a general semiconductor device will be described with reference to Table 2.

[0088] Table 2 shows the simulation results of the semiconductor device according to the present exemplary embodiment and a general semiconductor device.

[0089] Comparative Example 1 is a general trench gate MOSFET device, in which the gate does not include the PN junction portion J. Example 2 is a semiconductor device according to Figure 9 .

[0090] In Table 2, the breakdown voltages of the semiconductor device according to Example 2 and the semiconductor device according to Comparative Example 1 are compared at almost the same current density.

[0091] (Table 2)

[0092]

[0093] Referring to Table 2, the breakdown voltage of the semiconductor device according to Comparative Example 1 is expressed as 858 V, and the breakdown voltage of the semiconductor device according to Example 2 is expressed as 1098 V. That is, it can be seen that the breakdown voltage of the semiconductor device according to Example 2 increases by 28.0% compared with the breakdown voltage of the semiconductor device according to Comparative Example 1.

[0094] Then, a method of manufacturing the Figure 10 , Figure 9 and Figure 6 semiconductor device will be described with reference to Figure 9 .

[0095] Figure 10 FIG. Figure 9 is a diagram schematically showing an example of a method of manufacturing the

[0096] semiconductor device. Figure 9 The method of manufacturing the Figure 1 semiconductor device is different from the method of manufacturing the Figure 1 semiconductor device only in the method of forming the gate 600, but the remaining methods are the same as the remaining methods of the method of manufacturing the

[0097] semiconductor device. Therefore, the description of the same methods will be omitted. Figure 6 As shown in

[0098] Referring to Figure 10, the first gate 610 is formed by etching a part of the first gate material layer 610a. The first gate 610 is arranged to extend from the lateral surface to the lower surface of the trench 350. In this case, the first gate 610 is in contact with the gate insulating layer 500 disposed on the lower surface and the lateral surface of the first gate 610.

[0099] Then, as Figure 9 shown, the second gate 620 is formed on the first gate 610, and the method of manufacturing the remaining constituent elements is the same as the method of manufacturing a semiconductor device according to Figure 1 .

[0100] Figure 11 is a diagram schematically showing an example of a cross-section of a semiconductor device according to another exemplary embodiment of the present invention.

[0101] The semiconductor device according to the present exemplary embodiment includes a substrate 100, an n-type layer 200, a p-type region 300, an n+-type region 400, a gate 600, a p+-type region 700, a source electrode 900, and a drain electrode 950. The substrate 100 may be an n+-type silicon carbide substrate.

[0102] The n-type layer 200 is disposed on the first surface of the substrate 100, and the p-type region 300 is disposed on the n-type layer 200. The n+-type region 400 and the p+-type region 700 are disposed on the p-type region 300. Herein, the thickness of the p+-type region 700 may be greater than the thickness of the n+-type region 400.

[0103] The gate insulating layer 500 is disposed on the n-type layer 200, the p-type region 300, and the n+-type region 400, and the gate 600 is disposed on the gate insulating layer 500.

[0104] The gate 600 includes a first gate 610 and a second gate 620. The lower surface of the first gate 610 is in contact with the gate insulating layer 500, and the second gate 620 is disposed on the first gate 610 and in contact with the first gate 610. The boundary of the lateral surface of the first gate 610 may be the same as the boundary of the lateral surface of the second gate 620.

[0105] The first gate 610 includes n-type polysilicon, and the second gate 620 includes p-type polysilicon. Therefore, the gate 600 includes a PN junction portion J. The PN junction portion J is formed in the surface where the first gate 610 and the second gate 620 are in contact.

[0106] The oxide film 800 is disposed on the gate 600. The oxide film 800 covers the lateral surface of the gate 600. That is, the oxide film 800 is disposed on the second gate 620 and covers the lateral surfaces of the first gate 610 and the second gate 620. The oxide film 800 may include silicon dioxide (SiO2).

[0107] The source electrode 900 is disposed on the n+-type region 400, the p+-type region 700, and the oxide film 800, and the drain electrode 950 is disposed on the second surface of the substrate 100. Herein, the second surface of the substrate 100 refers to the surface opposite to the first surface of the substrate 100. The source electrode 900 and the drain electrode 950 may include ohmic metals.

[0108] As described above, the gate 600 includes a PN junction portion J so that the electric field is distributed to the gate insulating layer 500 and the PN junction portion J of the gate 600 in the off state of the semiconductor device. Accordingly, the electric field applied to the gate insulating layer 500 is relaxed, so that the breakdown voltage of the semiconductor device can be improved. Further, the durability of the gate insulating layer 500 can be improved according to the relaxation of the electric field applied to the gate insulating layer 500.

[0109] Figure 12 is a diagram schematically showing an example of a cross section of a semiconductor device according to another exemplary embodiment of the present invention.

[0110] Reference Figure 12 , the semiconductor device is different from the Figure 11 semiconductor device only in the structure of the gate 600, but the remaining structures are the same as those of the Figure 11 semiconductor device. Therefore, the description of the same structures will be omitted.

[0111] The gate insulating layer 500 is disposed on the n-type layer 200, the p-type region 300, and the n+-type region 400, and the gate 600 is disposed on the gate insulating layer 500.

[0112] The gate 600 includes a first gate 610 and a second gate 620. The lower surface of the first gate 610 is in contact with the gate insulating layer 500, and the second gate 620 is disposed on the first gate 610 and in contact with the first gate 610. Further, the second gate 620 covers the lateral surface of the first gate 610 and is in contact with the gate insulating layer 500.

[0113] The oxide film 800 is disposed on the gate 600. The oxide film 800 covers the lateral surface of the gate 600. That is, the oxide film 800 is disposed on the second gate 620 and covers the lateral surface of the second gate 620. The oxide film 800 may include silicon dioxide (SiO2).

[0114] Although the present invention has been described in conjunction with presently considered practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: An n-type epitaxial layer disposed on a first surface of a substrate; A p-type region disposed on the n-type epitaxial layer; An n+-type region disposed on the p-type region; A trench disposed in the n-type epitaxial layer; A gate disposed on the n-type epitaxial layer, wherein the gate includes a PN junction portion and a part of the gate protrudes outside the trench; A p+-type region disposed on the p-type region and laterally spaced from the trench; An oxide film disposed on the gate; A source electrode disposed on the oxide film and the n+-type region; and A drain electrode disposed on a second surface of the substrate, wherein the gate includes a first gate and a second gate disposed on the first gate, wherein an extension line of an upper surface of the first gate is disposed lower than a lower surface of the p-type region, wherein: The first gate includes n-type polysilicon; and The second gate includes p-type polysilicon.

2. The semiconductor device according to claim 1, wherein, The first gate is in contact with the second gate, and the PN junction portion is disposed at an interface between the first gate and the second gate.

3. The semiconductor device according to claim 2, further comprising: A gate insulating layer disposed in the trench, wherein the first gate is in contact with the gate insulating layer disposed in a lower surface of the trench.

4. The semiconductor device according to claim 1, wherein, The substrate is an n+-type silicon carbide substrate.

5. A method of manufacturing a semiconductor device, the method comprising: An n-type epitaxial layer, a p-type region, and an n+-type region are sequentially formed on a first surface of the substrate; A trench is formed by etching the n-type epitaxial layer, the p-type region, and the n+-type region; A gate insulating layer is formed in the trench; A gate is formed above the gate insulating layer, wherein the gate includes a PN junction portion, and a part of the gate protrudes outside the trench; An oxide film is formed above the gate; A source electrode is formed on the oxide film and the n+-type region; and A drain electrode disposed on the second surface of the substrate is formed, The method further includes: forming a p+-type region disposed on the p-type region and laterally spaced from the trench, wherein the gate includes a first gate and a second gate disposed on the first gate, wherein an extension line of an upper surface of the first gate is disposed lower than a lower surface of the p-type region, wherein forming the gate includes: Forming a gate material layer on the gate insulating layer; Forming the first gate by etching the gate material layer, the first gate including n-type polysilicon; and The second gate includes p-type polysilicon.

6. The method according to claim 5, wherein,The first gate is in contact with the second gate, and the PN junction portion is disposed at an interface between the first gate and the second gate.

7. According to the method of claim 6, wherein The first gate is in contact with the gate insulating layer disposed in a lower surface of the trench.

8. According to the method of claim 5, wherein The substrate is an n+-type silicon carbide substrate.

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