A Communication-Type Encoder Feedback Position Estimation Method and System

Abstract

The present invention discloses a method for estimating the position feedback of a communication encoder. The method first performs high-precision counting on the time between the previous encoder communication and the current encoder communication, calculates the increment of the encoder position between the previous encoder communication and the current encoder communication. When encoder data is obtained, these two data are used to calculate the magnitude of the encoder position increment per unit time. In each unit time, it is determined whether the encoder periodic communication is completed. If so, the encoder position prediction value is directly updated to the position data obtained from the current periodic communication; if not, the current encoder position prediction value is updated to the encoder position prediction value plus the encoder position increment per unit time. At any time, when the controller needs to use the encoder position data, the encoder position prediction value can be directly used. The present invention can improve the time density of the communication encoder feedback data and improve the accuracy of the encoder position data.

Description

Technical Field

[0001] The present invention relates to an encoder position data processing system, and particularly to a communication encoder feedback position estimation method and system. Background Art

[0002] Currently, in many motion control applications, encoders are required for precise position measurement. Currently, the commonly used encoders have three data output methods: incremental pulse, analog, and communication. Among them, the incremental pulse output is limited by the pulse output frequency and cannot achieve a very high data resolution; the analog output requires an additional signal subdivision circuit at the backend, increasing costs and being susceptible to interference; the communication output realizes communication between the controller and the encoder according to a certain protocol, has no resolution limit, generally uses a digital interface, and has a low cost. Therefore, it is used more and more widely and has become the mainstream choice.

[0003] Due to cost limitations, communication encoders generally use serial communication interfaces. The commonly used ones include the asynchronous serial communication interfaces of Japanese manufacturers. For example, manufacturers such as Tamagawa, Panasonic, and Mitsubishi use a 2.5Mbps half-duplex communication method; the synchronous serial communication interfaces of European manufacturers, such as BISS-C, SSI, EnDAT2.2, etc., use a set of clocks and a set of data lines. During communication, the controller initiates a data request, and the encoder serially sends the current position data to the controller at a predefined baud rate.

[0004] The existing technologies mainly have the following problems: Please refer to Figure 1 , the communication between the controller and the encoder is periodic, so the encoder position data obtained by the controller is discretized. Between two communications, the encoder position data in the controller does not change. In motion control applications, functions such as capturing or comparing an exact position are often used. If the encoder feedback position is discrete, there is a high probability that this position has passed between two communication cycles, and the comparison accuracy cannot be improved. Increasing the communication baud rate and shortening the communication cycle can increase the density of discrete position data, but the problem cannot be completely solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a communication encoder feedback position estimation method and system that can improve the time density of the feedback data of the communication encoder, so that the update of the encoder position data is not affected by the length of the communication cycle, and at the same time can improve the accuracy of the encoder position data.

[0006] The present invention will be described in more detail below with reference to the accompanying drawings and embodiments.

[0007] A communication type encoder feedback position estimation method, which is implemented based on a system. The system includes an encoder, an FPGA processor, and a CPU processor. The FPGA processor includes an encoder communication module, a cycle communication time counter, a cycle position increment register, a position prediction clock increment register, and a position prediction register. The method includes the following steps: Step S1, the encoder communication module establishes communication with the encoder, reads the encoder position data within each FPGA clock cycle, and after each reading of the encoder position data, executes: Step S1.0, performs a difference processing on the currently read encoder position data and the encoder position data read in the previous FPGA clock cycle to obtain the encoder position increment data and writes it into the cycle position increment register; Step S1.1, issues an FPGA clock cycle communication completion signal; Step S1.2, updates the currently read encoder position data to the position prediction register; Step S2, the cycle communication time counter increments by 1 after each FPGA clock cycle is completed, and when the FPGA clock cycle communication completion signal arrives, latches the current value of the cycle communication time counter, then the cycle communication time counter is reset to zero and starts counting again; Step S3, when the CPU processor receives the FPGA clock cycle communication completion signal, reads the values of the cycle communication time counter and the cycle position increment register, divides the encoder position increment data by the value of the cycle communication time counter to obtain the encoder position increment data within each FPGA clock cycle, and writes the encoder position increment data into the position prediction clock increment register; Step S4, within each FPGA clock cycle during the processing by the CPU processor, determines whether the FPGA clock cycle communication completion signal is received in this FPGA clock cycle. If so, writes the currently read encoder position data into the position prediction register; if not, adds the data in the position prediction clock increment register and the data in the position prediction register and updates it to the position prediction register; Step S5, when the system needs the encoder position data, directly calls the encoder position prediction data in the position prediction register.

[0008] Preferably, the position prediction clock increment register includes a position prediction clock increment integer part register and a position prediction clock increment decimal part register. The step S3 includes: Step S3.0, writes the integer part of the encoder position increment data into the position prediction clock increment integer part register; Step S3.1, writes the decimal part of the encoder position increment data into the position prediction clock increment decimal part register.

[0009] A communication type encoder feedback position estimation system, which includes an encoder, an FPGA processor, and a CPU processor. The FPGA processor includes an encoder communication module, a cycle communication time counter, a cycle position increment register, a position prediction clock increment register, and a position prediction register, where: The encoder communication module is used to establish communication with the encoder, read the encoder position data within each FPGA clock cycle, and after each reading of the encoder position data: perform a difference processing on the currently read encoder position data and the encoder position data read in the previous FPGA clock cycle to obtain the encoder position increment data and write it into the cycle position increment register; send an FPGA clock cycle communication completion signal; update the currently read encoder position data to the position prediction register; The cycle communication time counter is used to increment by 1 after each FPGA clock cycle is completed, and when the FPGA clock cycle communication completion signal arrives, latch the current value of the cycle communication time counter, then reset and clear the cycle communication time counter and start counting again; The CPU processor is used to read the values of the cycle communication time counter and the cycle position increment register when receiving the FPGA clock cycle communication completion signal, divide the encoder position increment data by the value of the cycle communication time counter to obtain the encoder position increment data within each FPGA clock cycle, and write the encoder position increment data into the position prediction clock increment register; and, within each FPGA clock cycle during the processing, determine whether the FPGA clock cycle communication completion signal is received in this FPGA clock cycle. If so, write the currently read encoder position data into the position prediction register; if not, add the data in the position prediction clock increment register and the data in the position prediction register and update it to the position prediction register; when the system needs the encoder position data, directly call the encoder position prediction data in the position prediction register.

[0010] Preferably, the position prediction clock increment register includes: a position prediction clock increment integer part register for writing the integer part of the encoder position increment data; a position prediction clock increment decimal part register for writing the decimal part of the encoder position increment data.

[0011] In the communication encoder feedback position estimation method and system disclosed by the present invention, first, high-precision counting is performed on the time between the last encoder communication and the current encoder communication, and the increment of the encoder position between the last encoder communication and the current encoder communication is calculated. When encoder data is obtained, these two data are used to calculate the magnitude of the encoder position increment per unit time. In each unit time, it is determined whether an encoder cycle communication is completed. If so, the encoder position prediction value is directly updated to the position data obtained in this cycle communication; if not, the current encoder position prediction value is updated to the encoder position prediction value plus the encoder position increment per unit time. At any time, when the controller needs to use the encoder position data, the encoder position prediction value can be directly used. Compared with the prior art, the present invention predicts the position data of the encoder during the next communication cycle interval through the encoder data of the previous cycle. The density of the encoder position prediction value during the communication cycle interval can reach the action beat level of the high-precision counter and is no longer affected by the length of the encoder cycle communication time interval. In addition, the present invention can improve the accuracy of the encoder position data by performing position estimation within the communication cycle, and preferably meets the application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the process of obtaining position data by a traditional communication encoder;

[0013] Figure 2 It is a schematic diagram of the process of predicting the position data of the communication encoder by the present invention;

[0014] Figure 3 It is a block diagram of the composition of the communication encoder feedback position estimation system of the present invention;

[0015] Figure 4 It is a flowchart of the algorithm of the present invention after the CPU processor receives the encoder communication completion signal;

[0016] Figure 5 It is a flowchart of the algorithm of the FPGA processor in each clock cycle of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The present invention will be described in more detail below in conjunction with the drawings and embodiments.

[0018] The present invention discloses a communication encoder feedback position estimation method, in combination with Figures 2 to 5As shown, the method is implemented based on a system, which includes an encoder 1, an FPGA processor 2, and a CPU processor 3. The FPGA processor 2 includes an encoder communication module 20, a cycle communication time counter 21, a cycle position increment register 22, a position prediction clock increment register 23, and a position prediction register 24. The method includes the following steps:

[0019] Step S1, the encoder communication module 20 establishes communication with the encoder 1, reads the encoder position data within each FPGA clock cycle, and after each reading of the encoder position data, executes:

[0020] Step S1.0, performs a difference operation on the currently read encoder position data and the encoder position data read in the previous FPGA clock cycle to obtain the encoder position increment data and writes it into the cycle position increment register 22;

[0021] Step S1.1, issues an FPGA clock cycle communication completion signal;

[0022] Step S1.2, updates the currently read encoder position data to the position prediction register 24;

[0023] Step S2, the cycle communication time counter 21 is incremented by 1 after each FPGA clock cycle is completed, and when the FPGA clock cycle communication completion signal arrives, latches the current value of the cycle communication time counter, then the cycle communication time counter 21 is reset to zero and starts counting again;

[0024] Step S3, when the CPU processor 3 receives the FPGA clock cycle communication completion signal, reads the values of the cycle communication time counter 21 and the cycle position increment register 22, divides the encoder position increment data by the value of the cycle communication time counter to obtain the encoder position increment data within each FPGA clock cycle, and writes the encoder position increment data into the position prediction clock increment register 23;

[0025] Step S4, within each FPGA clock cycle during the processing by the CPU processor 3, determines whether the FPGA clock cycle communication completion signal is received in this FPGA clock cycle. If so, writes the currently read encoder position data into the position prediction register 24; if not, adds the data in the position prediction clock increment register 23 and the data in the position prediction register 24 and updates it to the position prediction register 24;

[0026] Step S5, when the system needs the encoder position data, directly calls the encoder position prediction data in the position prediction register 24.

[0027] During the operation of the above method, the time between the last encoder communication and the current encoder communication is counted with high precision, and the increment of the encoder position between the last encoder communication and the current encoder communication is calculated. When the encoder data is obtained, these two data are used to calculate the magnitude of the encoder position increment per unit time. In each unit time, it is determined whether an encoder cycle communication is completed. If so, the encoder position prediction value is directly updated to the position data obtained in this cycle communication; if not, the current encoder position prediction value is updated to the encoder position prediction value plus the encoder position increment per unit time. At any time, when the controller needs to use the encoder position data, the encoder position prediction value can be directly used. Compared with the prior art, the present invention predicts the position data of the encoder in the next communication cycle interval through the encoder data of the previous cycle. The density of the encoder position prediction value in the communication cycle interval can reach the action beat level of the high-precision counter and is no longer affected by the length of the encoder cycle communication time interval. In addition, the present invention can improve the accuracy of the encoder position data by performing position estimation within the communication cycle, which better meets the application requirements.

[0028] As a preferred method, the position prediction clock increment register 23 includes a position prediction clock increment integer part register 230 and a position prediction clock increment fractional part register 231, and the step S3 includes:

[0029] Step S3.0, writing the integer part of the encoder position increment data into the position prediction clock increment integer part register 230;

[0030] Step S3.1, writing the fractional part of the encoder position increment data into the position prediction clock increment fractional part register 231.

[0031] In the above process, the position prediction clock increment integer part register is used to hold the integer part of the encoder prediction position increment in each FPGA clock cycle, and in each FPGA clock cycle, it is added to the position prediction register; the position prediction clock increment fractional part register is used to hold the fractional part of the encoder prediction position increment in each FPGA clock cycle, and in each FPGA clock cycle, the value of the fractional part is increased. When this value is greater than 1, 1 is added to the position prediction register.

[0032] On this basis, the position prediction register determines whether the encoder communication is completed in each FPGA clock cycle. If so, the encoder position obtained in this encoder communication is updated to this register. If not, the position prediction clock increment is accumulated according to the calculation rule of position prediction.

[0033] To better describe the technical solution of the present invention, the present invention also discloses a communication type encoder feedback position estimation system. Please refer to Figure 3 , which includes an encoder 1, an FPGA processor 2, and a CPU processor 3. The FPGA processor 2 includes an encoder communication module 20, a cycle communication time counter 21, a cycle position increment register 22, a position prediction clock increment register 23, and a position prediction register 24, where:

[0034] The encoder communication module 20 is used to establish communication with the encoder 1, read the encoder position data within each FPGA clock cycle, and after each reading of the encoder position data: perform a difference processing on the currently read encoder position data and the encoder position data read in the previous FPGA clock cycle to obtain the encoder position increment data and write it into the cycle position increment register 22; send a communication completion signal for one FPGA clock cycle; update the currently read encoder position data to the position prediction register 24;

[0035] The cycle communication time counter 21 is used to increment by 1 after each FPGA clock cycle is completed, and when the communication completion signal for the FPGA clock cycle arrives, latch the current value of the cycle communication time counter, and then the cycle communication time counter 21 is reset to zero and starts counting again;

[0036] The CPU processor 3 is used to read the values of the cycle communication time counter 21 and the cycle position increment register 22 when receiving the communication completion signal for the FPGA clock cycle, divide the encoder position increment data by the value of the cycle communication time counter to obtain the encoder position increment data within each FPGA clock cycle, and write the encoder position increment data into the position prediction clock increment register 23;

[0037] And, within each FPGA clock cycle during the processing, determine whether the communication completion signal for the FPGA clock cycle is received in this FPGA clock cycle. If so, write the currently read encoder position data into the position prediction register 24; if not, add the data in the position prediction clock increment register 23 and the data in the position prediction register 24 and update it to the position prediction register 24;

[0038] When the system needs the encoder position data, directly call the encoder position prediction data in the position prediction register 24.

[0039] In the above system, the encoder communication module communicates with the encoder periodically to obtain the encoder position data. Each time the position data is obtained, the difference between the current encoder position data and the encoder position data of the previous periodic communication is calculated, and the result is written into the periodic position increment register. Each time the position data is obtained, the value of the periodic communication time counter is saved, then the counter is cleared and restarted. After that, the periodic position increment is divided by the periodic communication time to obtain the increment of the encoder position in each counter beat, and this increment is written into the position prediction clock increment register. In each beat during the operation process, it is judged whether the encoder periodic communication is completed in this beat. If so, the encoder position data obtained in this periodic communication is written into the position prediction register; if not, the value of the position prediction clock increment register plus the position prediction register is updated to the position prediction register.

[0040] For the encoder position increment data, in this embodiment, the position prediction clock increment register 23 includes:

[0041] The integer part register 230 of the position prediction clock increment is used to write the integer part of the encoder position increment data;

[0042] The fractional part register 231 of the position prediction clock increment is used to write the fractional part of the encoder position increment data.

[0043] The communication type encoder feedback position estimation method and system disclosed by the present invention can refer to the following embodiments during the actual application process: Embodiment

[0044] Please refer to Figure 3 , Figure 3 which is the logic block diagram of the system of the present invention, mainly including an encoder, an FPGA processor and a CPU processor. The encoder is an encoder with a serial communication interface. The FPGA processor includes an encoder communication module, a periodic communication time counter, a periodic position increment register, an integer part register of the position prediction clock increment, a fractional part register of the position prediction clock increment and a position prediction register. Combined with Figures 3 to 5 shown, in the system of the present invention:

[0045] The encoder communication module implements the communication protocol of the encoder, periodically initiates the encoder data reading, and after obtaining the encoder position data, performs the following operations:

[0046] a. Calculate the encoder position increment of this period and the previous period, and write it into the periodic position increment register;

[0047] b. Send a signal indicating the completion of this periodic communication;

[0048] c. Update the encoder position data to the position prediction register.

[0049] The cycle communication time counter is incremented by 1 after each FPGA clock cycle. When the signal indicating the completion of the current cycle communication of the encoder communication module arrives, the following operations are performed:

[0050] d. Latch the current counter value;

[0051] e. Reset the counter value and start counting.

[0052] The CPU processor is mainly used to calculate the increment of the encoder position in each FPGA clock cycle. After receiving the signal indicating the completion of the current cycle communication sent by the encoder, it reads the values of the cycle communication time counter and the cycle position increment register, divides the cycle position increment by the cycle communication time to obtain the increment of the encoder position in each FPGA clock cycle, and then splits the increment into an integer part and a decimal part, which are written into the integer part of the position prediction clock increment register and the decimal part register of the position prediction clock increment in the FPGA.

[0053] The communication-type encoder feedback position estimation method and system disclosed in the present invention, compared with the prior art, has the beneficial effect that the present invention can improve the time density of the communication-type encoder feedback data, so that the update of the encoder position data is no longer affected by the length of the communication cycle of the communication-type encoder. In addition, the present invention can improve the accuracy of the encoder position data by performing position estimation during the communication cycle, and preferably meets the application requirements.

[0054] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements or improvements made within the technical scope of the present invention shall be included within the scope protected by the present invention.

Claims

1. A communication-type encoder feedback position estimation method, characterized in that This method is implemented based on a system, which includes an encoder (1), an FPGA processor (2), and a CPU processor (3). The FPGA processor (2) includes an encoder communication module (20), a cycle communication time counter (21), a cycle position increment register (22), a position prediction clock increment register (23), and a position prediction register (24). The method includes the following steps: Step S1, the encoder communication module (20) establishes communication with the encoder (1), reads the encoder position data within each FPGA clock cycle, and after each reading of the encoder position data, executes: Step S1.0, perform a difference processing on the currently read encoder position data and the encoder position data read in the previous FPGA clock cycle to obtain the encoder position increment data and write it into the cycle position increment register (22); Step S1.1, issue a signal indicating the completion of communication in one FPGA clock cycle; Step S1.2, update the currently read encoder position data to the position prediction register (24); Step S2, the cycle communication time counter (21) is incremented by 1 after each FPGA clock cycle is completed. When the signal indicating the completion of communication in the FPGA clock cycle arrives, latch the current value of the cycle communication time counter, then the cycle communication time counter (21) is reset to zero and starts counting again; Step S3, when the CPU processor (3) receives the signal indicating the completion of communication in the FPGA clock cycle, reads the values of the cycle communication time counter (21) and the cycle position increment register (22), divides the encoder position increment data by the value of the cycle communication time counter to obtain the encoder position increment data within each FPGA clock cycle, and writes the encoder position increment data within each FPGA clock cycle into the position prediction clock increment register (23); Step S4, within each FPGA clock cycle during the processing by the CPU processor (3), determine whether the signal indicating the completion of communication in the FPGA clock cycle is received in this FPGA clock cycle. If so, write the currently read encoder position data into the position prediction register (24); if not, add the data in the position prediction clock increment register (23) and the data in the position prediction register (24) and update the result to the position prediction register (24); Step S5, when the system needs the encoder position data, directly call the encoder position prediction data in the position prediction register (24).

2. The communication encoder feedback position estimation method according to claim 1, wherein The position prediction clock increment register (23) includes a position prediction clock increment integer part register (230) and a position prediction clock increment fractional part register (231). Step S3 includes: Step S3.0, write the integer part of the encoder position increment data into the position prediction clock increment integer part register (230); Step S3.1: Write the fractional part of the encoder position increment data into the position prediction clock increment fractional part register (231).

3. A communication encoder feedback position estimation system, characterized in that, It includes an encoder (1), an FPGA processor (2), and a CPU processor (3). The FPGA processor (2) includes an encoder communication module (20), a cycle communication time counter (21), a cycle position increment register (22), a position prediction clock increment register (23), and a position prediction register (24), where: The encoder communication module (20) is used to establish communication with the encoder (1), read the encoder position data in each FPGA clock cycle, and after each reading of the encoder position data: perform a difference processing on the currently read encoder position data and the encoder position data read in the previous FPGA clock cycle to obtain the encoder position increment data and write it into the cycle position increment register (22); send an FPGA clock cycle communication completion signal; update the currently read encoder position data to the position prediction register (24); The cycle communication time counter (21) is used to increment by 1 after each FPGA clock cycle is completed, and when the FPGA clock cycle communication completion signal arrives, latch the current value of the cycle communication time counter, then the cycle communication time counter (21) is reset to zero and starts counting again; The CPU processor (3) is used to read the values of the cycle communication time counter (21) and the cycle position increment register (22) when receiving the FPGA clock cycle communication completion signal, divide the encoder position increment data by the value of the cycle communication time counter to obtain the encoder position increment data in each FPGA clock cycle, and write the encoder position increment data in each FPGA clock cycle into the position prediction clock increment register (23); Moreover, in each FPGA clock cycle during the processing, it is judged whether the FPGA clock cycle communication completion signal is received in this FPGA clock cycle. If so, write the currently read encoder position data into the position prediction register (24); if not, add the data in the position prediction clock increment register (23) and the data in the position prediction register (24) and update the result to the position prediction register (24); When the system needs the encoder position data, directly call the encoder position prediction data in the position prediction register (24).

4. The communication type encoder feedback position estimation system according to claim 3, wherein The position prediction clock increment register (23) includes: A position prediction clock increment integer part register (230) for writing the integer part of the encoder position increment data; A position prediction clock increment fractional part register (231) for writing the fractional part of the encoder position increment data.

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