Test structure and method for detecting edge fin deformation in FinFET process

Abstract

The present invention provides a test structure for detecting the deformation of transistor edge fins in FinFET process, and provides a test method based on the test structure, which is used to detect the bending problem of edge fins caused by the characteristics of FinFET process; the test structure for detecting the deformation of edge fins in FinFET process, the test structure comprises a plurality of fins and a plurality of non-interconnected connection layers, the connection layers are connected to the two ends of each fin to be tested, the number of the fins ranges from 3 to 1000, the width of the fins ranges from 1 to 50nm, the length of the fins ranges from 0.1 to 1000um, and the distance between adjacent fins ranges from 1 to 100nm.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor manufacturing and relates to a test structure, in particular to a test structure for transistor edge fin deformation in a FinFET process. Background Art

[0002] With the continuous development of large-scale integrated circuit process technology, the integration of circuits continues to increase. When the process technology node is less than 28nm, there is a trend that traditional planar MOS devices are gradually replaced by three-dimensional fin field-effect transistors (FinFETs) due to rapid performance degradation. Figure 1 is a schematic diagram of the structure of a planar transistor. Figure 2 This is a schematic diagram of the structure of a three-dimensional fin field effect transistor. Compared with a planar transistor, the key dimensions of a FinFET device are determined by both gate height and width, and the gate material is distributed on both sides and the top of the transistor. A standard FinFET can be manufactured by etching away part of the silicon layer in the substrate to form a vertical thin fin (fin structure) extending from the substrate. Compared with the substrate surface channel under the gate of a traditional planar transistor, the FinFET channel is vertical, and the gates on both sides of the channel can control the channel from both sides.

[0003] FinFET devices are the best choice for processes below 22nm, but since they are manufactured at the nanometer level, they face many challenges. Based on the characteristics of FinFET devices, the channel source and drain in FinFET technology form a three-dimensional structure. To ensure this structure, etching must be carried out in a certain proportion according to the width and depth. In order to evenly distribute the doping on the three-dimensional surface, all fin structures need to be grown and arranged in a certain spacing ratio. All Fin structures must be placed on the Fin specified row. Therefore, the gate-controlled channel can only be adjusted by placing more data Fin structure gates at equal distances. This process characteristic results in the Fin manufactured in the middle area having better shape and performance, while the Fin manufactured in the edge area often has problems such as crystal deformation, bending, and collapse, such as Figure 3 . In the FinFET manufacturing process, after the STI OX (shallow trench isolation silicon oxide) is filled, it needs to be treated at a high temperature of more than 1000 degrees. During the treatment, the STI OX will shrink and generate tensile stress. The outermost Fin has inconsistent volumes of OX (silicon oxide) on the left and right, and the tensile stress generated is also inconsistent, which can easily cause the edge Fin to bend, thereby affecting the subsequent EPI (epitaxial wafer) growth, especially the size and intrinsic stress of EPI, which can greatly improve the flexibility of device design and device performance. Therefore, a test structure is needed in the process of integrated circuit manufacturing to detect, characterize and monitor this process problem. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the existing process technology, the purpose of the present invention is to provide a test structure for detecting the deformation of transistor edge fins in the FinFET process, and to provide a test method based on the test structure for detecting the bending problem of the edge fins caused by the characteristics of the FinFET process.

[0005] A test structure for detecting edge fin deformation in FinFET process, the test structure includes a plurality of fins and a plurality of non-interconnected connection layers, the connection layers are connected to both ends of each fin to be tested, the number of the fins ranges from 3 to 1000, the width of the fins ranges from 1 to 50 nm, the length of the fins ranges from 0.1 to 1000 um, and the distance between adjacent fins ranges from 1 to 100 nm.

[0006] Preferably, the test structure is arranged based on a FinFET transistor, including a substrate, a gate, a source, a drain, a plurality of fins and a plurality of non-interconnected connection layers, wherein the plurality of non-interconnected connection layers are arranged on the fins to be tested.

[0007] Preferably, two connection layers form a group, each group of connection layers covers the same fin, and positions of the two connection layers in the group are symmetrical with respect to the gate.

[0008] Based on the test method of the test structure for detecting edge fin deformation in the FinFET process, the current acquisition unit, voltage source, voltage acquisition unit, and current source are connected to the test structure to test any two combinations of resistance, current, or voltage of the fin to be tested; the fin to be tested includes at least one edge fin located at the edge and one middle fin located in the middle, and the deformation degree of the edge fin is determined with reference to the test value of the middle fin: the deformation degree of the fin to be tested is characterized by testing the resistance of the fin to be tested, with reference to the resistance value of the middle fin, the greater the resistance of the edge fin, the greater the deformation degree of the fin; or when the test structure is based on the FinFET transistor setting, the deformation degree of the FinFET transistor is characterized by testing the saturation current Idsat or Ioff of the FinFET transistor, with reference to the resistance value of the middle fin, the smaller the Idsat measured by the edge fin or the larger the Ioff, the greater the deformation degree of the fin. In some embodiments, each fin in a test structure is configured with a connection layer and each fin is a fin to be tested; in some embodiments, all fins in a test structure are configured with a connection layer, and the fins configured with the connection layer are fins to be tested.

[0009] Preferably, when the deformation degree of the fin to be tested is characterized by testing its resistance, the combination of the access test structure is: a current acquisition unit and a voltage source, and the voltage source and the current acquisition unit are connected in series to the connection layers at both ends of the fin to be tested. The method of accessing this structure for testing is called a two-terminal measurement method.

[0010] Preferably, when the deformation degree of the fin to be tested is characterized by testing its resistance, the combination of the access test structure is: a current source and two voltage acquisition units, the current source is connected to the connection layer at both ends of the fin to be tested, and the two voltage acquisition units are respectively connected to the two ends of the fin. The method of accessing this structure for testing is a four-terminal measurement method.

[0011] Preferably, when the test structure is set up based on a FinFET transistor, the combination connected to the test structure is: a current collection unit and two voltage sources; the substrate end of the FinFET transistor in the test structure is grounded, the first voltage source is connected to the gate of the FinFET transistor, the second voltage source is connected to one end of the fin to be tested through a connecting layer, and the current collection unit is connected between the other end of the fin to be tested and the ground.

[0012] Preferably, two or more edge fins in one test structure are divided into one or more pattern tests.

[0013] Preferably, a plurality of test structures are included, and the fins in each test structure are numbered according to the same rule, and the fins with the same serial number in the plurality of test structures can be connected in series or in parallel for testing.

[0014] In some embodiments, fins with the same serial number in multiple test structures can be tested in series or in parallel. The above-mentioned test structure for detecting the deformation of the edge fins of the transistor in the FinFET process is designed according to the characteristics of the FINFET process, and the structure is simple and easy to manufacture. And the test reliability is high, and it can accurately detect and compare the deformation degree of the edge fins, so as to monitor the integrated circuit manufacturing process, help manufacturers to find problems in time, improve the manufacturing plan in time, and greatly save production cost investment. In the method of using resistance to characterize the degree of fin deformation, the two-terminal measurement method has a simple circuit structure and convenient testing. The four-terminal measurement method circuit eliminates the lead resistance and contact resistance test compared to the two-terminal measurement method, which is more accurate. In the method of using current to characterize the fin deformation, the deformation degree can be comprehensively characterized by multiple current parameters (Idsat, Ioff) of the transistor, and the test is accurate and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the structure of a planar transistor.

[0016] Figure 2 It is a schematic diagram of the structure of a three-dimensional fin field effect transistor.

[0017] Figure 3 Schematic diagram of the bending and eventual collapse of the fins of a three-dimensional FinFET.

[0018] Figure 4 This is a test structure diagram in Example 1.

[0019] Figure 5 Based on Figure 4 Circuit connection diagram for testing the test structure (two-terminal method test).

[0020] Figure 6 Based on Figure 4 Circuit connection diagram for testing the test structure (four-terminal test).

[0021] Figure 7 This is the result distribution diagram of Example 1 based on the data in Table 1.

[0022] Figure 8 This is a circuit connection diagram for testing the test structure based on the FinFET transistor in Example 2.

[0023] Fig. 9 for Figure 8 Circuit connection diagram of a fin under test.

[0024] Fig.10 This is a distribution diagram of the test results of Example 2 based on the data in Table 2. DETAILED DESCRIPTION

[0025] Embodiment 1:

[0026] A test structure used in FinFET process to detect the deformation of transistor edge fins, the test structure includes a plurality of fins and a plurality of non-interconnected connection layers, the connection layers are located at both ends of each fin to be tested. The number of fins ranges from 1 to 1000, the width of the fin is 1 to 50 nm, the length of the fin is 0.1 to 1000 um, and the distance between the fins is between 1 and 100 nm. Figure 4 is a schematic diagram of the test structure.

[0027] Based on the above-mentioned test structure for detecting edge fin deformation, the present invention also provides a method for detecting edge fin deformation, wherein the degree of deformation is characterized by testing the resistance of the fin, with the resistance value of the middle fin as a reference. The greater the resistance of the edge fin, the greater the degree of deformation of the fin.

[0028] Adapted to the above-mentioned test method for detecting edge fin deformation, the present invention also provides a test circuit for detecting edge fin deformation: a two-terminal test circuit and a four-terminal test circuit.

[0029] The two-terminal method test circuit specifically includes the test structure used to detect edge fin deformation in the FinFET process, a current collection unit and a voltage source, wherein the voltage source is connected to the connection layer at both ends of the edge fin to be tested, and the current collection unit is connected to one end of the edge fin. The circuit structure diagram and equivalent circuit diagram are as follows: Figure 5 shown.

[0030] The voltage source applies a certain voltage excitation to the fin structure through the connection layer, and the current of the current acquisition test circuit is used to calculate the resistance value by the formula R=U / I. The resistance of the middle fin is used as a reference, and the degree of bending of the edge fin is determined by detecting and comparing the resistance values ​​of multiple fins.

[0031] The four-terminal method test circuit specifically includes the test structure used for detecting edge fin deformation in FinFET process, a current source and two voltage acquisition units. f The connection layer connected to the two ends of the edge fin to be tested, the two voltage collection units V h 、V l They are connected to the two ends of the edge fins respectively. The circuit structure diagram and equivalent circuit diagram are as follows: Figure 6 shown.

[0032] Current source to I f A certain current is applied to the fin under test, and the voltage acquisition unit V h 、V l The voltages at both ends of the fin under test are collected respectively, and the formula R = (V h -V l ) / I f The resistance value is calculated, and the resistance of the middle fin is used as a reference. The bending degree of the edge fin is determined by detecting and comparing the resistance values ​​of multiple fins. The four-terminal measurement collects the potential difference between the two ends of the fin to be measured through two voltage acquisition units, avoiding the lead voltage drop and contact resistance, so the measured resistance value is more accurate.

[0033] In this embodiment, 29 fins were selected for actual measurement, and the test results are shown in Table 1 and Figure 7 As shown in the figure, it can be seen that the resistance of the middle fin is smaller and its EPI size is larger, and the resistance of the fin increases and its EPI size decreases as it moves toward the edge.

[0034] Fin location Resistance EPI Size 1 150 50.94916 3 140 60.53714 5 130 70.87391 7 125 75.92162 9 120 80.41777 11 119 81.20692 13 118 82.92535 15 117 83.6805 17 117 83.35445 19 118 82.6315 21 120 80.38091 23 125 75.37433 25 131 69.53383 27 141 59.95234 29 149 51.42127

[0035] Table 1

[0036] In this embodiment, the two-terminal test structure selects the fins with connection layers configured at intervals as the fins to be tested; the four-terminal test structure selects one fin with connection layers configured at every three fins as the fins to be tested. Users can define the density of the fins to be tested according to their needs.

[0037] In some embodiments, the fins to be tested include at least two: an edge fin and a middle fin.

[0038] In some embodiments, each fin in the test structure is configured with a connection layer and each fin is a fin to be tested.

[0039] In some embodiments, if there are multiple identical test structures, fins with the same serial number in each test structure can be tested in series or in parallel, wherein the series test can amplify the resistance change of the fins, which is particularly suitable for testing situations where deformation is not obvious.

[0040] In some embodiments, several edge fins in a test structure can be connected externally to a test device in the test structure for testing, or several edge fins can be divided into two or more patterns for testing. Dividing the pattern test is particularly suitable for situations where the fin density is high and it is not easy to connect all the leads externally to the test device for testing.

[0041] Embodiment 2:

[0042] A test structure for detecting fin deformation at the edge of a transistor in a FinFET process. The test structure is based on a FinFET transistor structure and includes a plurality of FinFET transistors and a plurality of non-interconnected connection layers. The FinFET transistor includes a substrate, a gate, a source, a drain and a plurality of fins. The plurality of connection layers are connected to the two ends of the fin to be tested. The number of the fins ranges from 3 to 1000, the width of the fin is 1 to 50 nm, the length of the fin is 0.1 to 1000 um, and the distance between the fins is between 1 and 100 nm.

[0043] Based on the above-mentioned test structure for detecting the deformation of the edge fins of the transistor, the present invention also provides a method for detecting the deformation of the edge fins, by testing the saturation current Idsat or the off current Ioff of the FinFET transistor to characterize its deformation degree, and taking the Idsat or Ioff of the middle fin as a reference. The smaller the Idsat or the larger the Ioff, the greater the deformation degree of the fin.

[0044] Based on the above-mentioned test structure and test method for detecting the deformation of transistor edge fins, the present invention also provides a test circuit, which specifically includes a test structure, a current collection unit and a voltage source for detecting the deformation of transistor edge fins in the FinFET process. The substrate end of the FinFET transistor is grounded, and the voltage source includes a first voltage source applied to the gate of the FinFET transistor and a second voltage source applied to one end of the fin to be tested through a connecting layer, and the current collection unit is connected between the other end of the fin to be tested and the ground end. Its circuit structure diagram is shown as follows Figure 8-9 shown.

[0045] When measuring Idsat, the first voltage source of the gate applies voltage to control the operation of the transistor, and the second voltage source applies voltage to the fin to be measured, which is equivalent to applying voltage to the source or drain of the transistor, and the current collection unit collects the current between the source and the drain. Taking the middle fin as a reference, the deformation degree of the edge fin is determined by comparing the saturation current Idsat of the measured edge fin with that of the middle fin. The smaller the Idsat is relative to the middle fin, the greater the deformation of the fin.

[0046] When measuring Ioff, the first voltage source does not apply voltage or applies a voltage less than the threshold voltage, and the second voltage source does not apply voltage, and Ioff is directly tested at the drain. Taking the middle fin as a reference, the deformation degree of the edge fin is determined by comparing the leakage current Ioff of the measured edge fin with that of the middle fin. The larger the Ioff relative to the middle fin, the greater the deformation of the fin.

[0047] In this embodiment, 25 fins were selected for actual measurement, and the test results are shown in Table 2 and Fig.10 As shown, it can be seen that the Idsat of the middle fin is larger, the Ioff is smaller, and the EPI intrinsic stress is larger. The closer to the edge, the smaller the Idsat of the fin, the larger its Ioff, and the smaller the intrinsic stress of its EPI.

[0048] Fin location Idsat EPI Intrinsic Stress Idoff 1 49.9 39.9 10 3 52.9 42.9 8 5 54.2 44.2 7.6 7 54.0 44.0 7.4 9 54.3 44.3 7.2 11 54.2 44.2 7.4 13 54.4 44.4 7.5 15 53.9 43.9 7.5 17 54.6 44.6 7.4 19 54.3 44.3 7.2 21 53.6 43.6 7.8 23 53.3 43.3 8.2 25 49.5 39.5 10

[0049] Table 2

[0050] In this embodiment, the test mechanism selects the fins to be tested that are configured with a connection layer between the fins and the fins configured with the connection layer. The user can define the density of the fins to be tested according to the requirements.

[0051] In some embodiments, the fin to be tested includes at least two fins, one edge fin and one middle fin.

[0052] In some embodiments, each fin in the test structure is configured with a connection layer and each fin is a fin to be tested.

[0053] In some embodiments, if there are multiple identical test structures, fins with the same serial number in each test structure can be tested in series or in parallel, wherein the series test can amplify the resistance change of the fins, which is particularly suitable for testing situations where deformation is not obvious.

[0054] In some embodiments, several edge fins in a test structure can be connected externally to a test device for testing in the test structure, or the several edge fins can be divided into two or more patterns for testing. Dividing the pattern testing into multiple patterns is particularly suitable for situations where the fin density is high and it is not easy to connect all the leads externally to the test device for testing.

Claims

1. A test structure for detecting edge fin deformation in FinFET process, characterized in that: The test structure includes a plurality of fins and a plurality of non-interconnected connection layers, wherein the connection layers are connected to both ends of each fin to be tested, and the non-interconnected connection layers refer to that the connection structures at both ends of each fin are connected separately; the number of the fins ranges from 3 to 1000, the width of the fins ranges from 1 to 50 nm, the length of the fins ranges from 0.1 to 1000 um, and the distance between the fins ranges from 1 to 100 nm; The deformation degree of the fin is characterized by testing the resistance of the fin, with the resistance value of the middle fin as a reference. The greater the resistance of the edge fin, the greater the deformation degree of the fin.

2. A test circuit generated by the test structure for detecting edge fin deformation according to claim 1, characterized in that: The test circuit includes a two-terminal test circuit and a four-terminal test circuit; The two-terminal method test circuit comprises the test structure, a current collection unit and a voltage source, wherein the voltage source and the current collection unit are connected in series to the connection layers at both ends of the fin to be tested; The four-terminal test circuit includes the test structure, a current source and two voltage collection units. The current source is connected to the connection layer at both ends of the fin to be tested, and the two voltage collection units are respectively connected to both ends of the fin.

3. A test structure for detecting edge fin deformation in FinFET process, characterized in that: The test structure includes a FinFET transistor and a plurality of non-interconnected connection layers, wherein the non-interconnected connection layers refer to that the connection structures at both ends of each fin are connected separately; the FinFET transistor includes a substrate, a gate, a source, a drain and a plurality of fins, wherein the plurality of non-interconnected connection layers vertically cover the fins to be tested; the number of the fins ranges from 3 to 1000, the width of the fins ranges from 1 to 50 nm, the length of the fins ranges from 0.1 to 1000 um, and the distance between the fins ranges from 1 to 100 nm; The deformation degree of the FinFET transistor is characterized by testing its saturation current Idsat or off current Ioff, with the Idsat or Ioff value of the middle fin as a reference. The smaller the Idsat or the larger the Ioff measured at the edge fin, the greater the deformation degree of the fin.

4. The test structure for detecting edge fin deformation according to claim 3, characterized in that: Two of the connection layers form a group, each group of connection layers covers the same fin, and positions of the two connection layers in the group are symmetrical relative to the gate.

5. A test circuit generated by the test structure for detecting edge fin deformation according to claim 3, characterized in that: The test circuit includes the test structure, a current collection unit and two voltage sources; the substrate end of the FinFET transistor in the test structure is grounded, the first voltage source is connected to the gate of the FinFET transistor, the second voltage source is connected to one end of the fin to be tested through a connecting layer, and the current collection unit is connected between the other end of the fin to be tested and the ground end. 6 . According to the test structure for detecting edge fin deformation in FinFET process according to claim 1 or 3 , the fin to be tested comprises at least two, one edge fin and one middle fin. 7 . According to the test structure for detecting edge fin deformation in FinFET process in claim 1 or 3 , each fin is configured with a connection layer and each fin is a fin to be tested. 8 . According to the test structure for detecting edge fin deformation in FinFET process in claim 1 or 3 , connection layers are arranged between all fins, and the fins arranged with connection layers are the fins to be tested. 9 . According to the test structure for detecting edge fin deformation in FinFET process according to claim 1 or 3 , the detection of edge fin can be tested on one or more patterns. 10 . According to the test structure for detecting edge fin deformation in FinFET process in claim 1 or 3 , fins with the same serial number in multiple test structures can be tested in series or in parallel.

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