Ferroelectric capacitor with a back-end transistor

Abstract

An integrated circuit includes a back-end thin film transistor (TFT) and a ferroelectric capacitor electrically connected to the back-end TFT. The back-end TFT has a gate electrode, a source region, a drain region, a semiconductor region between the source region and the drain region and physically connecting the source region and the drain region, and a gate dielectric between the gate electrode and the semiconductor region. The ferroelectric capacitor has a first terminal electrically connected to one of the source region and the drain region, a second terminal, and a ferroelectric dielectric between the first terminal and the second terminal. In an embodiment, a memory cell includes the integrated circuit, the gate electrode is electrically connected to a word line, the source region is electrically coupled to a bit line, and the drain region is one of the source region and the drain region. In an embodiment, an embedded memory includes word lines, bit lines, and a plurality of such memory cells at the intersection regions of the word lines and the bit lines.

Description

BACKGROUND OF THE INVENTION

[0001] Embedded dynamic random access memory (eDRAM) and embedded static RAM (eSRAM) are typically associated with silicon front-end processes. As such, due to factors such as transistor size and pitch limitations, such memories occupy a large amount of integrated circuit (IC) area. Ferroelectric memories can be used as non-volatile DRAM and eDRAM replacement memories. Ferroelectric materials are strong contenders for capacitor dielectric structures. However, with newer semiconductor process technologies, the dielectric structure area (and thus, the total stored polarization charge) in integrated circuit capacitors has been greatly reduced. This makes ferroelectric capacitor scaling very challenging. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 is a cross-sectional view of an example integrated circuit in accordance with an embodiment of the present disclosure, which includes a stacked ferroelectric capacitor with a back-end thin film transistor (TFT).

[0003] Figure 2 is a cross-sectional view of an example integrated circuit in accordance with an embodiment of the present disclosure, which includes a U-shaped ferroelectric capacitor with a back-end TFT.

[0004] Figure 3 is a cross-sectional view of an example embedded memory in accordance with an embodiment of the present disclosure.

[0005] Figures 4A - 4B are a cross-sectional view and a plan view, respectively, of an example selector TFT of a memory cell in accordance with an embodiment of the present disclosure.

[0006] Figures 5A - 5B is in accordance with an embodiment of the present disclosure Figures 4A - 4B of a cross-sectional view of an example structure of a selector TFT in a memory cell.

[0007] Figures 6A - 6B are respectively in accordance with an embodiment of the present disclosure Figures 4A - 4B of a cross-sectional view and a plan view of an example metal-insulator-metal (MIM) capacitor in a memory cell.

[0008] Figure 7 is in accordance with an embodiment of the present disclosure Figures 6A - 6B of a cross-sectional view of an example structure of a MIM capacitor in a memory cell.

[0009] Figure 8 is a schematic plan view of an example embedded memory configuration in accordance with an embodiment of the present disclosure.

[0010] FIG. 9A is a plan view of an example layout of an embedded memory where the memory array and the memory peripheral circuit do not overlap.

[0011] FIG. 9B-9C is a plan view of an example layout of an embedded memory in the case where a memory array and memory peripheral circuits overlap, according to an embodiment of the present disclosure.

[0012] Figure 10 FIG. illustrates an example method of fabricating an embedded memory according to an embodiment of the present disclosure.

[0013] Figure 11 FIG. illustrates an example computing system implemented using the integrated circuit structures and techniques disclosed herein, according to an embodiment of the present disclosure.

[0014] These and other features of the presented embodiments will be better understood by reading the following detailed description in conjunction with the Figure 1 illustrations herein. In the figures, each identical or nearly identical component illustrated in various figures may be represented by a like reference numeral. For clarity, not every component may be labeled in every figure. Further, as will be appreciated, the figures are not necessarily drawn to scale or are not intended to limit the described embodiments to the specific configurations shown. For example, although some figures generally depict straight lines, right angles, and smooth surfaces, given the limitations of manufacturing processes in the real world, the actual implementation of the disclosed technology may not have perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth. In short, the figures are provided only to illustrate example structures. DETAILED DESCRIPTION

[0015] According to various embodiments of the present disclosure, an embedded one-transistor one-capacitor (1T1C) memory cell includes a ferroelectric capacitor that is electrically coupled to a back-end transistor. An array of such memory cells may form an embedded non-volatile memory (eNVM). The back-end transistor may be a thin-film transistor (TFT). The back-end TFT may assist in ferroelectric scaling, such as by improving memory array efficiency due to the ability to tuck in a sensing peripheral (e.g., memory peripheral circuits) under the back-end TFT 1T1C array. Looking in further detail, a ferroelectric material switches its polarization from a parallel to an anti-parallel state (or vice versa). This change in internal polarization occurs at positive and negative voltages (referred to as coercive voltage or coercive field). This causes different amounts of charge polarization and polarity within the ferroelectric material. When used as a dielectric material in a capacitor, the switching of the ferroelectric material between the parallel and anti-parallel states can be used to create a non-volatile memory, such as an eNVM.

[0016] In one or more embodiments of the present disclosure, an integrated circuit is provided. The integrated circuit includes a back-end thin film transistor (TFT) and a ferroelectric capacitor on or otherwise electrically connected to the back-end TFT. The back-end TFT (which may be, for example, on a front-end circuit such as a memory array controller, electrically coupled to the front-end circuit, or otherwise electrically connected to the front-end circuit) has a gate electrode, a source region, and a drain region, a semiconductor region between the source region and the drain region and physically connecting the source region and the drain region, and a gate dielectric between the gate electrode and the semiconductor region. The ferroelectric capacitor has a first terminal electrically connected to one of the source region and the drain region, a second terminal, and a ferroelectric dielectric between the first terminal and the second terminal. In an embodiment, a memory cell includes the TFT-capacitor arrangement, where the gate electrode is electrically connected to a word line, the source region is electrically connected to a bit line, and the drain region is one of the source region and the drain region. In another embodiment, an embedded memory includes a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of such memory cells at the intersection regions of the word lines and the bit lines.

[0017] Overall Overview

[0018] According to some embodiments of the present disclosure, an eNVM memory cell includes a ferroelectric capacitor that is connected to a back-end transistor, such as a back-end TFT. The ferroelectric capacitor uses a ferroelectric material to store a bit (logic 1 or 0) in the eNVM. Reading of the memory cell can be either destructive or non-destructive. Two different states (parallel or anti-parallel) of the ferroelectric capacitor can be sensed, for example, on the bit line. For example, by selecting the memory cell (e.g., using a unique combination of a bit line and a word line driven by a control circuit such as a word line driver), amplifying the bias brought by the ferroelectric capacitor on the bit line (e.g., using a sense amplifier), and comparing the amplified sensed bias with the bias of an unbiased bit line, the state (e.g., parallel or anti-parallel) of the ferroelectric capacitor can be determined. Using a back-end TFT, such as a TFT formed during a back-end-of-line (BEOL) process, a front-end-of-line (FEOL) process can be used to fabricate memory controller (e.g., word line driver, sense amplifier, etc.) logic under the memory array. This allows for more space for the ferroelectric capacitors, and the more space increases their corresponding capacitance, thus allowing them to continue to act as memory devices even when using smaller process technologies such as 10 nanometers (nm), 7 nm, 5 nm, and others.

[0019] In short, by creating 1T1C eNVM memory cells using ferroelectric capacitors electrically connected to back-end TFTs, one or more embodiments of the present disclosure allow a memory cell array to be embedded in an interconnecting upper metal layer (BEOL). This allows for higher memory density, better performance, and scalability. In other words, by creating memory cells by embedding a ferroelectric capacitor memory array in upper BEOL interconnects using back-end TFTs, one or more embodiments of the present disclosure provide a viable path for integrating ferroelectric capacitors in advanced technology nodes, where FEOL ferroelectric capacitor sizing would otherwise be extremely challenging. With TFT-based ferroelectric capacitor eNVM, the memory array can be integrated in higher metal layers where design rules are relaxed and process variations from generation to generation are less. This enables an easier path for integrating ferroelectric capacitors as memory devices into different process nodes.

[0020] Architecture and Methodology

[0021] Figure 1 FIG. 7 is a cross-sectional (X-Z) view of an example integrated circuit in accordance with an embodiment of the present disclosure, the example integrated circuit including a stacked ferroelectric capacitor 190 with back-end thin film transistors (TFTs). Throughout, the z-axis represents the vertical dimension (e.g., perpendicular to the integrated circuit substrate), while the x-axis and y-axis represent the horizontal dimensions (e.g., parallel to the word line and bit line directions, respectively). Figure 1 The components of can be fabricated using semiconductor manufacturing techniques such as deposition and lithography. Figure 1 The components of can be part of a back-end process, such as the back-end-of-line (BEOL) process of a semiconductor integrated circuit. As such, Figure 1 the components of can be part of, or fabricated concurrently with, a metal interconnect layer of a semiconductor manufacturing process, such as an upper metal interconnect layer or an intermediate metal interconnect layer.

[0022] For example, Figure 1 the fabrication of the components of can be part of the metal 4 (interconnect) layer of the BEOL process, typically formed using a custom process (e.g., separate from other metal 4 features). In Figure 1 FIG. 8, an interlayer dielectric (ILD) 110 is formed. In some embodiments, the ILD 110 is an etch stop covering a metal interconnect layer, such as a metal 3 interconnect layer. The ILD 110 can be an etch-resistant material, such as silicon nitride (e.g., Si3N4) or silicon carbide (e.g., SiC).

[0023] A gate (or gate electrode) 120 is formed over the ILD 110. The gate 120 is conductive and may represent one or more layers or features for supplying a gate signal to the back-end TFT. For example, the gate 120 may include word lines for supplying a gate signal from a word line driver (such as word lines made of copper (Cu) or aluminum (Al)), together with a diffusion barrier and a metal gate electrode for supplying a gate signal to the channel region of the back-end TFT, as will be described in further detail below.

[0024] The gate 120 is covered with a gate dielectric 130 corresponding to the active (semiconductor) layer 140 of the back-end TFT (or the channel region of the active layer corresponding to the back-end TFT). The gate dielectric 130 may be a high-k dielectric material, such as hafnium dioxide (HfO2). The gate dielectric 130 is thin, such as 4 nanometers (nm). In some embodiments, the gate dielectric 130 is in the range of 3 nm to 7 nm. In some embodiments, the gate dielectric 130 is in the range of 2 nm to 10 nm.

[0025] A semiconductive active layer 140 is formed over the gate dielectric 130. The active layer 140 may be formed of, for example, one or more of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), and amorphous germanium (a-Ge). The active layer 140 may be divided into three different regions, namely a source region 142 and a drain region 144, where a channel region 146 is between the source region 142 and the drain region 144 and physically connects the source region 142 and the drain region 144. The active layer 140 forms a transistor device having the gate 120 and the gate dielectric 130. When a gate signal is supplied to the gate 120, the active layer 140 becomes conductive, and current flows between the source region 142 and the drain region 144 via the channel region 146.

[0026] In some embodiments, the active layer 140 is formed of a first type of channel material, which may be an n-type channel material or a p-type channel material. The n-type channel material may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), amorphous silicon (a-Si), zinc oxide (e.g., ZnO), amorphous germanium (a-Ge), polysilicon (or poly-Si), polycrystalline germanium (poly-Ge), or polycrystalline III-V indium arsenide (InAs). On the other hand, the p-type channel material may include amorphous silicon, zinc oxide (e.g., ZnO), amorphous germanium (a-Ge), polysilicon, polycrystalline germanium, polycrystalline III-V InAs, copper oxide (e.g., CuO), or tin oxide (e.g., SnO). The channel region 146 has a thickness in the range of about 10 nm to about 100 nm.

[0027] Above the active layer 140, a source electrode 150 is formed above the source region 142 and the source electrode 150 is electrically connected to the source region 142, a drain electrode 170 is formed above the drain region 144 and the drain electrode 170 is electrically connected to the drain region 144, and a capping layer 160 is formed above the channel region 146 and between the source electrode 150 and the drain electrode 170. The capping layer 160 forms a good interface with the material of the active layer 140, thereby preventing leakage and being hermetic to other metal layers or features. In some embodiments, the capping layer 160 physically connects the source electrode 150 and the drain electrode 170 and electrically isolates the source electrode 150 from the drain electrode 170. For example, in some embodiments, the capping layer 160 comprises an insulator material such as aluminum oxide (e.g., Al2O3), gallium oxide (e.g., Ga2O3), silicon nitride (e.g., Si3N4, SiN), silicon dioxide (SiO2), titanium dioxide (TiO2), hafnium dioxide (HfO2), silicon oxynitride (e.g., Si2N2O, SiO x N y , where 0 ≤ x ≤ 2 and 0 ≤ y ≤ 4 / 3), aluminum silicate (e.g., Al2O3(SiO2) x , where x>0), tantalum oxide (e.g., Ta2O5), hafnium tantalum oxide (e.g., HfTa x O y , where x>0 and y>2), aluminum nitride (e.g., AlN), aluminum silicon nitride (e.g., AlSi x N y , where x > 0 and y > 1), silicon aluminum oxynitride (sialon) (e.g., AlSi x O y N z , where x>0, y>0 and z>0), zirconium dioxide (ZrO2), hafnium zirconium oxide (e.g., HfZr x O y , where x>0 and y>2), tantalum silicate (e.g., TaSi x O y , where x>0 and y>0), hafnium silicate (e.g., HfSiO4, HfSi x O y , where x>0 and y>2), etc.

[0028] The source electrode 150 and the drain electrode 170 may be metals such as metal interconnect layer materials (e.g., Cu, Al, or tungsten (W)). The back-end TFT acts as a switch that electrically connects the source electrode 150 and the drain electrode 170 in response to a gate signal supplied to the gate 120.

[0029] The storage node 180 (e.g., additional metal interconnect material) is formed over the drain electrode 170 and is electrically connected to the drain electrode 170. The ferroelectric capacitor 190 is formed over the storage node 180 and is electrically connected to the storage node 180. In Figure 1 , the ferroelectric capacitor 190 is a metal-insulator-metal (MIM) capacitor having a stacked structure. For example, Figure 1 the ferroelectric capacitor 190 in is formed using layers that include a first terminal 192 and a second terminal 194 composed of metal or other conductive material and a ferroelectric dielectric layer 196 between the first terminal 192 and the second terminal 194 that electrically insulates the first terminal 192 from the second terminal 194. The first terminal 192 is electrically connected to the drain region 144 through the drain electrode 170 and the storage node 180. The ferroelectric dielectric layer 196 includes one or more of the following: lead zirconate titanate (PZT), hafnium zirconium oxide (HZO), barium titanate (BaTiO3), lead titanate (PbTiO3), and doped hafnium dioxide (HfO2). Doped HfO2 may include one or more of silicon-doped HfO2, yttrium-doped HfO2, and aluminum-doped HfO2.

[0030] The ferroelectric material in the dielectric layer 196 has a hysteresis effect; each lattice in different lattices in the ferroelectric material aligns parallel or anti-parallel. By using a coercive field to align all or most of the lattices parallel or anti-parallel, the ferroelectric material can exhibit a memory value (logic 0 or 1) corresponding to one of two orientations. The ferroelectric material continues to maintain this value (orientation) even when power is no longer supplied to the integrated circuit. For example, the lattice orientation in the ferroelectric material does not change under normal conditions, which is different from ordinary DRAM capacitors that leak the charge they store over time and require frequent refreshing to maintain their memory state.

[0031] Figure 2 is a cross-sectional (X-Z) view of an example integrated circuit according to an embodiment of the present disclosure. The example integrated circuit includes a U-shaped ferroelectric capacitor 290 with a back-end TFT. Here, the integrated circuit has a structure similar to Figure 1 , but the ferroelectric capacitor 290 has a U-shaped structure having a first terminal 292 and a second terminal and a U-shaped ferroelectric dielectric 296. The U-shape can utilize a thicker metal interconnect layer to etch relatively deep trenches to increase the capacitance surface area and capacitance without increasing the planar area. The example U-shaped capacitor is described in further detail below.

[0032] Figure 3 is a cross-sectional (Y-Z) view of an example embedded memory 300 according to an embodiment of the present disclosure. Figure 3The figure shows the Y and Z dimensions (width and height respectively), and the X dimension (length) extending into and out of the Y-Z plane. The embedded memory 300 includes a FEOL 310, which includes most of the various logic layers, circuits, and devices for driving and controlling the fabrication of an integrated circuit (e.g., a chip) using the embedded memory 300. As shown in Figure 3 As shown in, the embedded memory 300 also includes a BEOL 320, which in this case includes seven metal interconnect layers (i.e., a metal 1 layer 325, a metal 2 layer 330, a metal 3 layer 335, a metal 4 layer 340, a metal 5 layer 345, a metal 6 layer 350, and a metal 7 layer 365, and the metal 7 layer 365 includes a metal 7 via portion 355 and a metal 7 interconnect portion 360) for interconnecting the various inputs and outputs of the FEOL 310.

[0033] Generally speaking and specifically described for the metal 7 layer 365, each of the metal 1 layer 325 to the metal 7 layer 365 includes a via portion and an interconnect portion located above the via portion. The interconnect portion is used to transfer signals along metal lines extending in the X or Y direction, and the via portion is used to transfer signals through metal vias extending in the Z direction (such as extending to the next lower metal layer below). Thus, the vias connect metal structures (e.g., metal lines or vias) from one metal layer to metal structures in the next lower metal layer. In addition, each of the metal 1 layer 325 to the metal 7 layer 365 includes a pattern of conductive metal (such as copper (Cu) or aluminum (Al)) formed in a dielectric or interlayer dielectric (ILD) such as by lithography.

[0034] In addition, the embedded memory 300 is further divided into a memory array 390 (e.g., an eNVM memory array) and a memory peripheral circuit 380. The memory array 390 is built in the metal 4 layer 340 to the metal 7 layer 365 and includes low-leakage selector TFTs (in the metal 5 layer 345) and MIM capacitors 370 (in the metal 6 layer 350 and the metal 7 via portion 355), as well as word lines (e.g., row selectors in the metal 4 layer 340) and bit lines (e.g., column selectors in the metal 5 layer 345) that make up the eNVM memory cells. The memory peripheral circuit 380 is built in the FEOL and the metal 1 layer 325 to the metal 3 layer 335 to control (e.g., access, store, refresh) the memory array 390.

[0035] Compared with the following other technologies: positioning such a memory control circuit in the same layer as the memory array, but in the macro (or X-Y) region of an integrated circuit different from the memory array (such as at the periphery of the memory array), the embedded memory 300 positions the memory peripheral circuit 380 below the memory array 390 (e.g., in the same X-Y region). This saves valuable X-Y regions in a finished integrated circuit. Looking in more detail, the embedded memory 300 embeds low-leakage selector TFTs (e.g., back-end TFTs) in the metal 5 layer 345 (such as the via portion of the metal 5 layer 345). For example, the metal 4 layer 340 may include word lines extending in the X direction for selecting rows of memory cells (bits), and the metal 5 layer 345 may include bit lines extending in the Y direction for sensing each of the memory cells (bits) in the selected rows (and for writing memory data to any of the memory cells in the selected rows). The selector TFTs may be fabricated in the metal 5 layer 345 above the word lines (which serve as or are connected to the gate electrodes or contacts) and below the bit lines (which serve as the source electrodes or contacts). For example, the selector TFT may have a transistor gate below a thin film layer (which may be formed at the bottom of the metal 5 layer 345, such as in the via portion) and source and drain contacts above the thin film layer.

[0036] Looking in more detail, in some embodiments, the metal gate of the selector TFT in each memory cell may be connected to a continuous metal 4 line below, such as a copper (Cu)-based metal line, which provides much lower resistance compared to the gate lines formed in the lower (e.g., FEOL) portion of the integrated circuit. The continuous metal 4 line serves as the word line of the memory array and is covered by a diffusion barrier or diffusion barrier layer including a dielectric layer, such as silicon nitride (e.g., Si3N4), silicon carbide (e.g., SiC), etc., where materials like tantalum nitride (TaN), tantalum (Ta), titanium zirconium nitride (e.g., Ti X Zr 1-XN, a metal diffusion barrier film such as titanium nitride (e.g., TiN), titanium tungsten (TiW), etc. is used to fill the through-hole. The metal gate layer covers the through-hole filled with the diffusion barrier film, which electrically connects the copper (Cu) word line to the metal gate of the selector TFT, and the diffusion barrier film prevents or helps prevent the diffusion or migration of copper (Cu) from the word line to the remaining part of the selector TFT. The active thin film layer (e.g., indium gallium zinc oxide or IGZO) and then the source contact and drain contact above the thin film layer use metal layer 5 345. The space between the source contact and the drain contact determines the gate length of the selector transistor. The three-dimensional MIM capacitor 370 (e.g., ferroelectric capacitor) is embedded in the through-hole part 355 of metal layer 6 350 and metal layer 7 365 (below the metal 7 interconnect part 360).

[0037] Figures 4A - 4B Are cross-sectional (Y-Z) and planar (Y-X) views of an example selector TFT 410 (e.g., back-end TFT) in an embedded memory cell 450 (such as a non-volatile memory cell using a ferroelectric capacitor) according to an embodiment of the present disclosure, respectively. Figures 5A - 5B Is according to an embodiment of the present disclosure Figures 4A - 4B Cross-sectional (X-Z and Y-Z, respectively) views of an example structure of the selector TFT 410 in the memory cell 450.

[0038] The selector TFT 410 in the memory cell 450 is coupled to a word line 420 (which acts as a gate), a bit line 430 (which acts as a source contact), and a storage node 440 (which acts as a drain contact), or is controlled by a word line 420 (which acts as a gate), a bit line 430 (which acts as a source contact), and a storage node 440 (which acts as a drain contact). In Figures 4A - 4B An example embodiment, the word line 420 is formed in metal layer 4 340 (such as using the same process for fabricating metal layer 4 340 for the rest of the integrated circuit), the selector TFT 410 is formed in metal layer 5 345 (e.g., in the through-hole part of metal layer 5 345), and the storage node 440 and the bit line 430 are formed in metal layer 5 345 (e.g., in the interconnect part of metal layer 5 345). The metal layer 5 345 and the upper layers are fabricated customized for the embedded memory (as opposed to the fabrication of metal layer 5 345 and the upper layers outside the memory) to account for the special structure in the memory.

[0039] For example, for the metal 5 layer 345 of the eNVM, a different metal from the remainder of the metal 5 layer 345 external to the memory, such as titanium nitride (e.g., TiN) or tungsten (W), may be used. In some embodiments, the same metal (e.g., copper) is used for the metal 5 layer 345 both internal and external to the eNVM. Regardless of the choice of metal for the storage node 440 and the bit line 430, the height (and width) of these structures may be further modified from those in the remainder of the metal 5 layer 345, e.g., to reduce the capacitance between the bit line 430 and the storage node 440. By first coupling the bit line 430 to the metal 6 layer 350 in a region external to the process (e.g., copper interconnect), these bit lines 430 can be connected to sense amplifiers and other bit line drivers below the memory array (e.g., below the metal 4 layer 340), where the bit line signals can be routed through the metal 5 layer 345, the metal 4 layer 340, the metal 3 layer 335, and via portions of layers further below as needed.

[0040] In Figures 5A - 5B an example embodiment of, the bottom gate selector TFT 410 may include thin film layers, such as one or more gate electrode layers (e.g., diffusion barrier 412 and metal gate 414), a gate dielectric layer (e.g., gate dielectric 416), and a semiconductor (active) layer (e.g., active layer 418). The diffusion barrier 412 may be a metal or copper diffusion barrier on the word line 420 (e.g., a conductive metal to reduce or prevent the diffusion of metal or copper from the word line 420 into the metal gate 414 while still maintaining the electrical connection between the word line 420 and the metal gate 414), such as tantalum nitride (TaN), tantalum (Ta), titanium zirconium nitride (e.g., Ti X Zr 1-X N, such as X = 0.53), titanium nitride (e.g., TiN), titanium tungsten (TiW), combinations (such as a stack structure of TaN on Ta), etc.

[0041] For example, the diffusion barrier 412 may include a single-layer or multi-layer structure that includes a compound of tantalum (Ta) and nitrogen (n), such as TaN or a TaN layer on a Ta layer. In some embodiments, a layer of an etch-resistant material (e.g., etch stop 411), such as silicon nitride (e.g., Si3N4) or silicon carbide (e.g., SiC), is formed over the word line 420, which has a via for a metal (or copper) diffusion barrier film 412 such as TaN or a TaN / Ta stack. The metal gate 414 may be a conductive material on the diffusion barrier 412, such as a metal, a conductive metal oxide, or a nitride, etc. For example, in one embodiment, the metal gate 414 is titanium nitride (TiN). In another embodiment, the metal gate 414 is tungsten (W).

[0042] The gate dielectric 416 can be silicon dioxide (SiO2), silicon nitride (e.g., Si3N4), hafnium dioxide (HfO2), or other high-k materials, or a multi-layer stack including a first layer of SiO2 and a second layer of a high-k dielectric (such as HfO2 on SiO2). As will be appreciated in view of the present disclosure, any number of gate dielectrics can be used. For example, in one embodiment, the gate dielectric 416 is a layer of SiO2. In another embodiment, the gate dielectric 416 is a stack of HfO2 on SiO2 (e.g., two or more layers).

[0043] The active layer 418 can be IGZO or the like that contacts the bit line 430 (e.g., at a first region of the active layer 418, such as a source region) and the storage node 440 (e.g., at a second region of the active layer 418, such as a drain region, with a semiconductive channel region between the first region and the second region). Such an active layer 418 channel may include only majority carriers in the thin film. Thus, the active layer 418 channel may require a high bias (as supplied by the word line 420, the diffusion barrier film 412, and the metal gate 414) to be activated. In addition to IGZO, in some embodiments, the active layer is one of a variety of polycrystalline semiconductors, which include, for example, zinc oxide nitride (ZnON, such as a composite of zinc oxide (ZnO) and zinc nitride (Zn3N2) or a composite of ZnO, ZnO x N y and Zn3N2), indium zinc oxide (ITO), tin oxide (e.g., SnO), copper oxide (e.g., Cu2O), polycrystalline germanium (poly-Ge) silicon-germanium (e.g., SiGe, such as Si 1-x Ge x ) structures (such as a stack of poly-Ge on SiGe), etc.

[0044] Figures 6A - 6B are cross-sectional (Y-Z) and plan view (Y-X) diagrams of an exemplary metal-insulator-metal (MIM) capacitor 610 (e.g., a ferroelectric capacitor having a U-shaped structure) in a memory cell 450 according to an embodiment of the present disclosure. Figures 4A - 4B of a memory cell 450 according to an embodiment of the present disclosure. Figure 7 is a cross-sectional (Y-Z) diagram of an exemplary structure of the MIM capacitor 610 in a memory cell 450 according to an embodiment of the present disclosure. Figures 6A - 6B of a memory cell 450 according to an embodiment of the present disclosure.

[0045] The storage node 440 (drain contact) of the selector TFT 410 in the memory cell 450 is separated between the cells 450. Each storage node 440 is connected to the MIM capacitor 610 through the MIM capacitor via 620. For example, the MIM capacitor via 620 can be fabricated in the via portion of the metal 6 layer 350, while the MIM capacitor 610 can be fabricated in the connection portion of the metal 6 layer 350 and the via portion 355 of the metal 7 layer 365. The MIM capacitor 610 can be fabricated by etching (e.g., by photolithography) deep and narrow trenches in the upper portion of the metal 6 layer 350 and the via portion 355 of the metal 7 layer 365 and aligning the trenches with a thin conductor (such as the bottom electrode 616), a thin insulator (such as the ferroelectric dielectric 614), and another thin conductor (such as the top electrode 612), with the thin insulator insulating one thin conductor from the other thin conductor. The MIM capacitor 610 is fabricated in a process separate from the remainder of the fabrication of the metal 6 layer and the metal 7 layer (to account for its relatively high height and different electrode materials from the remainder of the metal 6 layer and the metal 7 layer). This creates a relatively large capacitance in the MIM capacitor 610 by having a relatively large surface area for the terminals (such as the top electrode 612 and the bottom electrode 616) that separate a relatively small amount of insulation (such as the dielectric 614).

[0046] Looking further in detail, in one or more embodiments of the present disclosure, the MIM capacitor 610 is formed by etching trenches in the metal 6 layer (e.g., the interconnect portion) and the metal 7 layer (e.g., the via portion) and then filling the trenches with three layers by, for example, atomic layer deposition (ALD). For example, a conductive material (e.g., a metal, a conductive metal nitride or carbide, etc.) can be used, followed by the thin ferroelectric dielectric 614 (to increase the capacitance, e.g., 20 - 40 nm), followed by the top electrode 612 again, and the bottom electrode 616 is filled to a thickness of 20 - 40 nm with a metal (such as 20 - 40 nm thick) that can be coupled to the top electrode of each other MIM capacitor 610 (e.g., in an array of eNVM memory cells). The MIM capacitor 610 can be at least 300 nm in some embodiments (e.g., on the order of 140 nm for the metal 5 layer) to provide sufficient capacitance.

[0047] For example, in one embodiment, the bottom electrode 616 is tantalum (Ta). In another embodiment, the bottom electrode 616 is titanium nitride (TiN). In some embodiments, the bottom electrode 616 is titanium aluminum nitride (e.g., TiAlN, where the molar amount of titanium is at least the molar amount of aluminum). In another embodiment, the bottom electrode 616 is tantalum aluminum carbide (TaAlC). In another embodiment, the bottom electrode 616 is tantalum nitride (TaN). For example, in one embodiment, the top electrode 612 is TiN. For example, in one embodiment, the dielectric 614 is a ferroelectric material such as lead zirconate titanate (PZT), hafnium zirconium oxide (HZO), barium titanate (BaTiO3), lead titanate (PbTiO3), and doped hafnium dioxide (HfO2). Doped HfO2 may include one or more of silicon-doped HfO2, yttrium-doped HfO2, and aluminum-doped HfO2).

[0048] Each bottom electrode 616 of the MIM capacitor 610 is connected to a corresponding storage node 440 through a MIM capacitor via 620. The bottom electrodes 616 of the MIM capacitor 610 are electrically insulated from each other, while the top electrodes 612 of the MIM capacitor 610 are electrically connected to each other through a (shared) MIM capacitor plate 630 at the top of the MIM capacitor 610 and also located in the via portion 355 of the metal 7 layer 365. For example, there may be an independent MIM capacitor plate 630 for an independent array of MIM capacitors 610 or for an independent group of MIM capacitors 610 corresponding to the same bit line. The MIM capacitor plate 630 may be coupled to a common voltage line (e.g., in the interconnect portion 360 of the metal 7 layer 365) for supplying a common voltage (e.g., ground voltage) to all the top electrodes 612 through the MIM capacitor plate 630.

[0049] The source contact of the selector TFT 410 is continuous and serves as the bit line 430 of the memory array 390. For better sensing margin, the heights of the source contact and the drain contact can be optimized to reduce the bit line 430 capacitance (e.g., between the source contact and the drain contact). The source contact of the selector TFT also serves as the bit line 430 of the array. The dimensions of the source contact (bit line 430) can be customized for lower inter-metal capacitance (e.g., by using an independent manufacturing stage to form the bit line 430, which is relative to the manufacturing stage of this metal level in the region of the integrated circuit outside the memory array). Each MIM capacitor 410 is connected to the drain contact of the selector TFT 410 (e.g., storage node 440) through a MIM capacitor via 620.

[0050] Figure 8 is a schematic plan (X-Y) view of an example embedded memory configuration according to an embodiment of the present disclosure. Figure 8The memory array arrangement includes memory cells 450 (e.g., each memory cell 450 is driven by a unique pair of a word line 420 and a bit line 430) at the intersection region of the word lines 420 and the bit lines 430. Each memory cell 450 includes a selector TFT 410 and a MIM capacitor 610. Each word line 420 is selected by a corresponding word line driver 810, and the corresponding bit line 430 is used to sense the state (e.g., parallel or anti-parallel) of the ferroelectric material in the MIM capacitor 610 of each of the corresponding bits of the selected word line 420. In some embodiments, a reference column of memory cells provides a corresponding reference signal (e.g., between a logic low value and a logic high value) above a reference bit line 820 simultaneously with the desired bit on the sense bit line 430. These two values are compared by a sense amplifier 830, which determines whether the desired bit is a logic high value (e.g., 1) or a logic low value (e.g., 0).

[0051] The memory cells 450 are embedded in a BEOL layer (such as a higher metal interconnect layer of BEOL), while the peripheral circuits responsible for memory operations, including the read sense amplifier 830 (and other bit line driver circuits) and the word line driver circuit 810, are placed below the memory array (e.g., in the FEOL and lower metal interconnect layers of BEOL) to reduce the area of the embedded memory.

[0052] FIG. 9A is a plan (Y-X) view of an example layout of an embedded memory in a case where the memory array 390 and the memory peripheral circuits (illustrated as the word line driver 810 and the column circuit 910) do not overlap. FIGS. 9B-9C are plan (Y-X) views of an example layout or floorplan of an embedded memory in a case where the memory array 390 overlaps with the memory peripheral circuits 810 and 910 according to embodiments of the present disclosure.

[0053] The column circuit 910 (or bit line driver) includes devices such as a read (bit line) sense amplifier 830 and a precharge circuit. FIG. 9A shows a circuit that is spread out (e.g., occupies the FEOL macro region or the CMOS logic transistor region) and has no overlap. In contrast, FIG. 9B shows the memory array 390 occupying a higher metal interconnect layer of BEOL 320 (as illustrated in Figures 1 - 7 ), and Figure 9C shows the memory array 390 occupying (as illustrated in Figure 3As shown in the figure below, the memory peripheral circuits 810 and 910 of the lower metal interconnect layers of the following FEOL 310 and BEOL 320. Since the peripheral (memory control) circuit can occupy more than 35% of the embedded memory macro region, as in one or more embodiments of the present disclosure, by fabricating the memory array above the memory peripheral circuit, a large amount of X-Y macro region can be saved. In other words, according to some embodiments of the present disclosure, the embedded memory is provided with memory cells that use only the space in the upper metal layers (e.g., metal layer 4 and above), and the peripheral circuit is moved below the memory cells (e.g., in metal layer 3 and below, including FEOL) and the memory region is greatly reduced.

[0054] Figure 10 An example method 1000 of fabricating an embedded memory (e.g., eNVM) is shown in accordance with an embodiment of the present disclosure. As will be apparent in view of the present disclosure, the methods and other methods disclosed herein may be implemented using integrated circuit fabrication techniques such as lithography. The corresponding non-volatile memory cells and the embedded memory including the memory cells may be part of other (logic) devices on the same substrate, such as application specific integrated circuits (ASICs), microprocessors, central processing units, processing cores, etc. Unless otherwise described herein, verbs such as "couple" or "couple to" refer to electrically coupling (such as being able to transmit electrical signals) directly or indirectly (such as through one or more intermediate conductive layers).

[0055] Reference Figure 10 (where specific examples refer to Figure 1 -9's structure), method 1000 includes forming 1010 a plurality of word lines (such as word line 420) extending in a first direction (such as the X direction), forming 1020 a plurality of bit lines (such as bit line 430) extending in a second direction (such as the Y direction) intersecting the first direction, and at the intersection region of the word lines and the bit lines (see Figure 8At ( ) more than 1030 memory cells (such as memory cell 450) are formed. For some or all of the memory cells, method 1000 further includes forming 1040 back-end thin film transistors (TFTs, such as selector TFT 410) on or otherwise electrically connected to a front-end circuit (such as word line driver 810 and sense amplifier 830), and forming 1050 ferroelectric capacitors (such as MIM capacitor 610) on or otherwise electrically connected to the back-end TFT. The back-end TFT has a gate electrode (such as gate 120), a source region and a drain region (such as source region 142 and drain region 144), a semiconductor region (such as channel region 146) between the source region and the drain region and physically connecting the source region and the drain region, and a gate dielectric (such as gate dielectric 130) between the gate electrode and the semiconductor region. The ferroelectric capacitor has a first terminal (such as first terminal 192) electrically connected to the drain region, a second terminal (such as second terminal 194), and a ferroelectric dielectric (such as ferroelectric dielectric 196) between the first terminal and the second terminal. For some or all of the memory cells, method 1000 further includes electrically connecting 1060 the gate electrode to a corresponding one of the word lines in the word line, and electrically connecting 1070 the source region to a corresponding one of the bit lines in the bit line.

[0056] Although the example methods above are presented as a series of operations or stages, it is understood that no order is required for these operations or stages, unless specifically indicated otherwise. For example, in various embodiments of method 1000, for each memory cell, electrically connecting 1060 the gate electrode to a corresponding one of the word lines in the word line may occur before, during, or after electrically connecting 1070 the source region to a corresponding one of the bit lines in the bit line.

[0057] Example System

[0058] Figure 11 FIG. illustrates a computing system 1100 implemented using the integrated circuit structures or techniques disclosed herein, in accordance with an embodiment of the present disclosure. As can be seen, computing system 1100 houses a motherboard 1102. Motherboard 1102 may include a plurality of components, the plurality of components including but not limited to a processor 1104 (including embedded memory) and at least one communication chip 1106, each of which may be physically and electrically coupled to motherboard 1102, or otherwise integrated therein. As will be appreciated, motherboard 1102 may be, for example, any printed circuit board, whether a main board, a daughter board mounted on the main board, or the sole board of system 1100 (to name a few).

[0059] Depending on its application, computing system 1100 may include one or more other components, which may or may not be physically and electrically coupled to motherboard 1102. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM), resistive random access memory (RRAM), etc.), graphics processors, digital signal processors, crypto (or cryptographic) processors, chip sets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.). Any of the components included in computing system 1100 may include one or more integrated circuit structures or devices (e.g., one or more memory cells) formed using the disclosed techniques according to example embodiments. In some embodiments, multiple functions may be integrated into one or more chips (e.g., for example, note that communication chip 1106 may be part of or otherwise integrated into processor 1104).

[0060] Communication chip 1106 can enable wireless communication for transferring data to and from communication system 1100. The term “wireless” and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can convey data by using modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated devices do not contain any wires, although in some embodiments they may not. Communication chip 1106 can implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocol designated as 3G, 4G, 5G, and beyond. Computing system 1100 may include multiple communication chips 1106. For example, a first communication chip 1106 may be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip 1106 may be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0061] The processor 1104 of the computing system 1100 includes an integrated circuit die encapsulated within the processor 1104. In some embodiments, the integrated circuit die of the processor includes onboard circuitry implemented using one or more integrated circuit structures or devices (e.g., one or more memory cells) formed using the disclosed techniques, as described in various aspects herein. The term "processor" may refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform that electronic data into other electronic data that may be stored in registers and / or memory.

[0062] The communication chip 1106 may also include an integrated circuit die encapsulated within the communication chip 1106. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices (e.g., one or more memory cells) formed using the disclosed techniques as described in various aspects herein. As will be appreciated in view of the present disclosure, note that multi-standard wireless capabilities may be directly integrated within the processor 1104 (e.g., where the functionality of any chip 1106 is integrated within the processor 1104 rather than having a separate communication chip). Additionally note that the processor 1104 may be a chipset having such wireless capabilities. In short, any number of processors 1104 and / or communication chips 1106 may be used. Also, any one chip or chipset may have multiple functions integrated therein.

[0063] In various implementations, the computing device 1100 may be a laptop computer, netbook, notebook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices (e.g., one or more memory cells) formed using the disclosed techniques, as described in various aspects herein.

[0064] Additional Example Embodiments

[0065] The following examples pertain to additional embodiments, many permutations and configurations of which will be apparent in light of these embodiments.

[0066] Example 1 is an integrated circuit that includes: a back-end thin-film transistor (TFT) having a gate electrode, a source region, and a drain region, a semiconductor region between the source region and the drain region and physically connecting the source region and the drain region, and a gate dielectric between the gate electrode and the semiconductor region; and a ferroelectric capacitor electrically connected to the back-end TFT and having a first terminal electrically connected to one of the source region and the drain region, a second terminal, and a ferroelectric dielectric between the first terminal and the second terminal.

[0067] Example 2 includes the integrated circuit of Example 1, wherein the semiconductor region includes one or more of the following: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (ITO), amorphous silicon (a-Si), zinc oxide, polysilicon, polycrystalline germanium, low-temperature polysilicon (LTPS), amorphous germanium (a-Ge), indium arsenide, copper oxide, and tin oxide.

[0068] Example 3 includes the integrated circuit of Example 2, wherein the semiconductor region includes one or more of IGZO, IZO, a-Si, LTPS, and a-Ge.

[0069] Example 4 includes the integrated circuit of any one of Examples 1-3, wherein the gate dielectric includes hafnium dioxide (HfO2).

[0070] Example 5 includes the integrated circuit of Example 4, wherein the gate dielectric has a thickness between 2 and 10 nanometers (nm).

[0071] Example 6 includes the integrated circuit of any one of Examples 1-5, wherein the ferroelectric capacitor includes a metal-insulator-metal (MIM) capacitor having a stacked structure.

[0072] Example 7 includes the integrated circuit of any one of Examples 1-5, wherein the ferroelectric capacitor includes a metal-insulator-metal (MIM) capacitor having a U-shaped structure.

[0073] Example 8 includes the integrated circuit of any one of Examples 1-7, wherein the ferroelectric dielectric includes one or more of the following: lead zirconate titanate (PZT), hafnium zirconium oxide (HZO), barium titanate (BaTiO3), lead titanate (PbTiO3), and doped hafnium dioxide (HfO2).

[0074] Example 9 includes the integrated circuit of Example 8, wherein the doped HfO2 includes one or more of silicon-doped HfO2, yttrium-doped HfO2, and aluminum-doped HfO2.

[0075] Example 10 includes the integrated circuit of any one of Examples 1-9 and further includes a coating layer on the semiconductor region.

[0076] Example 11 includes the integrated circuit of Example 10, wherein the encapsulation layer includes one or more of the following: aluminum oxide, gallium oxide, silicon nitride, silicon dioxide, titanium dioxide, hafnium dioxide, silicon oxynitride, aluminum silicate, tantalum oxide, hafnium tantalum oxide, aluminum nitride, aluminum silicon nitride, silicon aluminum oxynitride, zirconium dioxide, hafnium zirconium oxide, tantalum silicate, and hafnium silicate.

[0077] Example 12 includes the integrated circuit of Example 11, wherein the encapsulation layer includes one or more of the following: aluminum oxide, silicon nitride, titanium dioxide, hafnium dioxide, silicon oxynitride, and aluminum nitride.

[0078] Example 13 includes the integrated circuit of any one of Examples 10 - 12, further including a source electrode and a drain electrode electrically connected to the source region and the drain region, wherein the encapsulation layer physically connects the source electrode and the drain electrode and electrically isolates the source electrode and the drain electrode.

[0079] Example 14 is a memory cell, the memory cell including the integrated circuit of any one of Examples 1 - 13, a gate electrode electrically connected to a word line, a source region electrically connected to a bit line, and the drain region being one of the source region and the drain region.

[0080] Example 15 includes the memory cell of Example 14, wherein a back - end TFT is electrically connected to a front - end circuit, and the front - end circuit includes a word - line driver electrically connected to the word line and a sense amplifier electrically connected to the bit line.

[0081] Example 16 is an embedded memory, the embedded memory including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of memory cells at the intersection regions of the word lines and the bit lines, the memory cells including a first memory cell and a second memory cell, each of the first memory cell and the second memory cell having the structure of the memory cell of any one of Examples 14 - 15, wherein the word line is a corresponding one of the word lines and the bit line is a corresponding one of the bit lines.

[0082] Example 17 includes the embedded memory of Example 16, wherein a back - end TFT is electrically connected to a front - end circuit, and the front - end circuit includes a plurality of word - line drivers electrically connected to the word lines and a plurality of sense amplifiers electrically connected to the bit lines.

[0083] Example 18 is a memory cell that includes: a back-end thin film transistor (TFT) having a gate electrode electrically connected to a word line, a source region electrically connected to a bit line, a drain region, a semiconductor region between the source region and the drain region and physically connecting the source region and the drain region, and a gate dielectric between the gate electrode and the semiconductor region; and a ferroelectric capacitor electrically connected to the back-end TFT and having a first terminal electrically connected to the drain region, a second terminal, and a ferroelectric dielectric between the first terminal and the second terminal.

[0084] Example 19 includes the memory cell of Example 18, wherein the semiconductor region includes one or more of the following: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (ITO), amorphous silicon (a-Si), zinc oxide, polysilicon, polycrystalline germanium, low temperature polysilicon (LTPS), amorphous germanium (a-Ge), indium arsenide, copper oxide, and tin oxide.

[0085] Example 20 includes the memory cell of Example 19, wherein the semiconductor region includes one or more of IGZO, IZO, a-Si, LTPS, and a-Ge.

[0086] Example 21 includes the memory cell of any one of Examples 18-20, wherein the gate dielectric includes hafnium dioxide (HfO2).

[0087] Example 22 includes the memory cell of Example 21, wherein the gate dielectric has a thickness between 2 and 10 nanometers (nm).

[0088] Example 23 includes the memory cell of any one of Examples 18-22, wherein the ferroelectric capacitor includes a metal-insulator-metal (MIM) capacitor having a stacked structure.

[0089] Example 24 includes the memory cell of any one of Examples 18-22, wherein the ferroelectric capacitor includes a metal-insulator-metal (MIM) capacitor having a U-shaped structure.

[0090] Example 25 includes the memory cell of any one of Examples 18-25, wherein the ferroelectric dielectric includes one or more of the following: lead zirconate titanate (PZT), hafnium zirconium oxide (HZO), barium titanate (BaTiO3), lead titanate (PbTiO3), and doped hafnium dioxide (HfO2).

[0091] Example 26 includes the memory cell of Example 25, wherein the doped HfO2 includes one or more of silicon-doped HfO2, yttrium-doped HfO2, and aluminum-doped HfO2.

[0092] Example 27 includes the memory cell of any one of Examples 18-26, and further includes a coating layer on the semiconductor region.

[0093] Example 28 includes the memory cell of Example 27, wherein the coating layer includes one or more of the following: aluminum oxide, gallium oxide, silicon nitride, silicon dioxide, titanium dioxide, hafnium dioxide, silicon oxynitride, aluminum silicate, tantalum oxide, hafnium tantalum oxide, aluminum nitride, aluminum silicon nitride, aluminum silicon oxynitride, zirconium dioxide, hafnium zirconium oxide, tantalum silicate, and hafnium silicate.

[0094] Example 29 includes the memory cell of Example 28, wherein the coating layer includes one or more of the following: aluminum oxide, silicon nitride, titanium dioxide, hafnium dioxide, silicon oxynitride, and aluminum nitride.

[0095] Example 30 includes the memory cell of any one of Examples 27-29, and further includes a source electrode and a drain electrode electrically connected to the source region and the drain region, wherein the coating layer physically connects the source electrode and the drain electrode and electrically isolates the source electrode and the drain electrode.

[0096] Example 31 includes the memory cell of any one of Examples 18-30, wherein the back-end TFT is electrically connected to the front-end circuit, and the front-end circuit includes a word line driver electrically connected to the word line and a sense amplifier electrically connected to the bit line.

[0097] Example 32 is an embedded memory, the embedded memory including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of memory cells at the intersection region of the word lines and the bit lines, the memory cells including a first memory cell and a second memory cell, each of the first memory cell and the second memory cell having the structure of the memory cell of any one of Examples 18-30, wherein the word line is a corresponding one of the word lines and the bit line is a corresponding one of the bit lines.

[0098] Example 33 includes the embedded memory of Example 32, wherein the back-end TFT is electrically connected to the front-end circuit, and the front-end circuit includes a plurality of word line drivers electrically connected to the word lines and a plurality of sense amplifiers electrically connected to the bit lines.

[0099] Example 34 is a method of manufacturing an integrated circuit, the method including: forming a back-end thin film transistor (TFT) having a gate electrode, a source region and a drain region, a semiconductor region between the source region and the drain region and physically connecting the source region and the drain region, and a gate dielectric between the gate electrode and the semiconductor region; and forming a ferroelectric capacitor having a first terminal electrically connected to one of the source region and the drain region, a second terminal, and a ferroelectric dielectric between the first terminal and the second terminal.

[0100] Example 35 includes the method of Example 34, wherein the semiconductor region includes one or more of the following: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (ITO), amorphous silicon (a-Si), zinc oxide, polysilicon, polycrystalline germanium, low temperature polysilicon (LTPS), amorphous germanium (a-Ge), indium arsenide, copper oxide, and tin oxide.

[0101] Example 36 includes the method of Example 35, wherein the semiconductor region includes one or more of IGZO, IZO, a-Si, LTPS, and a-Ge.

[0102] Example 37 includes the method of any one of Examples 34 - 36, wherein the gate dielectric includes hafnium dioxide (HfO2).

[0103] Example 38 includes the method of Example 37, wherein the gate dielectric has a thickness between 2 and 10 nanometers (nm).

[0104] Example 39 includes the method of any one of Examples 34 - 38, wherein the ferroelectric capacitor includes a metal-insulator-metal (MIM) capacitor having a stacked structure.

[0105] Example 40 includes the method of any one of Examples 34 - 38, wherein the ferroelectric capacitor includes a metal-insulator-metal (MIM) capacitor having a U-shaped structure.

[0106] Example 41 includes the method of any one of Examples 34 - 40, wherein the ferroelectric dielectric includes one or more of the following: lead zirconate titanate (PZT), hafnium zirconium oxide (HZO), barium titanate (BaTiO3), lead titanate (PbTiO3), and doped hafnium dioxide (HfO2).

[0107] Example 42 includes the method of Example 41, wherein the doped HfO2 includes one or more of silicon-doped HfO2, yttrium-doped HfO2, and aluminum-doped HfO2.

[0108] Example 43 includes the method of any one of Examples 34 - 42, further comprising forming a capping layer on the semiconductor region.

[0109] Example 44 includes the method of Example 43, wherein the capping layer includes one or more of the following: aluminum oxide, gallium oxide, silicon nitride, silicon dioxide, titanium dioxide, hafnium dioxide, silicon oxynitride, aluminum silicate, tantalum oxide, hafnium tantalum oxide, aluminum nitride, aluminum silicon nitride, silicon aluminum oxynitride, zirconium dioxide, hafnium zirconium oxide, tantalum silicate, and hafnium silicate.

[0110] Example 45 includes the method of Example 44, wherein the capping layer includes one or more of the following: aluminum oxide, silicon nitride, titanium dioxide, hafnium dioxide, silicon oxynitride, and aluminum nitride.

[0111] Example 46 includes the method of any one of Examples 43-45, and further includes forming a source electrode and a drain electrode electrically connected to a source region and a drain region, wherein a coating layer physically connects the source electrode and the drain electrode and electrically isolates the source electrode and the drain electrode.

[0112] Example 47 is a method of manufacturing a memory cell, the method including: manufacturing an integrated circuit by the method of any one of Examples 34-46; electrically connecting a gate electrode to a word line; and electrically connecting a source region to a bit line, wherein the drain region is one of the source region and the drain region.

[0113] Example 48 includes the method of Example 47, wherein a back-end TFT is electrically connected to a front-end circuit, and the method further includes: forming a word line driver as part of the front-end circuit; forming a sense amplifier as part of the front-end circuit; electrically connecting the word line driver to the word line; and electrically connecting the sense amplifier to the bit line.

[0114] Example 49 is a method of manufacturing an embedded memory, the method including: forming a plurality of word lines extending in a first direction; forming a plurality of bit lines extending in a second direction intersecting the first direction; and forming a plurality of memory cells at an intersection region of the word lines and the bit lines, the memory cells including a first memory cell and a second memory cell, each of the first memory cell and the second memory cell being manufactured by the method of any one of Examples 47-48, wherein the word line is a corresponding one of the word lines and the bit line is a corresponding one of the bit lines.

[0115] Example 50 includes the method of Example 49, wherein a back-end TFT is electrically connected to a front-end circuit, and the method further includes: forming a plurality of word line drivers as part of the front-end circuit; forming a plurality of sense amplifiers as part of the front-end circuit; electrically connecting the word line drivers to the word lines; and electrically connecting the sense amplifiers to the bit lines.

[0116] The foregoing description of example embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the disclosure. It is intended that the scope of the disclosure not be limited by this detailed description, but rather be limited by the claims appended hereto. Future filings claiming priority to this application may claim the disclosed subject matter in a different manner and may generally include any combination of one or more of the limitations disclosed herein or otherwise shown.

Claims

1. An integrated circuit, comprising: a back-end thin film transistor (TFT) having a gate electrode, a source region, and a drain region, a semiconductor region physically connecting the source region and the drain region between the source region and the drain region and along a direction from the source region to the drain region, and a gate dielectric between the gate electrode and the semiconductor region, wherein the gate electrode is a bottom gate electrode that laterally extends beyond the outermost sides of the source region and the drain region along a direction from the source region to the drain region, and the bottom gate electrode laterally extends beyond the outermost side of the gate dielectric along a direction from the source region to the drain region; and a ferroelectric capacitor electrically connected to the back-end TFT and having a first terminal electrically connected to one of the source region and the drain region, a second terminal, and a ferroelectric dielectric between the first terminal and the second terminal.

2. The integrated circuit according to claim 1, wherein the semiconductor region comprises one or more of the following: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (ITO), amorphous silicon (a-Si), zinc oxide, polysilicon, polycrystalline germanium, low-temperature polysilicon (LTPS), amorphous germanium (a-Ge), indium arsenide, copper oxide, and tin oxide.

3. The integrated circuit according to claim 2, wherein the semiconductor region comprises one or more of IGZO, IZO, a-Si, LTPS, and a-Ge.

4. The integrated circuit according to claim 1, wherein the gate dielectric comprises hafnium dioxide (HfO2).

5. The integrated circuit according to claim 4, wherein the gate dielectric has a thickness between 2 and 10 nanometers (nm).

6. The integrated circuit according to claim 1, wherein the ferroelectric capacitor comprises a metal-insulator-metal (MIM) capacitor having a stacked structure.

7. The integrated circuit according to claim 1, wherein the ferroelectric capacitor comprises a metal-insulator-metal (MIM) capacitor having a U-shaped structure.

8. The integrated circuit according to claim 1, wherein the ferroelectric dielectric comprises one or more of the following: lead zirconate titanate (PZT), hafnium zirconium oxide (HZO), barium titanate (BaTiO3), lead titanate (PbTiO3), and doped hafnium dioxide (HfO2).

9. The integrated circuit according to claim 8, wherein the doped HfO2 comprises one or more of silicon-doped HfO2, yttrium-doped HfO2, and aluminum-doped HfO2.

10. The integrated circuit according to claim 1, further comprising a coating layer on the semiconductor region.

11. The integrated circuit according to claim 10, wherein the coating layer comprises one or more of the following: aluminum oxide, gallium oxide, silicon nitride, silicon dioxide, titanium dioxide, hafnium dioxide, silicon oxynitride, aluminum silicate, tantalum oxide, hafnium tantalum oxide, aluminum nitride, aluminum silicon nitride, silicon aluminum oxynitride, zirconium dioxide, hafnium zirconium oxide, tantalum silicate, and hafnium silicate.

12. The integrated circuit according to claim 11, wherein the encapsulation layer comprises one or more of the following: aluminum oxide, silicon nitride, titanium dioxide, hafnium dioxide, silicon oxynitride, and aluminum nitride.

13. The integrated circuit according to claim 10, further comprising a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively, wherein the encapsulation layer physically connects the source electrode and the drain electrode and electrically isolates the source electrode and the drain electrode.

14. A memory cell, the memory cell comprising an integrated circuit according to any one of claims 1-13, wherein the gate electrode is electrically connected to a word line, the source region is electrically connected to a bit line, and the drain region is one of the source region and the drain region.

15. The memory cell according to claim 14, wherein the back-end TFT is electrically connected to a front-end circuit, and the front-end circuit comprises a word line driver electrically connected to the word line and a sense amplifier electrically connected to the bit line.

16. An embedded memory, the embedded memory comprising a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of memory cells at the intersection region of the word lines and the bit lines, the memory cells comprising a first memory cell and a second memory cell, each of the first memory cell and the second memory cell having the structure of the memory cell according to claim 14, wherein the word line is a corresponding one of the word lines and the bit line is a corresponding one of the bit lines.

17. The embedded memory according to claim 16, wherein the back-end TFT is electrically connected to a front-end circuit, and the front-end circuit comprises a plurality of word line drivers electrically connected to the word lines and a plurality of sense amplifiers electrically connected to the bit lines.

18. A method of manufacturing an integrated circuit, the method comprising: forming a back-end thin film transistor (TFT), the back-end TFT having a gate electrode, a source region and a drain region, a semiconductor region physically connecting the source region and the drain region between the source region and the drain region and along a direction from the source region to the drain region, and a gate dielectric between the gate electrode and the semiconductor region, wherein the gate electrode is a bottom gate electrode, the bottom gate electrode laterally extends beyond the outermost sides of the source region and the drain region along the direction from the source region to the drain region, and the bottom gate electrode laterally extends beyond the outermost side of the gate dielectric along the direction from the source region to the drain region; and forming a ferroelectric capacitor, the ferroelectric capacitor having a first terminal electrically connected to one of the source region and the drain region, a second terminal, and a ferroelectric dielectric between the first terminal and the second terminal.

19. The method according to claim 18, wherein the ferroelectric capacitor comprises a metal-insulator-metal (MIM) capacitor having a stacked structure.

20. The method according to claim 18, wherein the ferroelectric capacitor comprises a metal-insulator-metal (MIM) capacitor having a U-shaped structure.

21. The method according to claim 18, wherein the ferroelectric dielectric comprises one or more of the following: lead zirconate titanate (PZT), hafnium zirconium oxide (HZO), barium titanate (BaTiO3), lead titanate (PbTiO3), and doped hafnium dioxide (HfO2).

22. The method according to claim 21, wherein the doped HfO2 comprises one or more of silicon-doped HfO2, yttrium-doped HfO2, and aluminum-doped HfO2.

23. The method according to claim 18, further comprising forming a capping layer over the semiconductor region.

24. The method according to claim 23, further comprising forming a source electrode and a drain electrode electrically connected to the source region and the drain region, wherein the capping layer physically connects the source electrode and the drain electrode and electrically isolates the source electrode and the drain electrode.

25. A method of manufacturing a memory cell, the method comprising: manufacturing the integrated circuit by the method according to any one of claims 18-24; electrically connecting the gate electrode to a word line; and electrically connecting the source region to a bit line, wherein the drain region is one of the source region and the drain region.

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