Doped insulator capping for reducing source / drain diffusion in germanium NMOS transistors

Abstract

An integrated circuit transistor structure is disclosed that reduces the diffusion of an n-type dopant, such as phosphorus or arsenic, from the source and drain regions of a germanium n-MOS device into an adjacent insulator region during fabrication. The n-MOS transistor device may include at least 75 atomic percent germanium. In an exemplary embodiment, a dopant-rich insulator cap is deposited adjacent to the source and / or drain regions to provide reduced dopant diffusion. In some embodiments, the dopant-rich insulator cap is doped with an n-type dopant including phosphorus at a concentration between 1 and 10 atomic percent. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.

Description

BACKGROUND OF THE INVENTION

[0001] A semiconductor device is an electronic component that utilizes the electronic properties of semiconductor materials such as silicon (Si), germanium (Ge), and silicon germanium (SiGe). A field effect transistor (FET) is a semiconductor device that includes three terminals (a gate, a source, and a drain). The FET uses an electric field applied through the gate to control the conductivity of a channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain. When the charge carriers are electrons, the FET is called an n-channel device, and when the charge carriers are holes, the FET is called a p-channel device. Standard dopants for Si, Ge, and SiGe include boron (B) as a p-type (acceptor) dopant and phosphorus (P) or arsenic (As) as an n-type (donor) dopant. Some FETs have a fourth terminal called a body or substrate, which can be used to bias the transistor. Additionally, a metal oxide semiconductor FET (MOSFET) includes a gate dielectric between the gate and the channel. A MOSFET can also be referred to as a metal insulator semiconductor FET (MISFET) or an insulated gate FET (IGFET). A complementary MOS (CMOS) structure uses a combination of p-channel MOSFETs (p-MOS) and n-channel MOSFETs (n-MOS) to implement logic gates and other digital circuits.

[0002] A FinFET is a MOSFET transistor built around a thin strip of semiconductor material, generally referred to as a fin. The conductive channel of a FinFET device exists on the outer portions of the fin adjacent to the gate dielectric. Specifically, current flows along two sidewalls of the fin (the sides perpendicular to the substrate surface) or within the two sidewalls of the fin and along the top of the fin (the side parallel to the substrate surface). Since the conductive channel with such a configuration substantially exists along three different outer planar regions of the fin, such a FinFET design is sometimes referred to as a triple-gate transistor. Other types of FinFET configurations are also available, for example, the so-called double-gate FinFET, in which the conductive channel mainly exists only along two sidewalls of the fin (and not along the top of the fin). BRIEF DESCRIPTION OF THE DRAWINGS

[0003] As the detailed description of the present disclosure continues and with reference to the drawings, the features and advantages of embodiments of the claimed subject matter will become apparent, in which like reference numerals refer to like parts.

[0004] Figures 1A - 1BA method of forming an integrated circuit (IC) including at least one germanium (Ge)-rich n-MOS transistor according to some embodiments of the present disclosure is shown, where the transistor employs one or more dopant-rich insulator caps, which particularly helps prevent source / drain (S / D) dopants from diffusing into adjacent insulator regions.

[0005] Figures 2A - 2Q An exemplary IC structure formed when performing the Figures 1A - 1B method according to some embodiments is shown.

[0006] Figure 3A An exemplary cross-sectional view along Figure 2P plane A-A according to some embodiments is shown.

[0007] Figure 3B An exemplary cross-sectional view along Figure 2P plane B-B according to some embodiments is shown.

[0008] Figure 4 A computing system implemented with an integrated circuit structure and / or transistor device formed using the techniques disclosed herein according to some embodiments of the present disclosure is shown.

[0009] These and other features of the presented embodiments will be better understood by reading the detailed description herein in conjunction with the accompanying drawings depicted herein. In the drawings, each equivalent or substantially equivalent component shown in the various drawings may be represented by similar reference numerals. For clarity, not every component is labeled in each drawing. Additionally, it should be recognized that the drawings are not necessarily drawn to scale and are not intended to limit the described embodiments to the specific configurations shown. For example, although some of the drawings generally indicate straight lines, right angles, and smooth surfaces, considering the real-world limitations of manufacturing processes, the actual implementations of the disclosed techniques may have non-ideal straight lines and right angles, and some features may have surface topographies or otherwise be non-smooth. Furthermore, some of the features in the drawings may include filled patterns and / or shading provided only to assist in visually differentiating different features. In short, the drawings are provided only to illustrate exemplary structures.

[0010] Although the detailed description below will continue to refer to exemplary embodiments, many alternatives, modifications, and variations of the embodiments will be apparent in light of the present disclosure. Detailed Description

[0011] An integrated circuit transistor structure is disclosed that reduces the diffusion of n-type dopants (e.g., phosphorus or arsenic) from source and drain regions into adjacent insulator regions during the fabrication of n-MOS devices having a germanium-rich channel (e.g., a germanium concentration of 75 atomic % or higher up to 100 atomic %). In an exemplary embodiment, the structure includes an intervening diffusion glass capping or structure that is deposited between the n-MOS transistor and the insulator regions adjacent to the source and drain (S / D) regions. The diffusion glass capping is an insulator (e.g., silicon dioxide) that is doped with an n-type dopant to effectively provide a reduction in the diffusion of dopants from the S / D regions. In some embodiments, the n-type dopant is phosphorus (P) that is implanted into the silicon dioxide after the formation of the gate structure to create the diffusion glass capping such that the gate structure prevents the dopant from being implanted into the region of the insulator capping adjacent to the channel region under the gate structure. In some embodiments, the concentration of the n-type impurity implanted into the insulator capping is in the range of 1 atomic % to 10 atomic %. In some embodiments, the dopant-rich insulator capping may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers, which will be explained in more detail below. Many configurations and process flows will be apparent in light of the present disclosure.

[0012] General Overview

[0013] Fabrication of Ge-rich n-MOS transistors is generally not well implemented because it is difficult to maintain a relatively high level of n-type dopants in the source / drain regions of the transistor. This is largely attributed to the physical properties of germanium, where typical n-type dopants such as phosphorus and arsenic readily diffuse from the Ge-rich source / drain regions under the high-temperature conditions associated with semiconductor fabrication processes. For example, Ge-rich n-MOS devices are prone to leakage of n-type dopants from the S / D regions into the surrounding insulator regions that separate and insulate adjacent transistors. This leakage is particularly problematic under the high-temperature conditions associated with semiconductor fabrication processes. The resulting transistor devices may exhibit poor S / D contact resistance due to the high energy barrier at the metal-semiconductor interface, which cannot be overcome by tunneling due to the low dopant levels caused by the diffusion of dopants outside the Ge material. Such high S / D contact resistance may cause significant performance degradation. As transistor devices are scaled down to include smaller critical dimensions (e.g., using sub-30nm technology and higher-generation technologies), these problems caused by dopant diffusion will be further exacerbated.

[0014] Thus, and in accordance with various embodiments of the present disclosure, techniques are provided for forming Ge-rich n-MOS transistors that include one or more dopant-rich insulator caps or cap structures configured to isolate source / drain fin structures from adjacent insulator regions, as described in more detail below. As can be understood based on the present disclosure, a dopant-rich insulator cap proximate to the source / drain regions helps to inhibit the undesired diffusion of dopants (e.g., P or As) from the S / D regions into adjacent insulator regions. The dopant n-type impurities (e.g., P) of the dopant-rich insulator cap provide improved diffusion resistance characteristics as they reduce the dopant gradient between the S / D regions and adjacent insulator regions. Generally, the dopant-rich insulator cap can effectively act as a dopant reflector, where, due to the relatively high dopant impurity concentration in the insulator cap, approximately the same amount of dopant diffuses in opposite directions (e.g., from the S / D regions into the insulator cap and from the insulator cap back into the S / D regions). For example, in some embodiments, the insulator cap can have a dopant concentration that is 2 to 10 times the dopant concentration of the S / D regions.

[0015] In some embodiments, the dopant-rich insulator cap can include silicon dioxide (SiO2) having a phosphorus concentration between 1 atomic % and 10 atomic %, although other compositions are possible. In some embodiments, the dopant-rich insulator cap can extend a distance in the range of 10 to 200 nanometers vertically upward (e.g., in the Y-axis direction) from the top surface of an adjacent shallow trench isolation (STI) region. In some embodiments, the dopant-rich insulator cap can also extend a distance in the range of 10 to 100 nanometers horizontally (e.g., in the X-axis direction) around the source / drain fin structure.

[0016] Note that, as used herein, "Ge-rich" includes Ge-containing bodies having a Ge atomic percentage greater than 50%, where any suitable material(s) can be used to dope Ge or Si 1-x Ge x (x > 0.5), and / or Ge or Si 1-x Ge x(x>0.5) alloyed with other Group IV elements (e.g., carbon and / or tin up to 2 atomic percent). For example, in some embodiments, the Ge-rich material can be n-type doped, such as Ge:As, Ge:P, SiGe:P (with more than 50 atomic percent Ge), or SiGe:As (with more than 50 atomic percent Ge), to provide some examples. In addition, in some embodiments, the Ge-rich material can include alloys of carbon and / or tin, such as Ge:C, GeSn, SiGe:C, SiGeSn, GeSn:C, SiGeSn:C. It should also be noted that in some embodiments, the rich Ge can include Ge at different threshold concentrations (atomic percent), such as at least 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90% or 95%. For example, in some applications, it may be desirable to obtain an embodiment in which the Ge-rich channel region of the transistor includes at least 80 atomic percent Ge, or even a pure Ge channel, so as to (for example) achieve a desired charge carrier mobility. It should also be noted that including a Ge-rich material in a given feature described herein does not exclude including materials other than Ge. For example, in some embodiments, a Ge-rich channel region may include a multilayer structure including at least one Ge-rich layer and at least one non-Ge-rich layer. However, in other embodiments, a Ge-rich feature has Ge-rich material substantially throughout the feature. In addition, a Ge-rich channel region may include a Ge concentration graded throughout at least a portion of the channel region, such that the channel region may have one or more portions including a Ge concentration of less than 50 atomic percent, and may even include no Ge content at all.

[0017] Moreover, as used herein, "Group-IV semiconductor material" (or "Group-IV material" or generally "IV") includes at least one Group-IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), etc. Note that alloys of Group-IV elements should not be confused with compounds of these elements. Thus, when alloying carbon with any of the other Group-IV elements, the resulting alloy will be expressed herein as "X:C", where "X" is a Group-IV element or alloy, and ":C" indicates alloying with carbon. For example, silicon alloyed with carbon can be referred to herein as Si:C (thereby preventing confusion with silicon carbide (SiC)), silicon-germanium alloyed with carbon can be referred to herein as SiGe:C, germanium alloyed with carbon can be referred to herein as Ge:C (thereby preventing confusion with germanium carbide (GeC)), etc. It should also be noted that the molecular ratio or atomic percentage of the elements included in the Group-IV alloy can be adjusted as desired. In addition, in this document, "X:Z" is used to represent a doping relationship, where "X" is the element or alloy doped with "Z". For example, SiGe:As represents silicon-germanium doped with arsenic, or SiGe:C:P represents silicon-germanium alloyed with carbon and doped with phosphorus, by way of some examples. Generally speaking, when referring to the Group-IV semiconductor materials described herein (e.g., Si, SiGe, Ge, SiSn, SiGeSn, GeSn, Si:C, SiGe:C, Ge:C, SiSn:C, SiGeSn:C, GeSn:C), the Group-IV semiconductor material has a single-crystal (or single-crystalline) structure, unless otherwise stated, e.g., where polycrystalline silicon (or polycrystalline Si) can be utilized, as described herein.

[0018] In some embodiments, the techniques can be used to benefit a number of transistor devices. For example, in some embodiments, the techniques can be used to benefit one or more n-channel transistor devices, such as n-channel MOSFET (n-MOS) devices, where the charge carriers are electrons. In some embodiments, the techniques described herein can be used to benefit complementary transistor circuits (e.g., CMOS circuits), where the techniques can be used to benefit one or more of the included n-channel transistors (e.g., n-MOS devices) that make up a given CMOS circuit. Moreover, in some embodiments, the techniques described herein can be used to benefit transistors including a number of transistor architectures, e.g., these transistor architectures can be planar and non-planar architectures, where the non-planar architectures can include fin or FinFET architectures (e.g., double-gate or triple-gate), gate-all-around (GAA) architectures (e.g., nanowire or nanoribbon), or some combination thereof, by way of providing several examples. Other exemplary transistor devices that can benefit from the techniques described herein include, for example, few-electron to single-electron quantum transistor devices.

[0019] It will be further appreciated that the Ge-rich n-MOS transistors provided herein, including one or more dopant-rich insulator caps or cap structures configured to separate source / drain fin structures from adjacent insulator regions, can also be mixed on the same substrate with other transistor devices having Ge-free channel regions. For example, the other transistor devices are transistors having a silicon channel region, a gallium arsenide channel region, an indium arsenide channel region, an indium gallium arsenide channel region, or some combination of channel regions with various compositions. It should also be noted that some channel regions can be native to the substrate (i.e., fins formed from the substrate), while other channel regions can be epitaxially provided onto the substrate.

[0020] Note that, as used herein, the expression "X includes at least one of A and B" means that X can, for example, include only A, only B, or both A and B. To this end, X that includes at least one of A and B should not be construed as X that requires each of A and B, unless expressly stated as such. For example, the expression "X includes A and B" means that X expressly includes both A and B. Further, this is the case for any number of terms greater than two, where "at least one of" those terms is included in X. For example, as used herein, the expression "X includes at least one of A, B, and C" means that X can include only A, only B, only C, only A and B (without C), only A and C (without B), only B and C (without A), or each of A, B, and C. This is the case even if any one of A, B, or C happens to include multiple types or variations. To this end, X that includes at least one of A, B, and C should not be construed as X that requires each of A, B, and C, unless expressly stated as such. For example, the expression "X includes A, B, and C" means that X expressly includes each of A, B, and C. Similarly, the expression "X included in at least one of A and B" means that X can, for example, be included only in A, only in B, or in both A and B. It should be appreciated that the discussion above regarding "X includes at least one of A and B" applies equally here.

[0021] The use of the techniques and structures provided herein can be detected using tools such as, for example, electron microscopes including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); compositional mapping; x-ray crystallography or diffraction (XRD); energy dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SFMS); time-of-flight SFMS (ToF-SFMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, which are just a few suitable exemplary analysis tools. Specifically, in some embodiments, such tools can indicate an integrated circuit (IC) including at least one Ge-rich n-MOS transistor as described herein, the transistor including a dopant-rich insulator capping or capping structure doped with an n-type impurity. For example, in some such embodiments, the technique can be detected by observing (e.g., via SEM / TEM) the presence of P in the dopant-rich insulator capping adjacent to one or more S / D regions. In some embodiments, the techniques and structures can be detected based on the benefits obtained by the techniques and structures described herein, e.g., by observing that a Ge-rich n-MOS source / drain fin structure does not exhibit a reduced dopant (e.g., P or As) level due to dopant diffusion into an adjacent insulator region, due to the dopant-rich insulator capping described herein (compared to a Ge-rich n-MOS transistor that does not employ the techniques described herein). Thus, in some embodiments, the techniques described herein can allow for the formation of enhanced performance Ge-rich transistor devices using sub-30 nanometer technology and higher generation technologies, and the technique can also be detected and characterized. Many configurations and variations will be apparent in view of the present disclosure.

[0022] Methods and Architectures

[0023] Figure 1( Figure 1A and Figure 1B ) illustrates a method 100 of forming an integrated circuit (IC) including at least one Ge-rich n-MOS transistor according to some embodiments of the present disclosure, the transistor employing one or more dopant-rich insulator caps doped with an n-type impurity, which particularly helps prevent or otherwise inhibit S / D dopant diffusion into an adjacent insulator region. Figures 2A - 2Q illustrates an exemplary IC structure formed when performing method 100 of FIG. 1. For purposes of illustration, Figures 2A - 2QThe structure is mainly depicted and described in the context of forming a finned or FinFET transistor configuration (e.g., a triple-gate transistor configuration). However, in some embodiments, the techniques can be used to form transistors having any suitable geometry or configuration, which can be understood based on the present disclosure. It should also be noted that the techniques and structures are mainly depicted and described in the context of forming a metal-oxide-semiconductor field-effect transistor (MOSFET). However, the present disclosure is not intended to be limited thereby, unless otherwise stated. It should also be noted that method 100 includes exemplifying the main path of a back-gate transistor fabrication process flow that can be employed according to some embodiments. However, in other embodiments, a front-gate process flow can instead be employed, as will be described herein (and will be indicated by the alternative front-gate flow 100' indicator of FIG. 1). Many variations and configurations will be apparent in light of the present disclosure.

[0024] According to some embodiments, method 100 of FIG. 1 (now referring to Figure 1A ) includes patterning 102 a hard mask on a substrate, e.g., patterning Figure 2A hard mask 210a on substrate 200 of Figure 2B to form exemplary structure 210b of

[0025] In some embodiments, the substrate 200 can be: a bulk substrate comprising a Group IV semiconductor material (e.g., Si, Ge, SiGe), a Group III-V semiconductor material (e.g., GaAs, GaAsSb, GaAsIn), and / or any other suitable material(s) that will be apparent from the present disclosure; an insulator-on-X (XOI) structure, where X is one of the foregoing materials (e.g., a Group IV and / or Group III-V semiconductor material), and the insulator material is an oxide material or a dielectric material or some other electrically insulating material such that the XOI structure includes an electrically insulating material between two semiconductor layers; or some other suitable multi-layer structure, in which the top layer comprises one of the foregoing semiconductor materials (e.g., a Group IV and / or Group III-V semiconductor material). As used herein, the term “Group IV semiconductor material” (or “Group IV material” or generally “Group IV”) includes at least one Group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and the like. As used herein, the term “Group III-V semiconductor material” (or “Group III-V material” or generally “Group III-V”) includes at least one Group III element (e.g., aluminum, gallium, indium) and at least one Group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), and the like. Note that, for example, Group III can also be referred to as the boron group or IUPAC Group 13, Group IV can also be referred to as the carbon group or IUPAC Group 14, and Group V can also be referred to as the nitrogen group or IUPAC Group 15. In some embodiments, the substrate 200 can include a Ge-rich material that will be used in the channel region of one or more transistors.

[0026] In some embodiments, the substrate 200 may be doped with any suitable n-type and / or p-type dopants. For example, in the case of a Si substrate, the Si may be p-type doped with a suitable acceptor (e.g., boron), or the Si may be n-type doped with a suitable donor (e.g., phosphorus, arsenic) to provide some exemplary cases. However, in some embodiments, for example, the substrate 200 may be undoped / intrinsic or have a relatively low doping (e.g., including a doping concentration of less than 1E16 atoms / cm3). In some embodiments, the substrate 200 may include a surface crystal orientation described by Miller indices (100), (110), or (111) or their equivalent schemes, as will be apparent from this disclosure at this point. Although for ease of illustration, the substrate 200 is shown in this exemplary embodiment as having a thickness (dimension in the Y-axis direction) similar to that of other layers shown in the subsequent structures, in some cases, the substrate 200 may be much thicker than the other layers, for example, having a thickness in the range of 50 to 950 microns, or any other suitable thickness as will be apparent from this disclosure. In some embodiments, depending on the end use or target application, the substrate 200 may be used in one or more other IC devices, such as various diodes (e.g., light-emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various radio frequency (RF) devices, various sensors, or any other suitable semiconductor or IC device. Accordingly, in some embodiments, the structures described herein may be included in a system-on-chip (SoC) application, as will be apparent from this disclosure at this point.

[0027] According to some embodiments, method 100 of FIG. 1 continues to perform 104 shallow trench isolation (STR) etching to form fins 202 from the substrate 200, thereby forming Figure 2CThe resulting exemplary structure shown. In some embodiments, the STR etch 104 for forming the trenches 215 and fins 202 may include any suitable techniques, such as various masking processes and wet and / or dry etch processes. In some cases, the STR etch 104 may be performed in-situ or without an air break, while in other cases, for example, the STR etch 104 may be performed ex-situ. The trenches 215 may be formed with varying widths (dimensions in the X-axis direction) and depths (dimensions in the Y-axis direction), as can be understood based on the present disclosure. For example, multiple hard mask patterning 102 and STR etch 104 processes may be performed to achieve varying depths in the trenches 215 between the fins 202. The fins 202 may be formed to have varying widths Fw (dimensions in the X-axis direction) and heights Fh (dimensions in the Y-axis direction). Note that although the hard mask structure 210b still exists in Figure 2C the exemplary structure, this may not necessarily be the case in some situations as it may have been consumed (e.g.) during the STR etch. It should also be noted that although the fins 202 are shown for ease of depiction as being relatively rectangular in nature (having straight sides and a flat top), in reality, the fins may include a tapered profile in which the top of the fin is narrower than the base of the fin (as viewed in a cross-section taken perpendicular to the fin). Additionally, the very top of the fin may be rounded rather than flat. Many other real-world geometries will also be understood.

[0028] In some embodiments, for example, the fin width Fw (dimension in the horizontal or X-axis direction) can be in the range of 2 - 400 nm (or in the sub-ranges of 2 - 10, 2 - 20, 2 - 50, 2 - 100, 2 - 200, 4 - 10, 4 - 20, 4 - 50, 4 - 100, 4 - 200, 4 - 400, 5 - 20, 10 - 20, 10 - 50, 10 - 100, 10 - 200, 10 - 400, 50 - 100, 50 - 200, 50 - 400, 100 - 400 nm or in any other sub-ranges) or can be at any other suitable value or range that would be apparent in accordance with the present disclosure. In some embodiments, for example, the fin height Fh (dimension in the vertical or Y-axis direction) can be in the range of 4 - 800 nm (or in the sub-ranges of 4 - 10, 4 - 20, 4 - 50, 4 - 100, 4 - 200, 4 - 400, 10 - 20, 10 - 50, 10 - 80, 10 - 100, 10 - 200, 10 - 400, 10 - 800, 50 - 100, 50 - 200, 50 - 400, 50 - 800, 100 - 400, 100 - 800, 400 - 800 nm or in any other sub-ranges) or can be at any other suitable value or range that would be apparent in accordance with the present disclosure. In some embodiments, the fin height Fh can be at least 10, 25, 35, 50, 75, 100, 125, 150, 175, 200, 300, 400, 500, 600, 700 or 800 nm high, or can be at any other desired height that would be apparent in accordance with the present disclosure. In some embodiments, the ratio of the height to the width of the fin (Fh:Fw) can be greater than 1, for example, greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9 or 10, or greater than any other suitable threshold ratio that would be apparent in accordance with the present disclosure. Note that in this exemplary structure, for the sake of illustration, both the trench 215 and the fin 202 are shown as having substantially the same size and shape; however, it is not intended to limit the present disclosure in such a way. For example, in some embodiments, the fin 202 can be formed to have a varying height F, a varying width Fw, a varying starting point (or varying starting height), a varying shape, and / or any other suitable variations that would be apparent in accordance with the present disclosure. Additionally, the trench 215 can be formed to have a varying depth, a varying width, a varying starting point (or varying starting depth), a varying shape, and / or any other suitable variations that would be apparent in accordance with the present disclosure. Further, it should be noted that although for the sake of illustration Figure 2C four fins 202 are shown in the exemplary structure ofFigure 2D shows a Figure 2C cross-sectional (2D) view of the exemplary structure shown for reference.

[0029] According to some embodiments, method 100 of FIG. 1 continues to deposit 106 shallow trench isolation (STI) material 220 to form Figure 2E an exemplary resulting structure. The deposition 106 of STI material 220 can include any suitable deposition technique, such as those deposition techniques described herein (e.g., CVD, ALD, PVD) or any other suitable deposition process. In some embodiments, STI material 220 (which can be referred to as an STI layer or an STI structure) can include any suitable electrically insulating material, such as one or more dielectrics, oxides (e.g., silicon dioxide) and / or nitrides (e.g., silicon nitride) materials. In some embodiments, the material of STI layer 220 can be selected based on the material of substrate 200. For example, in the case of a Si substrate, the STI material can be selected as silicon dioxide or silicon nitride to provide some examples. According to some embodiments, method 100 of FIG. 1 also continues to planarize / polish 108 the structure to form Figure 2F an exemplary resulting structure. The (one or more) planarization and / or polishing processes performed after forming STI material 220 can include any suitable technique, such as a chemical mechanical planarization / polishing (CMP) process. Note that in this exemplary embodiment, hard mask 210b can be removed by this planarization. In other embodiments, hard mask 210b can be retained.

[0030] Method 100 of FIG. 1 continues to recess 110 the native fin material 202. In embodiments where fin 202 will be removed and replaced with replacement semiconductor material (to be used in the channel regions of one or more transistor devices), Figure 2F the structure of Figure 2F is achieved for such a process. For example, continuing from Figure 2GFor the structure, selective etching can be used to recess or remove the fin 202 (e.g., the semiconductor material of the fin 202 can be selectively removed relative to the insulator material of the STI layer 220 for a given etchant), thereby forming fin-like trenches 209 between the STI materials 220 where replacement semiconductor material can be deposited / grown therein (e.g., using any suitable technique such as CVD, metalorganic CVD (MOCVD), ALD, molecular beam epitaxy (MBE), PVD). From one embodiment to the next, the depth of etching can vary. In the illustrated embodiment, a portion of the native fin is left to facilitate providing a base or fin root 207 on which replacement fin material can be deposited. In other embodiments, the native fin can be completely removed to be flush with the top surface of the substrate 200, thus not providing a base or fin root, or even the native fin can be below the top surface of the substrate 200, thereby providing an inverted base or fin root.

[0031] Method 100 of FIG. 1 continues to the deposition 112 of replacement semiconductor fin material. For example, according to some embodiments, Figure 2H Illustrated is the recessing and replacement process for forming replacement material fins 230. The replacement fins 230 (generally, and any replacement fins formed) can include any suitable semiconductor material (e.g., group IV and / or III-V semiconductor materials). For example, replacement fins including SiGe or Ge can be formed by removing the native Si fins and replacing the native Si fins with SiGe or Ge material during such a process to provide some examples. Additionally, the replacement fins 230 can include any suitable n-type or p-type dopant, or the replacement fins 230 can be undoped or lightly doped. In some embodiments, alternative processes can be used to form replacement material fins, e.g., Figure 2H of the replacement fins 230. For example, in some embodiments, the replacement material fins can be formed by uniformly growing the replacement material on the substrate (e.g., using an epitaxial deposition process) and then patterning the replacement material into replacement material fins to provide alternative examples. Note that the replacement fins 230 are shown with a pattern / shading which is only for assisting the visual identification of the feature. In any such case, the resulting structure can be planarized to provide a relatively flat top surface, as Figure 2H generally shown.

[0032] According to some embodiments, method 100 of FIG. 1 continues to recess the STI material 220 between the fins 114, as Figure 2I shown, such that at least a portion 231 of the fins 230 protrudes from the STI plane, thereby forming Figure 2IThe resulting exemplary structure shown. The recess 114 can be performed using any suitable technique, e.g., using one or more wet and / or dry etching processes that allow the STI material 220 to be selectively recessed relative to the material of the fin 230, and / or using any other suitable processing that will be apparent in light of the present disclosure. As can be understood based on the present disclosure, the exposed portion 231 of the fin 230 can be used to provide the channel region of one or more transistors, such that (e.g.) the fin portion 231 (the portion of the fin 230 above the top plane of the STI layer 220 after the recess 114 has been performed) can be referred to herein as the channel portion. More specifically, the fin portion 231 under the gate structure that will be formed subsequently is generally referred to as the channel portion, where source and drain regions will be formed on both sides of the channel portion, such that the channel is between the source and drain regions. Additionally, the portion of the fin 230 below the top plane of the STI layer 220 is denoted as portion 232, where such a portion can (e.g.) be referred to as a sub-channel portion.

[0033] As Figure 2I shown, the portion 231 of the fin 230 that protrudes above the top plane of the STI layer 220 has a fin height denoted as Fh, which can be in the range of 4 - 800 nm (e.g., in the sub-ranges of 4 - 10, 4 - 20, 4 - 50, 4 - 100, 4 - 200, 4 - 400, 10 - 20, 10 - 50, 10 - 80, 10 - 100, 10 - 200, 10 - 400, 10 - 800, 50 - 100, 50 - 200, 50 - 400, 50 - 800, 100 - 400, 100 - 800, 400 - 800 nm or in some other sub-range) or can be at any other suitable value or range that will be apparent in light of the present disclosure. In some particular embodiments, the fin height Fh can be at least 10, 25, 35, 50, 75, 100, 125, 150, 175, 200, 300, 400, 500, 600, 700 or 800 nm high. It should also be noted that in embodiments employing a planar transistor configuration, the recess process 114 need not be performed, since (e.g.) the top surface of the semiconductor body 230 as Figure 2H shown can be used to form the transistor.

[0034] Note that in Figure 2I the exemplary embodiments, all fins are shown as being replaced; however, it is not intended to limit the present disclosure in such a way. In some embodiments, as Figure 2J shown, only a subset can be replaced (e.g., such that some replacement fins 230 can be used for subsequent processing and some native fins 202 are retained for subsequent processing). Figure 2JThis is illustrated by a perspective view.

[0035] In addition, in some embodiments, many recess and replacement processes may be performed as desired by masking regions that will not be processed in each replacement fin subset process, thereby forming many replacement fin subsets as desired. For example, Figure 2K is illustrated therein, which shows two different replacement fin subsets 230 and 240. In some such embodiments, the first replacement fin subset may be formed for n-channel transistors (e.g., where the first replacement material is selected to improve electron mobility), and the second replacement fin subset may be formed for p-channel transistors (e.g., where the second replacement material is selected to improve hole mobility). So, for example, some of the native fins 202 are removed and replaced with a first material 230 (e.g., a Ge-rich material), and other native fins in the native fins 202 are removed and replaced with a second material 240 (e.g., a III-V material). Figure 2K This is illustrated by a perspective view.

[0036] In addition, in some embodiments, multi-layer replacement fins may be formed, thereby allowing nanowires or nanoribbons to be formed subsequently in the channel regions of one or more transistors, where some of the layers in the multi-layer replacement fins are sacrificial and are intended to be removed via selective etching (e.g., during replacement gate processing). It will be apparent that many such fin replacement schemes may be used.

[0037] According to some embodiments, the method 100 of FIG. 1 (now referring to Figure 1B ) continues to optionally form a dummy gate stack 116 to form Figure 2LExemplary resulting structure. Recall that in this document, method 100 is primarily described in the context of a back-gate transistor fabrication process flow, where the process includes forming a dummy gate stack, performing S / D processing, and then forming the final gate stack after the S / D regions have been processed. However, in other embodiments, the techniques may be performed using a front-gate process flow. In such an exemplary case, process 116 (forming the dummy gate stack) will not be performed, and thus, process 116 is optional in some embodiments (e.g., those employing a front-gate process flow). This will be reflected by an alternative location for performing 122 final gate stack processing (which is shown as optional front-gate flow 100' in FIG. 1), e.g., where, in embodiments employing a front-gate process flow, performing 122 final gate stack processing will instead occur at the location of block 116. However, the back-gate process flow will continue to be used to describe method 100, thus allowing for a full description of such a process flow (which generally includes additional processing).

[0038] In this exemplary embodiment, continuing to form 116 the dummy gate stack, such a dummy gate stack (when employed) may include a dummy gate dielectric 242 and a dummy gate electrode 244, thereby forming Figure 2L Exemplary resulting structure. In this exemplary embodiment, the dummy gate dielectric 242 (e.g., a dummy oxide material) and the dummy gate electrode 244 (e.g., a dummy polysilicon material) may be used for replacement gate processes. Note that gate spacers 250 are also formed on either side of the dummy gate stack, and such gate spacers 250 may be used (e.g.) to assist in channel length determination and / or to assist in replacement gate processes. As can be understood based on the present disclosure, the dummy gate stack (and gate spacers 250) may assist in defining the channel region and the source / drain (S / D) regions of each transistor device, where the channel region is beneath the dummy gate stack (since it will be beneath the final gate stack), and the S / D regions are on either side of and adjacent to the channel region. Note that since the IC structure is being described in the context of forming finned transistors, the final gate stack will also be adjacent to either side of the fin, since in embodiments employing a finned (e.g., FinFET) architecture, the gate stack will be present along the top and opposing sidewalls of the finned channel region.

[0039] The formation of the dummy gate stack may include depositing the dummy gate dielectric material 242 and the dummy gate electrode material 244, patterning the dummy gate stack, depositing the gate spacer material 250, and performing spacer etch to form (e.g.) Figure 2LThe structure shown. The gate spacer 250 can include any suitable material, such as any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide), and / or nitride (e.g., silicon nitride) material, as will be apparent from the present disclosure. Note that in some embodiments, as previously described, the techniques described herein do not necessarily include forming a dummy gate stack such that the final gate stack can be formed initially. In any case, the final structure will include a final gate stack, as will be apparent from the present disclosure. Also note that in some embodiments, for example, a hard mask can be formed over the dummy gate stack (the hard mask may or may not also be formed over the gate spacer 250) to protect the dummy gate stack during subsequent processing. The foregoing description of the hard mask 210 is equally applicable to such a hard mask feature (if used).

[0040] According to some embodiments, method 100 of FIG. 1 continues to perform source / drain (S / D) region processing 118 to form Figure 2M an exemplary resulting structure. S / D region processing 118 can include an etch and replacement process, where portions of the replacement fins 230 are removed in the S / D regions by selective etching (or any other suitable etching scheme) to obtain Figure 2M an exemplary structure. It should be appreciated that although Figure 2M shows removal of all of the replacement material occupying the source / drain regions, in some embodiments, the process can remove only a portion of the replacement material. In still other embodiments, the process can remove all of the replacement material in the source / drain and a portion of the native select fins.

[0041] In this exemplary embodiment, the process can continue to epitaxial deposition of the desired S / D material, thereby forming bulk S / D regions 261 (e.g., p-MOS) and 262 (e.g., n-MOS). In some embodiments, S / D regions 261, 262 can be formed using any suitable technique, such as one or more of the deposition processes (CVD, ALD, PVD, MBE) described herein and / or any other suitable process as will be apparent from the present disclosure. In some such embodiments, S / D regions 261, 262 can be formed using a selective deposition process such that, for example, the material of the features grows only from or substantially only from the exposed semiconductor material (or only in a single crystal structure), as can be understood based on the present disclosure. In other embodiments, S / D regions 261, 262 are ion-implanted doped portions of the fins (202, 230, 240).

[0042] Note that the S / D regions 261, 262 referred to herein are for ease of description, but each S / D region can be a source region or a drain region such that the corresponding S / D region (on the other side of the channel region and thus on the other side of the dummy gate stack) is the other of the source region and the drain region, thereby forming a source and drain region pair. For example, as Figure 2M shown, there are three channel regions and three corresponding S / D region pairs 261, 262, 261.

[0043] In some embodiments, the S / D region can include any suitable semiconductor material that will be apparent in accordance with the present disclosure, e.g., a single crystal Group IV semiconductor material. For example, a given S / D region can include at least one of Si, Ge, Sn, and C. In some embodiments, a given S / D region can include or can not include n-type and / or p-type dopants (e.g., in one of the schemes described herein). In the presence of dopants, for example, the dopants included can have a concentration in the range of 1E17 to 5E21 atoms per cubic centimeter or higher. In some embodiments, a given S / D region can include a grading (e.g., increasing and / or decreasing) of the concentration of one or more materials within the feature, e.g., a grading of the semiconductor material component concentration and / or the dopant concentration. For example, in some such embodiments, the dopant concentration included in a given S / D region can be graded such that the dopant concentration is lower near the corresponding channel region and higher near the corresponding S / D contact, which can be achieved using any suitable process, e.g., adjusting the amount of dopant in the reagent flow (e.g., during an in-situ doping scheme), to provide an example. In some embodiments, a given S / D region can include a multi-layer structure that includes at least two materially different material layers. For example, in the case of a Fermi field FET (FFFET) device, according to some embodiments, the source region can include a multi-layer structure that includes a p-type doped region and an n-type doped region. In some embodiments, a given S / D region can be elevated such that it extends to a level higher than the corresponding channel region (e.g., in the vertical or Y-axis direction).

[0044] In some embodiments, depending on the formation process used, the S / D regions 261, 262 can have different shapes and configurations, as will be apparent in accordance with the present disclosure. For example, in Figure 2MIn an exemplary structure thereof, the S / D region includes a three-dimensional diamond shape having two top surfaces that are faceted (e.g., taking {111} faceting) as shown. According to some embodiments, other exemplary structures can be formed, including a rounded (or curved) and non-faceted top, and the rounded or curved S / D region can extend beyond the underlying sub-fin portion in the X-axis direction. As can be understood based on the present disclosure, S / D regions including any shape (e.g., the diamond shape or the rounded shape of S / D regions 261, 262) can benefit from the techniques described herein.

[0045] In some embodiments, one of the S / D regions in a corresponding S / D region pair (e.g., region 261 on one side of the dummy gate stack) can be processed separately from the other S / D region in the pair (e.g., region 261 on the opposite side of the dummy gate stack) such that the corresponding S / D pair can include different materials, dopant types, dopant concentrations, sizes, shapes, and / or any other suitable differences as can be understood based on the present disclosure. For example, in the case of a TFET device, for an exemplary case, one of the S / D regions can include an n-type doped semiconductor material and the other of the S / D regions can include a p-type doped semiconductor material such that the n-type S / D region and the p-type S / D region can be processed separately. Any suitable technique can be employed to achieve this separate processing, e.g., masking the S / D region that will not be processed to allow processing of the other S / D region and then masking the other S / D region to allow processing of the initially masked S / D region. In some embodiments, a given S / D region can include the same or a similar material composition (e.g., within 1% difference) as the corresponding / adjacent channel region, e.g., both include the same Ge-rich material. However, in other embodiments, e.g., a given S / D region can include a different material composition (e.g., at least 1%, 2%, 3%, 4%, 5%, or 10% difference) relative to the corresponding / adjacent channel region.

[0046] According to some embodiments, method 100 of FIG. 1 continues to deposit 120 a dopant-rich insulator capping layer or region 212 to form Figure 2N an exemplary resulting structure.

[0047] The dopant-rich insulator capping layer 212 is configured to isolate the source / drain fin structure 262 from an adjacent undoped insulator region, as will be described below. As can be appreciated based on the present disclosure, the introduction of one or more dopant-rich insulators helps to inhibit the unwanted diffusion of n-type dopants or impurities (e.g., P or As) in the S / D region into the adjacent insulator region. In some embodiments, the dopant-rich insulator capping layer may include silicon dioxide (SiO2) having a phosphorus concentration between 1 atomic % and 10 atomic %, although other compositions are possible. In some embodiments, the dopant-rich insulator capping layer may extend vertically upward (e.g., in the Y-axis direction) from the top surface of the adjacent shallow trench isolation (STI) region 220 by a distance in the range of 10 to 200 nm, as represented by h in Figure 2N In some embodiments, the dopant-rich insulator capping layer may also extend horizontally (in the X-axis direction) around the source / drain fin structure by a distance in the range of 10 to 100 nm, as represented by w in Figure 2N Considering the present disclosure, other suitable ranges are possible and will be apparent.

[0048] Generally, the dopant-rich insulator capping layer 212 can be any material or composition that reduces or inhibits the depletion of S / D dopants, where in other cases the dopants would be allowed to leave the S / D at a rate faster than their replenishment rate. The insulator capping layer provides a benefit because dopants that would otherwise leave the S / D region and migrate into the adjacent insulator region (especially in the context of n-type Ge-rich channel devices) will no longer be available to activate free electrons in the S / D, and will thus result in degraded device performance. In some embodiments, the concentration of dopants in the dopant-rich insulator capping layer 212 adjacent to the n-type Ge S / D will exceed 2E21 phosphorus and arsenic atoms per cubic centimeter. This concentration can distinguish the unwanted n-type dopant diffusion from the Ge S / D to the adjacent undoped insulator in the absence of a dopant-rich insulator capping layer, where the concentration of phosphorus and arsenic atoms can be graded downward from a peak of approximately 7E20 atoms per cubic centimeter.

[0049] The deposition 120 of the dopant-rich insulator capping layer 212 can include any suitable deposition technique, such as those described herein (e.g., CVD, ALD, PVD) or any other suitable deposition process. In some embodiments, the dopant-rich insulator capping layer material 212 can be deposited with a uniform thickness over the entire or most of the S / D region (e.g., both p-MOS 261 and n-MOS 262), and then the material can be removed from the p-MOS region 261 by a masking and etching process.

[0050] According to some embodiments, method 100 of FIG. 1 proceeds to perform final gate stack processing 122 to form Figure 2P an exemplary resulting structure. As Figure 2P shown, the processing in this exemplary embodiment includes depositing an interlayer dielectric (ILD) layer 270 on the Figure 2N structure, and subsequently exposing the dummy gate stack by planarization and / or polishing (e.g., CMP). Note that the ILD layer 270 can include a multi-layer structure, although it is shown as a single layer. Additionally, it should be noted that in some cases, the ILD layer 270 and the STI material 220 may not include Figure 2P a distinct interface as shown in

[0051] , particularly in cases where (e.g.) the ILD layer 270 and the STI material 220 include the same dielectric material (e.g., where both include silicon dioxide). Generally, the ILD layer 270 can include any desired electrical insulator, dielectric, oxide (e.g., silicon oxide), and / or nitride (e.g., silicon nitride) material, as will be apparent from the present disclosure. In some embodiments, the ILD layer 270 may be referred to as an undoped insulating layer. Figure 2M In this exemplary embodiment, the gate stack processing proceeds to remove the dummy gate stack (including the dummy gate 244 and the dummy gate dielectric 242), thereby allowing the formation of the final gate stack. Recall that in some embodiments, the formation of the final gate stack including the gate dielectric 282 and the gate electrode 284 can be performed using a pre-gate process. In such embodiments, the final gate stack processing may have alternatively been performed at block 116 instead of forming the dummy gate stack. However, in this exemplary embodiment, the final gate stack is formed using a post-gate process (also known as a replacement gate or replacement metal gate (RMG) process). Regardless of whether a pre-gate or post-gate process is employed, the final gate stack can include the gate dielectric 282 and the gate electrode 284 as

[0052] shown and as described herein.

[0053] In some embodiments, a given channel region of a transistor device may include a single-crystalline Group-IV semiconductor material rich in Ge, e.g., single-crystalline Ge or single-crystalline SiGe having an atomic percentage of Ge exceeding 50%, and / or any other suitable material that would be apparent in light of the present disclosure. Generally speaking, a given channel region may include at least one of silicon (Si) and germanium (Ge) to provide some examples. In some embodiments, depending on the particular configuration, the channel region may be lightly doped (e.g., with any suitable n-type and / or p-type dopants) or intrinsic / undoped (or nominally undoped, having a dopant concentration below 1E16 atoms / cm3). In some embodiments, a given channel region may include a grading (e.g., an increase and / or decrease) in the concentration of one or more materials within the feature, e.g., a grading in the semiconductor material component concentration and / or a grading in the dopant concentration. In some embodiments, a given channel region may include a multi-layer structure that includes at least two materially different layers. Based on the present disclosure, it can be understood that in this exemplary embodiment, the channel region is at least under the gate stack. For example, in the case of a finFET configuration, the channel region may be under the gate stack and between the gate stacks, as the stacks are formed on the top and opposite sides of the semiconductor body or fin. However, if the transistor device is inverted and bonded to an object that will serve as the final substrate, then the channel region may be above the gate. Thus, generally speaking, according to some embodiments, the gate structure and the channel region may include a proximity relationship, where the gate structure is close to the channel region such that it can exert electrical control over the channel region. Additionally, in the case of a nanowire (or nanoribbon or GAA) transistor configuration, the gate stack may completely surround each nanowire / nanoribbon in the channel region (or at least substantially surround each nanowire, e.g., surround at least 70%, 80%, or 90% of each nanowire). Additionally, in the case of a planar transistor configuration, the gate stack may simply be above the channel region.

[0054] Note that the S / D regions 261, 262 are adjacent to the two sides of the corresponding channel region, e.g., from Figure 2PAs can be seen. It should also be noted that the construction / geometry of a transistor formed using the techniques described herein can be described primarily based on the shape of the corresponding channel region of the transistor. For example, a nanowire (or nanoribbon or GAA) transistor may be so named because it includes one or more nanowires (or nanoribbons) in the channel region of the transistor, and because the gate stack (including the gate) wraps (or at least substantially wraps) each nanowire (or nanoribbon). However, for example, the transistor type (e.g., MOSFET, TFET, FFFET, or other suitable type) can be described based on the doping and / or operating scheme of the source region, channel region, and drain region, and thus these corresponding regions can be used to determine the type or classification of a given transistor. For example, MOSFET transistors and TFET transistors can be very similar (or identical) in structure, but they include different doping schemes (e.g., p-p or n-n source-drain doping scheme for MOSFETs versus p-n or n-p source-drain doping scheme for TFETs).

[0055] According to some embodiments, after the dummy gate has been removed and any desired channel region processing has been performed, 122 final gate stack processing is continued, and then a final gate stack can be formed. In this exemplary embodiment, the final gate stack includes a gate dielectric 282 and a gate electrode 284, as Figure 2PAs shown. The gate dielectric 282 can include any suitable dielectric (e.g., silicon dioxide and / or high-k dielectric materials), which will be apparent from the present disclosure. Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and zinc zinc niobate, to provide some examples. In some embodiments, when using a high-k dielectric material, an annealing process can be performed on the gate dielectric 282 to improve its quality. The gate electrode 284 can include a wide range of materials, such as various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), and their carbides and nitrides. In some embodiments, for example, the gate dielectric 282 and / or the gate electrode 284 can include a multi-layer structure composed of two or more material layers. For example, in one embodiment, the gate dielectric includes a first layer composed of silicon dioxide on the channel region and a second layer composed of hafnium oxide on the first layer. The gate electrode can include, for example, metal plugs together with one or more work function layers, resistance reduction layers, and / or barrier layers. In some embodiments, the gate dielectric 282 and / or the gate electrode 284 can include grading (e.g., increasing and / or decreasing) the content / concentration of one or more materials in at least a portion of the (one or more) features. Note that although in Figure 2M the exemplary embodiment of, the gate dielectric 282 is only shown below the gate electrode 284, in other embodiments, for example, the gate dielectric 282 can also be present on one or both sides of the gate electrode 284, such that the gate dielectric 282 is U-shaped (in cross-sectional profile), and the gate dielectric 282 can also be between the gate electrode 284 and one or two gate spacers 250. According to the present disclosure, many different gate stack configurations will be apparent.

[0056] According to some embodiments, method 100 of FIG. 1 continues to perform 124 S / D contact processing to form Figure 2P the exemplary resulting structure. In this exemplary embodiment, the S / D contact processing 124 first includes forming S / D contact trenches 290 over the S / D regions 261, 262, as Figure 2PAs shown. In some such embodiments, the contact trench 290 may be formed using any suitable technique, e.g., performing one or more wet and / or dry etching processes to remove portions of the ILD layer 270 or the dopant-rich insulator capping 212 as shown, and / or performing any other suitable processing that will be apparent in light of the present disclosure. Such an etching process may be referred to as an S / D contact trench etching process, or simply a contact trench etching process. Additionally, in some such embodiments, e.g., the ILD may first be patterned such that areas that will not be removed by the contact trench etching process are masked. In some embodiments, one or more etch stop layers may have been formed over the S / D regions 261, 262 prior to performing the contact trench etching process to aid in the control of the process (e.g., thus aiding in stopping the etching and thereby preventing the etching from consuming the material of the S / D regions in an undesired manner). In some such embodiments, the etch stop layer may include an insulator material that is not similar to the ILD 270 material (e.g., to provide relative etch selectivity) and / or a material that is resilient to the contact trench etching, e.g., a carbon-based etch stop layer (e.g., having a carbon concentration in the range of 1-80%).

[0057] According to some embodiments, continuing from Figure 2P the exemplary structure of the contact portion processing 124 includes forming S / D contact portions 291 over the respective S / D regions 261, 262. In Figure 2PIn the exemplary structure of, it can be understood that the S / D contact portion 291 is electrically connected to the S / D regions 261, 262, and in some cases, they may also be in physical contact with these S / D regions. In some embodiments, the S / D contact portion 291 may be formed using any suitable technique, for example, depositing a metal or metal alloy (or other suitable conductive material) in the contact trench 290. In some embodiments, the formation of the S / D contact portion 291 may include silicidation, germanidation, and / or annealing processes, for example, where such a treatment may be performed before forming the body contact metal structure to form an intervening contact layer. In some embodiments, the S / D contact portion 291 may include aluminum, copper, cobalt, or tungsten, although any suitable conductive metal or alloy such as silver, nickel-platinum, or nickel-aluminum may be used. Generally, in some embodiments, for example, one or more of the S / D contact portions 291 may include a resistance-reducing metal and a contact plug metal, or may include only a contact plug. Exemplary contact resistance-reducing metals include (for example) nickel, aluminum, titanium, tantalum, nickel-platinum, or nickel-aluminum, and / or other such resistance-reducing and / or diffusion barrier metals or alloys. In some embodiments, depending on the specific configuration, the S / D contact portion 291 may employ (one or more) low work function metal materials and / or (one or more) high work function metal materials. In some embodiments, additional layers may be present in the S / D contact region, such as an adhesion layer (e.g., titanium nitride) and / or a liner or barrier layer (e.g., tantalum nitride), if desired.

[0058] According to an embodiment, Figure 2Q is shown in three dimensions (x, y, z) Figure 2P Another view of the exemplary structure of. The substrate 200 and the STI region 220 are shown in this figure. Both the p-MOS replacement S / D material 261 and the n-MOS replacement S / D material 262 after epitaxial S / D processing are shown (for example). The dopant-rich insulator capping 212 is also shown deposited over the pair of n-MOS S / D fins 262. The gate spacers 250 are also shown in the background. Additionally, the S / D isolation wall 295 is shown in this exemplary embodiment.

[0059] Figure 3A Shows an exemplary cross-sectional view along Figure 2P plane A-A of. Provided Figure 3A The cross-sectional view of is to assist in showing Figure 2P different features of the structure of. Thus, the relevant descriptions made about each feature with a similar reference numeral also apply to Figure 3A . However, note that for ease of illustration, Figure 3A the dimensions of the features shown may be relative to Figure 2PThe features in are different. It should also be noted that some variations can occur between the structures. For example, the shape of the gate spacer 250 and the shape of the finned channel region 230 can vary. It should also be noted that Figure 3A the channel region 230 shown is not native to the substrate 200; however, in other embodiments, the channel region (and thus, the material of the channel region) can be native to the substrate 200. In addition, it should be noted that in Figure 3A the specific S / D configuration employed in the structure of is from Figure 2P the same S / D configuration of.

[0060] In some embodiments, the length of the gate electrode 284, denoted as Lg in Figure 3A (the dimension between the transistors 250 in the Z-axis direction) can be any suitable length that would be apparent in light of the present disclosure. For example, in some embodiments, the gate length can be in the range of 3 - 100 nm (e.g., 3 - 10, 3 - 20, 3 - 30, 3 - 50, 5 - 10, 5 - 20, 5 - 30, 5 - 50, 5 - 100, 10 - 20, 10 - 30, 10 - 50, 10 - 100, 20 - 30, 20 - 50, 20 - 100, or 50 - 100 nm) or greater. In some embodiments, the gate length can be less than a given threshold, e.g., less than 100, 50, 45, 40, 35, 30, 25, 20, 15, 10, 8, or 5 nm, or less than some other suitable threshold that would be apparent in light of the present disclosure. In some embodiments, when scaled to such low thresholds (e.g., sub-50, sub-40, sub-30, or sub-20 nm thresholds and even lower thresholds), the techniques are capable of maintaining the desired device performance, which can be understood based on the present disclosure. For example, the techniques described herein in various ways can reduce short-channel effects, thereby increasing the effective channel length (the dimension between the S / D regions in the Z-axis direction). In addition, according to some embodiments, the techniques described herein can allow the gate length and the effective channel length to be the same or substantially the same. For example, in some such embodiments, the effective channel length and the gate length being substantially the same can include the difference between the effective channel length and the gate length (e.g., the effective channel length being shorter than the gate length) being within 1 - 10 nm (e.g., within 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 nm) or within 1% - 10% (e.g., within 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, or 10%).

[0061] Figure 3B shows, according to some embodiments, along Figure 2P plane B - B of and Figure 3AAnother exemplary cross-sectional view similar thereto. In this view, the S / D region 262 is of n-MOS material, and the dopant-rich insulator capping layer 212 is shown deposited over the adjacent S / D regions 262. Also, it can be seen that due to the protection provided by the gate structure during the deposition of the dopant-rich insulator cap, the dopant-rich insulator capping layer 212 does not appear adjacent to the channel region 230.

[0062] According to some embodiments, the method 100 of FIG. 1 proceeds to complete 126 the desired integrated circuit (IC) processing. For example, such additional processing of the completed IC can include back-end or back-end-of-line (BEOL) processing to form one or more metallization layers and / or to interconnect the transistor devices formed during front-end or front-end-of-line (FEOL) processing. Any other suitable processing can be performed, which will be apparent in light of the present disclosure. Note that for ease of description, the processes 102-126 of method 100 are shown in a particular order. However, one or more of the processes 102-126 can be performed in a different order or may not be performed at all. For example, block 116 is an optional process that need not be performed in embodiments employing a gate-first process flow. Recall that the techniques can be used to form many different transistor types and configurations. Although the techniques are primarily depicted and described in the context of using a dopant-rich insulator cap to reduce the undesired diffusion of n-type impurities from the source / drain structure of a given n-MOS transistor having a Ge-rich channel region to an adjacent insulator region, the present disclosure is not intended to be limited thereto, as in some embodiments the techniques can be used to benefit only one side rather than the other side of a given channel region. Many variations and configurations will be apparent in light of the present disclosure.

[0063] Exemplary System

[0064] Figure 4 A computing system 1000 is shown that is implemented in accordance with some embodiments of the present disclosure as having an integrated circuit structure and / or transistor devices formed using the techniques disclosed herein. It can be seen that the computing system 1000 houses a motherboard 1002. The motherboard 1002 can include several components, including but not limited to a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002 or otherwise integrated therein. It should be appreciated that the motherboard 1002 can be (e.g.) any printed circuit board, whether a main board, a daughter board mounted on the main board, or the sole board of the system 1000, etc.

[0065] Depending on its application, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), graphics processors, digital signal processors, cryptographic processors, chip sets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact disks (CDs), digital versatile disks (DVDs), etc.). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques according to an exemplary embodiment. In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that communication chip 1006 may be part of processor 1004 or otherwise integrated within processor 100).

[0066] Communication chip 1006 is capable of enabling wireless communication for transferring data to and from computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transfer data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the relevant devices do not contain any wiring, but in some embodiments they may not. Communication chip 1006 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher generations. Computing system 1000 may include multiple communication chips 1006. For example, a first communication chip 1006 may be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and a second communication chip 1006 may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0067] The processor 1004 of the computing system 1000 includes an integrated circuit die encapsulated within the processor 1004. In some embodiments, the integrated circuit die of the processor includes on-board circuitry implemented as one or more integrated circuit structures or devices formed using the techniques disclosed herein in various ways. The term "processor" may refer to any device or portion of a device that processes, for example, electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory.

[0068] The communication chip 1006 may also include an integrated circuit die encapsulated within the communication chip 1006. According to some such exemplary embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the techniques disclosed herein in various ways. As will be appreciated in accordance with the present disclosure, it should be noted that multi-standard wireless capabilities may be directly integrated into the processor 1004 (e.g., where the functionality of any chip 1006 is integrated into the processor 1004 rather than having a separate communication chip). Additionally note that the processor 1004 may be a chipset having such wireless capabilities. In short, any number of processors 1004 and / or communication chips 1006 may be used. Similarly, any one chip or chipset may have multiple functions integrated therein.

[0069] In various embodiments, the computing system 1000 may be a laptop, netbook, notebook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device or system that processes data or incorporates one or more integrated circuit structures or devices formed using the techniques disclosed herein in various ways. Note that the reference to a computing system is intended to include computing devices, apparatuses, and any other structure configured to compute or process information.

[0070] Other Exemplary Embodiments

[0071] The following examples relate to other embodiments, by way of which many permutations and configurations will be apparent.

[0072] Example 1 is an integrated circuit (IC) that includes: a semiconductor body including germanium with an atomic percentage of at least 75%; a gate structure on the semiconductor body, the gate structure including a gate dielectric and a gate electrode; a source region and a drain region, both adjacent to the gate structure such that the gate structure is between the source region and the drain region, at least one of the source region and the drain region including an n-type impurity; and a dopant-rich insulator capping region between at least one of the source region and the drain region and an undoped insulator region, the dopant-rich insulator capping region including an n-type impurity and being distinct from the undoped insulator region.

[0073] Example 2 includes the subject matter of Example 1, wherein the n-type impurity is phosphorus.

[0074] Example 3 includes the subject matter of Example 1 or 2, wherein the concentration of the n-type impurity in the dopant-rich insulator capping region is in the range of 1 atomic percent to 10 atomic percent.

[0075] Example 4 includes the subject matter of any of Examples 1-3, wherein the thickness of the dopant-rich insulator capping region is in the range of 10 nanometers to 100 nanometers, and the thickness is the distance between a first adjacent undoped insulator on a first side of at least one of the source region and the drain region and a second adjacent undoped insulator on a second side of at least one of the source region and the drain region.

[0076] Example 5 includes the subject matter of any of Examples 1-4, wherein the height of the dopant-rich insulator capping region is in the range of 10 nanometers to 200 nanometers, and the height is the distance extending vertically from the surface of a shallow trench isolation (STI) region adjacent to at least one of the source region and the drain region.

[0077] Example 6 includes the subject matter of any of Examples 1-5, wherein the dopant-rich insulator capping region includes silicon dioxide.

[0078] Example 7 includes the subject matter of any of Examples 1-6, wherein the semiconductor body further includes at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

[0079] Example 8 includes the subject matter of any of Examples 1-7, wherein the germanium concentration of the semiconductor body is 98 atomic percent or higher.

[0080] Example 9 includes the subject matter of any of Examples 1-8, wherein the semiconductor body further includes up to 2 atomic percent of tin.

[0081] Example 10 includes the subject matter of any of Examples 1-9, wherein, in addition to the n-type impurity, the source region and the drain region are compositionally distinct from the semiconductor body, and the source region and the drain region include at least one of silicon and germanium.

[0082] Example 11 includes the subject matter of any of Examples 1-10, wherein, in addition to the n-type impurity, the source region and the drain region are compositionally different from the semiconductor body, and the source region and the drain region further include at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

[0083] Example 12 includes the subject matter of any of Examples 1-11, wherein the source region and the drain region further include up to 2 atomic percent of tin.

[0084] Example 13 includes the subject matter of any of Examples 1-12, wherein the n-type impurity is arsenic.

[0085] Example 14 includes the subject matter of any of Examples 1-13, wherein the semiconductor body is on the fin root, and the dopant-rich insulator capping region is on the opposite sidewalls of the fin root and on the opposite sidewalls of the semiconductor body.

[0086] Example 15 includes the subject matter of any of Examples 1-14, wherein at least one of the source region and the drain region is on the fin root, and the dopant-rich insulator capping region is on the opposite sidewalls of the fin root and on the opposite sidewalls of at least one of the source region and the drain region.

[0087] Example 16 includes the subject matter of any of Examples 1-15, wherein the fin root is part of a lower semiconductor substrate.

[0088] Example 17 includes the subject matter of any of Examples 1-16, wherein the substrate is silicon and the semiconductor body includes at least one of germanium, gallium, arsenic, indium, antimony, and nitrogen.

[0089] Example 18 includes the subject matter of any of Examples 1-17, and further includes a first contact structure in the dopant-rich insulator capping region and on the source region, and a second contact structure in the dopant-rich insulator capping region and on the drain region.

[0090] Example 19 includes the subject matter of any of Examples 1-18, wherein the dopant-rich insulator capping region is on the uppermost surface of at least one of the source region and the drain region.

[0091] Example 20 includes the subject matter of any of Examples 1-19, wherein the semiconductor body is a fin.

[0092] Example 21 includes the subject matter of any of Examples 1 - 20, wherein the semiconductor body includes one or more nanowires.

[0093] Example 22 includes the subject matter of any of Examples 1 - 21, wherein the semiconductor body includes one or more nanoribbons.

[0094] Example 23 includes the subject matter of any of Examples 1 - 22, wherein the gate structure further includes a first gate spacer between the source region and the gate electrode and a second gate spacer between the drain region and the gate electrode.

[0095] Example 24 is a computing system of an IC including the subject matter of any of Examples 1 - 23.

[0096] Example 25 is a method of forming an integrated circuit (IC), the method including: forming a semiconductor body including at least 75 atomic percent germanium; forming a gate structure on the semiconductor body, the gate structure including a gate dielectric and a gate electrode; forming a source region and a drain region, both adjacent to the gate structure such that the gate structure is between the source region and the drain region, at least one of the source region and the drain region including an n-type impurity; and forming a dopant-rich insulator capping region between the at least one of the source region and the drain region and an undoped insulator region, the dopant-rich insulator capping region including the n-type impurity and being distinct from the undoped insulator region.

[0097] Example 26 includes the subject matter of Example 25, wherein the n-type impurity is phosphorus.

[0098] Example 27 includes the subject matter of Example 25 or 26, wherein the concentration of the n-type impurity in the dopant-rich insulator capping region is in the range of 1 atomic percent to 10 atomic percent.

[0099] Example 28 includes the subject matter of any of Examples 25 - 27, wherein the thickness of the dopant-rich insulator capping region is in the range of 10 nanometers to 100 nanometers, the thickness being the distance between a first adjacent undoped insulator on a first side of the at least one of the source region and the drain region and a second adjacent undoped insulator on a second side of the at least one of the source region and the drain region.

[0100] Example 29 includes the subject matter of any of Examples 25 - 28, wherein the height of the dopant-rich insulator capping region is in the range of 10 nanometers to 200 nanometers, the height being the distance extending perpendicularly from the surface of a shallow trench isolation (STI) region adjacent to the at least one of the source region and the drain region.

[0101] Example 30 includes the subject matter of any of Examples 25-29, wherein the germanium concentration of the semiconductor body is 98 atomic percent or higher.

[0102] Example 31 includes the subject matter of any of Examples 25-30, wherein the dopant-rich insulator capping region includes silicon dioxide.

[0103] Example 32 includes the subject matter of any of Examples 25-31, wherein the semiconductor body further includes at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

[0104] Example 33 includes the subject matter of any of Examples 25-32, wherein the semiconductor body further includes up to 2 atomic percent of tin.

[0105] Example 34 includes the subject matter of any of Examples 25-33, wherein, in addition to the n-type impurity, the source region and the drain region are compositionally distinct from the semiconductor body, and the source region and the drain region include at least one of silicon and germanium.

[0106] Example 35 includes the subject matter of any of Examples 25-34, wherein, in addition to the n-type impurity, the source region and the drain region are compositionally different from the semiconductor body, and the source region and the drain region further include at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

[0107] Example 36 includes the subject matter of any of Examples 25-35, wherein the source region and the drain region further include up to 2 atomic percent of tin.

[0108] Example 37 includes the subject matter of any of Examples 25-36, wherein the n-type impurity is arsenic.

[0109] Example 38 includes the subject matter of any of Examples 25-37, wherein the semiconductor body is on the fin root, and the dopant-rich insulator capping region is on opposite sidewalls of the fin root and on opposite sidewalls of the semiconductor body.

[0110] Example 39 includes the subject matter of any of Examples 25-38, wherein at least one of the source region and the drain region is on the fin root, and the dopant-rich insulator capping region is on the opposite sidewall of the fin root and on opposite sidewalls of at least one of the source region and the drain region.

[0111] Example 40 includes the subject matter of any of Examples 25-39, wherein the fin root is part of a lower semiconductor substrate.

[0112] Example 41 includes the subject matter of any of Examples 25-40, wherein the substrate is silicon and the semiconductor body includes at least one of germanium, gallium, arsenic, indium, antimony, and nitrogen.

[0113] Example 42 includes the subject matter of any of Examples 25-41, and further includes forming a first contact structure in a dopant-rich insulator capping region and over the source region, and forming a second contact structure in the dopant-rich insulator capping region and over the drain region.

[0114] Example 43 includes the subject matter of any of Examples 25-42, wherein the dopant-rich insulator capping region is on the uppermost surface of at least one of the source region and the drain region.

[0115] Example 44 includes the subject matter of any of Examples 25-43, wherein the semiconductor body is a fin.

[0116] Example 45 includes the subject matter of any of Examples 25-44, wherein the semiconductor body includes one or more nanowires.

[0117] Example 46 includes the subject matter of any of Examples 25-45, wherein the semiconductor body includes one or more nanoribbons.

[0118] Example 47 includes the subject matter of any of Examples 25-46, wherein the gate structure further includes a first gate spacer between the source region and the gate electrode and a second gate spacer between the drain region and the gate electrode.

[0119] The terms and expressions used herein are used as descriptive terms and not of a limiting nature, and the use of such terms and expressions is not intended to exclude any equivalents of the features (or portions thereof) shown and described, and it should be recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents. Various features, aspects, and embodiments have been described herein. These features, aspects, and embodiments are readily susceptible to combinations with one another as well as variations and modifications, which will be recognized in accordance with the present disclosure. Accordingly, it should be considered that the present disclosure covers such combinations, variations, and modifications. It is not intended that the scope of the present disclosure be limited by the present detailed description, but rather the scope of the present disclosure is defined by the appended claims. Future applications claiming the priority of this application may claim the rights to the disclosed subject matter in different ways and generally may include any set of one or more of the elements disclosed herein in various ways or otherwise shown.

Claims

1. An integrated circuit (IC) includes: A semiconductor body including germanium with an atomic percentage of at least 75%; A gate structure on the semiconductor body, the gate structure including a gate dielectric and a gate electrode; A source region and a drain region, both the source region and the drain region being adjacent to the gate structure such that the gate structure is between the source region and the drain region, and at least one of the source region and the drain region includes an n-type impurity; and A dopant-rich insulator capping region between at least one of the source region and the drain region and an interlayer dielectric layer, the dopant-rich insulator capping region including the n-type impurity and being compositionally distinct from the interlayer dielectric layer.

2. The IC according to claim 1, wherein The n-type impurity is phosphorus.

3. The IC according to claim 1, wherein, The concentration of the n-type impurity in the dopant-rich insulator capping region is in the range of 1 atomic % to 10 atomic %.

4. The IC according to claim 1, wherein, The thickness of the dopant-rich insulator capping region is in the range of 10 nanometers to 100 nanometers, and the thickness is the distance between a first adjacent interlayer dielectric layer on a first side of at least one of the source region and the drain region and a second adjacent interlayer dielectric layer on a second side of at least one of the source region and the drain region.

5. The IC according to claim 1, wherein The height of the dopant-rich insulator capping region is in the range of 10 nanometers to 200 nanometers, and the height is the distance extending vertically from the surface of a shallow trench isolation (STI) region adjacent to at least one of the source region and the drain region.

6. The IC according to claim 1, wherein, The dopant-rich insulator capping region includes silicon dioxide.

7. The IC according to claim 1, wherein, The semiconductor body further includes at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

8. The IC according to claim 1, wherein The germanium concentration of the semiconductor body is 98 atomic % or higher.

9. The IC according to any one of claims 1-8, wherein, The semiconductor body further includes up to 2 atomic % of tin.

10. The IC according to any one of claims 1-8, wherein, Except for the n-type impurity, the source region and the drain region are compositionally distinct from the semiconductor body, and the source region and the drain region include at least one of silicon and germanium.

11. The IC according to any one of claims 1 - 8, wherein, Except for the n-type impurity, the source region and the drain region are compositionally different from the semiconductor body, and the source region and the drain region further include at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

12. The IC according to any one of claims 1-8, wherein, The source region and the drain region further include up to 2 atomic % of tin.

13. The IC according to any one of claims 1-8, wherein, The n-type impurity is arsenic.

14. The IC according to any one of claims 1-8, wherein, The semiconductor body is on a fin root, and the dopant-rich insulator capping region is on opposite sidewalls of the fin root and on opposite sidewalls of the semiconductor body.

15. The IC according to claim 14, wherein, At least one of the source region and the drain region is on the fin root, and the dopant-rich insulator capping region is on opposite sidewalls of the fin root and on opposite sidewalls of at least one of the source region and the drain region.

16. The IC according to claim 14, wherein, The fin root is part of a lower semiconductor substrate.

17. The IC according to claim 16, wherein, The substrate is silicon and the semiconductor body includes at least one of germanium, gallium, arsenic, indium, antimony, and nitrogen.

18. The IC according to claim 1 further includes a first contact structure in the dopant-rich insulator capping region and over the source region, and a second contact structure in the dopant-rich insulator capping region and over the drain region.

19. A computing system includes the IC according to any one of claims 1-18.

20. A method of forming an integrated circuit (IC), the method comprising: forming a semiconductor body comprising at least 75 atomic percent germanium; forming a gate structure on the semiconductor body, the gate structure including a gate dielectric and a gate electrode; forming a source region and a drain region, both the source region and the drain region being adjacent to the gate structure such that the gate structure is between the source region and the drain region, at least one of the source region and the drain region including an n-type impurity; and forming a dopant-rich insulator capping region between at least one of the source region and the drain region and an interlayer dielectric layer, the dopant-rich insulator capping region including the n-type impurity, the dopant-rich insulator capping region being compositionally distinct from the interlayer dielectric layer.

21. The method according to claim 20, wherein The n-type impurity is phosphorus.

22. The method according to claim 20, wherein The concentration of the n-type impurity in the dopant-rich insulator capping region is in the range of 1 atomic percent to 10 atomic percent.

23. The method according to any one of claims 20-22, wherein The thickness of the dopant-rich insulator capping region is in the range of 10 nanometers to 100 nanometers, the thickness being the distance between a first adjacent interlayer dielectric layer on a first side of at least one of the source region and the drain region and a second adjacent interlayer dielectric layer on a second side of at least one of the source region and the drain region.

24. The method according to any one of claims 20-22, wherein, The height of the dopant-rich insulator capping region is in the range of 10 nanometers to 200 nanometers, the height being the distance extending perpendicularly from the surface of a shallow trench isolation (STI) region adjacent to at least one of the source region and the drain region.

25. The method according to any one of claims 20 - 22, wherein, The germanium concentration of the semiconductor body is 98 atomic percent or higher.

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