Storage module, storage system and method for operating storage module

Abstract

A memory module, a memory system, and a method for operating a memory module are provided. The memory module includes a semiconductor memory device mounted on a circuit board and a control device mounted on the circuit board. The control device receives a command, an address, and a clock signal from an external device, and provides the command, the address, and the clock signal to the semiconductor memory device. The control device performs command / address training on the at least one semiconductor memory device in a hidden training mode during normal operation by sending a first command / address and a first clock signal to at least one of the semiconductor memory devices, and receiving a second command / address and a second clock signal in response to the first command / address and the first clock signal from the at least one semiconductor memory device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0123522 filed on October 17, 2018, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the inventive concept relate to a memory module, a memory system, and a method of operating a memory module. Background Art

[0004] The semiconductor memory may be a memory device implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. Semiconductor memory devices are generally classified into volatile memory devices and nonvolatile memory devices.

[0005] A volatile memory device refers to a memory device in which stored data is lost when the power is turned off. On the other hand, a nonvolatile memory device refers to a memory device in which stored data is retained when the power is turned off.

[0006] Dynamic random access memory (DRAM) is a volatile memory device that is widely used as a working memory, buffer memory, main memory, etc. of a computing system due to its high access speed. Because a DRAM memory cell generally includes a capacitor and a transistor, it may be difficult to reduce the cell size beyond a certain level. Therefore, it may be difficult to implement a high-capacity DRAM in a limited area. In order to achieve high capacity, a plurality of DRAMs may be provided in the form of a memory module. Summary of the invention

[0007] According to an exemplary embodiment of the inventive concept, a memory module includes a plurality of semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. The control device receives a command, an address, and a clock signal from an external device, and provides the command, the address, and the clock signal to the plurality of semiconductor memory devices. The control device performs command / address training on the at least one semiconductor memory device in a hidden training mode during normal operation by sending a first command / address and a first clock signal to at least one semiconductor memory device among the plurality of semiconductor memory devices, and receiving a second command / address and a second clock signal in response to the first command / address and the first clock signal from the at least one semiconductor memory device.

[0008] According to an exemplary embodiment of the inventive concept, a storage system includes a storage module and a storage controller for controlling the storage module. The storage module includes a plurality of semiconductor storage devices and a control device for controlling the plurality of semiconductor storage devices, and the plurality of semiconductor storage devices and the control device are mounted on a circuit board. The control device receives a command, an address, and a clock signal from the storage controller, and provides the command, the address, and the clock signal to the plurality of semiconductor storage devices. The control device performs command / address training on the at least one semiconductor storage device in a hidden training mode during normal operation by sending a first command / address and a first clock signal to at least one semiconductor storage device among the plurality of semiconductor storage devices, and receiving a second command / address and a second clock signal in response to the first command / address and the first clock signal from the at least one semiconductor storage device.

[0009] According to an exemplary embodiment of the inventive concept, a method for operating a memory module is provided, wherein the memory module includes a plurality of semiconductor memory devices and a control device for controlling the plurality of semiconductor memory devices, and the plurality of semiconductor memory devices and the control device are mounted on a circuit board. According to the method, in an initial training mode of the memory module, the control device performs initial command / address training on each of the plurality of semiconductor memory devices to store initial skew information about the skew between the command / address and the clock signal associated with each of the plurality of semiconductor memory devices in a register in the control device; performs normal operation in each of the plurality of semiconductor memory devices; determines by the control device whether at least one of the plurality of semiconductor memory devices enters a hidden training mode during the normal operation; adjusts the skew by receiving the command / address and the clock signal from the at least one semiconductor memory device entering the hidden training mode; and performs the normal operation by the at least one semiconductor memory device based on the adjusted skew. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features of the present inventive concept will be more clearly understood by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0011] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

[0012] Figure 2 is a diagram showing in detail an exemplary embodiment according to the inventive concept Figure 1 Block diagram of the storage module in .

[0013] Figure 3 is a diagram showing an exemplary embodiment according to the inventive concept Figure 2 Block diagram of a semiconductor memory device in FIG.

[0014] Figure 4 An exemplary embodiment according to the present inventive concept is shown. Figure 3 A first memory bank array in a semiconductor memory device.

[0015] Figure 5 is a diagram showing an exemplary embodiment according to the inventive concept Figure 3 A block diagram of a loopback circuit in a semiconductor memory device.

[0016] Figure 6 is a diagram showing an exemplary embodiment according to the inventive concept Figure 5 Circuit diagram of the first selection circuit and the second selection circuit in .

[0017] Figure 7 is a diagram showing an exemplary embodiment according to the inventive concept Figure 5 Circuit diagram of the first selection circuit and the second selection circuit in .

[0018] Figure 8 An exemplary embodiment according to the present inventive concept is shown. Figure 2 A portion of a control device and a portion of a semiconductor storage device in a storage module.

[0019] Fig. 9 An exemplary embodiment according to the present inventive concept is shown. Figure 8 Registers in the interface circuit.

[0020] Fig.10 is a diagram showing an exemplary embodiment according to the inventive concept Figure 8 A timing diagram of the operation of a delay locked loop (DLL) circuit in FIG.

[0021] Fig.11 is a diagram showing an exemplary embodiment according to the inventive concept Figure 8 The timing diagram of the operation of the DLL circuit.

[0022] Fig.12 is a diagram showing an exemplary embodiment according to the inventive concept Figure 8 The timing diagram of the operation of the DLL circuit.

[0023] Fig.13 An exemplary embodiment according to the present inventive concept is shown. Figure 2 part of the storage module.

[0024] Fig.14 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 Block diagram of the storage module in .

[0025] Fig.15 is a flowchart illustrating a method of operating a memory module according to an exemplary embodiment of the inventive concept.

[0026] Fig.16 is a flowchart illustrating a method of operating a memory module according to an exemplary embodiment of the inventive concept.

[0027] Fig.17 is a block diagram illustrating a memory system having a quad-rank memory module according to an exemplary embodiment of the inventive concept.

[0028] Fig.18 is a block diagram illustrating a mobile system including a storage module according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0029] Exemplary embodiments of the inventive concept provide a memory module capable of autonomously performing command / address training.

[0030] Exemplary embodiments of the inventive concept also provide a memory system including a memory module capable of autonomously performing command / address training.

[0031] Example embodiments also provide a method of operating a memory module capable of autonomously performing command / address training.

[0032] Exemplary embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings.Throughout the application, like reference numerals may refer to like elements.

[0033] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

[0034] refer to Figure 1 , the storage system 10 includes a host 20 and a storage module 100. The host 20 may include a storage controller 25.

[0035] The memory module 100 may include a control device 500, a serial presence detect (SPD) chip 180, a power management integrated circuit (PMIC) 185, and a semiconductor memory device 200. The control device 500 may be a registered clock driver (RCD).

[0036] The control device 500 may control the semiconductor memory device 200 and the PMIC 185 under the control of the memory controller 25. For example, the control device 500 may receive an address ADDR, a command CMD, and a clock signal CK from the memory controller 25.

[0037] In response to the received signal, the control device 500 may control the semiconductor memory device 200 so that the data received through the data signal DQ and the data strobe signal DQS is written into the semiconductor memory device 200, or so that the data stored in the semiconductor memory device 200 is output through the data signal DQ and the data strobe signal DQS. For example, the control device 500 may send the address ADDR, the command CMD, and the clock signal CK from the memory controller 25 to the semiconductor memory device 200.

[0038] The semiconductor memory device 200 may write data received through the data signal DQ and the data strobe signal DQS under the control of the control device 500. Alternatively, the semiconductor memory device 200 may output the written data through the data signal DQ and the data strobe signal DQS under the control of the control device 500.

[0039] For example, the semiconductor memory device 200 may include a volatile memory device such as a dynamic random access memory (DRAM), a static RAM (SRAM), or a synchronous DRAM (SDRAM). For example, the semiconductor memory device 200 may be a volatile memory device based on DRAM. The semiconductor memory device 200 may include a double data rate 5 (DDR5) SDRAM.

[0040] The SPD chip 180 may be a programmable read-only memory (e.g., EEPROM). The SPD chip 180 may include initial information or device information DI of the storage module 100. In an exemplary embodiment of the inventive concept, the SPD chip 180 may include initial information or device information DI, such as a module form, module configuration, storage capacity, module type, execution environment, etc. of the storage module 100.

[0041] When the memory system 10 including the memory module 100 is started, the host 20 may read the device information DI from the SPD chip 180, and may identify the memory module 100 based on the device information DI. The host 20 may control the memory module 100 based on the device information DI from the SPD chip 180. For example, the host 20 may identify the type of the semiconductor memory device 200 included in the memory module 100 based on the device information DI from the SPD chip 180.

[0042] In an exemplary embodiment of the inventive concept, the SPD chip 180 may communicate with the host 20 through a serial bus. The host 20 may exchange signals with the SPD chip 180 through the serial bus. The SPD chip 180 may communicate with the control device 500 through the serial bus. The serial bus may include at least one of a 2-wire serial bus such as an inter-integrated circuit (I2C), a system management bus (SMBus), a power management bus (PMBus), an intelligent platform management interface (IPMI), a management component transport protocol (MCTP), and the like.

[0043] The control device 500 may control the PMIC 185 through a first control signal CTL1, and may control the semiconductor memory device 200 through a second control signal CTL2. The second control signal CTL2 may include an address ADDR, a command CMD, and a clock signal CK.

[0044] During normal operation, the control device 500 may exchange commands / addresses CA and clock signals CK with at least some of the semiconductor memory devices 200 in a hidden training mode.

[0045] The PMIC 185 receives an input voltage VIN, generates a power voltage VDD based on the input voltage VIN, and provides the power voltage VDD to the semiconductor memory device 200. The semiconductor memory device 200 operates based on the power voltage VDD.

[0046] Figure 2 is a diagram showing in detail an exemplary embodiment according to the inventive concept Figure 1 Block diagram of the storage module in .

[0047] refer to Figure 2 The storage module 100 includes a control device 500 arranged (or installed) on a circuit board 101, multiple semiconductor storage devices 201a~201e, 202a~202e, 203a~203e and 204a~204e, multiple data buffers (DB) 141~145 and 151~155, module resistance units 160 and 170, an SPD chip 180 and a PMIC 185.

[0048] Here, the circuit board 101 as a printed circuit board may extend in a second direction D2 perpendicular to the first direction D1 between the first edge portion 103 and the second edge portion 105. The first edge portion 103 and the second edge portion 105 may extend in the first direction D1.

[0049] The control device 500 may be disposed at the center of the circuit board 101. A plurality of semiconductor storage devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e may be arranged in a plurality of rows between the control device 500 and the first edge portion 103 or between the control device 500 and the second edge portion 105. In this case, the semiconductor storage devices 201a to 201e and 202a to 202e may be arranged in a plurality of rows between the control device 500 and the first edge portion 103. The semiconductor storage devices 203a to 203e and 204a to 204e may be arranged in a plurality of rows between the control device 500 and the second edge portion 105.

[0050] Some of the semiconductor memory devices 201a to 201e and 202a to 202e may be error correction code (ECC) memory devices. The ECC memory device may perform an ECC encoding operation to generate parity bits for data to be written into the memory cells of the plurality of semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e, and perform an ECC decoding operation to correct errors occurring in the data read from the memory cells.

[0051] Each of the plurality of semiconductor memory devices 201a-201e, 202a-202e, 203a-203e and 204a-204e may be coupled to a corresponding data buffer among the data buffers 141-145 and 151-155 through a data transmission line to receive / transmit a data signal DQ and a data strobe signal DQS.

[0052] The control device 500 may provide a command / address signal (e.g., CA) to the semiconductor storage devices 201a to 201e through the command / address transmission line 161, and may provide a command / address signal to the semiconductor storage devices 202a to 202e through the command / address transmission line 163. In addition, the control device 500 may provide a command / address signal to the semiconductor storage devices 203a to 203e through the command / address transmission line 171, and may provide a command / address signal to the semiconductor storage devices 204a to 204e through the command / address transmission line 173.

[0053] The command / address transmission lines 161 and 163 may be commonly connected to the module resistance unit 160 disposed adjacent to the first edge portion 103 , and the command / address transmission lines 171 and 173 may be commonly connected to the module resistance unit 170 disposed adjacent to the second edge portion 105 .

[0054] The module resistance units 160 and 170 may each include a terminal resistor Rtt / 2 connected to the terminal voltage Vtt. In this case, the arrangement of the module resistance units 160 and 170 may reduce the number of module resistance units, thereby reducing an area where the terminal resistors are disposed.

[0055] In addition, each of the plurality of semiconductor memory devices 201a to 201e, 202a to 202e, 203a to 203e, and 204a to 204e may be a DDR5 SDRAM.

[0056] The SPD chip 180 is disposed adjacent to the control device 500, and the PMIC 185 may be disposed between the semiconductor memory device 203e and the second edge portion 105. The PMIC 185 may generate a power supply voltage VDD based on an input voltage VIN, and may provide the power supply voltage VDD to the semiconductor memory devices 201a-201e, 202a-202e, 203a-203e, and 204a-204e.

[0057] Although Figure 2 , the PMIC 185 is illustrated as being disposed adjacent to the second edge portion 105 , but in an exemplary embodiment of the inventive concept, the PMIC 185 may be disposed in a central portion of the circuit board 101 to be adjacent to the control device 500 .

[0058] The control device 500 can perform command / address training on at least one semiconductor memory device in a hidden training mode during normal operation by sending a first command / address and a first clock signal to at least one semiconductor memory device among a plurality of semiconductor memory devices 201a~201e, 202a~202e, 203a~203e and 204a~204e, and receiving a second command / address and a second clock signal in response to the first command / address and the first clock signal from the at least one semiconductor memory device.

[0059] The control device 500 may receive a second command / address and a second clock signal from the at least one semiconductor memory device through the first loopback pin and the second loopback pin in the hidden training mode.

[0060] The control device 500 may receive the data signal DQ and the data strobe signal DQS from the at least one semiconductor memory device through the first loopback pin and the second loopback pin in an operation mode different from the hidden training mode.

[0061] Figure 3 is a diagram showing an exemplary embodiment according to the inventive concept Figure 2 Block diagram of a semiconductor memory device in FIG.

[0062] Figure 3 The configuration of the semiconductor storage device 201a is shown, and the configuration of each of the semiconductor storage devices 201b to 201e, 202a to 202e, 203a to 203e, and 204a to 204e is substantially the same as that of the semiconductor storage device 201a.

[0063] refer to Figure 3 , the semiconductor memory device 201a may include a control logic circuit 210, an address register 220, a clock buffer 225, a memory body control logic 230, a row address multiplexer (RA MUX) 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier unit 285, an input / output (I / O) selection circuit 290, a data input / output (I / O) buffer 295, a refresh counter 245, an ECC engine 410 and a loopback circuit 430.

[0064] The memory cell array 300 may include first to eighth memory bank arrays 310 to 380. The memory cell array 300 may operate based on a power supply voltage VDD.

[0065] The row decoder 260 may include first memory row decoders 260a to eighth memory row decoders 260h respectively connected to the first memory array 310 to the eighth memory array 380, the column decoder 270 may include first memory column decoders 270a to eighth memory column decoders 270h respectively connected to the first memory array 310 to the eighth memory array 380, and the read-out amplifier unit 285 may include first memory read-out amplifiers 285a to eighth memory read-out amplifiers 285h respectively connected to the first memory array 310 to the eighth memory array 380.

[0066] The first to eighth bank arrays 310 to 380, the first to eighth bank row decoders 260a to 260h, the first to eighth bank column decoders 270a to 270h, and the first to eighth bank sense amplifiers 285a to 285h may form first to eighth banks.

[0067] Each of the first to eighth memory bank arrays 310 to 380 may include a plurality of word lines WL, a plurality of bit lines BTL, and a plurality of memory cells MC respectively formed at intersections of the word lines WL and the bit lines BTL.

[0068] Although Figure 3 2A and 2B illustrate that the semiconductor memory device 201 a includes eight memory banks, but the semiconductor memory device 201 a may include any number of memory banks.

[0069] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the control device 500. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.

[0070] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. In response to the bank control signal, one of the first bank row decoder 260a to the eighth bank row decoder 260h corresponding to the bank address BANK_ADDR may be activated, and one of the first bank column decoder 270a to the eighth bank column decoder 270h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal.

[0071] The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 220 and may receive a refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to eighth bank row decoders 260a to 260h.

[0072] An activated one of the first to eighth bank row decoders 260a to 260h may decode the row address RA output from the row address multiplexer 240, and may activate a word line corresponding to the row address RA. For example, the activated bank row decoder may generate a word line driving voltage based on the power supply voltage VDD, and may apply the word line driving voltage to the word line corresponding to the row address RA.

[0073] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. In an exemplary embodiment of the inventive concept, in a burst mode, the column address latch 250 may generate a column address incremented from the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored column address or the generated column address to the first to eighth bank column decoders 270a to 270h.

[0074] An activated one of the first to eighth bank column decoders 270 a to 270 h may decode the column address COL_ADDR output from the column address latch 250 and may control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR.

[0075] The I / O gating circuit 290 may include a circuit for gating input / output data. The I / O gating circuit 290 may also include a read data latch for storing data output from the first memory array 310 to the eighth memory array 380, and a write driver for writing data into the first memory array 310 to the eighth memory array 380.

[0076] A code word CW to be read from one of the first to eighth memory bank arrays 310 to 380 may be sensed by a sense amplifier coupled to the one memory bank array from which data is to be read, and may be stored in a read data latch.

[0077] The codeword CW stored in the read data latch may be provided to the memory controller 25 via the data I / O buffer 295 after the ECC engine 410 performs ECC decoding on the codeword CW. Data to be written into one of the first to eighth memory bank arrays 310 to 380 may be provided from the memory controller 25 to the data I / O buffer 295. The ECC engine 410 performs ECC encoding on the data provided to the data I / O buffer 295 to generate the codeword CW, and the ECC engine 410 provides the codeword CW to the I / O gating circuit 290.

[0078] In a normal mode write operation, the data I / O buffer 295 may provide a data signal DQ to the ECC engine 410. In a normal mode read operation, the data I / O buffer 295 may receive the data signal DQ from the ECC engine 410 and may provide the data signal DQ and a data strobe signal DQS to the memory controller 25.

[0079] In the bit error rate test mode, the data I / O buffer 295 may provide the data signal DQ and the data strobe signal DQS to the loopback circuit 430. The data I / O buffer 295 may operate based on the control signal DCTL from the control logic circuit 210.

[0080] The clock buffer 225 may provide the clock signal CK to the core unit of the semiconductor memory device 201a in the normal mode. The clock buffer 225 may directly provide the clock signal CK to the loopback circuit 430 in the hidden training mode. The clock buffer 225 may operate based on the control signal CCTL from the control logic circuit 210.

[0081] The loopback circuit 430 may provide the data signal DQ and the data strobe signal DQS to the control device 500 in the bit error rate test mode. The loopback circuit 430 may provide the command / address CA and the clock signal CK to the control device 500 in the hidden training mode. The loopback circuit 430 may operate based on the selection signal SS from the control logic circuit 210.

[0082] The control logic circuit 210 may control the operation of the semiconductor memory device 201a. For example, the control logic circuit 210 may generate a control signal for the semiconductor memory device 201a to perform a write operation or a read operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the memory controller 25 through the control device 500 and a mode register 212 that sets the operation mode of the semiconductor memory device 201a.

[0083] For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. in the command CMD. The control logic circuit 210 may generate a control signal DCTL for controlling the operation of the data I / O buffer 295, a select signal SS for controlling the loopback circuit 430, and a control signal CCTL for controlling the clock buffer 225 according to the operation mode of the semiconductor memory device 201a. The control logic circuit 210 may provide the control signal DCTL to the data I / O buffer 295, the select signal SS to the loopback circuit 430, and the control signal CCTL to the clock buffer 225.

[0084] In an exemplary embodiment of the inventive concept, the control device 500 may directly provide the selection signal SS to the loopback circuit 430 .

[0085] Figure 4 An exemplary embodiment according to the present inventive concept is shown. Figure 3 A first memory bank array in a semiconductor memory device.

[0086] refer to Figure 4, the first memory array 310 includes a plurality of word lines WL1-WL2m (where m is a natural number greater than 2), a plurality of bit lines BTL1-BTL2n (where n is a natural number greater than 2), and a plurality of memory cells MC respectively arranged near intersections between the word lines WL1-WL2m and the bit lines BTL1-BTL2n. In an exemplary embodiment of the inventive concept, the plurality of memory cells MC may each include a DRAM cell structure. The plurality of word lines WL1-WL2m connected to the plurality of memory cells MC may be referred to as rows of the first memory array 310, and the plurality of bit lines BTL1-BTL2n connected to the plurality of memory cells MC may be referred to as columns of the first memory array 310.

[0087] Figure 5 is a diagram showing an exemplary embodiment according to the inventive concept Figure 3 A block diagram of a loopback circuit in a semiconductor memory device.

[0088] refer to Figure 5 The loopback circuit 430 may include a first selection circuit 440, a second selection circuit 450, a first transmitter 461, and a second transmitter 462. The first transmitter 461 may be connected to a first loopback pin 471, and the second transmitter 462 may be connected to a second loopback pin 472.

[0089] The first selection circuit 440 may select one of the first command / address CA1 from the first receiver 421 and the data signal DQ from the second receiver 422 in response to the selection signal SS, and may provide the selected one to the first transmitter 461. The first selection circuit 440 may select the first command / address CA1 in the hidden training mode, and provide the first command / address CA1 to the first transmitter 461. The first selection circuit 440 may select the data signal DQ in the bit error rate test mode. The first transmitter 461 may send one of the first command / address CA1 and the data signal DQ as the first loopback signal LBS1 to the control device 500 through the first loopback pin 471.

[0090] The second selection circuit 450 may select one of the first clock signal CK1 from the third receiver 423 and the data strobe signal DQS from the fourth receiver 424 in response to the selection signal SS, and may provide the selected one to the second transmitter 462. The second selection circuit 450 may select the first clock signal CK1 in the hidden training mode, and provide the first clock signal CK1 to the second transmitter 462. The second selection circuit 450 may select the data strobe signal DQS in the bit error rate test mode. The second transmitter 462 may send one of the first clock signal CK1 and the data strobe signal DQS as the second loopback signal LBS2 to the control device 500 through the second loopback pin 472.

[0091] In other words, during normal operation in the hidden training mode, the semiconductor memory device 201a can select the first command / address CA1 and the first clock signal CK1, and can transmit the first command / address CA1 and the first clock signal CK1 as the second command / address and the second clock signal, respectively, to the control device 500 through the first loopback pin 471 and the second loopback pin 472, respectively.

[0092] The control device 500 may control the semiconductor memory device 201 a such that the semiconductor memory device 201 a immediately enters the hidden training mode after the semiconductor memory device 201 a performs a refresh operation on a plurality of dynamic memory cells in the semiconductor memory device 201 a .

[0093] The control device 500 may autonomously and in real time perform command / address training on the semiconductor memory device 201 a in the hidden training mode without intervention of the memory controller 25 .

[0094] Figure 6 is a diagram showing an exemplary embodiment according to the inventive concept Figure 5 Circuit diagram of the first selection circuit and the second selection circuit in .

[0095] refer to Figure 6 The loopback circuit 430 a may include a first switch 440 a as a first selection circuit 440 , a second switch 450 a as a second selection circuit 450 , a first transmitter 461 , and a second transmitter 462 .

[0096] The first switch 440a may have a first terminal 441 receiving the first command / address CA1, a second terminal 442 receiving the data signal DQ, and a third terminal 443 coupled to the first transmitter 461. The third terminal 443 is connected to one of the first terminal 441 and the second terminal 442 in response to the selection signal SS.

[0097] The second switch 450a may have a first terminal 451 receiving the first clock signal CK1, a second terminal 452 receiving the data strobe signal DQS, and a third terminal 453 coupled to the second transmitter 462. The third terminal 453 is connected to one of the first terminal 451 and the second terminal 452 in response to the selection signal SS.

[0098] Figure 7 is a diagram showing an exemplary embodiment according to the inventive concept Figure 5 Circuit diagram of the first selection circuit and the second selection circuit in .

[0099] refer to Figure 7The loopback circuit 430 b may include a first multiplexer ( MUX1 ) 440 b as a first selection circuit 440 , a second multiplexer ( MUX2 ) 450 b as a second selection circuit 450 , a first transmitter 461 , and a second transmitter 462 .

[0100] The first multiplexer 440b may have a first input terminal receiving the first command / address CA1, a second input terminal receiving the data signal DQ, an output terminal coupled to the first transmitter 461, and a control terminal receiving the selection signal SS. The first multiplexer 440b may select the first command / address CA1 in response to the selection signal SS in the hidden training mode. The first multiplexer 440b may select the data signal DQ in response to the selection signal SS in the bit error rate test mode.

[0101] The second multiplexer 450b may have a first input terminal receiving the first clock signal CK1, a second input terminal receiving the data strobe signal DQS, an output terminal coupled to the second transmitter 462, and a control terminal receiving the selection signal SS. The second multiplexer 450b may select the first clock signal CK1 in response to the selection signal SS in the hidden training mode. The second multiplexer 450b may select the data strobe signal DQS in response to the selection signal SS in the bit error rate test mode.

[0102] Therefore, each of the semiconductor memory devices 201a-201e, 202a-202e, 203a-203e, and 204a-204e may be a synchronous memory device including a first loopback pin 471 and a second loopback pin 472. In an operation mode different from the hidden training mode, the first loopback pin 471 may be used to transmit a data signal DQ to the control device 500. In an operation mode different from the hidden training mode, the second loopback pin 472 may be used to transmit a data strobe signal DQS to the control device 500. The synchronous memory device may perform command / address training in the hidden training mode by using the first loopback pin 471 and the second loopback pin 472.

[0103] Figure 8 An exemplary embodiment according to the present inventive concept is shown. Figure 2 A portion of a control device and a portion of a semiconductor storage device in a storage module.

[0104] exist Figure 8 , an interface circuit 510 included in a control device 500 and a loopback circuit 430 included in a semiconductor storage device 201 a are shown.

[0105] refer to Figure 8, the interface circuit 510 may include transmitters 511 and 512 , a delay locked loop (DLL) circuit 520 , a delay circuit 550 , a command / address (CA) generator 560 , a clock generator 570 , and a register 580 .

[0106] The CA generator 560 may generate a first command / address CA1 and provide the first command / address CA1 to the delay circuit 550. The clock generator 570 may generate a first clock signal CK1 and provide the first clock signal CK1 to the transmitter 512. The delay circuit 550 may selectively adjust the delay amount of the first command / address CA1 and provide the selectively adjusted first command / address CA1 to the first selection circuit 440 in the loopback circuit 430 through the transmitter 511.

[0107] The clock generator 570 may provide the first clock signal CK1 to the second selection circuit 450 in the loopback circuit 430 through the transmitter 512 .

[0108] In the hidden training mode, the DLL circuit 520 can receive the second command / address CA2 through the first loopback pin 471 of the semiconductor storage device 201a and the first loopback pin 513 of the control device 500, and receive the second clock signal CK2 through the second loopback pin 472 of the semiconductor storage device 201a and the second loopback pin 514 of the control device 500.

[0109] The DLL circuit 520 detects a skew between the second command / address CA2 and the second clock signal CK2, and provides skew information SKWI about the detected skew to the delay circuit 550. The delay circuit 550 may adjust a delay amount of the first command / address CA1 based on the skew information SKWI, and provide the adjusted first command / address CA1 to the loopback circuit 430 through the transmitter 511.

[0110] In addition, the DLL circuit 520 may receive the first command / address CA1 and the first clock signal CK1 , and may store information about the center of the first command / address CA1 and the edge of the first clock signal CK1 .

[0111] The interface circuit 510 may receive the second command / address CA2 and the second clock signal CK2 from the loopback circuit 430 through the first loopback pin 513 and the second loopback pin 514 , respectively, in the hidden training mode.

[0112] In an exemplary embodiment of the inventive concept, the DLL circuit 520 may detect a skew by detecting a difference between an edge of the second clock signal CK2 and a center of the second command / address CA2 .

[0113] In an exemplary embodiment of the inventive concept, the interface circuit 510 may perform initial command / address training on the semiconductor memory device 201a to obtain initial skew information ISKWI based on the initial command / address training, and store the initial skew information ISKWI in the register 580. The delay circuit 550 may adjust the delay amount of the first command / address CA1 based on a comparison of the initial skew information ISKWI with the skew information SKWI.

[0114] In an exemplary embodiment of the inventive concept, the DLL circuit 520 may detect a skew between an edge of the first clock signal CK1 and an edge of the second clock signal CK2 , and may output skew information SKWI regarding the detected skew.

[0115] In an exemplary embodiment of the inventive concept, the DLL circuit 520 may detect a skew between the center of the first command / address CA1 and the center of the second command / address CA2 and may output skew information SKWI regarding the detected skew.

[0116] Fig. 9 An exemplary embodiment according to the present inventive concept is shown. Figure 8 Registers in the interface circuit.

[0117] refer to Figure 8 and Fig. 9 , the control device 500 may perform initial command / address training on each of the semiconductor storage devices 201a-201e, 202a-202e, 203a-203e, and 204a-204e to obtain initial skew information ISKWI1-ISKWIS respectively associated with the semiconductor storage device identifiers MD1-MDS based on the initial command / address training, and store the initial skew information ISKWI1-ISKWIS respectively associated with the semiconductor storage device identifiers MD1-MDS in the register 580. The semiconductor storage device identifiers MD1-MDS may correspond to the semiconductor storage devices 201a-201e, 202a-202e, 203a-203e, and 204a-204e, respectively.

[0118] Fig.10 is a diagram showing an exemplary embodiment according to the inventive concept Figure 8 The timing diagram of the operation of the DLL circuit.

[0119] refer to Figure 8 and Fig.10 The DLL circuit 520 may detect a skew between an edge of the second clock signal CK2 and a center of the second command / address CA2, and may provide skew information SKWI1 regarding the detected skew to the delay circuit 550.

[0120] Fig.11 is a diagram showing an exemplary embodiment according to the inventive concept Figure 8 The timing diagram of the operation of the DLL circuit.

[0121] refer to Figure 8 and Fig.11 The DLL circuit 520 may detect a skew between an edge of the first clock signal CK1 and an edge of the second clock signal CK2 and may provide skew information SKWI2 regarding the detected skew to the delay circuit 550 .

[0122] Fig.12 is a diagram showing an exemplary embodiment according to the inventive concept Figure 8 The timing diagram of the operation of the DLL circuit.

[0123] refer to Figure 8 and Fig.12 , the DLL circuit 520 may detect a skew between the center of the first command / address CA1 and the center of the second command / address CA2, and may provide skew information SKWI3 about the detected skew to the delay circuit 550. When the DLL circuit 520 detects the skew between the center of the first command / address CA1 and the center of the second command / address CA2, the first clock signal CK1 may be used as a reference signal.

[0124] The first clock signal CK1 and the second clock signal CK2 may be single-ended clock signals or differential clock signals. When the first clock signal CK1 and the second clock signal CK2 are differential clock signals, the edges of the first clock signal CK1 and the second clock signal CK2 may be detected based on the crossing point of the clock signal pair.

[0125] Fig.13 An exemplary embodiment according to the present inventive concept is shown. Figure 2 part of the storage module.

[0126] refer to Fig.13 , the control device 500 can be connected to the semiconductor storage devices 201a-201e and 202a-202e through the first loopback channel LBC1 and the second loopback channel LBC2. In addition, the control device 500 can be connected to the semiconductor storage devices 203a-203e and 204a-204e through corresponding loopback channels (for example, the third loopback channel and the fourth loopback channel).

[0127] Fig.14 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 Block diagram of the storage module in .

[0128] Fig.14The storage module 100a and Figure 2 The difference of the memory module 100 is that the memory module 100a does not include a data buffer for receiving / sending data signals DQ and data strobe signals DQS from / to a plurality of semiconductor memory devices 201a-201e, 202a-202e, 203a-203e, and 204a-204e, respectively. The memory module 100a can receive / send data signals DQ and data strobe signals DQS from / to the memory controller 25 through the control device 500.

[0129] Although Fig.14 , the PMIC 185 is illustrated as being disposed adjacent to the second edge portion 105 , but in an exemplary embodiment of the inventive concept, the PMIC 185 may be disposed in a central portion of the circuit board 101 to be adjacent to the control device 500 .

[0130] In the hidden training mode, the control device 500 can perform command / address training on the at least one semiconductor storage device in real time by sending a first command / address and a first clock signal to at least one semiconductor storage device among a plurality of semiconductor storage devices 201a~201e, 202a~202e, 203a~203e and 204a~204e, receiving a second command / address and a second clock signal in response to the first command / address and the first clock signal from the at least one semiconductor storage device, and detecting a time lag between the second command / address and the second clock signal to adjust the delay amount of the first command / address.

[0131] Fig.15 is a flowchart illustrating a method of operating a memory module according to an exemplary embodiment of the inventive concept.

[0132] refer to Figures 2 to 15 In a method of operating a storage module 100, wherein the storage module 100 includes a plurality of semiconductor storage devices 200 mounted on a circuit board 101 and a control device 500 that controls the plurality of semiconductor storage devices 200, the control device 500 performs initial command / address training on each of the plurality of semiconductor storage devices 200 in an initial training mode (S210).

[0133] The control device 500 stores initial skew information regarding a skew between a command / address and a clock signal associated with each semiconductor memory device 200 in the register 580 based on the result of the initial training (S220).

[0134] The control device 500 controls the semiconductor memory device 200 so that the semiconductor memory device 200 performs a normal operation ( S230 ).

[0135] The control device 500 determines whether at least one of the semiconductor memory devices 200 enters a hidden training mode during a normal operation ( S235 ).

[0136] For example, at least one semiconductor memory device among the semiconductor memory devices 200 that exits the self-refresh mode may enter the hidden training mode.

[0137] When no semiconductor memory device 200 enters the hidden training mode (No in S235 ), the process returns to operation S230 .

[0138] When at least one of the semiconductor storage devices 200 enters the hidden training mode (yes in S235), at least one semiconductor storage device entering the hidden training mode sends a command / address and a clock signal to the control device 500 through the first loopback pin and the second loopback pin (or through the loopback channel) respectively (S240).

[0139] The interface circuit 510 in the control device 500 determines the time skew between the command / address and the clock signal, and compares the determined time skew with the initial time skew determined in the initial training (S250).

[0140] The interface circuit 510 in the control device 500 adjusts the delay amount of the command / address based on the comparison, and transmits the adjusted command / address to the at least one semiconductor memory device (S260).

[0141] The interface circuit 510 in the control device 500 receives the adjusted command / address and clock signals from the at least one semiconductor memory device and determines whether the skew is adjusted (S270).

[0142] When the hysteresis is not adjusted (NO in S270), the process returns to operation S260.

[0143] When the time lag is adjusted (Yes in S270 ), the control device 500 ends the hidden training mode ( S280 ).

[0144] Fig.16 is a flowchart illustrating a method of operating a memory module according to an exemplary embodiment of the inventive concept.

[0145] refer to Figures 2 to 14 and Fig.16In a method of operating a storage module 100, wherein the storage module 100 includes a plurality of semiconductor storage devices 200 mounted on a circuit board 101 and a control device 500 for controlling the plurality of semiconductor storage devices 200, the control device 500 performs initial command / address training on each of the plurality of semiconductor storage devices 200 in an initial training mode to store initial skew information about a skew between a command / address and a clock signal associated with each semiconductor storage device 200 in a register 580 (S310).

[0146] The control device 500 controls the semiconductor memory device 200 so that the semiconductor memory device 200 performs a normal operation ( S320 ).

[0147] The control device 500 determines whether at least one of the semiconductor memory devices 200 enters a hidden training mode during a normal operation ( S330 ).

[0148] When no semiconductor memory device 200 enters the hidden training mode (No in S330 ), the process returns to operation S320 .

[0149] When at least one semiconductor memory device of the semiconductor memory device 200 enters the hidden training mode (Yes in S330), the interface circuit 510 in the control device 500 receives a command / address and a clock signal from the at least one semiconductor memory device and adjusts the time lag between the command / address and the clock signal (S340).

[0150] The at least one semiconductor memory device performs a normal operation based on the adjusted time lag under the control of the control device 500 ( S350 ).

[0151] Fig.17 is a block diagram illustrating a memory system having a quad-rank memory module according to an exemplary embodiment of the inventive concept.

[0152] refer to Fig.17 , the storage system 700 may include a storage controller 710 and at least one or more storage modules 720 and 730 .

[0153] The storage controller 710 may control the storage module to execute a command provided from a processor or a host. The storage controller 710 may be implemented in a processor or a host, or may be implemented using an application processor or a system on chip (SOC). For signal integrity, a resistor RTT of the storage controller 710 on the bus 740 may be used to implement a source terminal. The resistor RTT may be connected to a power supply voltage VDDQ. The storage controller 710 may include a transmitter 711 and a receiver 713, the transmitter 711 being used to send a signal to at least one or more storage modules 720 and 730, and the receiver 713 being used to receive a signal from at least one or more storage modules 720 and 730.

[0154] At least one or more storage modules 720 and 730 may be referred to as a first storage module 720 and a second storage module 730. The first storage module 720 and the second storage module 730 may be coupled to the storage controller 710 via a bus 740. The first storage module 720 and the second storage module 730 may each correspond to Figure 2 The storage module 100 or Fig.14 The first storage module 720 may include one or more storage blocks RK1 and RK2, and the second storage module 730 may include one or more storage blocks RK3 and RK4.

[0155] The first storage module 720 and the second storage module 730 may each include Figure 8 The control device can autonomously and in real time perform command / address training on at least one of the plurality of storage devices mounted on the circuit board in a hidden training mode through a loopback channel during normal operation to adjust the time lag between the command / address and the clock signal. Therefore, both the first storage module 720 and the second storage module 730 can enhance performance by improving the timing margin in the normal mode without intervention of the storage controller 710.

[0156] Fig.18 is a block diagram illustrating a mobile system including a storage module according to an exemplary embodiment of the inventive concept.

[0157] refer to Fig.18 , the mobile system 900 may include an application processor (AP) 910, a connection module 920, a memory module (MM) 950, a non-volatile memory device (NVM) 940, a user interface 930, and a power supply 970. The application processor 910 may include a memory controller (MCT) 911.

[0158] The application processor 910 may execute applications such as a web browser, a game application, a video player, etc. The connection module 920 may perform wired or wireless communication with an external device.

[0159] The storage module 950 may store data processed by the application processor 910 or be used as a working memory. The storage module 950 may include a plurality of semiconductor memory devices (MDs) 951 to 95q (where q is a natural number greater than 3) and a control device 961. The control device 961 may include Figure 8 The interface circuit 510 in the embodiment of the present invention can autonomously and in real time perform command / address training on at least one storage device among a plurality of storage devices mounted on a circuit board in a hidden training mode through a loopback channel during normal operation to adjust the time lag between the command / address and the clock signal.

[0160] The nonvolatile memory device 940 may store a boot image for booting the mobile system 900. The user interface 930 may include at least one input device such as a keypad, a touch screen, etc., and at least one output device such as a speaker, a display device, etc. The power supply 970 may provide an operating voltage to the mobile system 900.

[0161] In exemplary embodiments of the inventive concept, the mobile system 900 and / or components of the mobile system 900 may be packaged in various forms.

[0162] The inventive concept as described above may be applied to a system using a memory module.

[0163] Therefore, in a memory module including a plurality of semiconductor memory devices and a control device for controlling the plurality of semiconductor memory devices, the control device can autonomously and in real time perform command / address training on at least one of the plurality of semiconductor memory devices in a hidden training mode during normal operation to adjust the time lag between the command / address and the clock signal. Therefore, the memory module can have enhanced performance.

[0164] While the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without substantially departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A storage module, comprising: a plurality of semiconductor memory devices, the plurality of semiconductor memory devices being mounted on a circuit board, at least one semiconductor memory device of the plurality of semiconductor memory devices comprising a loopback circuit, the loopback circuit comprising a first selection circuit and a second selection circuit; as well as a control device mounted on the circuit board and configured to receive a command, an address, and a clock signal from an external device and provide the command, the address, and the clock signal to the plurality of semiconductor memory devices, The control device is configured to perform command / address training on the at least one semiconductor memory device in a hidden training mode during normal operation by: sending a first command / address and a first clock signal to the at least one semiconductor memory device, and receiving a second command / address and a second clock signal in response to the first command / address and the first clock signal from the at least one semiconductor memory device, and The first selection circuit is configured to select one of the first command / address and data signals in response to a selection signal, and the second selection circuit is configured to select one of the first clock signal and a data strobe signal in response to the selection signal.

2. The storage module according to claim 1, wherein: The at least one semiconductor storage device is configured to, under the control of the control device, send the second command / address and the second clock signal to the control device through a first loopback pin and a second loopback pin, respectively, in the hidden training mode.

3. The storage module according to claim 2, wherein: The loopback circuit also includes: a first transmitter coupled to the first selection circuit and the first loopback pin; and A second transmitter is coupled to the second selection circuit and the second loopback pin.

4. The storage module according to claim 3, wherein: In the hidden training mode, The first selection circuit is configured to select the first command / address in response to the selection signal to provide the first command / address to the first transmitter, and The second selection circuit is configured to select the first clock signal in response to the selection signal to provide the first clock signal to the second transmitter.

5. The storage module according to claim 3, wherein: The first selection circuit includes a first switch having a first terminal configured to receive the first command / address, a second terminal configured to receive the data signal, and a third terminal coupled to the first transmitter, and The second selection circuit includes a second switch having a first terminal configured to receive the first clock signal, a second terminal configured to receive the data strobe signal, and a third terminal coupled to the second transmitter.

6. The storage module according to claim 3, wherein: The first selection circuit includes a first multiplexer having a first input terminal configured to receive the first command / address, a second input terminal configured to receive the data signal, an output terminal coupled to the first transmitter, and a control terminal configured to receive the selection signal, and The second selection circuit includes a second multiplexer having a first input terminal configured to receive the first clock signal, a second input terminal configured to receive the data select signal, an output terminal coupled to the second transmitter, and a control terminal configured to receive the selection signal.

7. The storage module according to claim 1, wherein: The control device comprises an interface circuit, The interface circuit is configured to perform the command / address training in the hidden training mode by the following operations: receiving the second command / address and the second clock signal; detecting a skew between the second command / address and the second clock signal; and Based on the detected skew, adjusting the delay of the first command / address, and The interface circuit is configured to detect the skew by detecting a difference between an edge of the second clock signal and a center of the second command / address.

8. The storage module according to claim 7, wherein: The interface circuit comprises: a delay locked loop circuit configured to receive the second command / address and the second clock signal, detect the skew between the second command / address and the second clock signal, and output skew information about the detected skew in the hidden training mode; and A delay circuit is configured to adjust an amount of delay of the first command / address based on the skew information to output an adjusted command / address.

9. The storage module according to claim 8, wherein: The delay locked loop circuit is configured to receive the second command / address and the second clock signal from the at least one semiconductor memory device through a first loopback pin and a second loopback pin, respectively, in the hidden training mode.

10. The storage module according to claim 8, wherein: The interface circuit is configured to perform initial command / address training on the at least one semiconductor memory device to obtain initial skew information based on the initial command / address training, The interface circuit further includes a register configured to store the initial skew information, and The delay circuit is configured to adjust an amount of delay of the first command / address based on a comparison of the initial skew information and the skew information.

11. The storage module according to claim 1, wherein: The control device comprises an interface circuit, and The interface circuit is configured to perform the command / address training in the hidden training mode by the following operations: receiving the second command / address and the second clock signal; detecting a time skew between an edge of the first clock signal and an edge of the second clock signal; and Based on the detected skew, a delay of the first command / address is adjusted.

12. The storage module according to claim 11, wherein: The interface circuit comprises: a delay locked loop circuit configured to, in the hidden training mode, receive the second command / address and the second clock signal, detect the skew between an edge of the first clock signal and an edge of the second clock signal, and output skew information about the detected skew; and A delay circuit is configured to adjust an amount of delay of the first command / address based on the skew information to output an adjusted command / address.

13. The storage module according to claim 1, wherein: The control device comprises an interface circuit, The interface circuit is configured to perform the command / address training in the hidden training mode by the following operations: receiving the second command / address and the second clock signal; detecting a time lag between the first command / address and the second command / address; and Based on the detected skew, adjusting the delay of the first command / address, and Wherein, the interface circuit is configured to detect the time skew by detecting a difference between a center of the first command / address and a center of the second command / address.

14. The storage module according to claim 13, wherein: The interface circuit comprises: a delay locked loop circuit configured to receive the second command / address and the second clock signal in the hidden training mode, detect the skew between the center of the first command / address and the center of the second command / address, and output skew information about the detected skew; and A delay circuit is configured to adjust an amount of delay of the first command / address based on the skew information to output an adjusted command / address.

15. The storage module according to claim 1, wherein: The at least one semiconductor memory device includes a memory cell array including a plurality of dynamic memory cells coupled to a plurality of word lines and a plurality of bit lines, and The control device is configured to control the at least one semiconductor memory device so that after the at least one semiconductor memory device performs a refresh operation on the plurality of dynamic memory cells, the at least one semiconductor memory device enters the hidden training mode.

16. The storage module according to claim 1, further comprising: a power management integrated circuit, the power management integrated circuit being mounted on the circuit board, The power management integrated circuit is configured to generate a power supply voltage based on an input voltage and provide the power supply voltage to the plurality of semiconductor memory devices.

17. The storage module according to claim 1, wherein: Each of the plurality of semiconductor memory devices is a synchronous memory device, The synchronous storage device comprises a first loopback pin and a second loopback pin, The first loopback pin is configured to send a data signal to the control device in an operation mode different from the hidden training mode, The second loopback pin is configured to send a data strobe signal to the control device in the operating mode different from the hidden training mode, and The synchronous memory device performs the command / address training using the first loopback pin and the second loopback pin in the hidden training mode.

18. A storage system comprising: a storage module including a plurality of semiconductor storage devices and a control device configured to control the plurality of semiconductor storage devices, wherein the plurality of semiconductor storage devices and the control device are mounted on a circuit board; and a storage controller configured to control the storage module, wherein the control device is configured to receive a command, an address, and a clock signal from the storage controller, and provide the command, the address, and the clock signal to the plurality of semiconductor storage devices, wherein the control device is configured to perform command / address training on at least one semiconductor memory device among the plurality of semiconductor memory devices in a hidden training mode during normal operation by: sending a first command / address and a first clock signal to the at least one semiconductor memory device, and receiving a second command / address and a second clock signal in response to the first command / address and the first clock signal from the at least one semiconductor memory device, and Wherein, the at least one semiconductor storage device includes a loopback circuit, the loopback circuit includes a first selection circuit and a second selection circuit, the first selection circuit is configured to select one of the first command / address and data signals in response to a selection signal, and the second selection circuit is configured to select one of the first clock signal and data selection signal in response to the selection signal.

19. The storage system according to claim 18, wherein: The at least one semiconductor storage device is configured to, under the control of the control device, send the second command / address and the second clock signal to the control device through a first loopback pin and a second loopback pin, respectively, in the hidden training mode.

20. A method of operating a storage module, wherein: The storage module includes a plurality of semiconductor storage devices and a control device, the control device is configured to control the plurality of semiconductor storage devices, and the plurality of semiconductor storage devices and the control device are mounted on a circuit board, the method includes: In an initial training mode of the memory module, the control device performs initial command / address training on each of the plurality of semiconductor memory devices to store initial skew information about a skew between a command / address and a clock signal associated with each of the plurality of semiconductor memory devices in a register in the control device; performing a normal operation in each of the plurality of semiconductor memory devices based on a corresponding data signal and a corresponding data strobe signal; determining, by the control device, whether at least one semiconductor memory device among the plurality of semiconductor memory devices enters a hidden training mode during the normal operation; receiving, by the at least one semiconductor memory device in the hidden training mode, a first command / address instead of the data signal and a first clock signal instead of the data strobe signal; Sending, by the at least one semiconductor memory device in the hidden training mode, a second command / address based on the first command / address and a second clock signal based on the first clock signal; adjusting, by the control device, a skew by receiving the second command / address and the second clock signal from the at least one semiconductor memory device in the hidden training mode; and The normal operation is performed by the at least one semiconductor memory device based on the adjusted time skew.

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