Chip packaging devices

Abstract

The present invention discloses a chip packaging device, comprising: a chip, a first photosensitive medium layer, and a first metal layer; the first photosensitive medium layer is located between the chip and the first metal layer; a first metal connection portion and a second metal connection portion are provided on the surface of the first metal layer close to the first photosensitive medium layer; the first photosensitive medium layer is provided with a first through hole and a second through hole, the first metal connection portion is connected to the positive electrode in the chip electrode through the first through hole, and the second metal connection portion is connected to the negative electrode in the chip electrode through the second through hole. The chip electrode is not connected to the substrate through solder paste, silver paste, etc., but is directly connected to the metal layer, and a photosensitive medium layer is provided in the gap area between the chip and the metal layer, and the photosensitive medium layer is an insulator, thereby reducing the possibility of short circuit of the chip electrode, thereby improving the stability, reliability, safety and service life of the chip packaging device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging device. Background Art

[0002] With the rapid development of the Light Emitting Diode (LED) industry, chip packaging devices have attracted more and more attention. When preparing chip packaging devices, it is usually necessary to package the chip.

[0003] Currently, multiple LED chips are placed on a carrier board, and the positive and negative electrodes of the LED chips are connected using solder paste, silver paste, etc.

[0004] However, when the positive and negative electrodes of the LED chip are connected with solder paste or silver paste, considering the fluidity of liquids such as solder paste and silver paste, the positive and negative electrodes of the LED chip may be short-circuited, thereby reducing the service life of the chip packaging device. Summary of the invention

[0005] The present invention provides a chip packaging device, in which the chip electrodes are not connected to the substrate through solder paste, silver paste, etc., but are directly connected to the metal layer, thereby reducing the possibility of short circuit of the chip electrodes, thereby improving the stability, reliability, safety and service life of the chip packaging device; the metal layer and the chip electrodes are connected through a photosensitive medium layer, so that the chip packaging device can achieve miniaturization accuracy.

[0006] In a first aspect, the present invention provides a chip packaging device, comprising: a chip, a first photosensitive medium layer, and a first metal layer;

[0007] The first photosensitive medium layer is located between the chip and the first metal layer;

[0008] A first metal connecting portion and a second metal connecting portion are provided on a surface of the first metal layer close to the first photosensitive medium layer;

[0009] The first photosensitive medium layer is provided with a first through hole and a second through hole, the first metal connection portion is connected to the positive electrode in the chip electrode through the first through hole, and the second metal connection portion is connected to the negative electrode in the chip electrode through the second through hole.

[0010] Preferably, the positive electrode and the negative electrode are located on a surface of the chip close to the first photosensitive medium layer;

[0011] Then, the first through hole close to the bottom of the chip is the positive electrode, and the second through hole close to the bottom of the chip is the negative electrode.

[0012] Preferably, it further comprises: a protective layer, wherein the protective layer is in contact with a surface of the chip away from the first photosensitive medium layer.

[0013] Preferably, the positive electrode and the negative electrode are opposite to each other, and the positive electrode is close to the first photosensitive medium layer;

[0014] The bottom of the first through hole is the positive electrode, and the second through hole is located between the chip and a chip adjacent to the chip;

[0015] The protective layer has a third through hole at the position of the second through hole, and has a fourth through hole at the position of the negative electrode;

[0016] The second metal connection portion is connected to the negative electrode through the second through hole, the third through hole, the fourth through hole.

[0017] Preferably, the positive electrode and the negative electrode are located on a surface of the chip away from the first photosensitive medium layer;

[0018] Then, the first through hole and the second through hole are located between the chip and a chip adjacent to the chip;

[0019] The protective layer has a fifth through hole at the position of the first through hole, a sixth through hole at the position of the second through hole, a seventh through hole at the positive electrode position, and an eighth through hole at the negative electrode position;

[0020] The first metal connection portion is connected to the positive electrode through the first through hole, the fifth through hole, the seventh through hole;

[0021] The second metal connection portion is connected to the negative electrode through the second through hole, the sixth through hole, the eighth through hole.

[0022] Preferably, it also includes: at least one second photosensitive medium layer and at least one second metal layer, the second metal layer and the second photosensitive medium layer are alternately stacked on the side of the first metal layer away from the chip, the first metal layer is in contact with the second photosensitive medium layer, the second photosensitive medium layer is located between two second metal layers, and each second metal layer is conductive.

[0023] Preferably, a ninth through hole is formed in the second photosensitive medium layer, and a metal protrusion is formed in the surface of the second metal layer close to the chip;

[0024] The metal protrusion is located in the ninth through hole;

[0025] The bottom of the metal protrusion is connected to the second metal layer close to the bottom of the metal protrusion.

[0026] Preferably, the first metal layer and the second metal layer are provided with metal pads corresponding to the chip electrodes.

[0027] Preferably, the metal pad corresponding to the positive electrode and the metal pad corresponding to the negative electrode in the chip electrode are located in different metal layers.

[0028] Preferably, the chip includes any one or more of an LED chip, a laser chip, and a sensor chip.

[0029] The present invention provides a chip packaging device, comprising: a chip, a first photosensitive medium layer, and a first metal layer; the first photosensitive medium layer is located between the chip and the first metal layer; a first metal connection portion and a second metal connection portion are provided on the surface of the first metal layer close to the first photosensitive medium layer; the first photosensitive medium layer is provided with a first through hole and a second through hole, the first metal connection portion is connected to the positive electrode in the chip electrode through the first through hole, and the second metal connection portion is connected to the negative electrode in the chip electrode through the second through hole. The chip electrode is not connected to the substrate through solder paste, silver paste, etc., but is directly connected to the metal layer, and a photosensitive medium layer is provided in the gap area between the chip and the metal layer, and the photosensitive medium layer is an insulator, thereby reducing the possibility of chip electrode short circuit, thereby improving the stability, reliability, safety and service life of the chip packaging device; the metal layer and the chip electrode are connected through the photosensitive medium layer, which can meet the requirements for miniaturized chip packaging, so that the chip packaging device can achieve miniaturized accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the existing technical solutions, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative labor.

[0031] Figure 1 A schematic structural diagram of a first chip packaging device provided by an embodiment of the present invention;

[0032] Figure 2 for Figure 1 A process flow chart of a first chip packaging device is provided;

[0033] Figure 3 A schematic structural diagram of a second chip packaging device provided by an embodiment of the present invention;

[0034] Figure 4 A schematic structural diagram of a third chip packaging device provided by an embodiment of the present invention;

[0035] Figure 5 A process flow chart of a third chip packaging device provided by an embodiment of the present invention;

[0036] Figure 6 A schematic structural diagram of a first photosensitive medium layer in a process flow diagram of a third chip packaging device provided in an embodiment of the present invention;

[0037] Figure 7 A schematic structural diagram of a protective layer in a process flow diagram of a third chip packaging device provided by an embodiment of the present invention;

[0038] Figure 8 A structural flow chart of a fourth chip packaging device provided by an embodiment of the present invention;

[0039] Fig. 9 A process flow chart of a fourth chip packaging device provided by an embodiment of the present invention;

[0040] Fig.10 A schematic structural diagram of a first photosensitive medium layer in a process flow diagram of a fourth chip packaging device provided in an embodiment of the present invention;

[0041] Fig.11 A schematic structural diagram of a protective layer in a process flow diagram of a fourth chip packaging device provided by an embodiment of the present invention;

[0042] Fig.12 A schematic structural diagram of a fifth chip packaging device provided by an embodiment of the present invention;

[0043] Fig.13 A process flow of the second photosensitive medium layer and the second metal layer in the fifth chip packaging device provided by an embodiment of the present invention;

[0044] Fig.14 A schematic structural diagram of a sixth chip packaging device provided by an embodiment of the present invention;

[0045] Fig.15 A schematic structural diagram of a seventh chip packaging device provided in one embodiment of the present invention.

[0046] Among them, the reference numerals in the figure are:

[0047] 1-chip; 11-chip electrode; 111-positive electrode; 112-negative electrode; 2-first photosensitive medium layer; 21-first through hole; 22-second through hole; 3-first metal layer; 31-first metal connection part; 32-second metal connection part; 4-second photosensitive medium layer; 41-ninth through hole; 5-second metal layer; 51-metal protrusion; 6-protective layer; 61-third through hole; 62-fourth through hole; 63-fifth through hole; 64-sixth through hole; 65-seventh through hole; 66-eighth through hole; 7-carrier; 101-first metal connector; 102-second metal connector; 103-third metal connector. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] It should be noted that when a component is referred to as being "fixed on" or "disposed on" another component, it may be directly or indirectly located on the other component. When a component is referred to as being "connected to" another component, it may be directly or indirectly connected to the other component. The directions or positions indicated by the terms "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the directions or positions shown in the accompanying drawings and are only for the convenience of description and cannot be understood as limitations on the present technical solution. The terms "first" and "second" are only used for the convenience of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. "Multiple" means two or more, unless otherwise clearly and specifically defined.

[0050] Please refer to Figure 1 to Figure 2 , an embodiment of the present invention provides a chip packaging device, a chip 1, a first photosensitive medium layer 2, a first metal layer 3;

[0051] The first photosensitive medium layer 2 is located between the chip 1 and the first metal layer 3;

[0052] A first metal connecting portion 31 and a second metal connecting portion 32 are provided on a surface of the first metal layer 3 close to the first photosensitive medium layer 2;

[0053] The first photosensitive medium layer 2 is provided with a first through hole 21 and a second through hole 22 , the first metal connection part 31 is connected to the positive electrode 111 in the chip electrode 11 through the first through hole 21 , and the second metal connection part 32 is connected to the negative electrode 112 in the chip electrode 11 through the second through hole 22 .

[0054] In this embodiment, a chip 1, a first photosensitive medium layer 2, and a first metal layer 3 are provided; the first photosensitive medium layer 2 is located between the chip 1 and the first metal layer 3; a first metal connection portion 31 and a second metal connection portion 32 are provided on the surface of the first metal layer 3 near the first photosensitive medium layer 2; the first photosensitive medium layer 2 is provided with a first through hole 21 and a second through hole 22, the first metal connection portion 31 is connected to the positive electrode 111 in the chip electrode 11 through the first through hole 21, and the second metal connection portion 32 is connected to the negative electrode 112 in the chip electrode 11 through the second through hole 22. The chip electrode 11 is not connected to the substrate through solder paste, silver paste, etc., but is directly connected to the metal layer, the first photosensitive medium layer 2 is provided in the gap area between the chip 1 and the first metal layer 3, and the first photosensitive medium layer 2 is an insulator, thereby reducing the possibility of short circuit of the chip electrode 11, thereby improving the stability, reliability, safety and service life of the chip packaging device; the connection between the first metal layer 3 and the chip electrode 11 through the first photosensitive medium layer 2 can meet the requirements for miniaturized chip packaging, so that the chip packaging device can achieve miniaturized accuracy.

[0055] It should be noted that there are multiple chips 1, and the number of chips 1 needs to be determined according to actual needs. This embodiment does not limit the number of chips 1. At the same time, this embodiment does not limit the size of the chip 1, and it can be a miniaturized chip 1.

[0056] It should also be noted that the first photosensitive medium layer 2 contacts the chip 1 area outside the light-emitting surface of the chip 1 and the surface of the chip electrode 11, thereby reducing the possibility of short-circuiting the chip electrode 11 and ensuring the stability, reliability, safety and service life of the chip packaging device. The first photosensitive medium layer 2 is filled with photosensitive medium material. The embodiment of the present invention does not limit the photosensitive medium material, and photoresist is preferred.

[0057] Specifically, the surface of the first metal layer 3 close to the first photosensitive medium layer 2 is provided with a first metal connection part 31 and a second metal connection part 32, and correspondingly, the first photosensitive medium layer 2 is provided with a first through hole 21 and a second through hole 22, the chip electrode 11 includes a positive electrode 111 and a negative electrode 112, the first metal connection part 31 is connected to the positive electrode 111 through the first through hole 21, and the second metal connection part 32 is connected to the negative electrode 112 through the second through hole 22, so that the surface of the first metal connection part 31 away from the first photosensitive medium layer 2 is connected to the positive electrode 111, and the surface of the second metal connection part 32 away from the first photosensitive medium layer 2 is connected to the negative electrode 112. Obviously, the surface of the first metal connection part 31 away from the first photosensitive medium layer 2 can also be connected to the negative electrode 112, and the surface of the second metal connection part 32 away from the first photosensitive medium layer 2 is connected to the positive electrode 111, and the first and second should not be used as the basis for connecting with the positive electrode 111 and the negative electrode 112.

[0058] It should be noted that the position of the first through hole 21 needs to be determined according to the position of the chip electrode 11. The embodiment of the present invention does not limit the shape of the first through hole 21, which is usually circular.

[0059] It should also be noted that when the required diameter of the first through hole 21 is smaller, the punching accuracy is higher, and the photosensitive medium layer is filled with photosensitive medium material. The embodiment of the present invention does not limit the photosensitive medium material, and the photosensitive medium material can meet the accuracy requirements for smaller sizes.

[0060] Obviously, the number of the first through holes 21 , the number of the second through holes 22 , the number of the first metal connection parts 31 , and the number of the second metal connection parts 32 are respectively the same as the number of the chips 1 .

[0061] In one embodiment of the present invention, chip 1 includes but is not limited to any one or more chips of LED chip, laser chip, sensor chip, preferably LED chip, LED chip includes but is not limited to purple chip, blue chip, red chip and green chip, to ensure that the chip packaging device can be applied to different business scenarios, for example, the chip packaging device can be a display screen, in which case chip 1 can include red chip, blue chip, green chip, and the red chip, blue chip and green chip form a pixel unit. The metal in the first metal layer 3 can conduct electricity, including but not limited to copper.

[0062] Please refer to Figure 1 and Figure 2 In one embodiment of the present invention, the positive electrode 111 and the negative electrode 112 are located on the surface of the chip 1 close to the first photosensitive medium layer 2;

[0063] Then, the first through hole 21 close to the bottom of the chip 1 is the positive electrode 111 , and the second through hole 22 close to the bottom of the chip 1 is the negative electrode 112 .

[0064] In this embodiment, for each chip 1, the first photosensitive medium layer 2 is provided with a first through hole 21 at the position of the positive electrode 111 in the chip electrode 11, and the first through hole 21 is close to the bottom of the chip 1 for the positive electrode 111; a second through hole 22 is provided at the position of the negative electrode 112 in the chip electrode 11, and the second through hole 22 is close to the bottom of the chip 1 for the negative electrode 112, so that the chip electrode 11 leaks out of the first photosensitive medium layer 2, so that the first metal connection part 31 is directly connected to the positive electrode 111 through the first through hole 21, and the second metal connection part 32 is directly connected to the negative electrode 112 through the second through hole 22, thereby ensuring the normal operation of the chip packaging device and reducing the possibility of short circuit of the chip electrode 11.

[0065] It should be noted that the surface contact between the first photosensitive medium layer 2 and the positive electrode 111 and the negative electrode 112 in the chip 1, as well as the side contact of the chip 1, reduces the possibility of short circuit of the chip electrode 11, ensures the normal operation of the chip packaging device, and improves the stability, reliability, safety and service life of the chip packaging device.

[0066] Specifically, the first metal connection part 31 and the second metal connection part 32 are both metal protrusions. The bottom area of ​​the first through hole 21 close to the chip 1 is not less than the surface area of ​​the positive electrode 111, and the bottom area of ​​the second through hole 22 close to the chip 1 is not less than the surface area of ​​the negative electrode 112, thereby ensuring the connection between the positive electrode 111 and the first metal connection part 31, and the negative electrode 112 and the second metal connection part 32, so that the chip packaging device works normally.

[0067] Please refer to Figure 2 , the manufacturing method of the chip packaging device of this embodiment is as follows:

[0068] Bond the chip 1 to the carrier 7, or directly obtain the carrier 7 bonded with the chip 1 made in the factory, and the opposite surface of the chip electrode 11 is in contact with the carrier 7;

[0069] A photosensitive medium material is coated on one side of the carrier board 7 to which a plurality of chips 1 are bonded, and the photosensitive medium material covers all the chips 1 to form a first photosensitive medium layer 2;

[0070] A mask is placed on the first photosensitive medium layer 2 to cover the non-electrode area of ​​the chip 1, and then exposure and development are performed, thereby opening a first through hole 21 and a second through hole 22 on the photosensitive medium layer 2 to expose the positive electrode 111 and the negative electrode 112 of all chips 1;

[0071] A metal such as copper is plated on the first photosensitive medium layer 2 to form a first metal layer 3. At this time, the first through hole 21 and the second through hole 22 are filled with metal, and the outer side of the first metal layer 3 is patterned to form metal pads corresponding to each positive electrode 111 and negative electrode 112;

[0072] The carrier board 7 is removed to form a chip packaging device.

[0073] Considering that the operation of opening holes through the photosensitive medium material is a chemical method, compared with the mechanical method, it is not limited by the size of the mechanical tool, and can improve the hole opening accuracy, that is, encapsulate the chip electrodes 11 of smaller size. At the same time, there is no need to align the chip 1, which can save manufacturing time and improve manufacturing efficiency.

[0074] The embodiment of the present invention does not limit the material of the carrier plate 7, and it can be glass, polyethylene terephthalate (PET), or membrane material (a material used in membrane structure engineering, a composite material consisting of a high-strength fabric substrate and a polymer coating).

[0075] Please refer to Figure 3 , Figure 4 , Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.14 and Fig.15 In one embodiment of the present invention, the present invention further includes: a protective layer 6 , wherein the protective layer 6 is in contact with a surface of the chip 1 away from the first photosensitive medium layer 2 .

[0076] In this embodiment, the chip packaging device further includes a protective layer 6, and the protective layer 6 contacts the surface of the chip 1 away from the first photosensitive medium layer 2. The protective layer 6 can protect the chip 1 to a certain extent, and improve the reliability, stability, safety and service life of the chip packaging device. In order to more effectively protect the chip 1 and reduce the possibility of damaging the chip 1 during use, and at the same time to meet the light emission requirements of the chip packaging device, the material of the protective layer 6 can specifically be any one or more of silica gel, epoxy resin, black glue, and ink. The embodiment of the present invention does not limit the shape of the surface of the protective layer 6 away from the chip 1. For example, it can be a curved surface to expand the light emission angle of the chip packaging device. The protective layer 6 needs to be determined according to the light emission requirements of the chip 1. For example, when the chip 1 is a red light chip, a blue light chip, or a green light chip, and the chip packaging device is a display screen, at this time, the material of the protective layer 6 should be transparent.

[0077] Please refer to Figures 8 to 11 In one embodiment of the present invention, the positive electrode 111 and the negative electrode 112 are opposite to each other, and the positive electrode 111 is close to the first photosensitive medium layer 2;

[0078] The bottom of the first through hole 21 is the positive electrode 111, and the second through hole 22 is located between the chip 1 and the chip 1 adjacent to the chip 1;

[0079] The protective layer 6 defines a third through hole 61 at the position of the second through hole 22 and defines a fourth through hole 62 at the position of the negative electrode 112;

[0080] The second metal connection portion 32 is connected to the negative electrode 112 through the second through hole 22 , the third through hole 61 , the fourth through hole 62 .

[0081] In this embodiment, for each chip 1, when the positive electrode 111 and the negative electrode 112 in the chip electrode 11 are opposite to each other, if the positive electrode 111 is close to the first photosensitive medium layer 2, the first through hole 21 opened in the protective layer 6 is close to the bottom of the chip 1 for the positive electrode 111, and the first metal connection part 31 is located in the first through hole 21, and the bottom of the first metal connection part 31 is connected to the positive electrode 111 of the first through hole 21 close to the bottom of the chip 1; the second through hole 22 is located between the chip 1 and the chip adjacent to the chip 1, and correspondingly, the protective layer 6 opens a third through hole 61 at the position of the second through hole 22, and the third through hole 61 is close to the bottom of the chip 1 for the second through hole 22, and opens a fourth through hole 62 at the position of the negative electrode 112, and the fourth through hole 62 is close to the bottom of the chip 1 for the negative electrode 112, and the second metal connection part 32 is connected to the negative electrode 112 through the second through hole 22, the third through hole 61, the fourth through hole 62 and the negative electrode 112.

[0082] Specifically, the first metal connection part 31 may be a metal protrusion 51; the second metal connection part 32 includes a first metal connection member 101, a second metal connection member 102, and a third metal connection member 103 connecting the first metal connection member 101 and the second metal connection member 102, the first metal connection member 101 is located in the connected first through hole 21 and the third through hole 61, the second metal connection member 102 is located in the fourth through hole 62, and is connected to the negative electrode 112. The third metal connection member 103 contacts the surface of the protective layer 6 away from the chip 1.

[0083] It should be noted that the bottom area of ​​the first through hole 21 close to the chip 1 is not less than the surface area of ​​the positive electrode 111 , and the bottom area of ​​the second through hole 22 close to the chip 1 is not less than the surface area of ​​the negative electrode 112 .

[0084] It should also be noted that there are multiple chips adjacent to chip 1. The embodiment of the present invention does not limit the number and position of the chips adjacent to chip 1, nor does it limit the position of the second through hole 22 between chip 1 and the chip connected to chip 1. The specific position needs to be determined in combination with the number of chips 1 and circuit routing requirements.

[0085] Please refer to Fig. 9 , the manufacturing method of the chip packaging device of this embodiment is as follows:

[0086] Bond the chip 1 to the carrier 7, or directly obtain the carrier 7 bonded with the chip 1 made in the factory, and the surface of the chip electrode 111 where the chip negative electrode 112 is located is in contact with the carrier 7;

[0087] A photosensitive medium material is coated on one side of the carrier board 7 where the chip 1 is bonded to form a first photosensitive medium layer 2;

[0088] A mask is placed on the first photosensitive medium layer 2 for exposure and development. For each chip 1, a first through hole 21 is opened to expose the negative electrode 112, and a second through hole 22 is opened between the chip 1 and the chip adjacent to the chip 1;

[0089] After a mask is covered on the first photosensitive medium layer 2, metal is plated to form a first metal layer 3, and patterning is performed on the outer side of the first metal layer 3 to form metal pads corresponding to each positive electrode 111 and negative electrode 112;

[0090] The carrier plate is removed, and a protective material is coated on the surface of the chip 1 away from the first photosensitive medium layer 2 to form a protective layer 6;

[0091] A third through hole 61 is formed at the position of the second through hole 22 on the protective layer 6 to allow the metal in the second through hole 22 to leak out, and a fourth through hole 62 is formed at the position of the negative electrode 112 to allow the negative electrode 112 to leak out;

[0092] A mask is placed on the protective layer 6 to cover the portion that does not require metal connection, and then metal is plated to form a chip packaging device.

[0093] Please refer to Figures 4 to 7 In one embodiment of the present invention, the positive electrode 111 and the negative electrode 112 are located on a surface of the chip 1 away from the first photosensitive medium layer 2;

[0094] Then, the first through hole 21 and the second through hole 22 are located between the chip 1 and a chip 1 adjacent to the chip 1;

[0095] The protective layer 6 defines a fifth through hole 64 at the position of the first through hole 21 , defines a sixth through hole 64 at the position of the second through hole 22 , defines a seventh through hole 65 at the position of the positive electrode 111 , and defines an eighth through hole 66 at the position of the negative electrode 112 ;

[0096] The first metal connection portion 31 is connected to the positive electrode 111 through the first through hole 21, the fifth through hole 64, the seventh through hole 65;

[0097] The second metal connection portion 32 is connected to the negative electrode 112 through the second through hole 22 , the sixth through hole 64 , the eighth through hole 66 .

[0098] In this embodiment, for each chip 1, when the positive electrode 111 and the negative electrode 112 are both located on the surface of the chip 1 away from the first photosensitive medium layer 2, at this time, the first through hole 21 and the second through hole 22 are located between the chip 1 and the chip adjacent to the chip 1, and the protective layer 6 opens a fifth through hole 64 at the position of the first through hole 21, and the fifth through hole 64 is close to the bottom of the chip 1 as the first through hole 21, that is, the first through hole 21 and the fifth through hole 64 are connected; and opens a sixth through hole 64 at the position of the second through hole 22, and the sixth through hole 64 is close to the bottom of the chip 1 as the second through hole 21. The hole 22, that is, the second through hole 22 and the sixth through hole 64 are connected; the seventh through hole 65 is opened at the position of the positive electrode 111, and the bottom of the seventh through hole 65 close to the chip 1 is the positive electrode 111; the eighth through hole 66 is opened at the position of the negative electrode 112, and the bottom of the eighth through hole 66 close to the chip 1 is the negative electrode 112; the first metal connection part 31 is connected to the positive electrode 111 through the first through hole 21, the fifth through hole 64, the seventh through hole 65; the first metal connection part 31 is connected to the negative electrode 112 through the second through hole 22, the sixth through hole 64, the eighth through hole 66.

[0099] Specifically, the second metal connection part 32 and the first metal connection part 31 have the same structure, both including a first metal connection part 101, a second metal connection part 102, and a third metal connection part 103 connecting the first metal connection part 101 and the second metal connection part 102. For the second metal connection part 32, the first metal connection part 101 is located in the connected first through hole 21 and the fifth through hole 64, and the second metal connection part 102 is located in the seventh through hole 65. For the second metal connection part 102, the first metal connection part 101 is located in the connected second through hole 22 and the sixth through hole 64, and the second metal connection part 102 is located in the eighth through hole 66 with the negative electrode 112 at the bottom.

[0100] Please refer to Figure 5 , the manufacturing method of the chip packaging device of this embodiment is as follows:

[0101] Bond the chip 1 to the carrier 7, or directly obtain the carrier 7 bonded with the chip 1 made in the factory, and make the surface opposite to the surface where the chip electrode 11 is located contact with the carrier 7;

[0102] A photosensitive medium material is coated on one side of the carrier board 7 where the chip 1 is bonded to form a first photosensitive medium layer 2;

[0103] A mask is placed on the first photosensitive medium layer 2 for exposure and development, and for each chip 1, a first through hole 21 and a second through hole 22 are opened between the chip 1 and the chip adjacent to the chip 1;

[0104] After a mask is covered on the first photosensitive medium layer 2, metal is plated to form a first metal layer 3, and patterning is performed on the outer side of the first metal layer 3 to form metal pads corresponding to each positive electrode 111 and negative electrode 112;

[0105] The carrier plate is removed, and a protective material is coated on the surface of the chip 1 away from the first photosensitive medium layer 2 to form a protective layer 6;

[0106] A fifth through hole 64 and a sixth through hole 64 are respectively formed at the positions of the first through hole 21 and the second through hole 22 on the protective layer 6 to allow metal in the first through hole 21 and the second through hole 22 to leak out, and a seventh through hole 65 and an eighth through hole 66 are respectively formed at the positions of the positive electrode 111 and the negative electrode 112 to allow the positive electrode 111 and the negative electrode 112 to leak out;

[0107] A mask is placed on the protective layer 6 to cover the area where metal connection is not required, and then metal is plated to form a chip packaging device.

[0108] Please refer to Fig.12 , Fig.14 and Fig.15 In one embodiment of the present invention, it also includes: at least one second photosensitive medium layer 4 and at least one second metal layer 5, the second metal layer 5 and the second photosensitive medium layer 4 are alternately stacked on the side of the first metal layer 3 away from the chip 1, the first metal layer 3 is in contact with the second photosensitive medium layer 4, the second photosensitive medium layer 4 is located between two second metal layers 5, and each second metal layer 5 is conductive.

[0109] In this embodiment, when the number of chips 1 is large, multiple metal layers are required to meet the needs of complex circuit routing. At this time, the chip packaging device also includes a plurality of second photosensitive medium layers 4 and a plurality of second metal layers 5. The second metal layers 5 and the second photosensitive medium layers 4 are alternately stacked on the side of the first metal layer 3 away from the chip 1. The surfaces of the first metal layer 3 and the second photosensitive medium layer 4 are in contact. The second photosensitive medium layer 4 is located between the two second metal layers 5. The second metal layers 5 are conductive to ensure that the circuit routing corresponding to the positive electrode 111 and the negative electrode 112 of the same chip 1 do not contact, thereby ensuring the normal operation of the chip packaging device.

[0110] Those skilled in the art should understand that the greater the number of chips 1, the more complex the circuit routing structure, and the greater the number of second metal layers 5, thereby reducing the possibility of short circuits between circuits, thereby ensuring the safety, stability, reliability and service life of the chip packaging device.

[0111] The number of the second photosensitive medium layer 4 and the second metal layer 5 are the same. The present invention does not limit the number of the second metal layer 5. The specific number needs to be determined according to the number of chips 1. For example, when there are 12 chips 1, the number of the second metal layer 5 can be 1; when there are 48 chips 1, the number of the second metal layer 5 can be 2; when there are 300 chips 1, the number of the second metal layer 5 can be 3; when there are 30,000 chips 1, the number of the second metal layer 5 can be 4.

[0112] Obviously, the metal in the first metal layer 3 and the second metal layer 5 is usually the same, that is, copper. The metal in the plurality of second metal layers 5 is usually the same, that is, copper.

[0113] In one embodiment of the present invention, the second photosensitive medium layer 4 is provided with a ninth through hole 41, and the surface of the second metal layer 5 close to the chip 1 is provided with a metal protrusion 51;

[0114] The metal protrusion 51 is located in the ninth through hole 41;

[0115] The bottom of the metal protrusion 51 is connected to the second metal layer 5 close to the bottom of the metal protrusion 51 .

[0116] In this embodiment, the second photosensitive medium layer 4 is provided with a ninth through hole 41, and the surface of the second metal layer 5 close to the chip 1 is provided with a metal protrusion 51, and the metal protrusion 51 is located in the ninth through hole 41, and the bottom of the metal protrusion 51 is connected to the second metal layer 5 close to the bottom of the metal protrusion 51, so that several second metal layers 5 are connected to each other, meeting the requirements of circuit routing, and the second photosensitive medium layer 4 is used to isolate several second metal layers 5, thereby avoiding contact between several second metal layers 5, reducing the possibility of short circuit of the chip electrode 11, so that complex circuits can be spatially arranged, thereby improving the safety and service life of the chip packaging device. The embodiment of the present invention does not limit the shape, number, position, etc. of the ninth through hole 41, which needs to be determined in combination with the actual circuit routing requirements. Obviously, the bottom of the ninth through hole 41 close to the chip 1 is the second metal layer 5.

[0117] It should be noted that the lines between the positive electrode 111 and the negative electrode 112 in the chip 1 do not cross, and the same electrodes in different chips 1 may cross. Fig.12 , Fig.14 and Fig.15 , the positive electrodes of the two chips 1 are on the same metal line of the second metal layer.

[0118] In one embodiment of the present invention, the first metal layer 3 and the second metal layer 5 are provided with metal pads corresponding to the chip electrodes 11 .

[0119] The metal pad is a basic component unit of the surface mount assembly, which is used to form a pad pattern to ensure the normal operation of the chip packaging device. In order to ensure that the circuit routing of the chip 1 can be arranged, the first metal layer 3 and the second metal layer 5 are provided with metal pads corresponding to the positive electrode 111 and the negative electrode 112.

[0120] Please refer to Fig.13 The manufacturing process of the second metal layer 5 and the second photosensitive medium layer 4 is as follows:

[0121] A photosensitive medium material is coated on the first metal layer 3 to form a second photosensitive medium layer 4, a mask is placed on the second photosensitive medium layer 4 to block unnecessary metal connection areas, and then exposure and development are performed, thereby opening a plurality of ninth through holes 41 on the second photosensitive medium layer 4 to expose the metal in the first metal layer 3 that needs to be routed;

[0122] After a mask is placed on the second photosensitive medium layer 4 to block the areas where metal connection is not required, metal, such as copper, is plated to form a second metal layer 5. At this time, metal is filled in the ninth through hole 41 to connect the first metal layer 3 and the second metal layer 5, and part of the metal is patterned as required to form metal pads corresponding to the positive electrode 111 and / or the negative electrode 112, and the circuit routing of multiple chips 1 is reasonably designed to ensure the normal operation of the chip packaging device.

[0123] The above operation is repeated until the number of second metal layers 5 meets the target value, and metal pads corresponding to the positive electrode 111 and / or the negative electrode 112 are arranged on the outermost second metal layer 5, thereby forming a chip packaging device.

[0124] In one embodiment of the present invention, the metal pad corresponding to the positive electrode 111 and the metal pad corresponding to the negative electrode 112 in the chip electrode 11 are located in different metal layers.

[0125] Please refer to Fig.12 , Fig.14 and Fig.15 In order to ensure the arrangement of the circuit wiring of the chip 1, the metal pad corresponding to the positive electrode 111 and the metal pad corresponding to the negative electrode 112 in the chip electrode 11 are located in different metal layers.

[0126] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip packaging device, characterized in that: include: Chip, a first photosensitive medium layer, and a first metal layer; The first photosensitive medium layer is located between the chip and the first metal layer; A first metal connecting portion and a second metal connecting portion are provided on a surface of the first metal layer close to the first photosensitive medium layer; The first photosensitive medium layer is provided with a first through hole and a second through hole, the first metal connection portion is connected to the positive electrode in the chip electrode through the first through hole, and the second metal connection portion is connected to the negative electrode in the chip electrode through the second through hole; The chip packaging device further includes: at least one second photosensitive medium layer and at least one second metal layer, wherein the second metal layer and the second photosensitive medium layer are alternately stacked on a side of the first metal layer away from the chip, the first metal layer is in contact with the second photosensitive medium layer, the second photosensitive medium layer is located between two second metal layers, and each of the second metal layers is conductive; The second photosensitive medium layer is provided with a ninth through hole, and the second metal layer is provided with a metal protrusion on a surface close to the chip; The metal protrusion is located in the ninth through hole; The connection between the bottom of the metal protrusion and a second metal layer close to the bottom of the metal protrusion; The first metal layer and the second metal layer are provided with metal pads corresponding to the positive electrode and the negative electrode of the chip electrode; The metal pad corresponding to the positive electrode and the metal pad corresponding to the negative electrode in the chip electrode are located in different metal layers.

2. The chip packaging device according to claim 1, characterized in that: The positive electrode and the negative electrode are located on the surface of the chip close to the first photosensitive medium layer; Then, the first through hole close to the bottom of the chip is the positive electrode, and the second through hole close to the bottom of the chip is the negative electrode.

3. The chip packaging device according to claim 1, characterized in that: Also includes: A protective layer is in contact with a surface of the chip away from the first photosensitive medium layer.

4. The chip packaging device according to claim 3, characterized in that: The positive electrode is opposite to the negative electrode, and the positive electrode is close to the first photosensitive medium layer; The bottom of the first through hole is the positive electrode, and the second through hole is located between the chip and a chip adjacent to the chip; The protective layer has a third through hole at the position of the second through hole, and has a fourth through hole at the position of the negative electrode; The second metal connection portion is connected to the negative electrode through the second through hole, the third through hole, the fourth through hole.

5. The chip packaging device according to claim 3, characterized in that: The positive electrode and the negative electrode are located on a surface of the chip away from the first photosensitive medium layer; Then, the first through hole and the second through hole are located between the chip and a chip adjacent to the chip; The protective layer has a fifth through hole at the position of the first through hole, a sixth through hole at the position of the second through hole, a seventh through hole at the positive electrode position, and an eighth through hole at the negative electrode position; The first metal connection portion is connected to the positive electrode through the first through hole, the fifth through hole, the seventh through hole; The second metal connection portion is connected to the negative electrode through the second through hole, the sixth through hole, the eighth through hole.

6. The chip packaging device according to claim 1, characterized in that: The chip includes any one or more of an LED chip, a laser chip, and a sensor chip.

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