Source / drain diffusion barrier for germanium NMOS transistors

Abstract

An integrated circuit transistor structure is disclosed that reduces n-type dopant diffusion, such as phosphorus or arsenic, from the source and drain regions of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intermediate diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide having a carbon concentration between 5% and 50% by atomic percentage. In some embodiments, the diffusion barrier layer may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier layer thickness in the 1-5 nanometer range.

Description

Technical Field

[0001] Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials such as silicon (Si), germanium (Ge), and silicon-germanium (SiGe). A field-effect transistor (FET) is a type of semiconductor device that includes three terminals: gate, source, and drain. FETs use an electric field applied by the gate to control the conductivity of a channel, through which charge carriers (e.g., electrons or holes) flow from source to drain. When the charge carriers are electrons, the FET is called an n-channel device, while when the charge carriers are holes, the FET is called a p-channel device. Standard dopants for Si, Ge, and SiGe include boron (B) for p-type (acceptor) dopants and phosphorus (P) or arsenic (As) for n-type (donor) dopants. Some FETs have a fourth terminal, called the body or substrate, which can be used to bias the transistor. Additionally, metal-oxide-semiconductor FETs (MOSFETs) include a gate dielectric between the gate and the channel. MOSFETs may also be referred to as metal-insulator-semiconductor FETs (MISFETs) or insulated-gate FETs (IGFETs). The complementary MOS (CMOS) structure uses a combination of p-channel MOSFETs (p-MOS) and n-channel MOSFETs (n-MOS) to implement logic gates and other digital circuits.

[0002] A FinFET is a MOSFET transistor built around a thin strip of semiconductor material (commonly called a fin). The conductive channel of a FinFET device is on the outer portion of the fin adjacent to the gate dielectric. Specifically, current flows along / inside the two sidewalls of the fin (the sides perpendicular to the substrate surface) and along the top of the fin (the sides parallel to the substrate surface). Because the conductive channel of this configuration is essentially in three different external planar regions along the fin, this FinFET design is sometimes called a tri-gate transistor. Other types of FinFET configurations are also available, such as the so-called dual-gate FinFET, in which the conductive channel is primarily located only along the two sidewalls of the fin (and not along the top of the fin). BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Features and advantages of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds and with reference to the drawings, wherein like numerals represent like parts.

[0004] Figures 1A-1BA method of forming an integrated circuit (IC) according to some embodiments of the present disclosure is shown, wherein the integrated circuit (IC) includes at least one germanium (Ge)-rich n-MOS transistor, which transistor employs one or more dopant diffusion barriers, particularly to help prevent source / drain dopants from diffusing into surrounding shallow trench isolation (STI) material.

[0005] Figures 2A-2N shows that according to some embodiments, Figures 1A-1B An example IC structure is formed during the method.

[0006] Figure 3 shows a method according to some embodiments Figure 2M Example cross-sectional view of plane AA in FIG.

[0007] Figure 4 Computing systems implemented using transistor devices and / or integrated circuit structures formed using the techniques disclosed herein are shown according to some embodiments of the present disclosure.

[0008] These and other features of the present embodiments will be better understood by reading the following detailed description in conjunction with the drawings described herein. In the accompanying drawings, each identical or nearly identical component shown in each of the figures may be represented by a similar number. For clarity, not every component is labeled in every figure. In addition, it will be appreciated that the drawings are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For example, although some of the drawings generally show straight lines, right angles, and smooth surfaces, actual implementations of the disclosed technology may be less than perfect straight lines and right angles, and certain features may have surface topography, or otherwise, are not smooth, given the practical limitations of the manufacturing process. Further, some features in the drawings may include patterning and / or hatching, which is provided only to help visually distinguish different features. In short, the drawings are provided only to show example structures.

[0009] Although the following detailed description will be made with reference to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure. DETAILED DESCRIPTION

[0010] An integrated circuit transistor structure is disclosed that reduces diffusion of n-type dopants, such as phosphorus or arsenic, from source and drain regions into adjacent shallow trench isolation (STI) regions during fabrication of an n-MOS device having a germanium-rich channel (e.g., a germanium concentration of 75% atomic concentration or greater, up to 100% atomic concentration). In an exemplary embodiment, the structure includes an intermediate diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier comprises silicon dioxide having a carbon concentration, on an atomic basis, of between 5 and 50%. In other embodiments, the diffusion barrier comprises at least one of silicon nitride, hafnium oxide, and aluminum oxide. In some embodiments, the diffusion barrier is deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers. Many configurations and process flows will be apparent in light of this disclosure.

[0011] General Overview

[0012] The fabrication of Ge-rich n-MOS transistors is generally impractical due to the difficulty in maintaining relatively high levels of n-type dopants in the source / drain regions of the transistor. This is primarily due to the physical properties of Ge, where typical n-type dopants (such as phosphorus and arsenic) readily diffuse from the Ge-rich source / drain regions under the high-temperature conditions associated with semiconductor manufacturing processes. For example, Ge-rich n-MOS devices are prone to overflow of n-type dopants from the S / D regions into the isolation trench material that separates and insulates adjacent transistors. This overflow is particularly problematic under the high-temperature conditions associated with semiconductor manufacturing processes. Due to the high energy barrier at the metal-semiconductor interface, the resulting transistor device may exhibit poor S / D contact resistance, a problem that cannot be overcome by tunneling due to the low dopant levels caused by dopant diffusion from the Ge material. This high S / D contact resistance can lead to significant performance degradation. These problems caused by dopant diffusion are further exacerbated as transistor devices are scaled down to include smaller critical dimensions (e.g., using technologies below 30 nm and beyond).

[0013] Therefore, and in accordance with many embodiments of the present disclosure, techniques are provided for forming a Ge-rich n-MOS transistor including one or more dopant diffusion barriers configured to separate a source / drain fin structure from a shallow trench isolation (STI) region, as will be described in more detail below. Based on the present disclosure, it will be understood that the introduction of one or more dopant diffusion barriers helps to inhibit the undesirable diffusion of dopants (e.g., P or As) into adjacent insulators or STI regions. The dopant diffusion barrier is configured as an insulator having good surface charge passivation properties and improved anti-diffusion properties. In some embodiments, the diffusion barrier (e.g., a layer of insulating material different from the STI region) may include: silicon dioxide (SiO2) having a carbon concentration between 5% and 50% by atomic percentage; silicon nitride; hafnium oxide or aluminum oxide, although other compositions are also possible.

[0014] Note that as used herein, "Ge-rich" includes Ge-containing hosts containing more than 50% Ge by atomic percentage, wherein Ge or Si 1-x Ge x (x>0.5) can be doped with any suitable material (single or multiple) and / or alloyed with other Group IV elements (e.g., up to 2% carbon and / or tin by atomic percentage). For example, in some embodiments, the Ge-rich material can be n-type doped, such as Ge:As, Ge:P, SiGe:P (greater than 50% Ge by atomic percentage), or SiGe:As (greater than 50% Ge by atomic percentage), to provide just a few examples. Furthermore, in some embodiments, the Ge-rich material can include alloys of carbon and / or tin, such as Ge:C, GeSn, SiGe:C, SiGeSn, GeSn:C, SiGeSn:C. It should also be noted that in some embodiments, the Ge-rich can include different Ge threshold concentrations (by atomic percentage), such as, for example, at least 55, 60, 65, 70, 75, 80, 85, 90, or 95%. For example, in some applications, it may be desirable to have an embodiment in which a Ge-rich channel region of a transistor includes at least 80% Ge by atomic percentage, or even a pure Ge channel, such as to achieve, for example, a desired charge carrier mobility. It should also be noted that the inclusion of a Ge-rich material in a given feature as described herein does not preclude the inclusion of materials other than Ge. For example, in some embodiments, a Ge-rich channel region may include a multilayer structure comprising at least one Ge-rich layer and at least one non-Ge-rich layer. However, in other embodiments, a Ge-rich feature has Ge-rich material substantially throughout the entirety of the feature. Furthermore, a Ge-rich channel region may include a gradation of Ge concentrations throughout at least a portion of the channel region, such that one or more portions of the channel region include a Ge concentration of less than 50% by atomic percentage, and may even include no Ge content at all.

[0015] Additionally, as used herein, a "Group IV semiconductor material" (or "Group IV material" or generally, "IV") includes at least one Group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and the like. Note that alloys of Group IV elements should not be confused with compounds of those elements. Thus, when carbon is alloyed with any other Group IV element, the resulting alloy will be represented herein as "X:C," where "X" is the Group IV element or alloy, and ":C" indicates the alloy is alloyed with carbon. For example, silicon alloyed with carbon may be referred to herein as Si:C (to avoid confusion with silicon carbide (SiC)), silicon germanium alloyed with carbon may be referred to herein as SiGe:C, germanium alloyed with carbon may be referred to herein as Ge:C (to avoid confusion with germanium carbide (GeC)), and so on. It should also be noted that the molecular ratios or atomic percentages of the elements included in the Group IV alloy may be adjusted as desired. It should also be noted that the use of "X:Z" herein refers to a doping relationship where "X" is an element or alloy doped with "Z," such as arsenic-doped silicon germanium represented by SiGe:As, or phosphorus-doped silicon germanium alloyed with carbon represented by SiGe:C:P, to provide just a few examples. Generally, when referring to a Group IV semiconductor material described herein (e.g., Si, SiGe, Ge, SiSn, SiGeSn, GeSn, Si:C, SiGe:C, Ge:C, SiSn:C, SiGeSn:C, GeSn:C), the Group IV semiconductor material has a single crystal (or single crystal) structure, unless otherwise indicated, such as, for example, as described herein, where polycrystalline silicon (or poly-Si) may be utilized.

[0016] In some embodiments, the technology can be used to benefit a wide range of transistor devices. For example, in some embodiments, the technology can be used to benefit one or more n-channel transistor devices (wherein the charge carriers are electrons), such as n-channel MOSFET (n-MOS) devices. In some embodiments, the technology described herein can be used to benefit complementary transistor circuits such as CMOS circuits, wherein the technology can be used to benefit one or more n-channel transistors (e.g., n-MOS devices) included in a given CMOS circuit. Further, in some embodiments, the technology described herein can be used to benefit transistors including a variety of transistor configurations (such as planar and non-planar positions), wherein the non-planar configuration can include a fin or FinFET configuration (e.g., dual gate or tri-gate), a gate-all-around (GAA) configuration (e.g., nanowire or nanoribbon), or some combination thereof, to provide just a few examples. Other example transistor devices that can benefit from the technology described herein include, for example, as few as single-electron quantum transistor devices.

[0017] As will be further appreciated, the Ge-rich n-MOS transistors provided herein that include one or more dopant diffusion barriers configured to separate the source / drain fin structure from the STI region may also be intermixed on the same substrate with other transistors having channel regions that do not contain any germanium, such as transistors having silicon channel regions, gallium arsenide channel regions, indium arsenide channel regions, gallium inarsenide channel regions, or some combination of channel regions having diverse compositions. Note also that some channel regions may be substrate native (i.e., fins formed from the substrate), while other channel regions may be epitaxially disposed on the substrate.

[0018] Note that, as used herein, the phrase “X includes at least one of A and B” means that X can include, for example, only A, only B, or both A and B. Thus, unless explicitly stated, X including at least one of A and B should not be construed as requiring each of A and B. For example, the phrase “X includes A and B” means that X explicitly includes both A and B. Furthermore, this is true for any number of items greater than two, where “at least one” of those items is included in X. For example, as used herein, the phrase “X includes at least one of A, B, and C” means that X can include: only A; only B; only C; only A and B (but not C); only A and C (but not B); only B and C (but not A); or each of A, B, and C. This is true even if any of A, B, or C happens to include multiple types or variations. For this reason, unless explicitly stated, X including at least one of A, B, and C should not be construed as requiring each of A, B, and C. For example, the phrase “X includes A, B, and C” means that X explicitly includes each of A, B, and C. Similarly, the expression “X included in at least one of A and B” means that X may be included in only A, only B, or both A and B, for example. The above discussion on “X includes at least one of A and B” also applies here, as will be understood.

[0019] The use of the techniques and structures provided herein can be detected using tools such as: electron microscopy including scanning / transmission electron microscopy (SEM / TEM); scanning transmission electron microscopy (STEM); nanobeam electron diffraction (NBD or NBED); and reflection electron microscopy (REM); compositional mapping; x-ray crystallography or diffraction (XRD); energy dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools can indicate an integrated circuit (IC) including at least one Ge-rich n-MOS transistor that includes one or more dopant diffusion barriers as described herein. For example, in some such embodiments, the technique can be detected by observing (e.g., by SEM / TEM) that SiO2 with carbon is present in the dopant diffusion barrier separating the S / D region from the STI region. In some embodiments, the techniques and structures described herein can be tested based on the benefits gained therefrom, such as by observing a Ge-rich n-MOS source / drain fin structure that does not exhibit reduced dopant (e.g., P or As) levels due to diffusion into adjacent STI regions due to the use of one or more dopant diffusion barriers as described herein (e.g., compared to a Ge-rich n-MOS transistor that does not employ the techniques described herein). Thus, in some embodiments, the techniques described herein can enable the formation of Ge-rich transistor devices with enhanced performance using sub-30 nm technologies and beyond, which can also be tested and measured. Many configurations and variations will be apparent in light of this disclosure.

[0020] Methodology and Architecture

[0021] Figure 1 (1A and 1B) shows a method 100 of forming an integrated circuit (IC) according to some embodiments of the present disclosure, wherein the integrated circuit (IC) includes at least one Ge-rich n-MOS transistor, which transistor employs one or more dopant diffusion barriers, specifically for preventing or otherwise inhibiting S / D dopants from diffusing into the insulator material of adjacent isolation regions or so-called STI regions. Figure 2A -N shows an example IC structure formed when performing method 100 of Figure 1 according to some embodiments. For ease of illustration, this document primarily depicts and describes the structure in the context of forming a fin or FinFET transistor configuration (e.g., a tri-gate transistor configuration). Figure 2A-N structure. However, in some embodiments, as can be understood based on the present disclosure, the technology can be used to form transistors of any suitable geometry or configuration. It should also be noted that these techniques and structures are depicted and described primarily in the context of forming metal oxide semiconductor field effect transistors (MOSFETs). However, unless otherwise indicated, it is not intended that the contents of the present disclosure be limited thereto. It should also be noted that method 100 includes a main path that illustrates a gate-last transistor manufacturing process flow that can be adopted according to some embodiments. However, in other embodiments, a gate-first process flow can be adopted instead, as will be described herein (and shown in FIG1 with an alternative gate-first process flow 100' indicator). In light of the present disclosure, many variations and configurations will be apparent.

[0022] According to some embodiments, the method 100 of FIG. 1 (now referring to Figure 1A ) includes patterning 102 a hard mask on a substrate, such as in Figure 2A A hard mask 210a is patterned on the substrate 200 to form Figure 2B 210b. In some embodiments, as will be apparent in light of this disclosure, the hard mask 210a can be deposited or otherwise formed on the substrate 200 using any suitable technique. For example, the hard mask 210a can be blanket deposited or otherwise grown on the substrate 200 using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), a spin-on process, and / or any other suitable process for forming the hard mask 210a on the substrate 200. In some cases, the top surface of the substrate 200 where the hard mask 210a is to be deposited can be treated (e.g., by chemical treatment, thermal treatment, etc.) prior to depositing the hard mask 210a material. After being blanket formed on the substrate 200, the hard mask 210a can then be patterned using any suitable technique, such as one or more photolithography and etching processes, for example, to produce the structure 210b. The hard mask 210a can include any suitable material, such as, for example, an oxide material, a nitride material, and / or any other suitable masking material. Specific oxide and nitride materials may include silicon oxide, titanium oxide, hafnium oxide, aluminum oxide, silicon nitride, and titanium nitride, to name a few. In some cases, the material of the hard mask 210 a may be selected based on the material of the substrate 200 , for example.

[0023] In some embodiments, substrate 200 may be: a bulk substrate comprising a Group IV semiconductor material (e.g., Si, Ge, SiGe), a Group III-V semiconductor material (e.g., GaAs, GaAsSb, GaAsIn), and / or any other suitable material (single or multiple) as will be apparent from this disclosure; an X-on-insulator (XOI) structure, wherein X is one of the aforementioned materials (e.g., Group IV and / or Group III-V semiconductor materials), and the insulator material is an oxide material, a dielectric material, or some other electrically insulating material, such that the XOI structure includes an electrically insulating material layer between two semiconductor layers; or some other suitable multilayer structure, wherein the top layer includes one of the aforementioned semiconductor materials (e.g., Group IV and / or Group III-V semiconductor materials). The use of "Group IV semiconductor material" (or "Group IV material" or generally "IV") herein includes at least one Group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and the like. As used herein, "Group III-V semiconductor material" (or "Group III-V material" or generally "III-V") includes at least one Group III element (e.g., aluminum, gallium, indium) and at least one Group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), and the like. Note that, for example, Group III may also be referred to as the boron group or IUPAC Group 13, Group IV may also be referred to as the carbon group or IUPAC Group 14, and Group V may also be referred to as the nitrogen group or IUPAC Group 15. In some embodiments, substrate 200 may include a Ge-rich material to be used in the channel region of one or more transistors.

[0024] In some embodiments, the substrate 200 may be doped with any suitable n-type and / or p-type dopant. For example, in the case of a Si substrate, the Si may be p-type doped using a suitable acceptor (e.g., boron) or n-type doped using a suitable donor (e.g., phosphorus, arsenic), to name a few example cases. However, in some embodiments, for example, the substrate 200 may be undoped / intrinsic or relatively minimally doped (such as including a dopant concentration of less than 1E16 atoms per cubic centimeter). In some embodiments, as will be apparent from this disclosure, the substrate 200 may include a surface crystal orientation described by a Miller index of (100), (110), or (111), or its equivalent. Although in this example embodiment, for ease of illustration, the substrate 200 is shown as having a thickness (dimension in the Y-axis direction) similar to the other layers shown in the subsequent structures, in some cases, the substrate 200 may be much thicker than the other layers, such as having a thickness in the range of, for example, 50 to 950 microns, or any other suitable thickness as will be apparent from this disclosure. In some embodiments, substrate 200 may be used for one or more other IC devices, such as various diodes (e.g., light emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various radio frequency (RF) devices, various sensors, or any other suitable semiconductor or IC device, depending on the end use or target application. Accordingly, in some embodiments, as will be apparent from this disclosure, the structures described herein may be included in system-on-chip (SoC) applications.

[0025] According to some embodiments, the method 100 of FIG. 1 continues with performing 104 a shallow trench recess (STR) etch to form a fin 202 from the substrate 200, thereby forming Figure 2CThe resulting example structure is shown. In some embodiments, the STR etch 104 used to form the trenches 215 and the fins 202 may include any suitable technique, such as, for example, various mask processes and wet and / or dry etching processes. In some cases, the STR etch 104 may be performed in situ / without air breaks, while in other cases, the STR etch 104 may be performed, for example, ex-situ. Based on the present disclosure, it will be understood that the trenches 215 may be formed to have varying widths (dimensions in the X-axis direction) and depths (dimensions in the Y-axis direction). For example, multiple hard mask patterning 102 and STR etching 104 processes may be performed to obtain varying depths in the trenches 215 between the fins 202. The fins 202 may be formed to have varying widths Fw (dimensions in the X-axis direction) and heights Fh (dimensions in the Y-axis direction). Note that although the hard mask structure 210b may still be present in some cases, Figure 2C , but this is not required, as they may have been consumed, for example, during the STR etch. It should also be noted that although fin 202 is shown as being relatively rectangular (with straight sides and a flat top) for ease of illustration, in reality, the fin may include a tapered profile where the top of the fin is narrower than the bottom of the fin (as seen in a cross-section perpendicular to the fin). In addition, the very top of the fin may be rounded rather than flat. Many other real-world geometries are also contemplated.

[0026] In some embodiments, the fin width Fw (the dimension in the horizontal or X-axis direction) can be in the range of, for example, 2-400 nm (or in a sub-range of 2-10, 2-20, 2-50, 2-100, 2-200, 4-10, 4-20, 4-50, 4-100, 4-200, 4-400, 5-20, 10-20, 10-50, 10-100, 10-200, 10-400, 50-100, 50-200, 50-400, 100-400 nm, or any other sub-range), or in any other suitable value or range as will be apparent from this disclosure. In some embodiments, the fin height Fh (the dimension along the vertical or Y-axis direction) can be, for example, in the range of 4-800 nm (or in sub-ranges of 4-10, 4-20, 4-50, 4-100, 4-200, 4-400, 10-20, 10-50, 10-80, 10-100, 10-200, 10-400, 10-800, 50-100, 50-200, 50-400, 50-800, 100-400, 100-800, 400-800 nm, or any other sub-range), or any other suitable value or range that will be apparent in light of this disclosure. In some embodiments, the fin height Fh can be at least 10, 25, 35, 50, 75, 100, 125, 150, 175, 200, 300, 400, 500, 600, 700, or 800 nm high, or any other desired height as will be apparent from this disclosure. In some embodiments, the ratio of the height to the width of the fin (Fh:Fw) can be greater than 1, such as greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, or 10, or greater than any other suitable threshold ratio as will be apparent from this disclosure. Note that for ease of illustration, in this example structure, the trench 215 and the fin 202 are both shown as having substantially the same size and shape; however, the present disclosure is not intended to be limited in this regard. For example, in some embodiments, the fin 202 can be formed to have varying heights Fh, varying widths Fw, varying starting points (or varying starting heights), varying shapes, and / or any other suitable variations as will be apparent from this disclosure. Furthermore, the grooves 215 may be formed to have varying depths, varying widths, varying starting points (or varying starting depths), varying shapes, and / or any other suitable variations that will be apparent in light of this disclosure. Figure 2C Four fins 202 are shown in the example structure of FIG. 1 , but it will be understood based on this disclosure that any number of fins may be formed, such as one, two, three, five, ten, hundreds, thousands, millions, etc.

[0027] According to some embodiments, the method 100 of FIG. 1 continues with depositing 106 a diffusion barrier 212 to form Figure 2D The dopant diffusion barrier 212 is configured to separate the source / drain fin structure 202 from the shallow trench isolation (STI) region 220, as described below. Based on the present disclosure, it will be understood that the introduction of one or more dopant diffusion barriers helps to inhibit n-type dopants or impurities (e.g., P or As) from the S / D region (to be created later) from undesirably diffusing into the adjacent insulator or STI region. The dopant diffusion barrier 212 is configured as an insulator having good surface charge passivation properties and improved anti-diffusion properties. In some embodiments, the diffusion barrier 212 includes SiO2 having a carbon concentration of between 5% and 50% by atomic percentage. In some embodiments, the diffusion barrier 212 may also or alternatively include silicon nitride, hafnium oxide, or aluminum oxide, however other compositions are also possible. In a more general sense, the diffusion barrier 212 can be any material or composition that inhibits the diffusion of S / D dopants into adjacent STI regions, particularly in the case of n-type Ge-rich channel devices.

[0028] Deposition 106 of diffusion barrier material 212 may include any suitable deposition technique, such as those described herein (e.g., CVD, ALD, PVD), or any other suitable deposition process. In some embodiments, the thickness of the deposited barrier layer 212 may be, for example, on the order of 2 nm (or in the range of 1-5 nm, although other suitable ranges will be apparent in light of this disclosure).

[0029] According to some embodiments, the method 100 of FIG. 1 continues with depositing 108 a shallow trench isolation (STI) material 220 to form Figure 2E The example resulting structure. The deposition 108 of the STI material 220 may include any suitable deposition technique, such as those described herein (e.g., CVD, ALD, PVD), or any other suitable deposition process. In some embodiments, the STI material 220 (which may be referred to as an STI layer or STI structure) may include any suitable electrically insulating material, such as one or more dielectrics, oxides (e.g., silicon dioxide), and / or nitrides (e.g., silicon nitride) materials. In some embodiments, the material of the STI layer 220 may be selected based on the material of the substrate 200. For example, in the case of a Si substrate, the STI material may be selected to be silicon dioxide or silicon nitride, to provide just some examples. According to some embodiments, the method 100 of FIG. 1 further continues with planarizing / polishing 110 the structure to form Figure 2FThe planarization and / or polishing process performed after forming the STI material 220 may include any suitable technique, such as, for example, a chemical mechanical planarization / polishing (CMP) process. Note that in this example embodiment, the hard mask 210b is removed by the planarization. In other embodiments, the hard mask 210b may be retained.

[0030] The method 100 of FIG1 continues by recessing 112 the native fin material 202. In embodiments where the fin 202 is removed and replaced with an alternative semiconductor material (eg, for use in a channel region of one or more transistor devices), Figure 2F The structure of makes this possible. For example, Figure 2F The structure continues to Figure 2G In the embodiment shown, a selective etching process may be used to recess or remove the fin 202 (e.g., for a given etchant, selectively remove the semiconductor material of the fin 202 relative to the insulator material of the STI layer 220) to form a fin-shaped trench 209 between the STI material 220, in which a replacement semiconductor material may be deposited / grown (e.g., using any suitable technique, such as CVD, metal-organic CVD (MOCVD), ALD, molecular beam epitaxy (MBE), PVD). The depth of the etch may vary from one embodiment to the next. In the embodiment shown, a portion of the native fin is retained to provide a base or fin stub 207 on which the replacement fin material may be deposited. In other embodiments, the native fin may be completely removed so as to be flush with the top surface of the substrate 200 without providing a base or fin stub, or even below the top surface of the substrate 200 to provide an inverted base or fin stub.

[0031] The method 100 of FIG1 continues with deposition 114 of a replacement semiconductor fin material. For example, Figure 2H Recessing and alternative processing to form alternative material fins 230 are shown in accordance with some embodiments. The alternative fins 230 (and generally, any alternative fins formed) may include any suitable semiconductor material (e.g., Group IV and / or III-V semiconductor materials), but at least some of the fins will be Ge-rich fins for n-type transistor devices. For example, alternative fins comprising SiGe or Ge may be formed by removing native Si fins during such processing and replacing them with SiGe or Ge material, to provide just some examples. Additionally, the alternative fins 230 may include any suitable n-type or p-type dopant, or be undoped or lightly doped. In some embodiments, alternative processing may be used to form the alternative material fins, such as Figure 2HFor example, to provide an example alternative, in some embodiments, the alternative material fin may be formed by blanket growing the alternative material on a substrate (e.g., using an epitaxial deposition process) and then patterning the alternative material into an alternative material fin. Note that the alternative fin 230 is shown with a pattern / shading to aid visual identification of the feature only. In any such case, the resulting structure may be planarized to provide a relatively flat top surface, such as Figure 2H Shown overall.

[0032] According to some embodiments, the method 100 of FIG. 1 continues with recessing 116 of the STI material 220 between the fins, as shown in FIG. Figure 2I As shown, at least a portion 231 of the fin 230 protrudes from the STI plane, thereby forming Figure 2I . The resulting example structure shown in . The recess 116 can be performed using any suitable technique, such as using one or more wet and / or dry etching processes that allow the STI material 220 to be recessed selectively relative to the material of the fin 230, and / or the recess can be performed using any other suitable process as will be apparent in light of this disclosure. As can be understood based on this disclosure, the exposed portion 231 of the fin 230 can be used to provide a channel region for one or more transistors, for example, such that the fin portion 231 (the portion of the fin 230 above the top plane of the STI layer 220 after the recess 116 has been performed) can be referred to herein as a channel portion. More specifically, the fin portion 231 to be subsequently formed under the gate structure is generally referred to as a channel portion, wherein the source and drain regions are to be formed on either side of the channel portion such that the channel is between the source and drain regions. Additionally, the portions of the fin 230 below the top plane of the STI layer 220 are represented as portions 232, where these portions can be referred to herein as, for example, sub-channel portions.

[0033] like Figure 2IAs shown, the portion 231 of the fin 230 that protrudes above the top surface of the STI layer 220 has a fin height, denoted as Fh, which can be, for example, in the range of 4-800 nm (e.g., in a sub-range of 4-10, 4-20, 4-50, 4-100, 4-200, 4-400, 10-20, 10-50, 10-80, 10-100, 10-200, 10-400, 10-800, 50-100, 50-200, 50-400, 50-800, 100-400, 100-800, 400-800 nm, or some other sub-range), or any other suitable value or range, as will be apparent in light of this disclosure. In some specific embodiments, the fin height Fh may be at least 10, 25, 35, 50, 75, 100, 125, 150, 175, 200, 300, 400, 500, 600, 700, or 800 nm. It should also be noted that in embodiments employing a planar transistor configuration, the recess process 116 need not be performed, as, for example, the fin height Fh may be at least 10, 25, 35, 50, 75, 100, 125, 150, 175, 200, 300, 400, 500, 600, 700, or 800 nm. Figure 2H The top surface of the semiconductor body 230 is used to form a transistor as shown in FIG.

[0034] Note that in Figure 2I In the example embodiment of FIG, all fins are shown as being replaced; however, the present disclosure is not intended to be limited thereto. In some embodiments, as Figure 2J As shown, only a subset may be replaced (eg, such that some replacement fins 230 are available for subsequent processing, while some native fins 202 remain for subsequent processing). Figure 2J 'This is shown in perspective.

[0035] Furthermore, in some embodiments, the recessing and replacing process can be performed as many times as desired to form as many subsets of replacement fins as desired by masking the areas not to be processed for each replacement fin subset processed. Figure 2K , where two different sets of replacement fins 230 and 240 are shown. In some such embodiments, a first subset of replacement fins can be formed for n-channel transistors (e.g., where a first replacement material is selected to increase electron mobility), and a second subset of replacement fins can be formed for p-channel transistors (e.g., where a second replacement material is selected to increase hole mobility). Thus, for example, some native fins 202 are removed and replaced with a first material 230 (e.g., a Ge-rich material), and other native fins 202 are removed and replaced with a second material 240 (e.g., a III-V material). Figure 2KThis is shown in perspective. Further still, in some embodiments, multiple layers of replacement fins may be formed to enable subsequent formation of nanowires or nanoribbons in the channel region of one or more transistors, where some layers of the multiple layers of the replacement fins are sacrificial and intended to be removed by selective etching (e.g., during a replacement gate process). It will be apparent that many such fin replacement schemes may be used.

[0036] According to some embodiments, the method 100 of FIG. 1 (now referring to Figure 1B ) is continued, and a dummy gate stack 118 is optionally formed to form Figure 2L 1 , the gate stack processing step 122 is performed, and the gate stack processing step 122 is performed. The gate stack processing step 122 is performed in the gate-first process flow. The gate stack processing step 122 is performed in the gate-last ...

[0037] Continuing with forming 118 a dummy gate stack, in this example embodiment, such a dummy gate stack (when employed) may include a dummy gate dielectric 242 and a dummy gate electrode 244, thereby forming Figure 2L, an example resulting structure. In this example embodiment, a dummy gate dielectric 242 (e.g., a dummy oxide material) and a dummy gate electrode 244 (e.g., a dummy polysilicon material) can be used in a replacement gate process. Note that gate spacers 250 are also formed on either side of the dummy gate stack, and such gate spacers 250 can be used, for example, to help determine the channel length and / or to help with replacement gate processing. As can be understood based on this disclosure, the dummy gate stack (and gate spacers 250) can help define the channel region and source / drain (S / D) regions of each transistor device, wherein the channel region is below the dummy gate stack (as it will be below the final gate stack), and the S / D regions are located on either side of the channel region and adjacent to the channel region. Note that because the IC structure is described in the context of forming a fin transistor, the final gate stack will also be adjacent to either side of the fin, because in embodiments employing a fin (e.g., FinFET) configuration, the gate stack will be along the top and opposite sidewalls of the fin channel region.

[0038] The formation of the dummy gate stack may include depositing a dummy gate dielectric material 242 and a dummy gate electrode material 244, patterning the dummy gate stack, depositing a gate spacer material 250, and performing a spacer etch to form, for example, Figure 2L The structure shown. The gate spacer 250 can include any suitable material, such as any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide) and / or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure. Note that in some embodiments, as previously described, the techniques described herein need not include forming a dummy gate stack, such that a final gate stack can be formed in the first instance. In any event, it will be apparent in light of this disclosure that the final structure will include the final gate stack. Note also that in some embodiments, a hard mask (which may or may not be formed above the gate spacer 250) can be formed over the dummy gate stack to, for example, protect the dummy gate stack during subsequent processing. Where employed, the previous description related to the hard mask 210 also applies to such hard mask features.

[0039] According to some embodiments, the method 100 of FIG. 1 continues with performing 120 source / drain (S / D) region processing to form Figure 2L In this example embodiment, the S / D region processing 120 may include an etch and replacement process in which portions of the replacement fins 230 are removed in the S / D region by selective etching (or any other suitable etching scheme), followed by epitaxial deposition of the desired S / D material, thereby forming a bulk S / D region 261, thereby producing Figure 2L' example structure. In some embodiments, the S / D regions 261 can be formed using any suitable technique, such as one or more deposition processes described herein (e.g., CVD, ALD, PVD, MBE), and / or any other suitable process that will be apparent in light of this disclosure. In some such embodiments, the S / D regions 261 can be formed using a selective deposition process, e.g., such that the material of the feature grows only or predominantly only from exposed semiconductor material (or only in a single crystal structure), as will be understood based on this disclosure. In other embodiments, the S / D regions 261 are implant-doped portions of the fins (202, 230, 240).

[0040] Note that for ease of description, the S / D regions 261 are referred to herein as such, but each S / D region can be a source region or a drain region, such that the corresponding S / D region (on the other side of the channel region, and therefore on the other side of the dummy gate stack) is the other of the source region and the drain region, thereby forming a source region and drain region pair. For example, Figure 2L As shown in FIG. 1 , there are four channel regions and four corresponding S / D region 261 pairs.

[0041] In some embodiments, as will be apparent from this disclosure, the S / D region 261 can comprise any suitable semiconductor material, such as a single crystal Group IV semiconductor material. For example, a given S / D region can comprise at least one of Si, Ge, Sn, and C. In some embodiments, a given S / D region may or may not include n-type and / or p-type dopants (such as in one of the approaches described herein). When present, the dopants can be included, for example, at a concentration ranging from 1E17 to 5E22 atoms per cubic centimeter or higher. In some embodiments, a given S / D region can include a gradation (e.g., increasing and / or decreasing) of the concentration of one or more materials within a feature, such as, for example, a gradation of semiconductor material component concentrations and / or a gradation of dopant concentrations. For example, in some such embodiments, the dopant concentration included in a given S / D region can be graded such that it is lower near the corresponding channel region and higher near the corresponding S / D contact. This can be achieved using any suitable process, such as adjusting the amount of dopant in the reactant stream (e.g., during an in-situ doping approach), for example only. In some embodiments, a given S / D region 261 may include a multilayer structure comprising at least two material layers of different compositions. For example, in the case of a Fermi field FET (FFFET) device, according to some embodiments, the source region may include a multilayer structure comprising a p-type doped region and an n-type doped region. In some embodiments, a given S / D region 261 may be elevated such that it extends higher than the corresponding channel region (e.g., in the vertical or Y-axis direction).

[0042] In some embodiments, the S / D regions 261 may have different shapes and configurations depending on the formation process used, as will be apparent from this disclosure. Figure 2L In the example structure of FIG. 2 , the S / D region includes a three-dimensional diamond shape, as shown, with two faceted top surfaces (e.g., {11 1) facets. According to some embodiments, other example structures may be formed, including rounded (or curved) and non-faceted tops, and the rounded or curved S / D region may extend across the underlying sub-fin portion in the X-axis direction. Based on this disclosure, it will be understood that S / D regions including any shape (such as the diamond or circle shape of S / D region 261) may benefit from the techniques described herein.

[0043] In some embodiments, the processing of one S / D region in a corresponding pair of S / D regions (such as region 261 on one side of the dummy gate stack) can be separated from the processing of the other S / D region in the pair (such as region 261 on the opposite side of the dummy gate stack) so that the corresponding S / D pairs can include different materials, dopant types, dopant concentrations, sizes, shapes, and / or any other suitable differences, as will be understood based on this disclosure. For example, in the case of a TFET device, to provide an exemplary embodiment, one of the S / D regions can include an n-type doped semiconductor material, while the other S / D region can include a p-type doped semiconductor material, so that the n-type S / D region can be processed separately from the p-type S / D region. The separate processing can be achieved using any suitable technique, such as masking the unprocessed S / D region to allow processing of the other S / D region, and then masking the other S / D region to allow processing of, for example, the initially masked S / D region. In some embodiments, a given S / D region can include the same or similar material composition (e.g., within 1% of each other) as the corresponding / adjacent channel region (e.g., both include the same Ge-rich material). However, in other embodiments, for example, a given S / D region may include a different material composition (eg, by at least 1, 2, 3, 4, 5, or 10%) relative to a corresponding / adjacent channel region.

[0044] According to some embodiments, the method 100 of FIG. 1 continues with performing 122 a final gate stack process to form Figure 2M The example structure obtained is Figure 2M As shown, the processing in this example embodiment includes Figure 2L An interlayer dielectric (ILD) layer 270 is deposited on the structure of ' and then planarized and / or polished (e.g., CMP) to expose the dummy gate stack. Note that the ILD layer 270 may include a multi-layer structure even though it is shown as a single layer. Also note that in some cases, the ILD layer 270 and the STI material 220 may not include Figure 2M The different interfaces shown are particularly advantageous when, for example, the ILD layer 270 and the STI material 220 comprise the same dielectric material (e.g., where both comprise silicon dioxide). In general, as will be apparent in light of this disclosure, the ILD layer 270 may comprise any desired electrical insulator, dielectric, oxide (e.g., silicon oxide), and / or nitride (e.g., silicon nitride) material.

[0045] In this example embodiment, the gate stack processing continues with the removal of the dummy gate stack (including the dummy gate 244 and the dummy gate dielectric 242) to allow for the formation of the final gate stack. Recall that in some embodiments, the formation of the final gate stack including the gate dielectric 282 and the gate electrode 284 may be performed using a gate-first process. In such embodiments, the final gate stack processing may alternatively be performed at block 118 rather than forming the dummy gate stack. However, in this example embodiment, the final gate stack is formed using a gate-last process (also referred to as a replacement gate or replacement metal gate (RMG) process). Regardless of whether a gate-first or gate-last process is employed, the final gate stack may include, for example, Figure 2M A gate dielectric 282 and a gate electrode 284 are shown and described herein.

[0046] Note that when the dummy gate is removed, the channel regions of the fin 202 (or alternative fins 230, 240) are exposed to allow for any desired processing of those channel regions, which are the portion of the fin covered by the dummy gate stack. Such processing of a given channel region may include a variety of different techniques, such as removing and replacing the channel region with a replacement material, doping the channel region as desired, forming the channel region into one or more nanowires (or nanoribbons) for a gate-all-around (GAA) transistor configuration, covering the channel region, cleaning / polishing the channel region, and / or any other suitable processing as will be apparent in light of this disclosure.

[0047] In some embodiments, a given channel region of a transistor device may include a single crystal Ge-rich Group IV semiconductor material, such as single crystal Ge or single crystal SiGe having more than 50% Ge by atomic percentage, and / or any other suitable material, as will be apparent in light of this disclosure. Typically, a given channel region may include at least one of silicon (Si) and germanium (Ge), to provide just a few examples. In some embodiments, the channel region may be lightly doped (e.g., with any suitable n-type and / or p-type dopant) or intrinsic / undoped (or nominally undoped, with a dopant concentration of less than 1E16 atoms per cubic centimeter), depending on the particular configuration. In some embodiments, a given channel region may include grading (e.g., increasing and / or decreasing) the concentration of one or more materials within a feature, such as, for example, grading of semiconductor material composition concentrations and / or grading of dopants. In some embodiments, a given channel region may include a multilayer structure comprising at least two layers of materials having different compositions. Based on this disclosure, it will be understood that in this example embodiment, the channel region is at least below the gate stack. For example, in the case of a fin transistor configuration, the channel region can be located below and between the gate stacks because the stacks are formed on the top and opposite sides of the semiconductor body or fin. However, if the transistor device is inverted and bonded to what will be the final substrate, the channel region can be above the gate. Therefore, typically, according to some embodiments, the gate structure and the channel region can include an approximate relationship, wherein the gate structure is near the channel region so that it can electrically exert control over the channel region. In addition, in the case of a nanowire (or nanoribbon or GAA) transistor configuration, the gate stack can completely surround each nanowire / nanoribbon in the channel region (or at least substantially surround each nanowire, such as at least 70, 80 or 90% of each nanowire). In addition, in the case of a planar transistor configuration, the gate stack can simply be above the channel region.

[0048] It is noted that the S / D regions 261 are adjacent to either side of the corresponding channel region, such as, for example Figure 2MAs shown. It should also be noted that the configuration / geometry of a transistor formed using the techniques described herein can be described primarily based on the shape of the various channel regions of the transistor. For example, a nanowire (or nanoribbon or GAA) transistor may be so called because it contains one or more nanowires (or nanoribbons) in the channel region of the transistor and because the gate stack (including the gate) wraps (or at least substantially wraps) each nanowire (or nanoribbon). However, transistor types (e.g., MOSFET, TFET, FFFET, or other suitable types) can be described based on the doping and / or operating scheme of the source, channel, and drain regions, so that, for example, those corresponding regions can be used to determine the type or classification of a given transistor. For example, MOSFET and TFET transistors may be very similar (or identical) in structure, but they include different doping schemes (e.g., a source-drain doping scheme for a pp or nn MOSFET versus a source-drain doping scheme for a pn or np MOSFET for a TFET).

[0049] According to some embodiments, final gate stack processing is continued 122, after the dummy gate is removed and any desired channel region processing has been performed, a final gate stack can then be formed. In this example embodiment, the final gate stack includes a gate dielectric 282 and a gate electrode 284, as shown in FIG. Figure 2MAs shown. Gate dielectric 282 can include any suitable dielectric (such as silicon dioxide and / or a high-k dielectric material), as will be apparent from this disclosure. Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to name a few. In some embodiments, gate dielectric 282 can include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and other transition metal silicates). In some embodiments, when a high-k dielectric material is used, an annealing process can be performed on gate dielectric 282 to improve its quality. Gate electrode 284 can include a wide range of materials, such as various suitable metals or metal alloys, such as, for example, aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), and their carbides and nitrides. In some embodiments, the gate dielectric 282 and / or gate electrode 284 may include a multilayer structure of, for example, two or more material layers. For example, in one embodiment, the gate dielectric includes a first layer of silicon dioxide on the channel region and a second layer of hafnium oxide on the first layer. The gate electrode may include, for example, a metal plug and one or more work function layers, resistance reducing layers, and / or barrier layers. In some embodiments, the gate dielectric 282 and / or gate electrode 284 may include grading (e.g., increasing and / or decreasing) the content / concentration of one or more materials in at least a portion of the feature(s). Note that although in Figure 2M In the example embodiment of FIG, gate dielectric 282 is shown only below gate electrode 284, but in other embodiments, gate dielectric 282 may also be present on one or both sides of gate electrode 284, e.g., such that gate dielectric 282 is u-shaped (cross-sectional profile) and may also be between gate electrode 284 and one or both of gate spacers 250. Many different gate stack configurations will be apparent in light of this disclosure.

[0050] According to some embodiments, the method 100 of FIG. 1 continues with performing 124 S / D contact processing to form Figure 2M In this example embodiment, the S / D contact process 124 first includes forming an S / D contact trench 290 above the S / D region 261, as shown in FIG. Figure 2MAs shown. In some such embodiments, the contact trench 290 can be formed using any suitable technique and / or any other suitable process as will be apparent in light of this disclosure, such as performing one or more wet and / or dry etching processes to remove portions of the ILD layer 270 as shown. Such an etching process may be referred to as an S / D contact trench etching process, or simply a contact trench etching process. Furthermore, in some such embodiments, for example, the ILD may be patterned first, such as to mask areas that are not removed by the contact trench etching process. In some embodiments, one or more etch stop layers may be formed on the S / D region 261 before performing the contact trench etching process to aid in process controllability (e.g., to help stop the etching to prevent the etching from undesirably consuming material from the S / D region 261). In some such embodiments, the etch stop layer (single or multiple layers) may include an insulator material that is dissimilar to the ILD 270 material (e.g., to provide relative etch selectivity) and / or a material that is resilient to the contact trench etching, such as a carbon-based etch stop layer (e.g., having a carbon concentration in the range of 1-80%).

[0051] According to some embodiments, Figure 2M The example structure continues with the contact process 124 by forming S / D contacts 291 over corresponding S / D regions 261. Figure 2MIn the example structure, it will be appreciated that the S / D contacts 291 are electrically connected to the S / D regions 261, and in some cases, they may also physically contact those S / D regions 261. In some embodiments, the S / D contacts 291 may be formed using any suitable technique, such as depositing a metal or metal alloy (or other suitable conductive material) in the contact trenches 290. In some embodiments, the formation of the S / D contacts 291 may include, for example, silicidation, germanidation, and / or annealing processes, where such processes may be performed, for example, prior to forming the bulk contact metal structure to form an intermediate contact layer. In some embodiments, the S / D contacts 291 may include aluminum or tungsten, but any suitable conductive metal or alloy may be used, such as, for example, silver, nickel-platinum, or nickel-aluminum. In general, in some embodiments, one or more of the S / D contacts 291 may include, for example, a resistance-reducing metal and a contact plug metal, or may include only a contact plug. Example contact resistance-reducing metals include, for example, nickel, aluminum, titanium, cobalt, nickel-platinum, or nickel-aluminum, and / or other such resistance-reducing metals or alloys. While any suitable conductive contact metal or alloy may be used, exemplary contact plug metals include, for example, aluminum, copper, nickel, platinum, titanium, or tungsten, or alloys thereof. In some embodiments, depending on the specific configuration, the S / D contact 291 may utilize a low work function metal material (single or multiple) and / or a high work function metal material (single or multiple). In some embodiments, additional layers such as an adhesion layer (e.g., titanium nitride) and / or a liner or barrier layer (e.g., tantalum nitride) may be present in the S / D contact region, if desired.

[0052] Figure 2N The three-dimensional (x, y, z) diagram according to the embodiment is shown. Figure 2L ' example structure. Shown in this figure is a substrate 200 with a diffusion barrier 212 separating source / drain fin structures 232, 261 from STI regions 220. Gate spacers 250 are also shown in the background. P-MOS 261a and n-MOS 261b are shown as replacement S / D materials, for example after epitaxial S / D processing. Additionally, S / D spacers 295 are shown in this example embodiment.

[0053] Figure 3 shows a method according to some embodiments Figure 2M Example cross-sectional view of plane AA in . Figure 3 A cross-sectional view to help illustrate Figure 2M Therefore, the relevant description of each similarly numbered feature applies equally to Figure 3 However, please note that for ease of explanation, Figure 3 The dimensions of the features shown in Figure 2MIt should also be noted that some variations occur between the structures, such as, for example, the shape of the gate spacer 250 and the shape of the fin channel region 230. It should also be noted that Figure 3 The channel region 230 shown is not native to the substrate 200; however, in other embodiments, the channel region (and therefore, the material of the channel region) can be native to the substrate 200. Additionally, note that Figure 3 The specific S / D configuration used in the structure of Figure 2M The S / D configuration is the same. Figure 2M and Figure 3 , showing the vertical extent of STI 220 (along the Y axis), however, STI does not exist in the AA plane, but exists at other locations along the X axis, such as Figure 2M shown.

[0054] In some embodiments, the length of the gate electrode 284 (eg, the dimension between the spacers 250 in the Z-axis direction) is within Figure 3100, 150, 10, 8, or 5 nm, or less than some other suitable threshold, as will be apparent from this disclosure. In some embodiments, these techniques can maintain desired device performance when scaled to low thresholds such as sub-50, sub-40, sub-30, or sub-20 nm thresholds, as can be understood based on the present disclosure. For example, the various techniques described herein can reduce short channel effects, thereby increasing the effective channel length (the dimension between the S / D regions in the Z-axis direction). In addition, according to some embodiments, the techniques described herein can allow the gate length and the effective channel length to be the same or approximately the same. For example, in some such embodiments, the effective channel length and the gate length being approximately the same can include: the effective channel length is within 1-10 nm (e.g., within 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 nm) or is within 1-10% (e.g., within 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10%) of the gate length (e.g., shorter than the gate length). Therefore, in some such embodiments, particularly where the dopant diffusion blocking techniques described herein substantially prevent dopants from diffusing into the channel region, the gate length can be close to the effective channel length.

[0055] In accordance with some embodiments, method 100 of FIG. 1 continues with completing 126 the desired integrated circuit (IC) processing. This additional processing to complete the IC may include back-end or back-end-of-line (BEOL) processing to, for example, form one or more metallization layers and / or interconnect transistor devices formed during the front-end or front-end-of-line. It will be apparent from this disclosure that any other suitable processing may be performed. Note that for ease of description, processes 102-126 of method 100 are shown in a particular order. However, one or more of processes 102-126 may be performed in a different order or may not be performed at all. For example, block 118 is an optional process that does not have to be performed in embodiments employing a gate-first process flow. Recall that this technique can be used to form a variety of different transistor types and configurations. Although the technology is depicted and described herein primarily in the context of using one or more dopant diffusion barriers to separate heavily doped source / drain structures from shallow trench isolation (STI) regions of a given n-MOS transistor having a Ge-rich channel region, the disclosure is not intended to be limited thereto, as in some embodiments, the technology can be used to benefit only one side of a given channel region without benefiting the other side. Many variations and configurations will be apparent in light of this disclosure.

[0056] Example System

[0057] Figure 4 A computing system 1000 is shown that is implemented using transistor devices and / or integrated circuit structures formed using the techniques disclosed herein, according to some embodiments of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a plurality of components, including but not limited to a processor 1004 and at least one communication chip 1006, each of which may be physically and electrically coupled to the motherboard 1002 or otherwise integrated into the motherboard 1002. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a motherboard, a daughterboard mounted on a motherboard, or the sole board of the system 1000.

[0058] Depending on its application, the computing system 1000 may include one or more other components that may be physically and electrically coupled to the motherboard 1002 or not. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). According to an example embodiment, any component included in the computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed technology. In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that the communication chip 1006 may be part of the processor 1004 or otherwise integrated into the processor 1004).

[0059] The communication chip 1006 can enable wireless communication of data transmitted from the computing device 1000 and data transmitted to the computing device 1000. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can transmit data through non-solid media using modulated electromagnetic radiation. The term does not imply that the associated devices do not include any cables, but in some embodiments, they may not include cables. The communication chip 1006 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. The computing device 1000 may include multiple communication chips 1006. For example, the first communication chip 1006 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 1006 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0060] The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes on-board circuitry implemented by one or more integrated circuit structures or devices formed using the disclosed technology, as described variously herein. The term "processor" can refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0061] The communication chip 1006 may also include an integrated circuit die packaged within the communication chip 1006. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. As will be understood in light of this disclosure, it is noted that multi-standard wireless capabilities may be integrated directly into the processor 1004 (e.g., where the functionality of any chip 1006 is integrated into the processor 1004, rather than having a separate communication chip). It should also be noted that the processor 1004 may be a chipset that has such wireless capabilities. In short, any number of processors 1004 and / or communication chips 1006 may be used. Likewise, any one chip or chipset may have multiple functionalities integrated therein.

[0062] In various embodiments, computing system 1000 can be a laptop computer, a netbook computer, a notebook computer, a smartphone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed technology, as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatus, and other structures configured to compute or process information.

[0063] Further example embodiments

[0064] The following examples relate to further embodiments from which numerous permutations and configurations will be apparent.

[0065] Example 1 is an integrated circuit (IC) comprising: a semiconductor body comprising at least 75% germanium by atomic percentage; a gate structure on the semiconductor body, the gate structure comprising a gate dielectric and a gate electrode; a source region and a drain region, both adjacent to the gate structure, such that the gate structure is between the source region and the drain region, at least one of the source region and the drain region comprising n-type impurities; a shallow trench isolation (STI) region adjacent to the at least one of the source region and the drain region; and an insulating material layer between the at least one of the source region and the drain region and the STI region, wherein the insulating material layer is different from the STI region.

[0066] Example 2 includes the subject matter of Example 1, wherein the semiconductor body further comprises at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

[0067] Example 3 includes the subject matter of Example 1 or 2, wherein the semiconductor body has a germanium concentration of 98 atomic percent or greater.

[0068] Example 4 includes the subject matter of any of Examples 1-3, wherein the semiconductor body further comprises up to 2 atomic percent tin.

[0069] Example 5 includes the subject matter of any of Examples 1-4, wherein the source region and the drain region are compositionally different from the semiconductor body except for the n-type impurity, the source region and the drain region comprising at least one of silicon and germanium.

[0070] Example 6 includes the subject matter of any of Examples 1-5, wherein, in addition to the n-type impurity, the source region and the drain region are compositionally different from the semiconductor body, the source region and the drain region further comprising at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

[0071] Example 7 includes the subject matter of any of Examples 1-6, wherein the source region and the drain region further include up to 2 atomic percent tin.

[0072] Example 8 includes the subject matter of any of Examples 1-7, wherein the layer of insulating material comprises silicon dioxide having a carbon concentration between 5% and 50% by atomic percentage.

[0073] Example 9 includes the subject matter of any of Examples 1-8, wherein the layer of insulating material comprises silicon nitride.

[0074] Example 10 includes the subject matter of any of Examples 1-9, wherein the layer of insulating material comprises hafnium oxide.

[0075] Example 11 includes the subject matter of any of Examples 1-10, wherein the layer of insulating material comprises aluminum oxide.

[0076] Example 12 includes the subject matter of any of Examples 1-11, wherein the n-type impurity is phosphorus or arsenic.

[0077] Example 13 includes the subject matter of any of Examples 1-12, wherein the insulating material layer has a thickness in a range of 1 nanometer to 5 nanometers, the thickness being a distance between the STI region and the at least one of the source region and the drain region.

[0078] Example 14 includes the subject matter of any of Examples 1-13, wherein the layer of insulating material is further located between the STI region and the substrate.

[0079] Example 15 includes the subject matter of any of Examples 1-14, wherein the layer of insulating material includes a chemical composition that provides surface charge passivation and anti-diffusion properties.

[0080] Example 16 includes the subject matter of any of Examples 1-15, wherein the semiconductor body is on a fin pile, and the insulating material layer is on opposing sidewalls of the fin pile and on opposing sidewalls of the semiconductor body.

[0081] Example 17 includes the subject matter of any of Examples 1-16, wherein the at least one of the source region and the drain region is on the fin pile, and the insulating material layer is on opposite sidewalls of the fin pile and on opposite sidewalls of the at least one of the source region and the drain region.

[0082] Example 18 includes the subject matter of any of Examples 1-17, wherein the fin pile is part of a lower semiconductor substrate.

[0083] Example 19 includes the subject matter of any of Examples 1-18, wherein the substrate is silicon, and the semiconductor body comprises at least one of germanium, gallium, arsenic, indium, antimony, and nitrogen.

[0084] Example 20 includes the subject matter of any of Examples 1-19, wherein the at least one of the source region and the drain region extends beyond an uppermost surface of the insulating material layer.

[0085] Example 21 includes the subject matter of any of Examples 1-20, further comprising an interlayer dielectric (ILD) material on an upper portion of the at least one of the source region and the drain region.

[0086] Example 22 includes the subject matter of any of Examples 1-21, further comprising a first contact structure in the ILD material and on the source region, and a second contact structure in the ILD material and on the drain region.

[0087] Example 23 includes the subject matter of any of Examples 1-22, wherein the ILD material is on the uppermost surface of the insulating material layer and the STI region.

[0088] Example 24 includes the subject matter of any of Examples 1-23, wherein the semiconductor body is a fin.

[0089] Example 25 includes the subject matter of any of Examples 1-24, wherein the semiconductor body comprises one or more nanowires.

[0090] Example 26 includes the subject matter of any of Examples 1-25, wherein the semiconductor body comprises one or more nanoribbons.

[0091] Example 27 includes the subject matter of any of Examples 1-26, wherein at least one of the gate dielectric and the gate electrode is on an uppermost surface of the layer of insulating material.

[0092] Example 28 includes the subject matter of any of Examples 1-27, wherein the gate structure further comprises a first gate spacer between the source region and the gate electrode, and a second gate spacer between the drain region and the gate electrode.

[0093] Example 29 includes the subject matter of any of Examples 1-28, wherein at least one of the first gate spacer and the second gate spacer is on an uppermost surface of the layer of insulating material.

[0094] Example 30 is a computing system comprising the IC of any of Examples 1-29.

[0095] Example 31 is a method of forming an integrated circuit (IC), the method comprising: forming a semiconductor body, the semiconductor body comprising at least 75% germanium by atomic percentage; forming a gate structure on the semiconductor body, the gate structure comprising a gate dielectric and a gate electrode; forming a source region and a drain region, the source region and the drain region both being adjacent to the gate structure, such that the gate structure is between the source region and the drain region, at least one of the source region and the drain region comprising n-type impurities; forming a shallow trench isolation (STI) region adjacent to the at least one of the source region and the drain region; and forming an insulating material layer between the at least one of the source region and the drain region and the STI region, wherein the insulating material layer is different from the STI region.

[0096] Example 32 includes the subject matter of Example 31, wherein the semiconductor body further comprises at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

[0097] Example 33 includes the subject matter of Example 31 or 32, wherein the semiconductor body has a germanium concentration of 98 atomic percent or greater.

[0098] Example 34 includes the subject matter of any of Examples 31-33, wherein the semiconductor body further comprises up to 2 atomic percent tin.

[0099] Example 35 includes the subject matter of any of Examples 31-34, wherein the source region and the drain region are compositionally different from the semiconductor body except for the n-type impurity, the source region and the drain region comprising at least one of silicon and germanium.

[0100] Example 36 includes the subject matter of any of Examples 31-35, wherein, in addition to the n-type impurity, the source region and the drain region are compositionally different from the semiconductor body, the source region and the drain region further comprising at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

[0101] Example 37 includes the subject matter of any of Examples 31-36, wherein the source region and the drain region further include up to 2 atomic percent tin.

[0102] Example 38 includes the subject matter of any of Examples 31-37, wherein the layer of insulating material comprises silicon dioxide having a carbon concentration between 5% and 50% by atomic percentage.

[0103] Example 39 includes the subject matter of any of Examples 31-38, wherein the layer of insulating material comprises silicon nitride.

[0104] Example 40 includes the subject matter of any of Examples 31-39, wherein the layer of insulating material comprises hafnium oxide.

[0105] Example 41 includes the subject matter of any of Examples 31-40, wherein the layer of insulating material comprises aluminum oxide.

[0106] Example 42 includes the subject matter of any of Examples 31-41, wherein the n-type impurity is phosphorus or arsenic.

[0107] Example 43 includes the subject matter of any of Examples 31-42, wherein the insulating material layer has a thickness in a range of 1 nanometer to 5 nanometers, the thickness being a distance between the STI region and the at least one of the source region and the drain region.

[0108] Example 44 includes the subject matter of any of Examples 31-43, wherein the layer of insulating material is further located between the STI region and the substrate.

[0109] Example 45 includes the subject matter of any of Examples 31-44, wherein the layer of insulating material includes a chemical composition that provides surface charge passivation and anti-diffusion properties.

[0110] Example 46 includes the subject matter of any of Examples 31-45, wherein the semiconductor body is on a fin pile, and the insulating material layer is on opposing sidewalls of the fin pile and on opposing sidewalls of the semiconductor body.

[0111] Example 47 includes the subject matter of any of Examples 31-46, wherein the at least one of the source region and the drain region is on the fin pile, and the insulating material layer is on opposite sidewalls of the fin pile and on opposite sidewalls of the at least one of the source region and the drain region.

[0112] Example 48 includes the subject matter of any of Examples 31-47, wherein the fin pile is a portion of an underlying semiconductor substrate.

[0113] Example 49 includes the subject matter of any of Examples 31-48, wherein the substrate is silicon, and the semiconductor body comprises at least one of germanium, gallium, arsenic, indium, antimony, and nitrogen.

[0114] Example 50 includes the subject matter of any of Examples 31-49, wherein the at least one of the source region and the drain region extends beyond an uppermost surface of the insulating material layer.

[0115] Example 51 includes the subject matter of any of Examples 31-50, further comprising an interlayer dielectric (ILD) material on an upper portion of the at least one of the source region and the drain region.

[0116] Example 52 includes the subject matter of any of Examples 31-51, further comprising a first contact structure in the ILD material and on the source region and a second contact structure in the ILD material and on the drain region.

[0117] Example 53 includes the subject matter of any of Examples 31-52, wherein an ILD material is located on the insulating material layer and the uppermost surface of the STI region.

[0118] Example 54 includes the subject matter of any of Examples 31-53, wherein the semiconductor body is a fin.

[0119] Example 55 includes the subject matter of any of Examples 31-54, wherein the semiconductor body comprises one or more nanowires.

[0120] Example 56 includes the subject matter of any of Examples 31-55, wherein the semiconductor body comprises one or more nanoribbons.

[0121] Example 57 includes the subject matter of any of Examples 31-56, wherein at least one of the gate dielectric and the gate electrode is on an uppermost surface of the layer of insulating material.

[0122] Example 58 includes the subject matter of any of Examples 31-57, wherein the gate structure further comprises a first gate spacer between the source region and the gate electrode, and a second gate spacer between the drain region and the gate electrode.

[0123] Example 59 includes the subject matter of any of Examples 31-58, wherein at least one of the first gate spacer and the second gate spacer is on an uppermost surface of the layer of insulating material.

[0124] Example 60 includes the subject matter of any of Examples 31-59, further comprising depositing the insulating material layer using one of chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques.

[0125] The terms and expressions used herein are used as descriptive terms rather than restrictive terms, and when such terms and expressions are used, there is no intention to exclude any equivalent forms (or parts) of the features shown and described, and it should be recognized that various modifications can be made within the scope of the claims. Therefore, the claims are intended to cover all such equivalents. Various features, aspects and examples have been described herein. As will be understood from this disclosure, features, aspects and examples are easy to combine with each other and to vary and modify. Therefore, it should be considered that this disclosure includes these combinations, variations and modifications. It is intended that the scope of this disclosure is not limited to this detailed description, but is defined by the appended claims. Future applications claiming priority to this application may claim the disclosed subject matter in different ways and may generally include any collection of one or more elements as disclosed in various ways or otherwise shown herein.

Claims

1. An integrated circuit (IC), comprising: A semiconductor body comprising at least 75 atomic percent germanium; a gate structure on the semiconductor body, the gate structure comprising a gate dielectric and a gate electrode; a source region and a drain region, both adjacent to the gate structure, such that the gate structure is between the source region and the drain region, at least one of the source region and the drain region including n-type impurities; a shallow trench isolation (STI) region adjacent to the at least one of the source region and the drain region; as well as An insulating material layer is between the at least one of the source region and the drain region and the STI region, wherein the insulating material layer is different from the STI region, and wherein the insulating material layer includes silicon, oxygen, and carbon.

2. The IC of claim 1, wherein: The semiconductor body also includes at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

3. The IC of claim 1, wherein: The semiconductor body has a germanium concentration of 98 atomic percent or greater.

4. The IC of claim 1, wherein: The semiconductor body also includes up to 2 atomic percent tin.

5. The IC of claim 1, wherein: The source region and the drain region also include up to 2 atomic percent tin.

6. The IC of claim 1, wherein: The insulating material layer includes silicon dioxide having a carbon concentration between 5 atomic percent and 50 atomic percent.

7. The IC of claim 1, wherein: The thickness of the insulating material layer is in a range of 1 nanometer to 5 nanometers, the thickness being a distance between the STI region and the at least one of the source region and the drain region.

8. The IC of claim 1, further comprising a substrate, wherein The insulating material layer is also between the STI region and the substrate.

9. The IC according to any one of claims 1 to 8, wherein The source region and the drain region are compositionally different from the semiconductor body except for the n-type impurity, the source region and the drain region including at least one of silicon and germanium.

10. The IC according to any one of claims 1 to 8, wherein In addition to the n-type impurity, the source region and the drain region are compositionally different from the semiconductor body, and further include at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

11. The IC according to any one of claims 1 to 8, wherein The insulating material layer includes silicon nitride.

12. The IC according to any one of claims 1 to 8, wherein The insulating material layer includes hafnium oxide.

13. The IC according to any one of claims 1 to 8, wherein The insulating material layer includes aluminum oxide.

14. The IC according to any one of claims 1 to 8, wherein The n-type impurity is phosphorus or arsenic.

15. The IC according to any one of claims 1 to 8, wherein The semiconductor body is on the fin pile, and the insulating material layer is on opposite sidewalls of the fin pile and on opposite sidewalls of the semiconductor body.

16. The IC of claim 15, wherein: The at least one of the source region and the drain region is on the fin pile, and the insulating material layer is on opposite sidewalls of the fin pile and on opposite sidewalls of the at least one of the source region and the drain region.

17. The IC of any one of claims 1 to 8, wherein: The at least one of the source region and the drain region extends beyond an uppermost surface of the insulating material layer.

18. The IC of claim 17, further comprising an interlayer dielectric (ILD) material on an upper portion of the at least one of the source region and the drain region, and the ILD material is on the uppermost surface of the insulating material layer and the STI region.

19. The IC of any one of claims 1 to 8, wherein At least one of the gate dielectric and the gate electrode is on an uppermost surface of the insulating material layer.

20. The IC of any one of claims 1 to 8, wherein The gate structure further includes: a first gate spacer between the source region and the gate electrode; and a second gate spacer between the drain region and the gate electrode, and at least one of the first gate spacer and the second gate spacer is on the uppermost surface of the insulating material layer.

21. A computing system comprising the IC of any one of claims 1-20.

22. A method of forming an integrated circuit (IC), the method comprising: forming a semiconductor body comprising at least 75 atomic percent germanium; forming a gate structure on the semiconductor body, the gate structure comprising a gate dielectric and a gate electrode; forming a source region and a drain region, the source region and the drain region both being adjacent to the gate structure such that the gate structure is between the source region and the drain region, at least one of the source region and the drain region including n-type impurities; forming a shallow trench isolation (STI) region adjacent to the at least one of the source region and the drain region; as well as An insulating material layer is formed between the at least one of the source region and the drain region and the STI region, wherein the insulating material layer is different from the STI region, and wherein the insulating material layer includes silicon, oxygen, and carbon.

23. The method of claim 22, wherein: The insulating material layer includes silicon dioxide having a carbon concentration between 5 atomic percent and 50 atomic percent.

24. The method of claim 22, wherein: The semiconductor body has a germanium concentration of 98 atomic percent or greater.

25. The method of any one of claims 22 to 24, wherein The thickness of the insulating material layer is in a range of 1 nanometer to 5 nanometers, the thickness being a distance between the STI region and the at least one of the source region and the drain region.

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