Semiconductor device package and manufacturing method thereof

Abstract

A package substrate includes a first dielectric layer, a first patterned conductive layer, and a first set of alignment marks. The first patterned conductive layer is disposed on the first dielectric layer. The first set of alignment marks is disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. The alignment marks in the first set of alignment marks are positioned at different distances from the first edge.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of and priority to U.S. Provisional Application No. 62 / 748,172, filed October 19, 2018, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device package and a method for manufacturing the same, and to a semiconductor device package including a multi-layer substrate and a method for manufacturing the same. Background Art

[0004] Multilayer substrates are widely used in many semiconductor device packages. A multilayer substrate may include multiple layers (e.g., dielectric layers). Each of the layers has a patterned conductive layer. Alignment between any two layers of the substrate can be important for achieving better alignment. Summary of the Invention

[0005] According to some embodiments of the present disclosure, a packaging substrate includes a first dielectric layer, a first patterned conductive layer, and a first set of alignment marks. The first patterned conductive layer is disposed on the first dielectric layer. The first set of alignment marks is disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. The alignment marks in the first set of alignment marks are located at different distances from the first edge.

[0006] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device package includes: (a) providing a substrate; (b) placing an electronic component on the substrate; and (c) forming a package body on the substrate to cover the electronic component. The substrate includes a first dielectric layer, a first patterned conductive layer, and a first set of alignment marks. The first patterned conductive layer is placed on the first dielectric layer. The first set of alignment marks is placed on the first dielectric layer and adjacent to a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. The lengths of the alignment marks in the first set of alignment marks are different from each other.

[0007] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device package includes: (a) providing a substrate; (b) placing an electronic component on the substrate; and (c) forming a package body on the substrate to cover the electronic component. The substrate comprises a first dielectric layer, a first patterned conductive layer, and a first set of alignment marks. The first patterned conductive layer is placed on the first dielectric layer. The first set of alignment marks is placed on the first dielectric layer and adjacent to a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. The alignment marks in the first set of alignment marks are located at different distances from the first edge. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A A perspective view illustrating a substrate according to certain comparative techniques.

[0009] Figure 1B A perspective view illustrating a substrate according to certain comparative techniques.

[0010] Figure 1C is an image showing a cross-sectional view of a substrate according to certain comparative techniques.

[0011] Figure 2 A top view of a layer of a substrate according to some embodiments of the present disclosure is illustrated.

[0012] Figure 3A A perspective view illustrating a substrate according to some embodiments of the present disclosure.

[0013] Figure 3B A perspective view illustrating a substrate according to some embodiments of the present disclosure.

[0014] Figure 4A A perspective view illustrating a substrate according to some embodiments of the present disclosure.

[0015] Figure 4B A perspective view illustrating a substrate according to some embodiments of the present disclosure.

[0016] Figure 5 A perspective view illustrating a substrate according to some embodiments of the present disclosure.

[0017] Figure 6A A top view of a layer of a substrate according to some embodiments of the present disclosure is illustrated.

[0018] Figure 6B A perspective view illustrating a substrate according to some embodiments of the present disclosure.

[0019] Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7DA method of manufacturing a semiconductor device package according to some embodiments of the present disclosure is described.

[0020] Figure 8 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is shown.

[0021] The present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0022] Figure 1A A cross-sectional view of a substrate package according to certain comparative technologies is illustrated. The substrate package includes a substrate 10 and a patterned conductive layer (e.g., a redistribution layer (RDL) or antenna radiation pattern) disposed within the substrate 10. The substrate 10 may be a multilayer substrate comprising a core structure 10a, dielectric layers 10b, 10c, and protective layers 10d, 10e (e.g., layers comprising solder resist or solder mask). The core structure 10a may be, for example, selected from, but not limited to, a silicon substrate, a plastic substrate, or a ceramic substrate. Dielectric layers 10b and 10c are disposed on the top and bottom surfaces of the core structure 10a, respectively. Each of the dielectric layers 10b and 10c may comprise a material such as polypropylene (PP), bismaleimide triazine (BT) resin, epoxy resin, polyimide (PI), or other dielectric materials. Dielectric layers 10b and 10c may comprise the same material or different materials. In other embodiments, the substrate 10 may be a coreless multilayer substrate that omits the core structure and comprises multiple dielectric layers (or sublayers).

[0023] One or more layers of the substrate 10 may include a patterned conductive layer. For example, Figure 1A As shown in FIG, a patterned conductive layer may be disposed on the core structure 10a and the dielectric layers 10b and 10c. For example, the patterned conductive layer may be disposed on both surfaces of the core structure 10a. For example, the patterned conductive layer may be disposed on the top surface of the dielectric layer 10b and covered by the protective layer 10d. For example, the patterned conductive layer may be disposed on the bottom surface of the dielectric layer 10c and covered by the protective layer 10e.

[0024] The substrate 10 includes one or more sets of alignment marks (e.g., a first set of alignment marks 10m1, a second set of alignment marks 10m2, a third set of alignment marks 10m3, and a fourth set of alignment marks 10m4 on a side of a layer of the substrate 10), and each of the sets of alignment marks has the same number of alignment marks. The spacing between the alignment marks is substantially the same. For example, the distance between any two adjacent alignment marks is substantially the same. The width of the alignment marks is substantially the same. In some embodiments, the width of each alignment mark is approximately 20 micrometers (μm).

[0025] Several sets of alignment marks 10m1, 10m2, 10m3, and 10m4 may be used to determine whether the layers of the substrate 10 (and the patterned conductive layers within the substrate 10) are aligned with each other. Figure 1A As shown in FIG, alignment marks 10m1, 10m2, 10m3, and 10m4 of substrate 10 are aligned with each other, and thus ensure that the layers of substrate 10 (and patterned conductive layers within substrate 10) are aligned with each other. In other words, shift, deviation, or drift is minimized or reduced in the layers of substrate 10.

[0026] like Figure 1B , the set of alignment marks 10m2 (the second set from the top) is misaligned with the other sets of alignment marks 10m1, 10m3, and 10m4, and thus the core structure 10a on which the set of alignment marks 10m2 is disposed is determined to have a shift, deviation, or drift. The distance or amount of the shift, deviation, or drift of the layer 10b can be determined based on the position of the set of alignment marks 10m2 relative to the position of the set of alignment marks 10m1 or 10m3.

[0027] Due to limitations in manufacturing alignment marks, the pitch of alignment marks may be limited (e.g., a minimum pitch of alignment marks of about 20 μm to about 25 μm), thereby reducing the accuracy with which the shift, deviation, or drift can be determined. Figure 1C As shown in FIG, it may be difficult to measure the displacement distance of the alignment mark. Figure 1C An image showing a substrate including alignment marks.

[0028] Figure 2 A multilayer substrate according to some embodiments of the present disclosure (e.g., Figure 3A or Figure 3B 1 is a top view of a portion of a layer (e.g., a quarter of the layer) of the substrate 20 shown in FIG. Figure 2 The substrate 20 described in Figure 1A The substrate 10 described in FIG. 1 and some descriptions of the substrate 10 may apply to Figure 2 The depicted layer of substrate 20 includes a circuit area 22 (which may extend beyond Figure 2 ). In some embodiments, circuit area 22 may be or include an RDL, an antenna radiation pattern, and / or a chip bonding area. Circuit area 22 is spaced apart from the edges of the layers of substrate 20. For example, a distance exists between each of the edges of the layers of substrate 20 and circuit area 22. In some embodiments, the distance between each of the edges of the layers of substrate 20 and circuit area 22 is approximately 100 μm to approximately 150 μm.

[0029] The layer of substrate 20 includes several groups of alignment marks 20m1, 20m2, and each group of alignment marks includes multiple alignment marks. It should be noted that in some other embodiments, the substrate or the layer of the substrate may include a single group (only one group) of alignment marks. Several groups of alignment marks 20m1 and 20m2 are located at the space (e.g., side rails) between the edge of the layer of substrate 20 and the circuit area 22. The group of alignment marks 20m1 is arranged along edge 201. The group of alignment marks 20m2 is arranged along edge 202. Figure 2 As shown in FIG. , the lengths of the alignment marks in the sets of alignment marks 20m1 and 20m2 differ from one another. For example, the lengths of the alignment marks in the set of alignment marks 20m1 gradually increase (e.g., monotonically) from edge 202 to circuit area 22 (e.g., in a direction from the outer edge toward the center portion). In some embodiments, the length difference D21 between two adjacent alignment marks is approximately 2 μm to approximately 5 μm. Any two adjacent alignment marks are separated from each other by substantially the same distance. In some embodiments, the alignment marks have substantially the same width (e.g., approximately 30 μm to approximately 50 μm). Alternatively, the widths of the alignment marks may be adjusted depending on design specifications. For example, a set of alignment marks may include nine alignment marks, wherein the first alignment mark has a first width (e.g., approximately 50 μm), the second through fourth alignment marks have a second width (e.g., approximately 30 μm), the fifth alignment mark has a first width (e.g., approximately 50 μm), and the sixth through ninth alignment marks have a second width (e.g., approximately 30 μm). In some embodiments, the last alignment mark (e.g., the longest alignment mark) can have a width that is different from the width of any other alignment mark to indicate an endpoint. In some embodiments, the difference in length of two adjacent alignment marks in a set of alignment marks is substantially equal to the difference in length of any other two adjacent alignment marks in the set of alignment marks.

[0030] The substrate 20 may include multiple layers, each having Figure 2 Multiple layers are stacked together to form a multilayer substrate 20, such as Figure 3A or Figure 3B The circuit regions 22 and the sets of alignment marks 20m1, 20m2 of the layers of the substrate 20 are aligned with each other. If there is little or no shift, deviation or drift in any of the layers of the substrate 20, then each layer of the substrate 20 should be aligned with its Figure 3A or Figure 3B The sides shown in FIG have the same number of alignment marks (for example, 20m1, 20m1′, 20m1″ and 20m1′″ should have the same number of alignment marks). For example, Figure 3AAs shown in , each of the layers of substrate 20 has one alignment mark on its side, and therefore it is determined that there is no shift, deviation or drift in any of the layers of substrate 20. Similarly, as Figure 3B , each of the layers of substrate 20 has three alignment marks on its side, and therefore it is determined that there is no shift, deviation, or drift in any of the layers of substrate 20.

[0031] Figure 3A The structure and Figure 3B One of the differences between the structures in FIG is the number of alignment marks shown on the side of each layer of substrate 20. The number of alignment marks varies from Figure 3A and Figure 3B One of the reasons why the side surfaces of each layer of the substrate 20 are exposed is that when a singulation operation is performed on the substrate strip, the substrate strip is exposed. Figure 3B The cutting means for the substrate 20 illustrated in FIG. 1 is relatively wide.

[0032] Figure 4A and Figure 4B A perspective view illustrating a substrate 20 according to some embodiments of the present disclosure in which one of the layers of the substrate 20 is displaced, deviated, or drifted. Figure 4A and Figure 4B As shown in FIG, the number of alignment marks in one set of alignment marks on the side of one layer of substrate 20 is different from the number of alignment marks in other sets of alignment marks on the side of other layers of substrate 20. Figure 4A , the number of alignment marks in the set of alignment marks 20m1′ on the side of the layer of the substrate 20 is different from (greater than) the number of alignment marks in the other sets of alignment marks 20m1, 20m1″, and 20m1′″ on the sides of other layers of the substrate 20, and thus it is determined that the layer on which the set of alignment marks 20m1′ is located is shifted, deviated, or drifted. Similarly, Figure 4B As shown in FIG, the number of alignment marks in the group of alignment marks 20m1″ on the side of the layer of the substrate 20 is different from (greater than) the number of alignment marks in the other groups of alignment marks 20m1, 20m1′ and 20m1′″ on the sides of other layers of the substrate 20, and therefore it is determined that the layer on which the group of alignment marks 20m1″ is positioned has a shift, deviation or drift. In other words, it can be determined based on the number of alignment marks shown on the side of the layer of the substrate 20 whether there is a shift, deviation or drift of the layer of the substrate 20.

[0033] Additionally, the distance of the shift, deviation, or drift of a layer of substrate 20 may be determined based on the number of alignment marks of the shifted layer relative to the number of alignment marks of any other non-shifted layer. Figure 4AAs shown in , the layer on which the set of alignment marks 20m1′ is positioned has two more alignment marks on its side than the number of alignment marks in the other sets of alignment marks 20m1, 20m1″, and 20m1″′ on the sides of the other layers. Therefore, the shifted layer is shifted by a distance of 2×N relative to the other non-shifted layers, where N is the length difference between two adjacent alignment marks. For example, if N is 5 μm, the shifted distance of the second layer is about 10 μm. Similarly, Figure 4B As shown in FIG, the layer on which the set of alignment marks 20m1″ is positioned has four more alignment marks on its side than the number of alignment marks in the other sets of alignment marks 20m1′, 20m1′, and 20m1′″ on the sides of the other layers. Therefore, the shift distance of the third layer relative to the other layers is 4×N, where N is the length difference between two adjacent alignment marks.

[0034] In some embodiments, alignment marks may be shown on two adjacent sides of each layer of substrate 20, such as Figure 5 As shown in , the shift, deviation or drift of the layer is measured in both the x-direction and the y-direction.

[0035] Figure 6A Illustrated is a top view of a portion of one layer (eg, one quarter of a layer) of a multilayer substrate according to some embodiments of the present disclosure. Figure 6A The structure described in is similar to Figure 2 The structure in which one of the differences is Figure 6A The alignment marks in the sets of alignment marks 60m1 and 60m2 illustrated in FIG are aligned with the edges 201 and 202 of the layers of the substrate, respectively, in the manner depicted. Figure 6B As shown in FIG, if there is a shift, deviation or drift in one layer of the substrate, the number of alignment marks on the side of the shifted layer of the substrate (for example, the layer on which the set of alignment marks 60m1' is positioned) is less than the number of alignment marks in the several sets of alignment marks 60m1, 60m1" and 60m1"' on the sides of other non-shifted layers of the substrate.

[0036] according to Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5 、 Figure 6A and Figure 6B In the embodiment of the present invention, since the shift distance is determined by the number of alignment marks present on the side of the shifted layer relative to the number of alignment marks present on the side of the non-shifted layer, it is possible to easily and accurately measure the shift distance. In addition, the means for determining the shift distance is by the length difference between two adjacent alignment marks - rather than by the length difference between the two adjacent alignment marks. Figure 1Aand 1B The width of the alignment mark shown in FIG is determined, which can provide greater accuracy in determining the shift distance.

[0037] Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D A method of manufacturing a semiconductor device package according to some embodiments of the present disclosure is described.

[0038] refer to Figure 7A , a substrate strip 70 comprising a plurality of multilayer substrates (e.g., substrate 20) is provided. As shown in FIG. 7 , alignment marks may be disposed at locations corresponding to each row and column of substrates. In other embodiments, alignment marks may be selectively disposed (e.g., at the four corners or edges of substrate strip 70). In some embodiments, each substrate of substrate strip 70 may also include an alignment mark. Thus, it is easier to determine which column or row of substrates contains a shift, deviation, or drift. Additionally, if it is determined that a column or row of substrates contains a shift, deviation, or drift, it is easier to determine which substrate in that column or row of substrates contains the shift, deviation, or drift.

[0039] refer to Figure 7B , an electronic component 71 (eg, a die or chip) is bonded to each of the substrates.

[0040] refer to Figure 7C , a package body 72 is formed on the substrate strip 70 to cover or encapsulate the electronic component 71. In some embodiments, the package body 72 can be formed by, for example, transfer molding, compression molding, or any other molding technique.

[0041] refer to Figure 7D Singulation may be performed to separate individual semiconductor package devices. That is, singulation may be performed through package body 72 and substrate strip 70 comprising a plurality of multilayer substrates (e.g., substrate 20). For example, singulation may be performed using a dicing saw, a laser, or other appropriate cutting techniques.

[0042] Figure 8 The semiconductor device package 8 according to some embodiments of the present disclosure is described. The semiconductor device package 8 includes a substrate 80, electronic components 81a, 81b, a package body 82, and electrical contacts 83. In some embodiments, the semiconductor device package 8 may be used Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D The process may be performed by the operations shown in FIG. 1 or any other suitable manufacturing process.

[0043] In some embodiments, the substrate 80 is a multi-layer substrate. For example, the substrate 80 may be or may include Figure 1A 、 Figure 1B 、 Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5 、 Figure 6A and Figure 6B The substrate 10 or 20 described in any one of the embodiments. The substrate 80 has a surface 801 and a surface 802 opposite to the surface 801.

[0044] Electrical components 81a and 81b are disposed on the top surface 801 of the substrate 80. Electrical component 81a can be an active component, such as an integrated circuit (IC) chip or die. Electrical component 81b can be a passive electrical component, such as a capacitor, a resistor, or an inductor. Each electrical component 81a and 81b can be electrically connected to one or more of the other electrical components 81a and 81b and / or to the substrate 80 (e.g., to an RDL), and the electrical connections can be achieved by flip-chip or wire bonding techniques.

[0045] The package body 82 is disposed on the surface 801 of the substrate 80 and encapsulates the surface 801 of the substrate 80 and a portion of the electrical components 81a and 81b. In some embodiments, the package body 82 includes an epoxy resin having a filler dispersed therein.

[0046] Electrical contacts 83 (e.g., solder balls) are disposed on surface 802 of substrate 80 and can provide electrical connections between semiconductor device package 8 and external components (e.g., external circuits or circuit boards). In some embodiments, electrical contacts 83 include control crash chip connection (C4) bumps, ball grid arrays (BGAs), or land grid arrays (LGAs).

[0047] In some embodiments, the semiconductor device package 8 can be formed by a process including the following: (i) providing a substrate 80; (ii) placing electronic components 81a and 81b on a surface 801 of the substrate 80; (iii) forming a package body 82 on the surface 801 of the substrate 80 to cover the electronic components 81a and 81b; and (iv) forming an electronic component 83 on the surface 802 of the substrate 80.

[0048] As used herein, the terms "substantially," "substantial," "approximately," and "about" are intended to indicate and account for small variations. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a film or layer having a thickness that is "substantially uniform" may refer to a standard deviation of less than or equal to ±10% of the average thickness of the film or layer, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces that are within microns along the same plane, for example, within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm along the same plane. Two surfaces or components may be considered "substantially perpendicular" if the angle between them is, for example, 90° ± 10° (e.g., ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1°, or ± 0.05°). When used in conjunction with an event or circumstance, the terms "substantially," "substantial," "approximately," and "about" may refer to both instances where the event or circumstance occurs precisely and instances where the event or circumstance occurs approximately.

[0049] Unless the context clearly dictates otherwise, as used herein, the singular terms "a," "an," and "the" may include plural referents. In the description of some embodiments, a component disposed "on" or "over" another component may encompass both the situation where the former component is directly on (e.g., in physical contact with) the latter component and the situation where one or more intervening components are located between the former and the latter component.

[0050] As used herein, the terms "conductive," "electrically conductive," and "conductivity" refer to the ability to carry an electric current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, a conductive material is one that has a conductivity greater than about 10 4 S / m (e.g. at least 10 5 S / m or at least 10 6 The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0051] In addition, amounts, ratios and other numerical values ​​are sometimes presented herein in a range format. It is understood that such range format is used for convenience and brevity and should be construed flexibly to include not only the values ​​explicitly specified as limits of the range, but also all individual values ​​or sub-ranges encompassed within the range, as if each value and sub-range were explicitly specified.

[0052] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, such description and illustration do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The description may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the process reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically described. The description and drawings should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it will be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. A packaging substrate, comprising: a first dielectric layer; a first patterned conductive layer disposed on the first dielectric layer; and a first set of alignment marks disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer, the first set of alignment marks comprising a plurality of alignment marks, wherein the plurality of alignment marks in the first set of alignment marks are at different distances from the first edge; a second dielectric layer disposed on the first dielectric layer and covering the first patterned conductive layer; a second patterned conductive layer disposed on the second dielectric layer; and A second set of alignment marks is disposed on the second dielectric layer and adjacent to a second edge of the second dielectric layer, the second set of alignment marks comprising a plurality of alignment marks, wherein the plurality of alignment marks in the second set of alignment marks have different distances from the second edge. 2 . The package substrate of claim 1 , wherein the first set of alignment marks are substantially aligned with the second set of alignment marks. 3 . The package substrate of claim 1 , wherein a number of the plurality of alignment marks in the first set of alignment marks exposed from the first dielectric layer is the same as a number of the plurality of alignment marks in the second set of alignment marks exposed from the second dielectric layer.

4. The packaging substrate according to claim 1, wherein the first dielectric layer has a central portion and a third edge adjacent to the first edge of the first dielectric layer, and the lengths of the plurality of alignment marks in the first group of alignment marks gradually increase in a direction from the third edge of the first dielectric layer toward the central portion of the first dielectric layer.

5. A method for manufacturing a semiconductor device package, comprising: (a) providing a substrate, the substrate having a first dielectric layer, a first patterned conductive layer disposed on the first dielectric layer, a first set of alignment marks disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and covering the first patterned conductive layer, a second patterned conductive layer disposed on the second dielectric layer, and a second set of alignment marks disposed on the second dielectric layer and adjacent to a second edge of the second dielectric layer, the first set of alignment marks comprising a plurality of alignment marks, and the second set of alignment marks comprising a plurality of alignment marks, wherein the plurality of alignment marks in the first set of alignment marks have different lengths from one another, and the plurality of alignment marks in the second set of alignment marks have different lengths from one another, and wherein at least one alignment mark in the first set of alignment marks is exposed from a side surface of the first dielectric layer; (b) placing an electronic component on the substrate; and (c) forming a package body on the substrate to cover the electronic component. The method of claim 5 , wherein the first set of alignment marks are substantially aligned with the second set of alignment marks. 7 . The method of claim 6 , wherein a number of the plurality of alignment marks in the first set of alignment marks exposed from the first dielectric layer is the same as a number of the plurality of alignment marks in the second set of alignment marks exposed from the second dielectric layer.

8. The method of claim 5 , wherein the first dielectric layer has a central portion and a third edge adjacent to the first edge of the first dielectric layer, and the lengths of the plurality of alignment marks in the first set of alignment marks gradually increase in a direction from the third edge of the first dielectric layer toward the central portion of the first dielectric layer.

9. The method of claim 5, wherein a difference in the lengths of two adjacent alignment marks in the first set of alignment marks is substantially equal to a difference in the lengths of any other two adjacent alignment marks in the first set of alignment marks.

10. The method according to claim 5, operation (a) further comprising: providing a substrate strip comprising the substrate, wherein the substrate comprises side rails and a chip bonding area, and The first set of alignment marks is disposed on the side rails of the substrate.

11. A method for manufacturing a semiconductor device package, comprising: (a) providing a substrate having a first dielectric layer, a first patterned conductive layer disposed on the first dielectric layer, a first set of alignment marks disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and covering the first patterned conductive layer, a second patterned conductive layer disposed on the second dielectric layer, and a second set of alignment marks disposed on the second dielectric layer and adjacent to a second edge of the second dielectric layer, the first set of alignment marks comprising a plurality of alignment marks, and the second set of alignment marks comprising a plurality of alignment marks, wherein the plurality of alignment marks in the first set of alignment marks have different distances from the first edge, and the plurality of alignment marks in the second set of alignment marks have different lengths, and wherein at least one alignment mark in the first set of alignment marks is exposed from a side surface of the first dielectric layer; (b) placing an electronic component on the substrate; and (c) forming a package body on the substrate to cover the electronic component.

12. The method of claim 11, wherein the first set of alignment marks are substantially aligned with the second set of alignment marks. 13 . The method of claim 12 , wherein a number of the plurality of alignment marks in the first set of alignment marks exposed from the first dielectric layer is the same as a number of the plurality of alignment marks in the second set of alignment marks exposed from the second dielectric layer.

14. The method according to claim 11, wherein the first dielectric layer has a central portion and a third edge adjacent to the first edge of the first dielectric layer, and the lengths of the plurality of alignment marks in the first set of alignment marks gradually increase in a direction from the third edge of the first dielectric layer toward the central portion of the first dielectric layer. 15 . The method of claim 11 , wherein a difference in the lengths of two adjacent alignment marks in the first set of alignment marks is substantially equal to a difference in the lengths of any other two adjacent alignment marks in the first set of alignment marks.

16. The method according to claim 11, operation (a) further comprising: A substrate strip comprising the substrate is provided, wherein The substrate includes side rails and a chip bonding area, and The first set of alignment marks is disposed on the side rails of the substrate.

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