A packaging structure for integrated packaging of depleted DMOS and ASIC chip

Abstract

The present invention discloses a packaging structure for integrated packaging of a depleted DMOS and an ASIC chip, comprising a substrate, a first chip and a second chip, wherein a placement groove is provided on the substrate, the first chip is provided in the placement groove, the second chip is provided on a side of the first chip away from the placement groove, a first bump is fixedly connected to a terminal of the first chip, an opening corresponding to the first bump is provided on one side of the substrate, slide grooves are provided on both sides of the substrate, second bumps corresponding to the slide grooves are provided at both ends of the second chip close to the first chip, the second bumps are inserted in the slide grooves, and a second opening corresponding to the first bump is provided on one side of the substrate. The present invention has a simple structure, is convenient for packaging, has a low manufacturing cost, and has higher stability after packaging.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor chip packaging related products, in particular to a packaging structure for integrated packaging of a depleted DMOS and an ASIC chip. Background Art

[0002] The chip of DMOS power device can be used as the front-stage drive control of electrical load, such as driving inductive loads such as DC motors, stepper motors and relays. ASIC chip is an integrated circuit chip technology used for special applications. In the integrated circuit industry, it is considered to be an integrated circuit designed for a special purpose.

[0003] However, the existing packaging structure of the integrated package of depletion DMOS and ASIC chip is usually connected by wire bonding, which has high consumables cost and low reliability. At the same time, it is not conducive to the miniaturization design trend of the overall size. Summary of the invention

[0004] The object of the present invention is to provide a packaging structure of integrated package of depletion DMOS and ASIC chip, so as to solve the problem that the existing packaging structure of integrated package of depletion DMOS and ASIC chip proposed in the above background technology is usually connected by wire bonding, which has high consumables cost and low reliability, and is not conducive to the miniaturization design trend of the overall size.

[0005] To achieve the above-mentioned purpose, the present invention provides the following technical solution: a packaging structure for integrated packaging of a depleted DMOS and an ASIC chip, comprising a substrate, a first chip and a second chip, wherein a placement groove is provided on the substrate, the first chip is provided in the placement groove, the second chip is provided on a side of the first chip away from the placement groove, a first bump is fixedly connected to a terminal of the first chip, an opening corresponding to the first bump is provided on one side of the substrate, slide grooves are provided on both sides of the substrate, second bumps corresponding to the slide grooves are provided at both ends of the second chip close to the first chip, the second bumps are inserted in the slide grooves, and the substrate A second opening corresponding to the second protrusion is provided on one side, a cover plate is provided on the side of the second chip away from the first chip, and both ends of the cover plate close to the second chip are fixedly connected with fixed blocks, a socket corresponding to the fixed block is provided on the substrate, and sliding grooves are provided on the inner walls on both sides of the socket, and a mounting block is slidably connected in the sliding grooves on the inner walls of the socket, a card block is fixedly connected on one side of the mounting block, and the outer walls on both sides of the fixing block located in the socket are provided with card grooves corresponding to the card block, springs are fixedly connected between the two ends of the mounting block and the sliding grooves on the inner walls of the socket, and an adhesive layer is provided between the first chip and the second chip.

[0006] Preferably, a buffer plate is fixedly connected to one side of the cover plate close to the second chip, and the buffer plate is made of plastic.

[0007] Preferably, two symmetrically arranged positioning grooves are provided on the inner wall of the substrate, and positioning blocks corresponding to the positioning grooves are fixedly connected to the outer wall of the first chip.

[0008] Compared with the prior art, the present invention has the following beneficial effects:

[0009] 1. The packaging structure of the depletion DMOS and ASIC chip integrated package: the first chip is placed inside the substrate, and the positioning block is used to align the positioning groove on the substrate, and then the second chip is placed on the first chip to form an integrated stacking method. After the stacking is completed, the openings corresponding to the first bump and the second bump and the second opening are respectively opened on the substrate to facilitate welding and ball planting on the first bump and the second bump;

[0010] 2. The packaging structure of the integrated package of the depleted DMOS and ASIC chip: after the chip integration is completed, the fixed block on the cover plate is inserted into the socket through the setting of the cover plate, the card block is pushed to be compressed, and then the card block rebounds and is inserted into the card groove on the fixed block under the rebound force of the spring to fix the cover plate. The present invention has a simple structure, convenient packaging, low cost, and higher stability after packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of a packaging structure of a depleted DMOS and an ASIC chip integrated package according to the present invention;

[0012] Figure 2 The figure is a schematic diagram of the structure of the integrated package of a depletion DMOS and an ASIC chip at A of the present invention.

[0013] In the figure: 1, substrate; 2, first chip; 3, second chip; 4, first bump; 5, opening; 6, second bump; 7, second opening; 8, cover plate; 9, fixing block; 10, mounting block; 11, clamping block; 12, spring; 13, adhesive layer; 14, buffer plate; 15, positioning block. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Example 1

[0015] See also Figure 1-2An embodiment of the present invention provides: a packaging structure for integrated packaging of a depleted DMOS and an ASIC chip, comprising a substrate 1, a first chip 2 and a second chip 3, wherein a placement groove is provided on the substrate 1, the first chip 2 is provided in the placement groove, the second chip 3 is provided on a side of the first chip 2 away from the placement groove, a first bump 4 is fixedly connected to the terminal of the first chip 2, an opening 5 corresponding to the first bump 4 is provided on one side of the substrate 1, a slide groove is provided on both sides of the substrate 1, second bumps 6 corresponding to the slide groove are provided at both ends of the second chip 3 close to the first chip 2, the second bump 6 is inserted in the slide groove, and a second opening 7 corresponding to the second bump 6 is provided on one side of the substrate 1 A cover plate 8 is provided on the side of the second chip 3 away from the first chip 2, and both ends of the cover plate 8 close to the second chip 3 are fixedly connected with fixed blocks 9, a socket corresponding to the fixed block 9 is provided on the substrate 1, and both inner walls of the socket are provided with sliding grooves, and a mounting block 10 is slidably connected in the sliding grooves on the inner wall of the socket, and a clamping block 11 is fixedly connected to one side of the mounting block (10), and both outer walls of the fixing block 9 located in the socket are provided with clamping grooves corresponding to the clamping block 11, and springs 12 are fixedly connected between the two ends of the mounting block 10 and the sliding grooves on the inner wall of the socket, and an adhesive layer 13 is provided between the first chip 2 and the second chip 3 to prevent the first chip 2 and the second chip 3 from falling off.

[0016] Furthermore, a buffer plate 14 is fixedly connected to one side of the cover plate 8 close to the second chip 3 . The buffer plate 14 is made of plastic and reduces the space between the cover plate 8 and the second chip 3 , making it more secure.

[0017] Furthermore, two symmetrically arranged positioning grooves are provided on the inner wall of the substrate 1, and positioning blocks 15 corresponding to the positioning grooves are fixedly connected to the outer wall of the first chip 2, so as to facilitate alignment of the first chip 2 in the storage groove.

[0018] Working principle: by placing the first chip 2 inside the substrate 1, aligning it with the positioning groove on the substrate 1 through the positioning block 15, and then placing the second chip 3 on the first chip 2 to form an integrated stacking method, after the stacking is completed, the openings 5 ​​and the second openings 7 corresponding to the first bump 4 and the second bump 6 are respectively opened on the substrate to facilitate welding and ball planting on the first bump 4 and the second bump 6. After the chip integration is completed, the cover plate 8 is set to insert the fixing block 9 on the cover plate 8 into the socket, pushing the card block 11 to compress, and then the card block 11 rebounds under the rebound force of the spring 12 and is inserted into the card groove on the fixing block 9 to fix the cover plate 8.

[0019] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A packaging structure for integrated packaging of a depleted DMOS and an ASIC chip, comprising a substrate (1), a first chip (2) and a second chip (3), characterized in that: The substrate (1) is provided with a storage groove, the first chip (2) is provided in the storage groove, the second chip (3) is provided on a side of the first chip (2) away from the storage groove, a first bump (4) is fixedly connected to the terminal of the first chip (2), an opening (5) corresponding to the first bump (4) is provided on one side of the substrate (1), both sides of the substrate (1) are provided with slide grooves, both ends of the second chip (3) close to the first chip (2) are provided with second bumps (6) corresponding to the slide grooves, the second bumps (6) are inserted into the slide grooves, a second opening (7) corresponding to the second bump (6) is provided on one side of the substrate (1), the second chip (3) is away from the first chip (2) A cover plate (8) is provided on one side of the substrate (1); both ends of the cover plate (8) close to the second chip (3) are fixedly connected to fixing blocks (9); a socket corresponding to the fixing block (9) is provided on the substrate (1); both inner walls of the socket are provided with sliding grooves; a mounting block (10) is slidably connected in the sliding grooves on the inner wall of the socket; a clamping block (11) is fixedly connected to one side of the mounting block (10); both outer walls of the fixing block (9) located in the socket are provided with clamping grooves corresponding to the clamping block (11); springs (12) are fixedly connected between the two ends of the mounting block (10) and the sliding grooves on the inner wall of the socket; and an adhesive layer (13) is provided between the first chip (2) and the second chip (3).

2. The packaging structure of the depletion DMOS and ASIC chip integrated package according to claim 1, characterized in that: A buffer plate (14) is fixedly connected to a side of the cover plate (8) close to the second chip (3), and the buffer plate (14) is made of plastic.

3. The packaging structure of a depletion DMOS and an ASIC chip integrated package according to claim 1, characterized in that: Two symmetrically arranged positioning grooves are provided on the inner wall of the substrate (1), and positioning blocks (15) corresponding to the positioning grooves are fixedly connected to the outer wall of the first chip (2).

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