Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device may include forming a dummy dielectric layer over a substrate and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent to the dummy gate; and removing the dummy gate to form a cavity, wherein the cavity is at least partially defined by the first spacer. The method may also include performing a plasma treatment on multiple portions of the first spacer, wherein the plasma treatment changes the material composition of the portions of the first spacer from the first material composition to the second material composition. The method may also include etching the portion of the first spacer having the second material composition to remove the portion of the first spacer having the second material composition; and filling the cavity with a plurality of conductive materials to form a gate structure.

Description

Technical Field

[0001] The embodiments of the present application relate to semiconductor manufacturing technology, and more particularly to semiconductor devices and methods for manufacturing the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material over a semiconductor substrate and patterning these various material layers using lithography to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a specific area. However, as the minimum feature size decreases, other problems arise that should be solved. Summary of the invention

[0004] According to some embodiments, a method for manufacturing a semiconductor device is provided. The method includes forming a dummy dielectric layer over a substrate; forming a dummy gate over the dummy dielectric layer; forming a first spacer adjacent to the dummy gate; removing the dummy gate to form a cavity, wherein the cavity is at least partially defined by the first spacer; performing a plasma treatment on a plurality of portions of the first spacer, wherein the plasma treatment changes the material composition of the portions of the first spacer from a first material composition to a second material composition; etching the portion of the first spacer having the second material composition to remove the portion of the first spacer having the second material composition; and filling the cavity with a plurality of conductive materials to form a gate structure.

[0005] According to some other embodiments, a method for manufacturing a semiconductor device is provided. The method includes depositing a dummy gate over a dummy dielectric layer and patterning the dummy gate; forming a plurality of spacers to surround the dummy gate; etching the dummy gate to form a gate cavity, the gate cavity being defined by a plurality of spacers; performing a plasma treatment on at least a portion of a first spacer of the spacers, wherein the portion of the first spacer is the portion of the first spacer farthest from the dummy dielectric layer; performing an etching process to remove the portion of the first spacer and a portion of the dummy dielectric layer, wherein after the etching process is completed, a top opening of the gate cavity is widened; depositing one or more gate dielectric layers and one or more gate electrode layers in the gate cavity through the top opening to form a gate structure; and forming an interlayer dielectric to surround the spacers.

[0006] According to yet other embodiments, a semiconductor device is provided. The semiconductor device includes a plurality of source / drain regions formed in a substrate; a gate structure located above the substrate between the source / drain regions, wherein the gate structure includes one or more gate dielectric layers and one or more gate electrode layers; and a plurality of spacers surrounding the gate structure, wherein a first spacer of the spacers contacts the one or more gate dielectric layers, wherein the first spacer has a first thickness at a first position and a second thickness at a second position, wherein the first position is farthest from the substrate, and the second position is between the first position and the substrate, and wherein a first sidewall of the first spacer contacting the one or more gate dielectric layers extends at an angle between the first position and the second position, the angle being relative to a direction perpendicular to a major surface of the substrate, and the angle being greater than or equal to 3 degrees. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description in conjunction with the accompanying drawings can better understand the content of the embodiments of the present application. It should be emphasized that, according to standard practices in the industry, many components (features) are not drawn to scale. In fact, in order to clearly discuss, the sizes of various components may be arbitrarily increased or reduced.

[0008] Figure 1 is a schematic cross-sectional view of a fin field effect transistor (FinFET) according to some embodiments.

[0009] Figures 2 to 7 , 8A, 8B, 9A, 9B, 10A, 10B, 10C, 10D, 11A, 11B, 11C, 12A, 12B, 13A, and 13B are cross-sectional schematic diagrams of intermediate stages during the fabrication of a FinFET device according to some embodiments.

[0010] Fig.14 is a schematic diagram of a FinFET device processing process at an intermediate stage during FinFET device fabrication according to some embodiments.

[0011] Fig.15A , 15B , 16A, 16B, 17A, 17B, 18A, 18B, 19A, and 19B are cross-sectional diagrams of intermediate stages during fabrication of a FinFET device according to some embodiments.

[0012] Description of reference numerals:

[0013] 50~base;

[0014] 50B, 50C~ area;

[0015] 51~separator;

[0016] 52, 58~ fins;

[0017] 53~Process chamber;

[0018] 54~Insulation material;

[0019] 55~Processing;

[0020] 56~Isolation area;

[0021] 60~dummy dielectric layer;

[0022] 62~dummy gate layer;

[0023] 64~mask layer;

[0024] 72~dummy gate;

[0025] 74~Mask;

[0026] 80~gate sealing spacer;

[0027] 82~source / drain region;

[0028] 86~gate spacer;

[0029] 87~contact etch stop layer;

[0030] 88, 108 ~ interlayer dielectric;

[0031] 90~gate cavity;

[0032] 92~gate dielectric layer;

[0033] 94~gate electrode;

[0034] 110, 112 ~ contact piece;

[0035] AA, BB, CC~ sections;

[0036] H1, H2, H3, H4 ~ height;

[0037] L1, L2, L3, L4~length;

[0038] L5~gate length;

[0039] θ1, θ2 ~ angles. DETAILED DESCRIPTION

[0040] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present application. Specific examples of components and configurations are described below to simplify the embodiments of the present application. Of course, these are merely examples and are not intended to limit the embodiments of the present application. For example, if the description mentions that a first component is formed on or above a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the embodiments of the present application may reuse reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not represent a specific relationship between the different embodiments and / or configurations discussed.

[0041] In addition, the embodiments of the present application may use spatially relative terms, such as "under", "below", "below", "above", "above" and similar terms. These spatially relative terms are for the convenience of describing the relationship between one (some) element or component and another (some) element or component as shown in the figure. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used in the embodiments of the present application will also be interpreted according to the orientation after the turn.

[0042] Various embodiments provide semiconductor devices and methods for manufacturing semiconductor devices. In some embodiments, a dummy gate is formed, and a spacer is formed along the sidewall of the dummy gate. The dummy gate is removed, thereby forming a gate cavity having a sidewall, the sidewall being at least partially defined by the spacer. A portion of the exposed spacer sidewall is treated. In some embodiments, the treatment may include plasma treatment. The treatment may change the material composition of the portion of the spacer. In some embodiments, for example, because of the aspect ratio of the gate cavity, the treatment may penetrate deeper into the top of the spacer than the bottom of the spacer. Then, the treated portion of the spacer is removed. Because the treatment process penetrates deeper into the top of the spacer than the bottom of the spacer, removing the treated portion of the spacer may cause a larger portion of the top area of ​​the spacer to be removed than the bottom portion. Therefore, after removing the treated portion of the spacer, the length of the gate cavity in the top of the gate cavity may be widened at least. In addition, the gate cavity may have one or more tapered sidewalls. Next, a gate dielectric layer is deposited along the sidewalls and bottom surface of the gate cavity, and then the remaining portion of the gate cavity is filled by depositing one or more gate adjustment layers and one or more gate electrode layers in the gate cavity.

[0043] Due to the widening of the opening at the top of the gate cavity, it is easier to fill the gate cavity with one or more gate dielectric layers, one or more gate adjustment layers, and one or more gate electrodes. For example, in some processes where the gate cavity is filled with a multi-layer structure, such as a gate dielectric layer, a gate adjustment layer, or a gate electrode layer, when the gate cavity has a high aspect ratio, the filling of the gate cavity may result in one or more voids and / or seams in the filled metal portion. The inclusion of one or more voids or seams in the gate structure may result in reduced performance. For example, due to the presence of one or more voids or seams, the gate resistance of the gate structure may increase. Due to the presence of one or more voids or seams, the gate structure may experience increased delay. According to some embodiments, widening the gate cavity enables the gate cavity to be filled with reduced voids or seams, or without voids or seams. In this way, the performance of the gate structure can be improved.

[0044] The present application discusses various embodiments in a specific context, namely forming a fin field effect transistor. However, various embodiments may be applied to other semiconductor devices / processes, such as planar transistors and similar transistors.

[0045] Figure 1 An example of a fin field effect transistor is shown in a three-dimensional schematic diagram according to some embodiments. The fin field effect transistor includes a fin 58 on a substrate 50 (e.g., a semiconductor substrate). An isolation region 56 is disposed on the substrate 50, and the fin 58 protrudes from between adjacent isolation regions 56 and protrudes above the isolation region 56. Although the isolation region 56 is described / illustrated as being separated from the substrate 50, the term "substrate" used in the embodiments of the present application may refer only to a semiconductor substrate or a semiconductor substrate including an isolation region. A gate dielectric layer 92 is along the sidewalls of the fin 58 and above the top surface of the fin 58, and a gate electrode 94 is above the gate dielectric layer 92. The source / drain region 82 is disposed on both sides of the fin 58 relative to the gate dielectric layer 92 and the gate electrode 94.

[0046] Figure 1 Reference cross sections used in subsequent figures are further shown. Cross section AA is along the longitudinal axis of gate electrode 94 and is oriented, for example, perpendicular to the direction of current flow between source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and is along the longitudinal axis of fin 58 and is oriented, for example, in the direction of current flow between source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0047] Some embodiments discussed herein are discussed in the context of forming a FinFET using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate orientation for planar devices (e.g., planar FETs).

[0048] Figures 2 to 19A ∼B is a cross-sectional view of an intermediate stage of a FinFET manufacturing process according to some embodiments. Figures 2 to 7 Show Figure 1 Reference cross section AA is shown in FIG. , except for multiple fins / FinFETs. Fig. 8A 19A-B to 19A-B, the drawings ending with "A" are shown along the Figure 1 The reference section AA is shown, and the drawings ending with "B" are shown along Figure 1 A similar cross section to that of BB is shown, except for multiple fins / FinFETs. Fig. 10C , 10D and 11C are shown along Figure 1 Reference cross section CC shows the addition of multiple fins / FinFETs.

[0049] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate, and the substrate may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. In general, a semiconductor-on-insulator substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or a similar film layer. The insulating layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination of the foregoing.

[0050] The substrate 50 has a region 50B and a region 50C. The region 50B can be used to form an n-type device, such as an N-type metal oxide semiconductor (NMOS) transistor, such as an n-type fin field effect transistor. The region 50C can be used to form a p-type device, such as a P-type metal oxide semiconductor (PMOS) transistor, such as a p-type fin field effect transistor. The region 50B can be physically separated from the region 50C (as shown by a divider 51), and any number of device components (such as other active devices, doped regions, isolation structures, etc.) can be set between the region 50B and the region 50C. In some embodiments, both the region 50B and the region 50C are used to form the same type of device, for example, both regions are used for n-type devices or p-type devices.

[0051] exist Figure 3 In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. Etching can be any suitable etching process, such as reactive ion etching (RIE), neutron beam etching (NBE), similar etching processes, or combinations thereof. Etching can be anisotropic.

[0052] The fins 52 may be patterned by any suitable method. For example, the fins 52 may be patterned using one or more lithography processes, the lithography process including a double patterning or multiple patterning process. Typically, the double patterning or multiple patterning process combines lithography and a self-alignment process, for example, allowing the pitch of the pattern produced to be smaller than the pitch of the pattern obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate, and the sacrificial layer is patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 52.

[0053] exist Figure 4In the embodiment, an insulating material 54 is formed above the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide, such as silicon oxide, nitride, a similar material, or a combination of the foregoing, and the formation of the insulating material 54 can be by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (flowable CVD, FCVD), or a combination of the foregoing. Other insulating materials formed by any suitable method can be used. In the embodiment shown, the insulating material 54 is silicon oxide formed by a flowable chemical vapor deposition process. In one embodiment, the insulating material 54 is formed so that excess insulating material 54 covers the fins 52.

[0054] exist Figure 5 In some embodiments, a planarization process is applied to the insulating material 54. In some embodiments, the planarization process includes chemical mechanical polishing (CMP), an etch back process, a combination of the foregoing, or a similar process. The planarization process may expose the fin 52. In an embodiment where the planarization process exposes the fin 52, after the planarization process is completed, the top surfaces of the fin 52 and the insulating material 54 may be flush. In some other embodiments, a metal pad (not shown) and / or a mask layer (not shown) may be provided along the top surface of the fin 52. In this case, the planarization process may expose the metal pad or the mask layer, and after the planarization process is completed, the insulating material 54 may be flush with the top surface of the metal pad or the mask layer.

[0055] exist Figure 6 In the embodiment, the insulating material 54 is etched back to form a shallow trench isolation (STI) region (also referred to as an isolation region) 56. The insulating material 54 is etched back so that the fins 58 in the region 50B and the region 50C protrude from between adjacent shallow trench isolation regions 56. In addition, the top surface of the shallow trench isolation region 56 may have a flat surface, a convex surface, a concave surface (e.g., a dishing) as shown in the figure, or a combination of the foregoing. The top surface of the shallow trench isolation region 56 may be formed to be flat, convex, and / or concave by suitable etching. The shallow trench isolation region 56 may be etched back using a suitable etching process, such as an etching process that is selective to the material of the insulating material 54. For example, using Etch or Applied Materials SICONI equipment or chemical oxide removal with dilute hydrofluoric (dHF).

[0056] Further in Figure 6 In the embodiment of the present invention, appropriate wells (not shown) may be formed in fin 58, fin 52, and / or substrate 50. In some embodiments, a P-type well may be formed in region 50B, and an N-type well may be formed in region 50C. In some embodiments, a P-type well or an N-type well is formed in both region 50B and region 50C.

[0057] In embodiments with different well types, photoresist or other masks (not shown) may be used to implement different implantation steps for region 50B and region 50C. For example, a photoresist may be formed over fin 58 and shallow trench isolation region 56 in region 50B. The photoresist is patterned to expose region 50C (e.g., a PMOS region) of substrate 50. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using a suitable lithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in region 50C, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into region 50B (e.g., an NMOS region). The n-type impurity may be phosphorus, arsenic, or a similar impurity, implanted into the region at a concentration equal to or less than 10 18 cm -3 , for example about 10 17 cm -3 to about 10 18 cm -3 After implantation, the photoresist is removed, for example, by a suitable ashing process.

[0058] After implantation of region 50C, a photoresist is formed over fin 58 and shallow trench isolation region 56 in region 50C. The photoresist is patterned to expose region 50B (e.g., NMOS region) of substrate 50. The photoresist may be formed using a spin coating technique, and may be patterned using a suitable lithography technique. Once the photoresist is patterned, p-type impurity implantation may be performed in region 50B, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into region 50C (e.g., PMOS region). The p-type impurity may be boron, BF2, or a similar impurity, implanted into the region at a concentration equal to or less than 10 18 cm -3 , for example about 10 17 cm -3 to about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by a suitable ashing process.

[0059] After implanting regions 50B and 50C, an anneal may be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the growing material of the epitaxial fins may be doped in situ during growth, which may eliminate implantation, but both in situ and implant doping may be used together.

[0060] exist Figure 7 In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 58. For example, the dummy dielectric layer 60 may be silicon oxide, silicon nitride, a combination of the foregoing, or a similar material, and the dummy dielectric layer 60 may be deposited or thermally grown according to a suitable technique. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 may be deposited over the dummy dielectric layer 60, and then the dummy gate layer 62 may be planarized, such as by a chemical mechanical polishing process. The mask layer 64 may be deposited over the dummy gate layer 62. The dummy gate layer 62 may be a conductive material, and may be selected from a group including polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. In one embodiment, amorphous silicon is deposited, and the amorphous silicon is recrystallized to produce polycrystalline silicon. The deposition of the dummy gate layer 62 can be by physical vapor deposition (PVD), chemical vapor deposition, sputtering deposition or other techniques known in the art and used to deposit conductive materials. The dummy gate layer 62 can be formed of other materials with high etching selectivity to the etching of the isolation region. The mask layer 64 can include, for example, SiN, SiON or similar materials. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed to span the region 50B and the region 50C. In some embodiments, separate dummy gate layers can be formed in the region 50B and the region 50C, and separate mask layers can be formed in the region 50B and the region 50C.

[0061] Fig. 8A 19A-B through 19A-B illustrate various additional steps during the manufacture of the embodiment device. Fig. 8A 19A-B to 19B-B show components in any one of the regions 50B and 50C. For example, Fig. 8A The structures shown in 19A-B to 19A-B are applicable to both region 50B and region 50C. The text accompanying each figure describes the differences, if any, in the structures of region 50B and region 50C.

[0062] In FIGS. 8A and 8B , the mask layer 64 may be patterned using suitable lithography and etching techniques to form a mask 74. Then, the pattern of the mask 74 may be transferred to the dummy gate layer 62 and the dummy dielectric layer 60 using suitable etching techniques to form a dummy gate 72. The dummy gate 72 covers each channel region of the fin 58. The pattern of the mask 74 may be used to physically separate each dummy gate 72 from an adjacent dummy gate. The length direction of the dummy gate 72 may also be substantially perpendicular to the length direction of the corresponding epitaxial fin 52 / 58.

[0063] Further in Fig. 8A and 8B In the embodiment, a gate sealing spacer 80 may be formed on the dummy gate 72, the mask 74 and the fin 58. The gate sealing spacer 80 may be formed by thermal oxidation or deposition followed by anisotropic etching.

[0064] After forming the gate sealing spacer 80, implantation for lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. Figure 6 As discussed above, a mask such as a photoresist may be formed over region 50B while exposing region 50C, and an appropriate type of impurity (e.g., n-type or p-type) may be implanted into exposed fins 58 in region 50C. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over region 50C while exposing region 50B, and an appropriate type of impurity may be implanted into exposed fins 58 in region 50B. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a thickness of about 10 15 cm -3 to about 10 16 cm -3 Annealing can be used to activate the implanted impurities.

[0065] exist Fig. 9A and 9B In the embodiment, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing a material and then anisotropically etching the material. The material of the gate spacer 86 can be silicon nitride, SiCN, a combination of the foregoing, or a similar material.

[0066] exist Figures 10A to 10DIn the embodiment of the present invention, epitaxial source / drain regions 82 are formed in the fin 58. The epitaxial source / drain regions 82 are formed in the fin 58 so that each dummy gate 72 is disposed between respective adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fin 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit the gate of a subsequently formed FinFET.

[0067] The formation of the epitaxial source / drain region 82 in the region 50B (e.g., NMOS region) can be performed by masking the region 50C (e.g., PMOS region) and etching the source / drain region of the fin 58 in the region 50B to form a groove in the fin 58. Then, the epitaxial source / drain region 82 in the region 50B is epitaxially grown in the groove. The epitaxial source / drain region 82 can include any suitable material, such as suitable for an n-type fin field effect transistor. For example, if the fin 58 is silicon, the epitaxial source / drain region 82 in the region 50B can include silicon, SiC, SiCP, SiP, or a similar material. The epitaxial source / drain region 82 in the region 50B can have a surface protruding from the corresponding surface of the fin 58 and can have facets.

[0068] The formation of the epitaxial source / drain region 82 in region 50C (e.g., a PMOS region) can be performed by shielding region 50B (e.g., an NMOS region) and etching the source / drain region of the fin 58 in region 50C to form a recess in the fin 58. Then, the epitaxial source / drain region 82 in region 50C is epitaxially grown in the recess. The epitaxial source / drain region 82 can include any suitable material, such as a p-type fin field effect transistor. For example, if the fin 58 is silicon, the epitaxial source / drain region 82 in region 50C can include SiGe, SiGeB, Ge, GeSn, or a similar material. The epitaxial source / drain region 82 in region 50C can also have a surface protruding from the corresponding surface of the fin 58 and can have a facet.

[0069] The source / drain regions 82 and / or the fins 58 may be formed by implanting the epitaxial source / drain regions 82 with dopants, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions may be about 10 19 cm -3 to about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 may be doped in-situ during growth.

[0070] Since an epitaxial process is used to form epitaxial source / drain regions 82 in regions 50B and 50C, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of the fins. Fig. 10C As shown, these facets allow adjacent source / drain regions 82 of the same fin field effect transistor to merge. Fig. 10D As shown, adjacent source / drain regions 82 remain separated after the epitaxial process is completed.

[0071] exist Fig.11A , 11B and 11C, in Figures 10A to 10D An interlayer dielectric (ILD) 88 is deposited over the structure shown. The interlayer dielectric 88 may be formed of a dielectric material or a semiconductor material, and the deposition of the interlayer dielectric 88 may be by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. The semiconductor material may include amorphous silicon, silicon germanium (Si x Ge 1-x , where x can be between about 0 and 1), pure germanium or similar materials. In some embodiments, oxide or nitride films can be used. Other insulating or semiconductor materials formed by any suitable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the interlayer dielectric 88 and the epitaxial source / drain regions 82, the hard mask 74, and the gate spacer 86. The contact etch stop layer 87 can include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or similar materials.

[0072] exist Fig. 12A and 12BIn the process, a planarization process such as chemical mechanical polishing may be performed to make the top surface of the interlayer dielectric 88 flush with the top surface of the dummy gate 72. The planarization process may also remove the mask 74 on the dummy gate 72 and a portion of the gate sealing spacer 80 and the gate spacer 86 along the sidewall of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the interlayer dielectric 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the interlayer dielectric 88.

[0073] exist Fig.13A and 13B In one or more etching steps, the dummy gate 72 is removed to form a gate cavity 90. In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 without etching the interlayer dielectric 88, the gate sealing spacer 80, or the gate spacer 86. Each gate cavity 90 exposes the upper surface of the dummy dielectric layer 60. During the removal, when etching the dummy gate 72, the dummy dielectric layer 60 may serve as an etch stop layer. Fig.13A and 13B As shown, the sidewalls of the gate cavity 90 are defined by the gate sealing spacer 80 .

[0074] In some embodiments, the gate height H1 may be from about 30 nanometers to about 100 nanometers. In some embodiments, the height H2 of the top surface of the fin 58 may be from about -15 nanometers to about +15 nanometers relative to the top surface of the epitaxial source / drain region 82. In some embodiments, the height H3 of the fin 58 above the substrate 50 may be from about 20 nanometers to about 50 nanometers. The length L1 of the gate cavity 90 may be from about 4 nanometers to about 24 nanometers. In some embodiments, the length L2 of the gate sealing spacer 80 may be from about 15 nanometers to about 35 nanometers. In some embodiments, the length L3 of the gate spacer 86 may be from about 15 nanometers to about 35 nanometers.

[0075] As the following combination Fig.16A As described in Figure 1-B, in a subsequent process, the gate cavity 90 is filled to form a gate structure. During the manufacture of some FinFET devices, the filling of the gate cavity 90 may produce one or more pores or seams in the gate structure. For example, in some FinFET devices, it may be necessary to reduce the length of the gate structure. Reducing the length of the gate structure may allow the gate cavity 90 to have a high aspect ratio, which may help the formation of seams or pores in the gate structure in some cases. For example, in some embodiments, according to the combination of Fig.13A and 13BIn the aspect ratios that the gate cavity 90 fabricated with the discussed dimensions may have, filling the gate cavity 90 may result in one or more voids and / or seams in the filled gate cavity 90. The seams and / or voids generated in the gate structure may result in reduced performance of the FinFET device. For example, the seams or voids may increase gate resistance and / or result in delayed electrical performance of the FinFET device.

[0076] According to some embodiments, at least some portions of the gate sealing spacer 80 may be processed. In a subsequent process, the processed portions of the gate sealing spacer 80 may be removed. Processing and removing the portions of the gate sealing spacer may change the profile of the gate cavity 90, such as widening the opening of the gate cavity 90, where the gate cavity 90 may be filled through the opening of the gate cavity 90. In some embodiments, the gate cavity 90 with the widened opening may be filled with reduced seams or pores, and in some embodiments may be filled without seams or pores. Thus, the performance of the FinFET device may be improved.

[0077] Fig.14 Depicting applying treatment 55 to gate seal spacer 80. In some embodiments, the fabricated fin field effect transistor device is placed in a process chamber 53 for treatment 55. Treatment 55 may be a plasma treatment. In some embodiments, treatment 55 may include an inductively coupled plasma (ICP) treatment. For example, plasma may be introduced into treatment chamber 53, a desired electrical power may be applied to treatment chamber 53, and a desired pressure may be generated in treatment chamber 53 so that the plasma reacts with a portion of gate seal spacer 80. In some embodiments, for example, because of the aspect ratio of gate cavity 90, the plasma may not penetrate to the bottom of gate cavity 90, or may penetrate to the bottom of gate cavity 90 only in a small concentration. During treatment 55, the plasma concentration in gate cavity 90 may vary depending on the height of gate cavity 90. Therefore, the penetration distance of plasma into gate seal spacer 80 may vary depending on the height of gate seal spacer 80.

[0078] In some embodiments, the plasma can be formed by a gas. For example, in some embodiments, a combination of oxygen (O2) and an inert gas (e.g., nitrogen (N2), helium (He), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe)) can be used to form a plasma for processing 55. In some embodiments, the ratio of oxygen to the inert gas can be about 10% to about 90%. In some embodiments, the desired electrical power can be about 200 watts (Watt) to 2000 watts. In some embodiments, the processing time can be about 10 seconds to about 120 seconds. In some embodiments, the desired pressure can be about 5 mTorr (mTorr) to about 200 mTorr.

[0079] like Fig.14 As shown, the process 55 can change the material composition of a portion of the gate sealing spacer 80. The top of the gate sealing spacer 80 farthest from the substrate 50 can be changed throughout the gate sealing spacer 80, while the bottom of the gate sealing spacer 80 can be changed only slightly along the surface of the gate sealing spacer 80 facing the gate cavity 90. In some embodiments, the penetration distance of the process 55 into the gate sealing spacer 80 can be changed according to the height within the gate cavity 90, with the maximum penetration distance located at the top of the gate sealing spacer 80 and the minimum penetration distance located within the gate cavity 90 (e.g., at the bottom of the gate sealing spacer 80, or along the lowest point of the gate sealing spacer 80, where the plasma is present in the process 55). In some embodiments, the penetration distance of the process 55 into the gate sealing spacer can be changed according to the height, and such a change can form an angle θ1 relative to the inner sidewall of each gate sealing spacer 80. In some embodiments, θ1 can be about 3 degrees to about 50 degrees.

[0080] As previously described, the process 55 may change the material composition of a portion of the gate sealing spacer 80. Prior to the process 55, the gate sealing spacer 80 may include Si 1-x-y-z O x N y C z , wherein x is about 45%±15%, y is about 15%±15%, and z is 10%±10%. After the process 55, the gate sealing spacer 80 may include a changed portion and an unchanged portion. In the changed portion where the material composition of the gate sealing spacer 80 is changed in the process 55, the changed portion may include Si 1-x-y- z O x N y C z , where x is about 55% ± 15%, y is about 10% ± 10%, and z is 5% ± 5%. Process 55 does not penetrate the unchanged portion, and the material composition of the gate sealing spacer remains Si 1-x-y-z Ox N y C z , wherein x is approximately 45%±15%, y is approximately 15%±15%, and z is approximately 10%±10%, and may be the same as the material composition of the gate sealing spacer 80 before the process 55 .

[0081] In some embodiments, the material composition of gate spacer 86 may remain unchanged after processing 55. For example, before processing 55, gate spacer may include Si 1-x-y-z O x N y C z , wherein x is about 45% ± 15%, y is about 15% ± 15%, and z is about 10% ± 10%. After processing 55, gate spacer 86 may still include Si 1-x-y-z O x N y C z , where x is about 45%±15%, y is about 15%±15%, and z is 10%±10%, and the material composition may be the same.

[0082] exist Fig.15A and 15B In the embodiment of the present invention, a portion of the dummy dielectric layer 60 exposed by the gate cavity 90 and a processed portion of the gate sealing spacer 80 are removed in one or more etching steps. In some embodiments, a portion of the dummy dielectric layer 60 exposed by the gate cavity 90 and a processed portion of the gate sealing spacer 80 are removed simultaneously by a single etching process (e.g., an anisotropic dry etching process). For example, the etching process may include a dry etching process using a reactive gas, and the reactive gas selectively etches a portion of the dummy dielectric layer 60 exposed by the gate cavity 90 and a processed portion of the gate sealing spacer 80, without etching the gate spacer 86 or an unprocessed portion of the gate sealing spacer 80.

[0083] like Fig.15A and 15BAs shown, removing the processed portion of the gate sealing spacer 80 produces a tapered sidewall of the gate cavity 90, which is defined by the unprocessed portion of the gate sealing spacer 80. After removing the processed portion of the gate sealing spacer 80, the thickness of the remaining portion of the gate sealing spacer 80 can vary according to the height, wherein the thinnest portion is located at the top of the gate cavity 90, and the thickest portion is further into the gate cavity 90, such as at the bottom of the gate cavity 90. The gate cavity 90 can be partially defined by the gate spacer 86, such as at the top of the gate cavity 90. Removing the processed portion of the gate sealing spacer 80 widens the top opening of the gate cavity. In some embodiments, after the treatment 55, the length L4 of the top opening of the gate cavity 90 can be about 0 nanometers to about 6.0 nanometers. In some embodiments, the treatment 55 of a portion of the gate sealing spacer 80 and the subsequent removal of the processed portion of the gate sealing spacer 80 can increase the length of the top opening of the gate cavity 90 by about 0% to about 30%.

[0084] exist Fig.16A and 16B In the embodiment of the present invention, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. The gate dielectric layer 92 is conformally deposited in the groove (also known as the gate cavity) 90, for example, on the top surface and sidewalls of the fin 58 and on the sidewalls of the gate sealing spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the interlayer dielectric 88. According to some embodiments, the gate dielectric layer 92 comprises silicon oxide, silicon nitride, or a multilayer structure of the foregoing. In some embodiments, the gate dielectric layer 92 is a high dielectric constant (high-k) dielectric material, and in these embodiments, the dielectric constant value of the gate dielectric layer 92 may be greater than about 7.0, and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The method for forming the gate dielectric layer 92 may include molecular beam deposition (MBD), atomic layer deposition, plasma enhanced chemical vapor deposition, and similar processes.

[0085] A plurality of gate electrodes 94 are deposited over the plurality of gate dielectric layers 92, respectively, and fill the remaining portion of the recess 90. The gate electrode 94 may be a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, a combination thereof, or a multilayer structure thereof. For example, although a single gate electrode 94 is shown, any number of work function adjustment layers may be deposited in the recess 90.

[0086] The formation of gate dielectric layer 92 may occur simultaneously in region 50B and region 50C, such that gate dielectric layer 92 in each region is formed of the same material, and the formation of gate electrode 94 may occur simultaneously, such that gate electrode 94 in each region is formed of the same material. In some embodiments, gate dielectric layer 92 in each region may be formed by a different process, such that gate dielectric layer 92 may be a different material, and gate electrode 94 in each region may be formed by a different process, such that gate electrode 94 may be a different material. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0087] exist Fig.17A and 17B In the process, a planarization process such as chemical mechanical polishing can be performed to remove the material of the gate electrode 94 and the excess portion of the gate dielectric layer 92 located above the top surface of the interlayer dielectric 88. The remaining portion of the gate dielectric layer 92 and the material of the gate electrode 94 thus form a replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 can be collectively referred to as a "gate", "gate stack" or "gate structure". The gate structure can extend along the sidewalls of the channel region of the fin 58.

[0088] The planarization process may continue until the height H4 of the gate structure above the fin 58 is a desired height. In some embodiments, the desired height H4 is about 10 nanometers to about 30 nanometers. After the planarization process, the gate structure may include tapered sidewalls. For example, the gate dielectric layer 92 and the gate electrode 94 may include tapered sidewalls. Fig. 17B As shown, the tapered sidewalls may form an angle θ2 relative to a direction perpendicular to the major surface of the substrate 50. In some embodiments, θ2 is about 3 degrees to about 50 degrees. In some embodiments, θ2 is substantially the same as θ1 (as described above in conjunction with Fig.14 ). The gate length L5 of the gate structure along the bottom surface of the gate structure closest to the fin 58 may be equal to the length L1 of the gate cavity 90 (shown in Fig. 13B ) are substantially the same. For example, the gate length L5 of the gate structure along the bottom surface of the gate structure can be about 4 nanometers to about 24 nanometers.

[0089] In some embodiments, widening the top opening of the gate cavity 90 can allow the gate dielectric layer 92 and / or the gate electrode 94 to be more easily deposited in the gate cavity 90. For example, in some embodiments, the gate dielectric layer 92 and / or the gate electrode 94 can be deposited with fewer pores or seams or without pores or seams. Therefore, the resistance of the gate structure can be reduced and / or the performance of the FinFET device can be improved. In some embodiments, the resistance of the gate structure can be reduced by about 10% to about 20%. In some embodiments, the seam defects of the gate structure can be reduced from about 578 defects in each gate structure to about 4 defects in each gate structure. In some embodiments, the manufacturing yield can be improved.

[0090] exist Fig.18A and 18B In the embodiment, interlayer dielectric 108 is deposited over interlayer dielectric 88. In one embodiment, interlayer dielectric 108 is a flowable film formed by a flowable chemical vapor deposition method. In some embodiments, interlayer dielectric 108 is formed of, for example, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and can be deposited by any suitable method, such as chemical vapor deposition and plasma enhanced chemical vapor deposition.

[0091] exist Fig.19A and 19B In the embodiment of the present invention, contacts 110 and 112 are formed via interlayer dielectric 108 and interlayer dielectric 88. In some embodiments, contacts 110 and 112 are formed of tungsten, but any suitable metal material may be used. In some embodiments, before forming contact 112, an annealing process may be performed to form silicide at the interface between epitaxial source / drain region 82 and contact 112. Contact 110 is physically and electrically connected to gate electrode 94, and contact 112 is physically and electrically connected to epitaxial source / drain region 82. Fig.19A and 19B The contacts 110 and 112 are shown in the same cross-section; however, in other embodiments, the contacts 110 and 112 may be arranged in different cross-sections. Fig.19A and 19B The positions of the contacts 110 and 112 in the figure are merely illustrative and are not limited in any way. For example, the contact 110 can be vertically aligned with the fin 52 as shown, or can be disposed at a different position on the gate electrode 94. In addition, the contact 112 can be formed before, at the same time, or after the contact 110 is formed.

[0092] As described in the embodiments of the present application, in some embodiments, a dummy gate is formed, and a spacer is formed along the sidewall of the dummy gate. The dummy gate is removed, thereby forming a gate cavity having a sidewall, which is at least partially defined by the spacer. A portion of the exposed spacer sidewall is treated. In some embodiments, the treatment may include plasma treatment. The treatment may change the material composition of a portion of the spacer. In some embodiments, for example, because of the depth-to-width ratio of the gate cavity, the treatment may penetrate deeper into the top of the spacer than the bottom of the spacer. Then remove the treated portion of the spacer. Because the treatment process penetrates deeper into the top of the spacer than the bottom of the spacer, removing the treated portion of the spacer may cause the top area of ​​the spacer to be removed more than the bottom portion. Therefore, after removing the treated portion of the spacer, the length of the gate cavity in the top of the gate cavity may be widened at least. In addition, the gate cavity may have one or more tapered sidewalls. Next, a gate dielectric layer is deposited along the sidewalls and bottom surface of the gate cavity, and then the remaining portion of the gate cavity is filled by depositing one or more gate adjustment layers and one or more gate electrode layers in the gate cavity.

[0093] Due to the widening of the opening in the top of the gate cavity, it is easier to fill the gate cavity with one or more gate adjustment layers and one or more gate electrodes. For example, in some processes where the gate cavity is filled with a metal layer, where the metal layer is, for example, a gate adjustment layer or a gate electrode layer, when the cavity has a high aspect ratio, the filling of the gate cavity may result in one or more pores and / or seams in the filled metal portion. A gate structure including pores or seams may experience reduced performance. For example, due to the presence of pores or seams, the gate resistance of the gate structure may increase. Due to the presence of pores or seams, the gate structure may experience increased delay. According to some embodiments, widening the gate cavity enables the gate cavity to be filled with reduced pores or seams or without pores or seams. In this way, the performance of the gate structure can be improved.

[0094] A method is provided according to some embodiments. The method includes forming a dummy dielectric layer over a substrate; forming a dummy gate over the dummy dielectric layer; forming a first spacer adjacent to the dummy gate; removing the dummy gate to form a cavity, wherein the cavity is at least partially defined by the first spacer; plasma treating a plurality of portions of the first spacer, wherein the plasma treating changes the material composition of the portions of the first spacer from the first material composition to the second material composition; etching the portion of the first spacer having the second material composition to remove the portion of the first spacer having the second material composition; and filling the cavity with a plurality of conductive materials to form a gate structure. In one embodiment, the gate structure extends along a remaining portion of the first spacer. In one embodiment, the method further includes etching the dummy dielectric layer, wherein the dummy dielectric layer and the portion of the first spacer having the second material composition are etched in a single etching process. In one embodiment, the penetration depth of the plasma treatment into the first spacer varies according to the height of the first spacer. In one embodiment, the portion of the first spacer having the second material composition is etched to remove the portion of the first spacer having the second material composition, so that the remaining portion of the first spacer has a tapered sidewall, wherein the tapered sidewall faces the cavity. In one embodiment, a first tapered sidewall of the tapered sidewall forms an angle relative to a direction perpendicular to the main surface of the substrate, and the angle is in a range of 3 degrees to 50 degrees. In one embodiment, the portion of the first spacer having the second material composition is etched to remove the portion of the first spacer having the second material composition, so that the top opening of the cavity is widened. In one embodiment, the cavity is filled with a plurality of conductive materials through the top opening. In one embodiment, the first material composition includes oxygen having a first concentration, the second material composition includes oxygen having a second concentration, and the second concentration is greater than the first concentration. In one embodiment, the first material composition includes nitrogen having a third concentration and carbon having a fourth concentration, the second material composition includes nitrogen having a fifth concentration and carbon having a sixth concentration, and the fifth concentration is less than the third concentration, and the sixth concentration is less than the fourth concentration.

[0095] According to some embodiments, a method is provided. The method includes depositing a dummy gate over a dummy dielectric layer and patterning the dummy gate; forming a plurality of spacers to surround the dummy gate; etching the dummy gate to form a gate cavity, the gate cavity being defined by the plurality of spacers; performing a plasma treatment on at least a portion of a first spacer of the spacers, wherein the portion of the first spacer is a portion of the first spacer farthest from the dummy dielectric layer; performing an etching process to remove the portion of the first spacer and a portion of the dummy dielectric layer, wherein after the etching process is completed, a top opening of the gate cavity is widened; depositing one or more gate dielectric layers and one or more gate electrode layers in the gate cavity through the top opening to form a gate structure; and forming an interlayer dielectric (ILD) to surround the spacers. In one embodiment, the method further includes performing a planarization process to planarize the interlayer dielectric and the gate structure. In one embodiment, after the planarization process is performed, the sidewalls of the one or more gate dielectric layers extend at an angle relative to a direction perpendicular to a planarized surface of the interlayer dielectric, and the angle is between 3 degrees and 50 degrees. In one embodiment, an etching process is performed to remove a portion of the first spacer, leaving a remaining portion of the first spacer with a tapered sidewall. In one embodiment, the one or more gate dielectric layers and the one or more gate electrode layers include a tapered sidewall along a portion of the one or more gate dielectric layers and the one or more gate electrode layers that extends along the remaining portion of the first spacer. In one embodiment, the plasma treatment changes the material composition of the portion of the first spacer from a first material composition to a second material composition.

[0096] According to some embodiments, a device is provided. The device includes a plurality of source / drain regions formed in a substrate; a gate structure above the substrate between the source / drain regions, wherein the gate structure includes one or more gate dielectric layers and one or more gate electrode layers; and a plurality of spacers surrounding the gate structure, wherein a first spacer of the spacers contacts the one or more gate dielectric layers, wherein the first spacer has a first thickness at a first position and a second thickness at a second position, wherein the first position is farthest from the substrate, and the second position is between the first position and the substrate, and wherein a first sidewall of the first spacer contacting the one or more gate dielectric layers extends at an angle between the first position and the second position, the angle being relative to a direction perpendicular to a major surface of the substrate, and the angle being greater than or equal to 3 degrees. In one embodiment, the sidewall of the one or more gate dielectric layers contacting the first spacer extends at the same angle as the first sidewall of the first spacer. In one embodiment, the second sidewall of the first spacer extends in a direction perpendicular to the major surface of the substrate, the second sidewall being opposite to the first sidewall. In one embodiment, the thickness of the first spacer varies according to a height of the first spacer between the first position and the second position, wherein the height is in a direction perpendicular to the major surface of the substrate.

[0097] The above summarizes the components of several embodiments so that technicians in the technical field of the application can better understand the aspects of the embodiments of the present application. Technicians in the technical field of the application should understand that they can design or modify other processes and structures based on the embodiments of the present application to achieve the same purposes and / or advantages as the embodiments introduced herein. Technicians in the technical field of the application should also understand that such equivalent structures do not deviate from the concept and scope of the embodiments of the present application, and they can make various changes, substitutions and replacements without violating the concept and scope of the embodiments of the present application.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a dummy dielectric layer over a substrate; forming a dummy gate above the dummy dielectric layer; forming a first spacer adjacent to the dummy gate; removing the dummy gate to form a cavity, wherein the cavity is at least partially defined by the first spacer; performing a plasma treatment on a plurality of portions of the first spacer, wherein the plasma treatment changes the material composition of the portions of the first spacer from a first material composition to a second material composition; Etching the portions of the first spacer composed of the second material to remove the portions of the first spacer composed of the second material; as well as The cavity is filled with a plurality of conductive materials to form a gate structure. 2 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the gate structure extends along a remaining portion of the first spacer. 3 . The method for manufacturing a semiconductor device as claimed in claim 1 , further comprising etching the dummy dielectric layer, wherein the dummy dielectric layer and the portions of the first spacer composed of the second material are etched in a single etching process. 4 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein a penetration depth of the plasma treatment into the first spacer varies according to a height of the first spacer.

5. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the portions of the first spacer composed of the second material are etched to remove the portions of the first spacer composed of the second material, so that the remaining portion of the first spacer has a plurality of tapered sidewalls, wherein the tapered sidewalls face the cavity. 6 . The method for manufacturing a semiconductor device as claimed in claim 5 , wherein a first tapered sidewall of the tapered sidewalls forms an angle with respect to a direction perpendicular to a main surface of the substrate, and the angle is in a range of 3 degrees to 50 degrees. 7 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the portions of the first spacer composed of the second material are etched to remove the portions of the first spacer composed of the second material, so that a top opening of the cavity is widened. 8 . The method for manufacturing a semiconductor device as claimed in claim 7 , wherein the cavity is filled with the conductive materials through the top opening. 9 . The method for manufacturing a semiconductor device according to claim 1 , wherein the first material composition includes oxygen having a first concentration, and the second material composition includes oxygen having a second concentration, and wherein the second concentration is greater than the first concentration.

10. The method for manufacturing a semiconductor device as described in claim 9, wherein the first material composition includes nitrogen having a third concentration and carbon having a fourth concentration, and the second material composition includes nitrogen having a fifth concentration and carbon having a sixth concentration, and wherein the fifth concentration is less than the third concentration, and the sixth concentration is less than the fourth concentration.

11. A method for manufacturing a semiconductor device, comprising: Depositing a dummy gate over a dummy dielectric layer and patterning the dummy gate; forming a plurality of spacers surrounding the dummy gate; etching the dummy gate to form a gate cavity defined by a plurality of spacers; performing a plasma treatment on at least a portion of a first spacer of the spacers, wherein the portion of the first spacer is a portion of the first spacer farthest from the dummy dielectric layer; After performing the plasma treatment, performing an etching process to remove the portion of the first spacer and a portion of the dummy dielectric layer, wherein after completing the etching process, a top opening of the gate cavity becomes wider; depositing one or more gate dielectric layers and one or more gate electrode layers in the gate cavity through the top opening to form a gate structure; and An inter-layer dielectric is formed to surround the spacers. 12 . The method for manufacturing a semiconductor device as claimed in claim 11 , further comprising performing a planarization process to planarize the interlayer dielectric and the gate structure.

13. The method for manufacturing a semiconductor device as claimed in claim 12, wherein after the planarization process is performed, the sidewalls of the one or more gate dielectric layers extend at an angle relative to a direction perpendicular to a planarized surface of the interlayer dielectric, and the angle is between 3 degrees and 50 degrees. 14 . The method for manufacturing a semiconductor device as claimed in claim 11 , wherein the etching process is performed to remove the portion of the first spacer, so that the remaining portion of the first spacer has a plurality of tapered sidewalls.

15. A method for manufacturing a semiconductor device as described in claim 11, wherein the one or more gate dielectric layers and the one or more gate electrode layers include a plurality of tapered sidewalls along a plurality of portions of the one or more gate dielectric layers and the one or more gate electrode layers, which extend along the remaining portion of the first spacer. 16 . The method for manufacturing a semiconductor device as claimed in claim 11 , wherein the plasma treatment changes the material composition of the portion of the first spacer from a first material composition to a second material composition.

17. A method for manufacturing a semiconductor device, comprising: forming a first dielectric layer over a substrate; forming a dummy gate above the first dielectric layer; forming a first spacer along a side wall of the dummy gate; forming a second dielectric layer along a first sidewall of the first spacer, wherein the first spacer is between the second dielectric layer and the dummy gate; removing the dummy gate to expose a second sidewall of the first sidewall; treating the first spacer to form a treated portion of the first spacer, wherein a remaining portion of the first spacer forms an untreated portion of the first spacer, wherein the treated portion of the first spacer has a higher oxygen content than the untreated portion of the first spacer; as well as A gate electrode is formed, wherein the unprocessed portion of the first spacer is between the gate electrode and the second dielectric layer.

18. The method for manufacturing a semiconductor device according to claim 17, wherein the treatment comprises plasma treatment using oxygen and an inert gas.

19. The method for manufacturing a semiconductor device as described in claim 17, wherein a first thickness of the processed portion of the first spacer above a first height of the substrate is smaller than a second thickness of the processed portion of the first spacer above a second height of the substrate, wherein the first height is smaller than the second height. 20 . The method for manufacturing a semiconductor device according to claim 17 , further comprising removing the processed portion of the first spacer after performing the processing.

21. A semiconductor device comprising: A plurality of source / drain regions are formed in a substrate; a gate structure over the substrate between the source / drain regions, wherein the gate structure comprises one or more gate dielectric layers and one or more gate electrode layers; and A plurality of spacers surround the gate structure, wherein a first spacer of the spacers contacts the one or more gate dielectric layers, wherein the first spacer has a first thickness at a first position and a second thickness at a second position, wherein the first position is farthest from the substrate, and the second position is between the first position and the substrate, and wherein a first sidewall of the first spacer contacting the one or more gate dielectric layers extends at an angle between the first position and the second position, the angle being relative to a direction perpendicular to a major surface of the substrate, and the angle being greater than or equal to 3 degrees. 22 . The semiconductor device of claim 21 , wherein a sidewall of the one or more gate dielectric layers contacting the first spacer extends at the same angle as the first sidewall of the first spacer. 23 . The semiconductor device of claim 21 , wherein a second sidewall of the first spacer extends in the direction perpendicular to the main surface of the substrate, the second sidewall being opposite to the first sidewall.

24. The semiconductor device of claim 21, wherein a thickness of the first spacer varies according to a height of the first spacer between the first position and the second position, wherein the height is in the direction perpendicular to the main surface of the substrate.

25. The semiconductor device of claim 21, wherein the first spacer comprises SiONC.

26. The semiconductor device of claim 21, wherein the first spacer comprises Si 1-x-y-z O x N y C z , where x is 45% ± 15%, y is 15% ± 15% and z is 10% ± 10%.

27. The semiconductor device of claim 21, wherein the spacers include a second spacer, wherein the first spacer is between the second spacer and the one or more gate dielectric layers, and wherein the second spacer directly contacts the one or more gate dielectric layers.

28. The semiconductor device of claim 21, further comprising a dielectric layer, wherein the dielectric layer is interposed between the spacers and the substrate.

29. A semiconductor device comprising: A first source / drain region and a second source / drain region are formed in a substrate; a gate structure over the substrate between the first source / drain region and the second source / drain region, wherein the gate structure comprises a gate dielectric layer and one or more conductive layers over the gate dielectric layer; a first spacer on a sidewall of the gate structure; as well as A second spacer is on a first sidewall of the first spacer opposite to the gate structure, wherein in a cross-sectional view, a second sidewall of the first spacer tapers at an angle greater than or equal to 3 degrees relative to a line perpendicular to a surface of the substrate. 30 . The semiconductor device of claim 29 , wherein a width of an upper surface of the gate structure in the cross-sectional view is 0% to 30% greater than a width of a lower surface of the gate structure in the cross-sectional view.

31. The semiconductor device of claim 29, wherein a thickness of the first spacer decreases as the first spacer moves away from the substrate.

32. The semiconductor device of claim 29, further comprising a dielectric layer between the first spacer and the substrate, wherein the dielectric layer is between the second spacer and the substrate.

33. The semiconductor device of claim 32, wherein the gate structure extends along a sidewall of the dielectric layer.

34. The semiconductor device of claim 29, wherein the first spacer comprises SiONC. 35 . The semiconductor device of claim 29 , wherein a width of an upper surface of the gate structure in the cross-sectional view is 0 nm to 6.0 nm greater than a width of a lower surface of the gate structure in the cross-sectional view.

36. A semiconductor device comprising: A first source / drain region and a second source / drain region are formed in a substrate; a gate structure over the substrate between the first source / drain region and the second source / drain region, wherein the gate structure comprises a gate dielectric layer and one or more conductive layers over the gate dielectric layer; a first spacer, on a side wall of the gate structure, a first side wall of the first spacer faces the gate structure and a second side wall of the first spacer is away from the gate structure, and the first side wall of the first spacer has a first slope; and A second spacer is disposed on the second sidewall of the first spacer opposite to the gate structure, wherein a sidewall of the second spacer facing the first spacer has a second slope different from the first slope. 37 . The semiconductor device of claim 36 , wherein the first spacer comprises SiONC, and wherein the second spacer comprises silicon nitride, SiCN, or a combination thereof. 38 . The semiconductor device of claim 36 , wherein a thickness of the first spacer decreases as the first spacer extends away from the substrate, and wherein a thickness of the second spacer decreases as the second spacer extends away from the substrate.

39. The semiconductor device of claim 38, further comprising a dielectric layer extending from the substrate to the first source / drain region, wherein the first spacer and the second spacer contact an upper surface of the dielectric layer.

40. The semiconductor device of claim 36, wherein the gate structure contacts the second spacer.

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