Semiconductor device and display device having the same

Abstract

The present disclosure relates to a semiconductor device, which includes: a semiconductor chip, the semiconductor chip including a substrate having a first surface and a second surface opposite to each other; a through hole, the through hole passing through the substrate; a first conductive pad, the first conductive pad being on the first surface of the substrate; a first protrusion, the first protrusion being formed above the first conductive pad and electrically connected to the first conductive pad; a second conductive pad, the second conductive pad being on the second surface of the substrate; a second protrusion, the second protrusion being formed above the second conductive pad and electrically connected to the second conductive pad; and a connecting electrode, the connecting electrode being buried in the through hole, the connecting electrode electrically connecting the first protrusion and the second protrusion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0131175 filed on October 30, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of some example embodiments of the present disclosure generally relate to a semiconductor device and a display device having the same. Background Art

[0004] Various display devices for multimedia devices such as televisions, cellular phones, tablet computers, navigation systems, and game controllers have been developed. The display device includes a display panel for displaying an image.

[0005] A display device generally includes a display panel for displaying an image and a driver for generating various signals or data for driving the display panel. The driver generally includes various circuits and electronic components and may be mounted on the display panel to be electrically connected to an external printed circuit board.

[0006] Meanwhile, various electronic components such as a controller for generating a signal for controlling a driver, a power supply for supplying power to the driver, and a memory may be mounted on the printed circuit board. For example, when the electronic components are implemented in one printed circuit board, limitations may arise due to the problem of increased thickness and size of the printed circuit board. In addition, it may be difficult to ensure the distance between adjacent electronic components, and therefore, problems may arise in terms of reliability and the like.

[0007] The Background section of the specification includes information intended to provide a background for example embodiments and the information in this Background section necessarily constitutes prior art. Summary of the invention

[0008] Aspects of some example embodiments may include a display device in which some electronic components on a printed circuit board are directly mounted on a semiconductor device so that the printed circuit board can be reused while ensuring an effective area of ​​the printed circuit board.

[0009] According to some example embodiments of the present disclosure, a semiconductor device includes: a semiconductor chip, the semiconductor chip including a substrate having a first surface and a second surface opposite to each other; a through hole, the through hole passing through the substrate; a first conductive pad, the first conductive pad being on the first surface of the substrate; a first protrusion, the first protrusion being formed above the first conductive pad and being electrically connected to the first conductive pad; a second conductive pad, the second conductive pad being on the second surface of the substrate; a second protrusion, the second protrusion being formed above the second conductive pad and being electrically connected to the second conductive pad; and a connecting electrode, the connecting electrode being buried in the through hole, the connecting electrode electrically connecting the first protrusion and the second protrusion.

[0010] The first protrusion and the second protrusion may have different sizes. The size of the second protrusion may be larger than the size of the first protrusion.

[0011] The semiconductor device may include at least one passive element on the second protrusion.

[0012] The passive element may include at least one of a bypass capacitor and a decoupling capacitor.

[0013] The first protrusion and the second protrusion may include at least one metal layer.

[0014] The semiconductor device may further include: a first conductive dielectric layer between the first protrusion and the first conductive pad; and a second conductive dielectric layer between the second protrusion and the second conductive pad.

[0015] According to another aspect of the present disclosure, a display device is provided, the display device comprising: a substrate, the substrate having a display area and a non-display area; a printed circuit board, the printed circuit board comprising a transmission controller, a wireless data generator and a wireless transmission pad unit, the transmission controller being configured to output input image data, the wireless data generator being configured to convert the input image data into a data transmission signal, the wireless transmission pad unit being configured to wirelessly transmit the data transmission signal as wireless data, the printed circuit board being separated from the substrate; a radio receiving array, the radio receiving array being in the non-display area of ​​the substrate, the radio receiving array comprising a wireless receiving pad unit and a wireless data recovery unit, the wireless receiving pad unit being coupled to the wireless transmitting pad unit and being configured to output a data reception signal by receiving the wireless data, The wireless data recovery unit is configured to convert the data reception signal into restored image data; and a semiconductor device, which is in the non-display area of ​​the substrate, and is configured to convert the restored image data into a voltage, wherein the semiconductor device includes: a semiconductor chip, the semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to each other; a through hole, the through hole passing through the semiconductor substrate; a first conductive pad, the first conductive pad is on the first surface of the semiconductor substrate; a first protrusion, the first protrusion is formed above the first conductive pad and is electrically connected to the first conductive pad; a second conductive pad, the second conductive pad is on the second surface of the semiconductor substrate; and a second protrusion, the second protrusion is formed above the second conductive pad and is electrically connected to the second conductive pad.

[0016] The semiconductor device may include: a semiconductor chip, the semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to each other; a through hole, the through hole being arranged to pass through the semiconductor substrate; at least one first conductive pad, the at least one first conductive pad being on the first surface of the semiconductor substrate; at least one first protrusion, the at least one first protrusion being on the top of the first conductive pad to be electrically connected to the corresponding first conductive pad; at least one second conductive pad, the at least one second conductive pad being on the second surface of the semiconductor substrate; and at least one second protrusion, the at least one second protrusion being on the top of the second conductive pad to be electrically connected to the corresponding second conductive pad.

[0017] The display device may further include a connection electrode buried in the through hole, the connection electrode electrically connecting the first protrusion and the second protrusion.

[0018] The first protrusion and the second protrusion may have different sizes. The size of the second protrusion may be larger than the size of the first protrusion.

[0019] The display device may include at least one passive element on the second protrusion of the semiconductor device. The passive element may include at least one of a bypass capacitor and a decoupling capacitor.

[0020] The first protrusion and the second protrusion may include at least one metal layer.

[0021] The display device may further include a chip-on-film (CFO) on the semiconductor device to be electrically connected to the second protrusion. At least one passive component is on one surface of the chip-on-film (CFO).

[0022] One side surface of the chip on film may be connected to the printed circuit board, and the semiconductor device and the printed circuit board may be electrically connected through the chip on film.

[0023] The display device may further include a flexible printed circuit board disposed on the semiconductor device to be electrically connected to the second protrusion. At least one passive element and at least one active element may be on one surface of the flexible printed circuit board.

[0024] The substrate may include a lower surface and an upper surface facing each other. The semiconductor device may be disposed in the non-display region on the upper surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Aspects of some example embodiments will now be described more fully below with reference to the accompanying drawings; however, aspects of some example embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will more fully convey the scope of the example embodiments to those skilled in the art.

[0026] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals always represent the same elements.

[0027] Figure 1 is a schematic perspective view illustrating a display device according to some example embodiments of the present disclosure.

[0028] Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0029] Figure 3 yes Figure 2 An enlarged cross-sectional view of area EA1.

[0030] Figure 4 It is shown Figure 1 A schematic block diagram of a wireless receiving array and a wireless transmitting array is shown in FIG.

[0031] Figure 5 yes Figure 2 An enlarged cross-sectional view of area EA2.

[0032] Figure 6 is a perspective view illustrating a semiconductor device and passive elements according to some example embodiments of the present disclosure.

[0033] Figure 7 It is along Figure 6 A cross-sectional view taken along line II-II'.

[0034] FIG. 8A to FIG. 8H is shown sequentially in Figure 7 A cross-sectional view of a method for forming a second protrusion on a second surface of a semiconductor device.

[0035] Fig. 9 is a schematic perspective view of a display device according to another embodiment of the present disclosure.

[0036] Fig.10 It is along Fig. 9 A cross-sectional view taken along line III-III'.

[0037] Fig.11 It is schematically shown Fig. 9 A plan view of a semiconductor device and a chip on film shown in FIG.

[0038] Fig.12 is a plan view schematically illustrating a semiconductor device and a printed circuit board in a display device according to some example embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] The present disclosure can be applied to various changes and different shapes, so only specific details are shown using example embodiments. However, the examples are not limited to specific shapes, but are applicable to all changes and equivalent materials and replacements. For better understanding, the included drawings are shown in a way that the drawings are enlarged.

[0040] The same reference numerals always refer to the same elements. In the accompanying drawings, for the sake of clarity, the thickness of some lines, layers, components, elements or features may be exaggerated. It will be understood that although the terms "first", "second", etc. can be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0041] It will be further understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of the stated features, wholes, steps, operations, elements and / or components, but does not exclude the presence and / or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In addition, the statement that an element such as a layer, region, substrate or plate is placed "on" or "above" another element not only indicates the situation where the element is "directly" placed "on" or "just" placed "above" another element, but also indicates the situation where other elements are inserted between the element and the other element. Conversely, the statement that an element such as a layer, region, substrate or plate is placed "under" or "below" another element not only indicates the situation where the element is "directly" placed "under" or "just" placed "under" another element, but also indicates the situation where other elements are inserted between the element and the other element.

[0042] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0043] Figure 1 is a schematic perspective view showing a display device according to some example embodiments of the present disclosure. Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0044] refer to Figure 1 and Figure 2 , the display device 1 according to some example embodiments of the present disclosure may be provided in various shapes. For example, the display device 1 may be provided in a quadrilateral plate shape having two pairs of sides parallel to each other. When the display device 1 is provided in a rectangular plate shape, any pair of the two pairs of sides may be provided longer than the other pair of sides. In some example embodiments of the present disclosure, for ease of description, a case is shown in which the display device 1 is provided in a rectangular shape having a pair of long sides and a pair of short sides. The extension direction of the short side is represented as a first direction DR1, the extension direction of the long side is represented as a second direction DR2, and a direction orthogonal to the first direction DR1 and the second direction DR2 is represented as a third direction DR3.

[0045] The display device 1 may include a printed circuit board 100 and a display panel 200 overlapping the printed circuit board 100 in a thickness direction of the printed circuit board 100 .

[0046] In some example embodiments of the present disclosure, the display panel 200 may include a display area DA and a non-display area NDA. An image may be displayed in the display area DA, and the display area DA may include a plurality of pixels PXL. Figure 1 In the figure, only one pixel PXL is illustrated as an example, and illustration of other pixels PXL is omitted, but various numbers of pixels PXL may be included according to the design and size of the display panel 200.

[0047] No image may be displayed in the non-display area NDA. Lines, drive circuits, and drive elements configured to drive the pixels PXL may be positioned in the non-display area NDA. For example, the non-display area NDA may surround at least a portion of the display area DA. In some embodiments, the non-display area NDA may define a frame of the display device 1.

[0048] The display panel 200 includes gate lines GL1 to GLn, data lines DL1 to DLm, and pixels PXL. The gate lines GL1 to GLn extend along, for example, the second direction DR2, and are arranged along the first direction DR1. The data lines DL1 to DLm intersect with the gate lines GL1 to GLn to be insulated from the gate lines GL1 to GLn. For example, the data lines DL1 to DLm may extend along the first direction DR1, and be arranged along the second direction DR2. For example, the first direction DR1 and the second direction DR2 may intersect each other. In an embodiment of the present disclosure, the thickness direction of the display panel 200 may be parallel to the third direction DR3.

[0049] Each pixel PXL is connected to a corresponding gate line among the gate lines GL1 to GLn and a corresponding data line among the data lines DL1 to DLm. The pixels PXL may be arranged in a matrix along a first direction DR1 and a second direction DR2. Each pixel PXL may include a plurality of sub-pixels capable of presenting any one of the primary colors such as red, green, and blue. The colors that may be presented by the sub-pixels are not limited to red, green, and blue, and the sub-pixels may present various colors including secondary primary colors such as yellow, cyan, and magenta.

[0050] Each pixel PXL is an element for displaying a unit image, and the resolution of the display panel 200 may be determined according to the number of pixels PXL provided in the display panel 200 .

[0051] The display panel 200 may include a first substrate 201 and a second substrate 202 positioned on the first substrate 201. The second substrate 202 may be a packaging tool that covers the first substrate 201 to prevent or reduce the introduction of moisture and oxygen from the outside. In some embodiments, the second substrate 202 may be configured as a packaging substrate coupled to the first substrate 201 using a sealant, or may be a thin packaging film directly formed on the first substrate 201.

[0052] In addition, the display panel 200 may include a wireless receiving array 205 disposed on the first substrate 201 and a semiconductor device 300 disposed on the first substrate 201. The wireless receiving array 205 and the semiconductor device 300 may be positioned in the non-display area NDA of the display panel 200.

[0053] The semiconductor device 300 may be spaced apart from the display area DA of the display panel 200 in the first direction DR1. When viewed on a plane, the semiconductor device 300 may be positioned between the wireless receiving array 205 and the display area DA, but the position of the semiconductor device 300 is not limited thereto. In some example embodiments of the present disclosure, the semiconductor device 300 may be, for example, a data driver integrated circuit (IC) for transmitting a data voltage to the pixel PXL. The semiconductor device 300 may include a surface (hereinafter referred to as a "lower surface") that is in direct contact with the display panel 200 and an upper surface that is positioned above the lower surface while facing the lower surface along the third direction DR3.

[0054] The wireless receiving array 205 may be spaced apart from the display area DA of the display panel 200 in the first direction DR1 and arranged along one end of the first substrate 201 .

[0055] The printed circuit board 100 may include a base circuit substrate 101, a wireless transmission array 105 arranged on the base circuit substrate 101, and a circuit element 120 positioned on one surface of the base circuit substrate 101. In some example embodiments of the present disclosure, the circuit element 120 may include an active element, such as a memory implemented with an IC chip or a microprocessor. The circuit element 120 may include, for example, a main processor of the display device 1. The main processor may control the overall operation of the display panel 200. For example, the main processor receives an input image signal input from the outside, and generates input image data by changing the data format of the input image signal to be suitable for the interface specification and driving mode of the semiconductor device 300.

[0056] For example, the wireless transmission array 105 may be spaced apart from the circuit element 120 in the first direction DR1 and arranged along one end of the base circuit substrate 101. The wireless transmission array 105 may overlap the wireless reception array 205 in the thickness direction D3.

[0057] The wireless transmit array 105 may receive input image data and wirelessly transmit the input image data as wireless data Wd to the wireless receive array 205 .

[0058] The wireless receiving array 205 may receive the wireless data Wd, convert the wireless data Wd into restored image data, and output the restored image data to the semiconductor device 300. The semiconductor device 300 may convert the restored image data received from the wireless receiving array 205 into data voltages, and output the data voltages to corresponding pixels PXL.

[0059] The wireless transmit array 105 may wirelessly transmit power to the wireless receive array 205 .

[0060] In the embodiment of the present disclosure, the wireless transmission array 105 and the wireless reception array 205 are not physically connected. In other words, the current path through which the current flows is not directly formed in the wireless transmission array 105 and the wireless reception array 205.

[0061] The wireless transmission array 105 of the printed circuit board 100 wirelessly transmits the image data and the power to the wireless reception array 205 of the display panel 200 using the wireless data Wd, and therefore, some components (e.g., a flexible printed circuit board) for physically connecting the printed circuit board 100 and the display panel 200 can be omitted. Therefore, when manufacturing the display device 1, the process related to the connection of the flexible printed circuit board can be omitted, and the manufacturing process time of the display device 1 can be effectively reduced.

[0062] In addition, because the printed circuit board 100 and the display panel 200 are not physically connected, when the display device 1 is reprocessed, the printed circuit board 100 can be relatively easily separated from the display panel 200, thereby recycling some components of the display device 1. Therefore, the time required for reprocessing can be reduced, damage to the printed circuit board 100 and the display panel 200 can be prevented or reduced during reprocessing, and some components of the display device 1 can be recycled.

[0063] Meanwhile, in an embodiment of the present disclosure, at least one passive element 400 may be positioned on one surface of the semiconductor device 300. The one surface of the semiconductor device 300 may be an upper surface facing a lower surface of the semiconductor device 300 in contact with the display panel 200. The one surface of the semiconductor device 300 may not be in contact with the display panel 200.

[0064] The passive element 400 includes capacitors, inductors, resistors, etc. having relatively large capacity. For example, the passive element 400 may include bypass capacitors and decoupling capacitors, etc., which are required when the semiconductor device 300 converts restored image data into a data voltage.

[0065] The passive component 400 may be positioned on the one surface of the semiconductor device 300 by bonding. For example, on the one surface of the semiconductor device 300, the passive component 400 may be positioned on the plurality of second protrusions 360.

[0066] As described above, in some example embodiments of the present disclosure, a portion of the passive element 400 having a relatively large capacity is directly mounted on the semiconductor device 300 instead of the printed circuit board 100, so that the space limitation of the printed circuit board 100 can be minimized. Therefore, an effective mounting area of ​​the circuit element 120 can be ensured.

[0067] Reference will be made later Figures 5 to 7 The second protrusion 360 of the semiconductor device 300 is described in more detail.

[0068] Figure 3 yes Figure 2 An enlarged cross-sectional view of area EA1.

[0069] refer to Figures 1 to 3 , the display panel 200 may include a first substrate 201 and a second substrate 202 .

[0070] The first substrate 201 may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL.

[0071] The substrate SUB may be made of an insulating (or insulating) material such as glass or resin. The substrate SUB may be made of a material having flexibility so as to be bendable or foldable. The substrate SUB may have a single-layer or multi-layer structure.

[0072] For example, the material having flexibility may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0073] However, the material constituting the substrate SUB may be variously changed, and the substrate SUB may be made of fiber reinforced plastic (FRP) or the like.

[0074] The pixel circuit layer PCL may include a buffer layer BFL positioned on the substrate SUB and at least one transistor T positioned on the buffer layer BFL. Figure 3 A driving transistor T for driving the light emitting device OLED is exemplarily shown in FIG. 1 , but illustration of another transistor electrically connected to the driving transistor T is omitted.

[0075] The buffer layer BFL may prevent impurities from diffusing into the driving transistor T. The buffer layer BFL may be provided in a single layer, but may be provided in a multilayer including at least two layers. The buffer layer BFL may be omitted according to the material of the substrate SUB and process conditions.

[0076] The driving transistor T may include a semiconductor layer SCL, a gate electrode GE, a source electrode ET1 , and a drain electrode ET2 .

[0077] The semiconductor layer SCL may be positioned on the buffer layer BFL. The semiconductor layer SCL may include a first region and a second region that are in contact with the source electrode ET1 and the drain electrode ET2, respectively. The region between the first region and the second region may be a channel region. The semiconductor layer SCL may be a semiconductor pattern made of polycrystalline silicon, amorphous silicon, an oxide semiconductor, or the like. The channel region is a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. Each of the first region and the second region may be a semiconductor pattern doped with impurities. The impurities may include impurities such as n-type impurities, p-type impurities, and other metals.

[0078] The gate electrode GE may be disposed on the semiconductor layer SCL, and the gate insulating layer GI is disposed between the gate electrode GE and the semiconductor layer SCL. The gate insulating layer GI may be an inorganic insulating layer including an inorganic material. For example, the gate insulating layer GI may be formed of polysiloxane, silicon nitride, silicon oxide, silicon oxynitride, etc.

[0079] The source electrode ET1 and the drain electrode ET2 may respectively contact the first and second regions of the semiconductor layer SCL through contact holes passing through the interlayer insulating layer ILD and the gate insulating layer GI.

[0080] The interlayer insulating layer ILD may be an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material.

[0081] The pixel circuit layer PCL may include a protective layer PSV disposed above the driving transistor T to cover the driving transistor T. The protective layer PSV may include at least one of an inorganic insulating layer made of an inorganic material and an organic insulating layer made of an organic material. For example, the protective layer PSV may include an inorganic insulating layer and an organic insulating layer on the inorganic insulating layer.

[0082] The display element layer DPL may include a light emitting device OLED disposed on the protective layer PSV. The light emitting device OLED may include a first electrode AE ​​and a second electrode CE and an emission layer EML disposed between the two electrodes AE and CE. Any one of the first electrode AE ​​and the second electrode CE may be an anode electrode, and the other of the first electrode AE ​​and the second electrode CE may be a cathode electrode. For example, the first electrode AE ​​may be an anode electrode, and the second electrode CE may be a cathode electrode. When the light emitting device OLED is a top-emitting organic light emitting device, the first electrode AE ​​may be a reflective electrode, and the second electrode CE may be a transmissive electrode. In the embodiments of the present disclosure, as an example, a case where the light emitting device OLED is a top-emitting organic light emitting device and the first electrode AE ​​is an anode electrode is described.

[0083] The first electrode AE ​​may be electrically connected to the drain electrode ET2 of the driving transistor T through a contact hole passing through the protective layer PSV. The first electrode AE ​​may include a reflective layer capable of reflecting light and a transparent conductive layer positioned on the top or bottom of the reflective layer. At least one of the transparent conductive layer and the reflective layer may be electrically connected to the drain electrode ET2.

[0084] The display element layer DPL may further include a pixel defining layer PDL having an opening OP for exposing a portion of the first electrode AE ​​(eg, an upper surface of the first electrode AE). The pixel defining layer PDL may include an organic insulating material.

[0085] The emission layer EML may be positioned on the exposed surface of the first electrode AE.

[0086] The emission layer EML may include a low molecular weight or high molecular weight material. In an embodiment of the present disclosure, the low molecular weight material may include copper phthalocyanine (CuPc), N,N'-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB) and tri-8-hydroxyquinoline aluminum (Alq 3 ) etc. These materials can be formed using methods such as vacuum deposition. The polymer material may include poly(3,4-ethylenedioxythiophene (PEDOT), poly(phenylene vinylene) (PPV), poly(fluorine) based materials.

[0087] The emission layer EML may be provided as a single layer, but may also be provided in a multilayer structure including various functions. When the emission layer EML is provided in a multilayer structure, the emission layer EML may have a structure in which a hole injection layer (HIL), a hole transport layer, an emission layer, an electron transport layer, and an electron injection layer, etc. are stacked in a single or composite structure.

[0088] However, the emission layer EML is not limited thereto, and it will be apparent that the emission layer EML may have various structures. In addition, at least a portion of the emission layer EML may be formed integrally across a plurality of first electrodes AE, or may be individually provided to correspond to each of the plurality of first electrodes AE. The color of light generated from the emission layer EML may be one of red, green, blue, and white, but the embodiment is not limited thereto. For example, the color of light generated from the light generating layer of the emission layer EML may be one of magenta, cyan, and yellow.

[0089] The second electrode CE may be positioned on the emission layer ELM. The second electrode CE may be a semi-transmissive reflective layer. For example, the second electrode CE may be a thin metal layer having a thickness sufficient to allow light emitted from the emission layer EML to be transmitted through the thin metal layer. The second electrode CE may transmit a portion of the light emitted from the emission layer EML and reflect the remaining light emitted from the emission layer EML.

[0090] The second substrate 202 may be disposed over the light emitting device OLED.

[0091] The second substrate 202 may be, for example, a thin encapsulation film formed directly above the light emitting device OLED. When the second substrate 202 is a thin encapsulation film, the second substrate 202 may include a plurality of insulating layers covering the light emitting device OLED. For example, the second substrate 202 may include at least one inorganic layer and at least one organic layer, and have a structure in which the inorganic layer and the organic layer are alternately stacked.

[0092] In some embodiments, the second substrate 202 may be a packaging substrate formed separately from the first substrate 201 and bonded to the first substrate 201 through a sealing material. When the second substrate 202 is a packaging substrate, the second substrate 202 may include a plastic substrate and / or a glass substrate.

[0093] Figure 4 It is shown Figure 1 A schematic block diagram of a wireless receiving array and a wireless transmitting array is shown in FIG.

[0094] refer to Figures 1 to 4 , the wireless transmission array 105 may include a wireless transmission pad unit 110 , a wireless data generator 130 , a wireless power generator 150 , a transmission determiner 170 , and a transmission controller 190 .

[0095] The transmission controller 190 may control the overall operation of the wireless data generator 130, the wireless power generator 150, and the transmission determiner 170. The transmission controller 190 may receive the input image data IDi and transmit the input image data IDi to the wireless data generator 130. In addition, the transmission controller 190 may output the input power Pi. The transmission controller 190 may directly generate the input power Pi or receive the input power Pi and transmit the input power Pi to the power generator 150.

[0096] The wireless data generator 130 may receive the input image data IDi and convert the input image data IDi into a transmission signal WDi so that the input image data IDi may be wirelessly transmitted through the wireless transmission pad unit 110 .

[0097] The wireless power generator 150 may receive input power Pi and convert the input power Pi into transmission power Ps so that the input power Pi may be wirelessly transmitted through the wireless transmission pad unit 110 .

[0098] The wireless transmission pad unit 110 may be used as an antenna for transmitting data or power. The wireless transmission pad unit 110 may receive a data transmission signal WDi and wirelessly transmit the data transmission signal WDi as wireless data Wd. In addition, the wireless transmission pad unit 110 may receive transmission power Ps and wirelessly transmit the transmission power Ps as wireless power Wp.

[0099] For example, the wireless transmission pad unit 110 may include a coil for forming a pad current Ip or an electrode for forming a pad voltage Vp to wirelessly transmit data or power within a short distance.

[0100] The transmission determiner 170 may determine whether the wireless data Wd and / or the wireless power Wp have been effectively transmitted, and transmit the determination result to the transmission controller 190. The transmission determiner 170 may sense the pad current flowing through the wireless transmission pad unit 110 or the pad voltage Vp applied to the wireless transmission pad unit 110, and determine whether the wireless data Wd and / or the wireless power Wp have been effectively wirelessly transmitted based on the pad current Ip or the pad voltage Vp.

[0101] When the transmission determiner 170 does not determine that the wireless data Wd has been effectively transmitted, the transmission determiner 170 may output a retransmission signal RTS to the transmission controller 190 so that the wireless transmission pad unit 110 may retransmit the wireless data Wd.

[0102] The wireless receiving array 205 may include a wireless receiving pad unit 210 , a wireless data recovery unit 230 , a wireless power recovery unit 250 , a coupling control circuit 270 , and a receiving controller 290 .

[0103] The wireless receiving pad unit 210 may be used as an antenna for transmitting data or power. The wireless receiving pad unit 210 is coupled to the wireless transmitting pad unit 110 through a magnetic field, an electric field, and / or an electromagnetic field, which may mean that electrical signals, data, or power are wirelessly received and transmitted.

[0104] The wireless reception pad unit 210 may wirelessly receive wireless data Wd and wireless power Wp, and output reception power Pr in response to the wireless data Wd. For example, the wireless reception pad unit 210 may include a coil or an electrode corresponding to the wireless transmission pad unit 110 to wirelessly receive data or power within a short distance.

[0105] The wireless data recovery unit 230 may receive the data reception signal Wdr and generate the restored image data IDrst from the data reception signal Wdr so as to restore the input image data IDi. The restored image data IDrst may have a form that can be processed in the receiving controller 290 or the semiconductor device 300 and have a high logic level or a low logic level corresponding to the data reception signal Wdr. The wireless data recovery unit 230 may output the restored image data IDrst to the receiving controller 290.

[0106] The wireless power recovery unit 250 may receive the reception power Pr and generate the recovery power Prst. The recovery power Prst may have a form that can be used in the reception controller 290 or the semiconductor device 300 and may be DC power. The wireless power recovery unit 250 may include an AC-DC converter and a DC-DC converter.

[0107] The coupling control circuit 270 may control the resonance frequency of the wireless reception pad unit 210 .

[0108] The reception controller 290 may control the overall operation of the wireless data recovery unit 230, the wireless power recovery unit 250, and the coupling control circuit 270. The reception controller 290 may receive the restored image data IDrst and the restored power Prst and transmit the restored image data IDrst and the restored power Prst to the semiconductor device 300.

[0109] Figure 5 yes Figure 2 An enlarged cross-sectional view of area EA2.

[0110] refer to Figures 1 to 5 , the semiconductor device 300 may be mounted in the non-display area NDA of the display panel 200 through a bonding process.

[0111] A plurality of connection pads CPD may be provided in the non-display area NDA of the display panel 200. The connection pads CPD may be made of a conductive material such as aluminum (Al). The connection pads CPD may be electrically connected to the semiconductor device 300 to transmit various power and / or signals supplied from the semiconductor device 300 to the pixels PXL of the display panel 200.

[0112] The semiconductor device 300 may include a semiconductor chip 310 , a plurality of first bumps 330 positioned on one surface of the semiconductor chip 310 , and a plurality of second bumps 360 disposed on another surface of the semiconductor chip 310 .

[0113] The semiconductor chip 310 may be provided in the form of a semiconductor substrate in which an electronic circuit is integrated and cut and processed into a die shape. In addition, the semiconductor chip 310 may be provided in the form of a semiconductor die in which an electronic circuit is integrated and packaged on a packaging substrate or a plurality of semiconductor dies are stacked by using a silicon via formed by a through silicon via (TSV) technology. The semiconductor chip 310 may be a memory chip in which a memory IC such as DRAM, SRAM, flash memory, MRAM, RERAM, FeRAM, or PcRAM is integrated, or a logic chip in which a logic IC is integrated, but the present disclosure is not limited thereto. In an embodiment of the present disclosure, the semiconductor chip 310 may be a data driver IC for transmitting a data signal to a pixel PXL of the display panel 200.

[0114] The first protrusions 330 may be positioned on the one surface of the semiconductor chip 310, and each of the first protrusions 330 may be spaced apart from an adjacent first protrusion 330 by a certain distance. The first protrusions 330 may be metal protrusions. Figure 5 , an embodiment in which the first protrusions 330 are regularly arranged on the one surface of the semiconductor chip 310 is shown, but the present disclosure is not limited thereto. That is, the size (e.g., length, width, and height) of the first protrusions 330, the number of the first protrusions 330, the arrangement structure of the first protrusions 330, and / or the distance between adjacent first protrusions 330 may be variously modified. In some example embodiments, the first protrusions 330 may be arranged on the one surface of the semiconductor chip 310 in a zigzag pattern.

[0115] The first protrusions 330 may be positioned on the one surface of the semiconductor chip 310 to be opposite to the connection pads CPD of the display panel 200 so as to be electrically connected to the connection pads CPD. That is, each first protrusion 330 may be positioned on the one surface of the semiconductor chip 310 to be opposite to a corresponding one of the connection pads CPD so as to be electrically connected to the corresponding one of the connection pads CPD. The first protrusions 330 may be made of a conductive material such as gold (Au).

[0116] In some embodiments, an adhesive layer ADL may be positioned between the connection pad CPD and the first protrusion 330. The adhesive layer ADL may include a non-conductive adhesive material and allow the display panel 200 and the semiconductor device 300 to be stably coupled to the connection pad CPD and the first protrusion 330, respectively, when the display panel 200 and the semiconductor device 300 are bonded to each other.

[0117] In some embodiments, the adhesive layer ADL may include a conductive adhesive material configured by mixing a conductive material constituting the connection pad CPD and a conductive material constituting the first protrusion 330. The adhesive layer ADL may be a solid bonding layer obtained by melting the surface of the first protrusion 330 and the surface of the connection pad CPD by the friction force between the first protrusion 330 and the connection pad CPD when the semiconductor device 300 is connected to the display panel 200, and then hardening the melted surface.

[0118] The second protrusions 360 may be positioned on the other surface of the semiconductor chip 310 on which the first protrusions 330 are not disposed, and each second protrusion 360 may be spaced apart from one adjacent second protrusion 360 by a certain distance. In some embodiments, the second protrusions 360 may be metal protrusions and include the same material as the first protrusions 330. However, the present disclosure is not limited thereto. In some embodiments, the second protrusions 360 may be solder protrusions.

[0119] Despite Figure 5 3 shows an embodiment in which the second protrusions 360 are regularly arranged on the other surface of the semiconductor chip 310, but the present disclosure is not limited thereto. That is, the size (e.g., length, width, and height) of the second protrusions 360, the number of the second protrusions 360, the arrangement structure of the second protrusions 360, and / or the distance between adjacent second protrusions 360 may be variously modified.

[0120] In an embodiment of the present disclosure, the second protrusion 360 and the first protrusion 330 may have different sizes. In an example, the size of the second protrusion 360 may be larger than the size of the first protrusion 330. This is because the passive component 400 having a relatively large capacity is mounted on the second protrusion 360. The method of mounting the passive component 400 on the second protrusion 360 may be performed using various techniques. In an example, reflow soldering, flow soldering, etc. may be applied. However, the present disclosure is not limited thereto, and various techniques for electrically connecting the second protrusion 360 and the passive component 400 may be applied.

[0121] Some of the second bumps 360 may be connected to some of the first bumps 330 through vias passing through the semiconductor chip 310. The vias may be formed by using a through silicon via (TSV) technology that electrically connects adjacent semiconductor chips or circuit elements by passing through the semiconductor chip 310 configured with a plurality of layers using a silicon via.

[0122] In some example embodiments of the present disclosure, the first protrusion 330 may be configured to provide an electrical connection component between the semiconductor device 300 and an external device (e.g., the display panel 200). In addition, the second protrusion 360 may be configured to provide an electrical connection component between the semiconductor device 300 and an external device (e.g., the passive element 400).

[0123] Figure 6 is a perspective view showing a semiconductor device and passive elements according to an embodiment of the present disclosure. Figure 7 It is along Figure 6 A cross-sectional view taken along line II-II'.

[0124] exist Figure 6 and Figure 7 , for convenience, only some of the components constituting the semiconductor chip are schematically shown.

[0125] refer to Figures 1 to 7 According to some example embodiments of the present disclosure, a semiconductor device 300 may include a semiconductor chip 310, a plurality of first protrusions 330 positioned on one surface 310a (hereinafter, referred to as a “lower surface”) of the semiconductor chip 310, and a plurality of second protrusions 360 positioned on another surface 310b (hereinafter, referred to as an “upper surface”) of the semiconductor chip 310.

[0126] The semiconductor chip 310 may include a semiconductor substrate 301 , at least one first conductive pad 305 positioned on a first surface 301 a of the semiconductor substrate 301 , a first insulating layer 303 positioned in at least one region on the first conductive pad 305 , and a first conductive medium layer 320 .

[0127] The semiconductor substrate 301 may be, for example, a semiconductor substrate made of a silicon material. The semiconductor substrate 301 may be used to implement a semiconductor chip 310 through a semiconductor manufacturing process such as a CMOS process. In the embodiments of the present disclosure, the semiconductor substrate 301 is not limited thereto, and the material and shape of the semiconductor substrate 301 may be modified. In some embodiments, various circuit elements and / or lines may be embedded in the semiconductor substrate 301.

[0128] In some embodiments, the first conductive medium layer 320 and the first protrusion 330 may be positioned on a surface (e.g., a lower surface) of the first conductive pad 305 corresponding to the first conductive medium layer 320 and the first protrusion 330 to overlap with the first conductive pad 305. In some embodiments, the first conductive medium layer 320 and the first protrusion 330 may be electrically connected to the first conductive pad 305 through a region of the conductive pad 305 that is not covered by the first insulating layer 303.

[0129] The first conductive pad 305 may include at least one conductive layer (e.g., at least one metal layer). Meanwhile, the material of the first conductive pad 305 is not necessarily limited to metal and may be modified. For example, the first conductive pad 305 may include at least one of a metal, an alloy of the metal, a conductive polymer, and a conductive metal oxide.

[0130] In some embodiments, examples of metals that can constitute the first conductive pad 305 may be copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), tin (Sn), aluminum (Al), cobalt (Co), rhodium (Rh), iridium (Ir), iron (Fe), ruthenium (Ru), osmium (Os), manganese (Mn), molybdenum (Mo), tungsten (W), niobium (Nb), tantalum (Ta), titanium (Ti), bismuth (Bi), antimony (Sb), and lead (Pb). In some embodiments, examples of conductive polymers that can constitute the first conductive pad 305 may be polythiophene compounds, polypyrrole compounds, polyaniline compounds, polyacetylene compounds, and polyphenylene compounds and mixtures thereof. For example, PEDOT / PSS compounds among polythiophene compounds may be used as conductive polymers that can constitute the first conductive pad 305. In some embodiments, examples of the conductive metal oxide that can constitute the first conductive pad 305 may be indium tin oxide (ITO), indium zinc oxide (IZO), antimony zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), and tin oxide (SnO2), etc. In addition, a material that can provide conductivity as well as the above-mentioned conductive materials can be used as a material constituting the first conductive pad 305.

[0131] In some example embodiments, the area of ​​the region where the first conductive pad 305 is formed may be greater than the area of ​​the region where the first conductive medium layer 320 and the first protrusion 330 corresponding to the first conductive medium layer 320 are formed, but the present disclosure is not limited thereto. However, the first conductive pad 305 is covered by the first insulating layer 303, the first conductive medium layer 320, and / or one first protrusion 330 corresponding to the first conductive medium layer 320. Therefore, the first conductive pad 305 is not exposed to the outside.

[0132] The first insulating layer 303 may be disposed over a region of the first conductive pad 305. The first insulating layer 303 may have an opening for exposing at least one region (e.g., a bonding region or a contact region) of the first conductive pad 305. For example, the first insulating layer 303 may be patterned so as to cover only an edge region of the first conductive pad 305 while exposing a central portion of the first conductive pad 305. That is, the first insulating layer 303 is positioned on the lower surface 301a of the semiconductor substrate 301 on which the first conductive pad 305 is positioned, and may have an opening for exposing a region (e.g., a central region) of the first conductive pad 305. The first insulating layer 303 may serve as a passivation layer for protecting the first surface 301a of the semiconductor substrate 301.

[0133] In some embodiments, the first insulating layer 303 may include at least one oxide layer or at least one nitride layer, but the present disclosure is not limited thereto. For example, the first insulating layer 303 may be formed using a silicon nitride layer (SiN x ) and / or silicon oxide layer (SiO x ) to configure.

[0134] The first conductive dielectric layer 320 may be disposed on the bottom of the first conductive pad 305 exposed by the first insulating layer 303. In some embodiments, the first conductive dielectric layer 320 may be implemented using at least one metal layer. For example, the first conductive dielectric layer 320 may be implemented using at least one metal layer including copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), tin (Sn), aluminum (Al), cobalt (Co), rhodium (Rh), iridium (Ir), iron (Fe), ruthenium (Ru), osmium (Os), manganese (Mn), molybdenum (Mo), tungsten (W), niobium (Nb), tantalum (Ta), titanium (Ti), bismuth (Bi), antimony (Sb), lead (Pb) and their alloys. The first conductive dielectric layer 320 is provided as a seed layer of the semiconductor chip 310 to electrically connect the first conductive pad 305 and the first protrusion 330 corresponding to the first conductive pad 305.

[0135] In some embodiments, the first protrusion 330 may be disposed on the bottom of the first conductive medium layer 320. In some embodiments, the first protrusion 330 is positioned together with the first conductive medium layer 320 on the top of a region of the first conductive pad 305 exposed by the opening of the first insulating layer 303 and on the top of the first insulating layer 303 surrounding the opening.

[0136] The first protrusion 330 may have a surface having an uneven structure along the contour of the first insulating layer 303. Figure 7 As shown, a protrusion corresponding to the opening of the first insulating layer 303 may be formed at a surface of the first protrusion 330 (e.g., a surface in contact with the first conductive medium layer 320). In some embodiments, the depth of the protrusion may be similar to or substantially equal to the height (or thickness) of the first insulating layer 303.

[0137] In some embodiments, the first protrusion 330 may be implemented using at least one metal layer. For example, the first protrusion 330 may be implemented using at least one metal layer including copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), tin (Sn), aluminum (Al), cobalt (Co), rhodium (Rh), iridium (Ir), iron (Fe), ruthenium (Ru), osmium (Os), manganese (Mn), molybdenum (Mo), tungsten (W), niobium (Nb), tantalum (Ta), titanium (Ti), bismuth (Bi), antimony (Sb), lead (Pb) and their alloys. The first protrusion 330 is connected to the connection pad CPD of the display panel 200 to electrically connect the semiconductor device 300 and the display panel 200.

[0138] The first bumps 330 may include first input bumps and first output bumps positioned in at least one row on the first surface 301a of the semiconductor substrate 301. The first input bumps and the first output bumps may be arranged to be spaced apart from each other by a certain distance or more.

[0139] In some example embodiments of the present disclosure, the semiconductor chip 310 may further include at least one second conductive pad 340 positioned on the second surface 301b of the semiconductor substrate 301, a second insulating layer 313 positioned in at least one region on the second conductive pad 340, and a second conductive medium layer 350. The second protrusion 360 may be positioned on the second conductive medium layer 350.

[0140] In some example embodiments, the second conductive medium layer 350 and the second protrusion 360 may be positioned on one surface (e.g., an upper surface) of the second conductive pad 340 corresponding to the second conductive medium layer 350 and the second protrusion 360 to overlap with the second conductive pad 340. In some embodiments, the second conductive medium layer 350 and the second protrusion 360 may be electrically connected to the second conductive pad 340 through one area of ​​the second conductive pad 340 that is not covered by the second insulating layer 313.

[0141] The second conductive pad 340 may include at least one conductive layer (eg, at least one metal layer). The second conductive pad 340 may be made of the same material as the first conductive pad 305, but the present disclosure is not limited thereto.

[0142] The area of ​​the region where the second conductive pad 340 is formed may be larger than the area of ​​the region where the second conductive medium layer 350 and the second protrusion 360 corresponding to the second conductive medium layer 350 are formed, but the present disclosure is not limited thereto. However, the second conductive pad 340 is covered by the second insulating layer 313, the second conductive medium layer 350 and / or one second protrusion 360 corresponding thereto. Therefore, the second conductive pad 340 is not exposed to the outside.

[0143] In some example embodiments of the present disclosure, the second conductive pad 340 may have a size larger than that of the first conductive pad 305. For example, the size of the second conductive pad 340 may be equal to or larger than that of the second protrusion 360 corresponding to the second conductive pad 340.

[0144] The second insulating layer 313 may be disposed over a region of the second conductive pad 340. The second insulating layer 313 may have an opening for exposing at least one region (e.g., a bonding region or a contact region) of the second conductive pad 340. For example, the second insulating layer 313 may be patterned to cover only an edge region of the second conductive pad 340 while exposing a central portion of the second conductive pad 340. The second insulating layer 313 may serve as a passivation layer for protecting the second surface 301b of the semiconductor substrate 301.

[0145] In some embodiments, the second insulating layer 313 may be configured using at least one inorganic insulating layer including an inorganic material. In an embodiment of the present disclosure, the second insulating layer 313 may include the same material as the first insulating layer 303 .

[0146] The second conductive medium layer 350 may be disposed on the top of the second conductive pad 340 exposed by the second insulating layer 313. The second conductive medium layer 350 may be implemented using at least one metal layer. In an embodiment of the present disclosure, the second conductive medium layer 350 may include the same material as the first conductive medium layer 320.

[0147] The second protrusion 360 corresponding to the second conductive medium layer 350 may be disposed on the top of the second conductive medium layer 350. In some embodiments, the second protrusion 360 is positioned together with the second conductive medium layer 350 on the top of a region of the second conductive pad 340 exposed by the opening of the second insulating layer 313 and on the top of the second insulating layer 313 surrounding the opening.

[0148] The second protrusion 360 may have a surface having an uneven structure along the contour of the second insulating layer 313. Figure 7 As shown, a protrusion corresponding to the opening of the second insulating layer 313 may be formed at a surface of the second protrusion 360 (e.g., a surface in contact with the second conductive medium layer 350). In some embodiments, the depth of the protrusion may be similar to or substantially equal to the height (or thickness) of the second insulating layer 313. The second protrusion 360 may include a second input protrusion and a second output protrusion positioned on at least one row on the second surface 301b of the semiconductor substrate 301. The second input protrusion and the second output protrusion may be arranged to be spaced apart from each other by a specific distance or more.

[0149] In some example embodiments of the present disclosure, since the passive component 400 having a relatively large capacity is mounted on the second protrusion 360, the second protrusion 360 may have a size larger than that of the first protrusion 330 in order to sufficiently ensure a contact area between the second protrusion 360 and the passive component 400. The size of the second protrusion 360 may be similar to or substantially equal to that of the passive component 400.

[0150] The passive component 400 may include at least one bonding pad positioned on a surface facing the second bump 360. The bonding pad of the passive component 400 may contact the second bump 360 to electrically connect the semiconductor chip 310 and the passive component 400. In an embodiment of the present disclosure, the second bump 360 may be a solder bump.

[0151] In an embodiment of the present disclosure, the number of first protrusions 330 formed on the lower surface 310a of the semiconductor chip 310 may be different from the number of second protrusions 360 positioned on the upper surface 310b of the semiconductor chip 310. When the lower surface 310a and the upper surface 310b of the semiconductor chip 310 have the same area, the second protrusions 360 having a size larger than that of the first protrusions 330 may be positioned on the upper surface 310b of the semiconductor chip 310 so that the number of the second protrusions 360 is smaller than the number of the first protrusions 330.

[0152] Meanwhile, in an embodiment of the present disclosure, the semiconductor chip 310 may include at least one through hole TH passing through the semiconductor substrate 301. A connection electrode 380 buried in the through hole TH using a conductive material may be disposed in the through hole TH. An insulating film 370 for blocking direct electrical connection between the connection electrode 380 and the semiconductor substrate 301 may be formed on an inner surface of the through hole TH.

[0153] The insulating film 370 may completely cover the inner surface of the through hole TH to prevent or reduce an undesirable short circuit that may occur between the connection electrode 380 and the semiconductor substrate 301. The insulating film 370 may include a layer made of SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 At least one insulating material selected from the group consisting of. However, the present disclosure is not limited thereto, and various materials having insulating properties may be used.

[0154] In an embodiment of the present disclosure, the through hole TH may be formed in the semiconductor substrate 301 using a through silicon via (TSV) technology. The connection electrode 380 may be formed of a conductive material and may be positioned between at least one first conductive pad 305 located on the first surface 301a of the semiconductor substrate 301 and at least one second conductive pattern 340 located on the second surface 301b of the semiconductor substrate 301 to electrically connect the first conductive pad 305 and the second conductive pad 340.

[0155] As described above, the first conductive pad 305 and the second conductive pad 340 are electrically connected through the connection electrode 380 in the through hole TH, so that the first bump 330 positioned on the first conductive pad 305 and the second bump 360 positioned on the second conductive pad 340 can be electrically connected to each other. Therefore, the passive element 400 arranged and / or mounted on the second bump 360 is electrically connected to the first bump 330, and a portion of the wireless power Wp received from the wireless transmission pad unit 190 to the semiconductor device 300 is transmitted to the passive element 400 through the first bump 330, the connection electrode 380, and the second bump 360.

[0156] In an embodiment of the present disclosure, the passive element 400 includes capacitors, inductors, resistors, etc. having relatively large capacity. For example, the passive element 400 may include bypass capacitors and decoupling capacitors, etc., which are required when the semiconductor device 300 converts restored image data into data voltages.

[0157] As described above, in the embodiment of the present disclosure, a portion of the passive element 400 having a relatively large capacity is directly positioned and / or mounted on the second protrusion 360 of the semiconductor chip 310 instead of the printed circuit board 100, so that the space limitation of the printed circuit board 100 can be minimized. Therefore, an effective mounting area of ​​at least one circuit element 120 mounted on the printed circuit board 100 can be sufficiently ensured.

[0158] FIG. 8A to FIG. 8H is shown sequentially in Figure 7 A cross-sectional view of a method for forming a second protrusion on a second surface of a semiconductor device.

[0159] refer to Figures 1 to 8A , a first conductive pad 305 , a first insulating layer 303 , a first conductive medium layer 320 and at least one first protrusion 330 are formed on the first surface 301 a of the semiconductor substrate 301 .

[0160] In some example embodiments of the present disclosure, the semiconductor substrate 301 may be a wafer substrate in which an electronic circuit or the like is integrated, and the first surface 301a of the semiconductor substrate 301 may be a surface bonded to and / or in contact with the display panel 200. The first protrusions 330 may be electrically connected to the corresponding first conductive pads 305 through the first conductive medium layer 320.

[0161] refer to Figures 1 to 8B , forming a through hole TH passing through the semiconductor substrate 301. The through hole TH can be formed using a through silicon via (TSV) packaging technology. The TSV packaging technology refers to a technology for electrically connecting some components positioned on the first surface 301a of the semiconductor substrate 301 and some components positioned on the second surface 301b of the semiconductor substrate 301 by vertically drilling a hole in the semiconductor substrate 301 from the second surface 301b of the semiconductor substrate 301. In some example embodiments of the present disclosure, the through hole TH may expose a portion of the first conductive pad 305 positioned on the first surface 301a of the semiconductor substrate 301 to the outside.

[0162] refer to Figures 1 to 8C An insulating film 370 made of an insulating (or insulating) material is formed on the inner surface of the through hole TH. The insulating film 370 may be used to minimize or reduce direct electrical connection between the connection electrode 380 to be formed by a subsequent process and the semiconductor substrate 301 .

[0163] refer to Figures 1 to 8D, a connection electrode 380 made of a conductive material is formed in the through hole TH. The conductive material may include copper, aluminum, tungsten or similar materials. In some embodiments, the connection electrode 380 may be formed by a deposition process. In other embodiments, the connection electrode 380 may be formed by a plating process (e.g., an electroplating process or an electroless plating process). The connection electrode 380 may be filled in the through hole TH and include a surface having the same plane as the second surface 301b of the semiconductor substrate 301.

[0164] In some example embodiments of the present disclosure, the connection electrode 380 may extend up to the first surface 301 a of the semiconductor substrate 301 to be physically and / or electrically connected to the first conductive pad 305 exposed to the outside.

[0165] refer to Figures 1 to 8E , a second conductive pad 340 is formed on the second surface 301b of the semiconductor substrate 301. The second conductive pad 340 may be formed of the same material as the first conductive pad 305. In some example embodiments of the present disclosure, the second conductive pad 340 may directly contact the connection electrode 380 to be electrically connected to the first conductive pad 305.

[0166] refer to Figures 1 to 8F , by forming an insulating material layer on the second conductive pad 340 and then patterning the insulating material layer through a process using a mask to form a second insulating layer 313 including an opening for exposing a portion of the second conductive pad 340 .

[0167] refer to Figures 1 to 8G , a second conductive dielectric layer 350 is formed on the second insulating layer 313 . The second conductive dielectric layer 350 may be physically and / or electrically connected to the second conductive pad 340 through the opening of the second insulating layer 313 .

[0168] The second conductive medium layer 350 may be formed of the same material as the first conductive medium layer 320. The second conductive medium layer 350 is a seed layer of the semiconductor chip 310 and may be used as a connection member for more stably connecting the second conductive pad 340 and the second bump 360 to be formed by a subsequent process.

[0169] refer to Figures 1 to 8H , a second bump 360 is formed on the second conductive medium layer 350. In some example embodiments, the second bump 360 may include a solder bump, a copper bump, a metal bump including nickel (Ni) or gold (Au), or a combination thereof.

[0170] The second bump 360 may directly contact the second conductive medium layer 350 to be physically and / or electrically connected to the second conductive medium layer 350. Therefore, the second bump 360 may be electrically connected to the second conductive pad 340. In addition, the second bump 360 may be electrically connected to the first bump 330 through the connection electrode 380 in the through hole TH.

[0171] Fig. 9 is a schematic perspective view of a display device according to another embodiment of the present disclosure. Fig.10 It is along Fig. 9 A cross-sectional view taken along line III-III'. Fig.11 It is schematically shown Fig. 9 A plan view of the semiconductor device and flip chip shown in FIG.

[0172] In this embodiment, the parts different from the parts of the above-described embodiment will be mainly described to avoid repetition. The parts not specifically described in this embodiment follow the parts of the above-described embodiment. In addition, the same reference numerals refer to the same components, and similar reference numerals refer to similar components.

[0173] refer to Figures 9 to 11 According to some example embodiments of the present disclosure, the display device 1' may be provided in a rectangular shape having a pair of long sides and a pair of short sides. In some example embodiments of the present disclosure, for ease of description, the extending direction of the short sides of the display device 1' is denoted as a first direction DR1, the extending direction of the long sides of the display device 1' is denoted as a second direction DR2, and the direction orthogonal to the first direction DR1 and the second direction DR2 is denoted as a third direction DR3.

[0174] The display device 1 ′ may include a printed circuit board 100 , a display panel 200 overlapping the printed circuit board 100 in the thickness direction DR3 , and a chip on film 500 .

[0175] The printed circuit board 100 may include a base circuit substrate 101 and at least one circuit element 120 arranged and / or mounted on one surface of the base circuit substrate 101. The printed circuit board 100 may also include a wireless transmission array (see Figure 1 105).

[0176] The display panel 200 may include a plurality of pixels (see Figure 1 The display panel 200 may include a display area DA of a substrate PXL and a non-display area NDA surrounding at least one side of the display area DA. The display panel 200 may include a first substrate 201 and a second substrate 202.

[0177] In some example embodiments of the present disclosure, the display panel 200 may include a semiconductor device 300 positioned in the non-display area NDA of the first substrate 201 and a COF 500 connected to the semiconductor device 300. The display panel 200 may also include a wireless receiving array (see FIG. 1 ) arranged and / or mounted in the non-display area NDA. Figure 1 205).

[0178] At least one connection pad CPD may be arranged and / or installed in the non-display area NDA of the display panel 200. The connection pad CPD may be electrically connected to the semiconductor device 300 to transfer various powers and / or signals supplied from the semiconductor device 300 to the pixel PXL.

[0179] The semiconductor device 300 may include a semiconductor substrate (see Figure 7 301 ), a semiconductor chip 310 , at least one first protrusion 330 formed on a lower surface 310 a of the semiconductor chip 310 , and at least one second protrusion 360 positioned on an upper surface 310 b of the semiconductor chip 310 .

[0180] The first protrusion 330 may be positioned on the lower surface 310a of the semiconductor chip 310 to be opposite to the connection pad CPD of the display panel 200 so as to be electrically connected to the connection pad CPD. In some embodiments, an adhesive layer ADL may be provided between the connection pad CPD and the first protrusion 330. When the display panel 200 and the semiconductor device 300 are bonded to each other, the adhesive layer ADL may allow the display panel 200 and the semiconductor device 300 to be stably coupled to the connection pad CPD and the first protrusion 330, respectively.

[0181] The second bump 360 may be positioned on the upper surface 310b of the semiconductor chip 310 and electrically connected to the chip on film 500. The second bump 360 and the chip on film 500 may be electrically connected through a welding process, but the present disclosure is not limited thereto.

[0182] The chip-on-film 500 may include one surface 500a and another surface 500b opposite to each other in a third direction DR3 (e.g., thickness direction). One surface 500a of the chip-on-film 500 is a surface facing the semiconductor device 300, and may be a lower surface of the chip-on-film 500 when viewed in cross section. The other surface 500b of the chip-on-film 500 may be an upper surface of the chip-on-film 500 when viewed in cross section.

[0183] At least one passive component 400 and at least one active component 410 may be positioned on the other surface 500 b of the chip on film 500 .

[0184] The passive element 400 may include a first passive element 400a and a second passive element 400b. In some example embodiments, each of the first passive element 400a and the second passive element 400b may include a passive element having a large capacity. For example, the first passive element 400a may be a bypass capacitor, and the second passive element 400b may be a decoupling capacitor.

[0185] The active element 410 may be a power supply in the form of an IC in which two or more circuit elements are integrated in a component. However, the present disclosure is not limited thereto, and the active element 410 may be a memory chip in which a memory IC such as a DRAM is integrated.

[0186] At least one film pad may be disposed on one surface 500a of the chip-on-film 500. The film pad may be disposed on one surface of the semiconductor device 300 to be opposite to the second protrusion 360 of the semiconductor device 300 so as to be electrically connected to the second protrusion 360. The one surface of the semiconductor device 300 may be the upper surface 310b of the semiconductor chip 310.

[0187] The chip-on-film 500 having the above-described configuration may be arranged and / or mounted on top of the semiconductor device 300 to be electrically connected to the second protrusion 360 of the semiconductor device 300. When viewed in a cross section, the chip-on-film 500 may be arranged on top of the semiconductor device 300. In addition, the chip-on-film 500 may be electrically connected to the printed circuit board 100.

[0188] As described above, some passive elements 400 and some active elements 410 having relatively large capacities are directly arranged and / or mounted on the chip on film 500 instead of the printed circuit board 100, and are electrically connected to the second protrusions 360 of the semiconductor chip 310, so that the space limitation of the printed circuit board 100 can be minimized. Therefore, the effective mounting area of ​​the circuit element 120 arranged and / or mounted on the printed circuit board 100 can be sufficiently ensured, and the distance between the circuit element 120 and the adjacent circuit element can be sufficiently maintained.

[0189] Fig.12 is a plan view schematically showing a semiconductor device and a printed circuit board in a display device according to still another embodiment of the present disclosure.

[0190] exist Fig.12 In the embodiment, a display device according to another embodiment of the present disclosure may have a configuration substantially similar to that of the display device according to the above-described embodiment, except that a flexible printed circuit board is arranged and / or mounted on a second protrusion of the semiconductor device so that the semiconductor device and the flexible printed circuit board are physically and / or electrically connected to each other.

[0191] Therefore, regarding Fig.12 In the present invention, the parts different from those of the above-described embodiment will be mainly described to avoid duplication. The parts not specifically described in this embodiment follow the parts of the above-described embodiment. In addition, the same reference numerals refer to the same components, and similar reference numerals refer to similar components.

[0192] refer to Fig.12 , a display device according to some example embodiments of the present disclosure may include a semiconductor device 300 and a flexible printed circuit board 600 arranged and / or mounted on the semiconductor device 300 to be electrically connected to the semiconductor device 300 .

[0193] The semiconductor device 300 may include a semiconductor chip 310 and at least one second bump 360 positioned on an upper surface 310b of the semiconductor chip 310. At least one first bump may be positioned on a lower surface facing the upper surface 310b of the semiconductor chip 310.

[0194] The flexible printed circuit board 600 may be arranged and / or mounted on the semiconductor device 300 to be physically and / or electrically connected to the second protrusion 360 of the semiconductor device 300. To this end, at least one metal line and / or at least one circuit element may be positioned on the other surface facing the one surface 600b of the flexible printed circuit board 600. The metal line and the circuit board may be positioned on one surface of the semiconductor device 300 to be opposite to the second protrusion 360 of the semiconductor device 300 so as to be electrically connected to the second protrusion 360. The one surface of the semiconductor device 300 may be the upper surface 310b of the semiconductor chip 310.

[0195] In some example embodiments of the present disclosure, the other surface of the flexible printed circuit board 600 is a surface facing the semiconductor device 300 and may be a lower surface of the flexible printed circuit board 600. One surface 600b of the flexible printed circuit board 600 may be an upper surface facing the lower surface of the flexible printed circuit board 600.

[0196] At least one passive component 400 and at least one active component 410 may be positioned on one surface 600 b of the flexible printed circuit board 600 .

[0197] The passive element 400 may include a first passive element 400a and a second passive element 400b. In some example embodiments, each of the first passive element 400a and the second passive element 400b may include a passive element having a large capacity. For example, the first passive element 400a may be a bypass capacitor, and the second passive element 400b may be a decoupling capacitor.

[0198] The active element 410 may include a first active element 410a, a second active element 410b, and a third active element 410c. In some example embodiments, the first active element 410a, the second active element 410b, and the third active element 410c may be a power supply in the form of an IC in which two or more circuit elements are integrated in a component, but the present disclosure is not limited thereto. In some example embodiments, the first active element 410a may be a sensor circuit in the form of an IC, the second active element 410b may be a power supply in the form of an IC, and the third active element 410c may be a memory chip in which a memory IC is integrated.

[0199] The flexible printed circuit board 600 having the above configuration may be positioned and / or formed on the top of the semiconductor device 300 to be electrically connected to the second protrusion 360 of the semiconductor device 300. In addition, the flexible printed circuit board 600 may be electrically connected to the second protrusion 360 of the semiconductor device 300. Figure 1 A printed circuit board 100 is provided.

[0200] As described above, some of the passive components 400 and some of the active components 410 having relatively large capacities among the plurality of passive components are directly mounted on the flexible printed circuit board 600 instead of the printed circuit board 100, and are electrically connected to the second protrusions 360 of the semiconductor chip 310, so that the space limitation of the printed circuit board 100 can be minimized. Therefore, the effective mounting area of ​​the circuit element 120 positioned and / or mounted on the printed circuit board 100 can be sufficiently ensured, and the distance between the circuit element 120 and the adjacent circuit element can be sufficiently maintained.

[0201] According to some example embodiments of the present disclosure, a semiconductor device and a display device having the semiconductor device may be provided, wherein a plurality of protrusions are respectively positioned on a first surface and a second surface of the semiconductor device, and some electronic components on a printed circuit board are directly mounted on the semiconductor device so that an effective area of ​​the printed circuit board can be ensured.

[0202] Furthermore, according to some example embodiments of the present disclosure, a display device having a recycled printed circuit board may be provided.

[0203] Aspects of some example embodiments have been described herein, and although specific terms are employed, the specific terms are used and interpreted only in a general and descriptive sense and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art from the date of filing this application, unless otherwise specifically indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the following claims and their equivalents.

Claims

1. A display device, wherein: The display device comprises: A substrate having a display area and a non-display area; a printed circuit board, the printed circuit board comprising a transmission controller, a wireless data generator and a wireless transmission pad unit, the transmission controller being configured to output input image data, the wireless data generator being configured to convert the input image data into a data transmission signal, the wireless transmission pad unit being configured to wirelessly transmit the data transmission signal as wireless data, the printed circuit board being separated from the substrate; a radio receiving array in the non-display area of ​​the substrate, the radio receiving array comprising a wireless receiving pad unit and a wireless data recovery unit, the wireless receiving pad unit being coupled to the wireless transmitting pad unit and configured to output a data receiving signal by receiving the wireless data, the wireless data recovery unit being configured to convert the data receiving signal into restored image data; and a semiconductor device in the non-display region of the substrate, the semiconductor device being configured to convert the restored image data into a voltage, Wherein, the semiconductor device comprises: A semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to each other; a through hole passing through the semiconductor substrate; a first conductive pad, the first conductive pad being on the first surface of the semiconductor substrate; a first protrusion formed over the first conductive pad and electrically connected to the first conductive pad; a second conductive pad, the second conductive pad being on the second surface of the semiconductor substrate; a second bump formed over the second conductive pad and electrically connected to the second conductive pad; and A connecting electrode is embedded in the through hole and electrically connects the first protrusion and the second protrusion.

2. The display device according to claim 1, wherein: The first protrusion and the second protrusion have different sizes.

3. The display device according to claim 2, wherein: The size of the second protrusion is larger than that of the first protrusion.

4. The display device according to claim 3, wherein: The semiconductor device also includes at least one passive component on the second protrusion.

5. The display device according to claim 4, wherein: The passive element includes at least one of a bypass capacitor and a decoupling capacitor.

6. The display device according to claim 1, wherein: The first protrusion and the second protrusion include at least one metal layer.

7. The display device according to claim 6, wherein: The semiconductor device further comprises: a first conductive dielectric layer, the first conductive dielectric layer being between the first protrusion and the first conductive pad; and A second conductive medium layer is between the second protrusion and the second conductive pad.

8. The display device according to claim 1, wherein: The semiconductor device further comprises: an insulating film disposed between the inner surface of the through hole and the connecting electrode, The insulating film completely covers the inner surface of the through hole, so as to block the direct electrical connection between the connecting electrode and the semiconductor substrate.

9. The display device according to claim 8, wherein: In a plan view, the first conductive pad overlaps the connection electrode, the insulating film, and a portion of the semiconductor substrate that is located outside the through hole.

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