Storage device and method for operating the storage device

Abstract

The present disclosure relates to a storage device and a method for operating the storage device. The storage device includes a main storage device and a storage controller for controlling the main storage. The main storage device stores data and includes a plurality of non-volatile storage devices. The storage controller loads at least one of (a) and (b) into the host storage buffer based on the size of the host storage buffer included in the external host device and the locality information associated with the data access mode of the external host device: (a) at least a portion of the mapping tables in the mapping table; (b) at least one directory in a portion of the directories in the directory. The mapping table is stored in the non-volatile storage device, and the mapping table is stored in the non-volatile storage device, and the mapping table indicates the mapping relationship between the physical address and the logical address of the corresponding non-volatile storage device in the non-volatile storage device. The directory is configured to store the address information of the mapping table stored in the non-volatile storage device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Priority is claimed on Korean Patent Application No. 10-2018-0132843 filed on November 1, 2018 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates generally to data processing, and more particularly to a memory device, a memory system including the memory device, and a method of operating the memory device. Background Art

[0004] The host typically uses a data storage device that includes a non-volatile memory such as flash memory. A flash translation layer (FTL) is used with the flash memory to map logical addresses generated by the host and corresponding physical addresses used by the data storage device. One or more mapping tables associated with the FTL can be stored in the data storage device.

[0005] The data storage device may include a separate volatile memory (e.g., dynamic random access memory (DRAM) or static RAM (SRAM)) that can be used to quickly access the mapping table. However, when the power supplied to the data storage device is interrupted, the mapping table stored in the volatile memory may be lost. In addition, as the size of the mapping table increases, the amount of volatile memory used to store the mapping table also increases, thereby increasing the cost and physical size of the data storage device. Summary of the invention

[0006] Embodiments of the inventive concept provide a storage device capable of reducing access time to access a mapping table, a storage system including the storage device capable of reducing access time to access a mapping table, and a method of operating the storage device capable of reducing access time to access a mapping table.

[0007] An embodiment of the inventive concept provides a storage device, the storage device including a main storage device and a storage controller controlling the main storage device. The main storage device stores data and includes a plurality of non-volatile storage devices. The storage controller loads at least one of (a) and (b) into the host storage buffer based on the size of the host storage buffer included in the external host device and the locality information associated with the data access mode of the external host device: (a) at least a portion of the mapping tables in the mapping table; (b) at least one directory in a portion of the directories in the directory. The mapping table is stored in the non-volatile storage device, and the mapping table indicates a mapping relationship between a physical address and a logical address of a corresponding non-volatile storage device in the non-volatile storage device. The directory stores address information of the mapping table stored in the non-volatile storage device.

[0008] An embodiment of the inventive concept also provides a storage system, the storage system comprising a storage device and a host device. The storage device comprises a main storage device for storing data and a storage controller for controlling the main storage device, the main storage device comprising a plurality of non-volatile storage devices. The host device comprises a host memory and controls the storage device. The host device allocates a portion of the host memory as a host storage buffer accessible to the storage controller in response to a request from the storage device. The storage controller loads at least one of (a) and (b) into the host storage buffer based on at least one of the size of the host storage buffer and locality information associated with a data access mode of the host device: (a) at least a portion of mapping tables in a mapping table; (b) at least one directory in a portion of directories in a directory. The mapping table is stored in the non-volatile storage device, the mapping table indicating a mapping relationship between a physical address and a logical address of a corresponding non-volatile storage device in the non-volatile storage device. The directory stores address information of the mapping table stored in the non-volatile storage device.

[0009] Embodiments of the inventive concept also provide a method for operating a storage device, the storage device including a main storage device storing data and a storage controller controlling the main storage device. The main storage device includes a plurality of non-volatile storage devices. The method includes: receiving, by the storage controller, size information of a host storage buffer included in an external host device controlling the storage device from the external host device; and loading, by the storage controller, at least one of (a) and (b) into the host storage buffer based on the size information of the host storage buffer and locality information associated with a data access mode of the external host device: (a) at least a portion of mapping tables in a mapping table, (b) at least one directory in a portion of directories in a directory. The mapping table is stored in the non-volatile storage device, the mapping table indicating a mapping relationship between a physical address and a logical address of a corresponding non-volatile storage device in the non-volatile storage device, and the directory is configured to store address information of the mapping table. The method also includes, by the storage controller, performing a storage operation specified by the command in a storage area of ​​the non-volatile storage device specified by the address based on a command and an address received from the host device by referring to the host storage buffer.

[0010] An embodiment of the inventive concept also provides a storage device, the storage device comprising a main storage device and a storage controller. The main storage device comprises a non-volatile storage device storing a directory and a mapping table, wherein the mapping table indicates a mapping relationship between a physical address and a logical address of a corresponding non-volatile storage device in the non-volatile storage device, and the directory stores address information of the mapping table stored in the non-volatile storage device. The storage controller is configured to control the main storage device in a plurality of modes and selectively load the directory and the mapping table from the non-volatile storage device to the host storage buffer based on a size of a host storage buffer of an external host device and a count value indicating the number of misses in which a logical address received from the external host device does not match any of the entries in the host storage buffer. The multiple modes include a first mode, a second mode, and a third mode, the first mode including preferentially loading the directory from the non-volatile memory device to the host memory buffer, the second mode including merging the directory and the mapping table from the non-volatile memory device to the host memory buffer, and the third mode including preferentially loading the mapping table from the non-volatile memory device to the host memory buffer.

[0011] Therefore, when the size of the host memory buffer cannot cover the entire address space of the mapping table of the main storage device in the storage device, the storage controller can dynamically load at least a portion of the mapping table and a portion of the directory into the host memory buffer based on the size of the host memory buffer and at least one of the locality information associated with the data access mode. The storage controller can perform a storage operation at a memory location specified by a physical address corresponding to a logical address by referring to the host memory buffer. The storage controller can reduce the access time of accessing the mapping table. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 A block diagram of a data storage system (or storage system) according to an embodiment of the inventive concept is shown.

[0014] Figure 2 The embodiment according to the present invention is shown Figure 1 Block diagram of the host device in .

[0015] Figure 3 It shows that according to the embodiment Figure 2 Example of host memory in .

[0016] Figure 4 The embodiment according to the present invention is shown Figure 1 Block diagram of the storage controller in .

[0017] Figure 5 The embodiment according to the present invention is shown Figure 4 A block diagram of an example of a loading controller in FIG.

[0018] Figure 6 Shows Figure 1 An example of the operation of a storage system.

[0019] Fig. 7A Shows the storage Figure 1 The directory and mapping table in each non-volatile storage device.

[0020] Figure 7B Shows Fig. 7A An example of a directory in .

[0021] Figure 8 Shows Figure 1 Another example of operation of a storage system in .

[0022] Fig. 9 shows that when executing with Figure 8The host memory buffer when associated with the operation.

[0023] Fig.10 Shows Figure 1 Another example of operation of a storage system in .

[0024] Fig.11 shows that when executing with Fig.10 The host memory buffer when associated with the operation.

[0025] Fig.12 The embodiment according to the present invention is shown Figure 1 An example of multiple channels and ways of a main storage device in FIG.

[0026] Fig.13 Shows Figure 1 A block diagram of the relationship between a storage controller and a nonvolatile memory device in a storage device.

[0027] Fig.14 The embodiment according to the present invention is shown Fig.13 Block diagram of a non-volatile memory device in FIG.

[0028] Fig.15 Shows Fig.14 A block diagram of a memory cell array in a nonvolatile memory device.

[0029] Fig.16 Shows Fig.15 A circuit diagram of one of the memory blocks.

[0030] Fig.17 Shows Fig.16 An example of the structure of a cell string CS in a memory block of FIG.

[0031] Fig.18 A flowchart of a method of operating a storage device according to an embodiment of the inventive concept is shown.

[0032] Fig.19 Shows Fig.18 Flowchart of the operations of loading directories and mapping tables in .

[0033] Fig. 20 A block diagram illustrating a memory system according to an embodiment of the inventive concept is shown.

[0034] Fig.21 The embodiment according to the present invention is shown Fig. 20 Block diagram of the storage controller in .

[0035] Fig.22A Shown according to Figure 1A graph showing the access time for accessing the mapping table as a function of the size of the host storage buffer in the storage system.

[0036] Fig. 22B Shown according to Fig. 20 The size of the buffer memory in the storage system and Fig.21 A graph of the access time for a storage controller to access a mapping table.

[0037] Fig.23 A block diagram of a system including a data storage device according to an embodiment of the inventive concept is shown.

[0038] Fig.24 A block diagram of a mobile device according to an embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0039] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown.

[0040] As is conventional in the field of the present invention, embodiments can be described and illustrated according to the blocks that perform the described one or more functions. These blocks (herein may be referred to as units or modules, etc.) are physically implemented by analog and / or digital circuits, such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and may be optionally driven by firmware and / or software. For example, the circuit may be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards, etc. The circuits constituting the blocks may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware that performs some functions of the blocks and processors that perform other functions of the blocks. Without departing from the scope of the present invention, each block of the embodiment may be physically divided into two or more interactive and discrete blocks. Similarly, without departing from the scope of the present invention, the blocks of the embodiment may be physically combined into more complex blocks.

[0041] Figure 1 A block diagram of a memory system (or a data storage system) according to an embodiment of the inventive concept is shown.

[0042] Reference Figure 1 , the storage system 10 includes a host device 100 and a storage device (or a solid state drive (ie, SSD)) 200 .

[0043] The host device 100 may control the overall operation of the storage device 200. The host device 100 may exchange signals with the storage device (SD) 200. The signals exchanged between the host device 100 and the storage device 200 may include, for example, commands, addresses, data, or other types of signals.

[0044] The storage device 200 includes a storage controller 300 and a main storage device 400, and the main storage device 400 may include a plurality of non-volatile storage devices (ie, non-volatile memory devices) 410-4k0. Each non-volatile storage device 410-4k0 (ie, NVM1-NVMk) may include a NAND flash memory. Here, k is an integer greater than 2.

[0045] The storage device 200 may further include a cache 210. The cache 210 is connected to the storage controller 300 and the main storage device 400 and may temporarily store metadata stored in the nonvolatile storage devices 410-4k0. The storage controller 300 may set the main storage device 400 based on the metadata temporarily stored in the cache 210.

[0046] The memory controller 300 may exchange signals such as commands, addresses, data, or other types of signals with the host device 100. The memory controller 300 may write and read data into and from a corresponding nonvolatile memory device according to a command.

[0047] A plurality of nonvolatile memory devices 410-4k0 may be used as storage media of the storage device 200. The nonvolatile memory devices 410-4k0 may be connected to the storage controller 300 through a plurality of channel groups CHG1-CHGk. Each channel group CHG1-CHGk may include at least one channel. One or more nonvolatile memory devices may be connected to one channel group. The nonvolatile memory devices connected to one channel group may be connected to the same data bus.

[0048] Although not shown, the storage device 200 may further include a pad to be connected to the host device 100. The storage device 200 may be easily attached to or detached from the host device 100 through the pad.

[0049] The pad may be formed inside the storage device 200, or may be formed in the form of a connector outside the storage device 200. In some embodiments, the storage device 200 may not include the pad and may be connected to the host device 100 through a routing process.

[0050] Figure 2 The embodiment according to the present invention is shown Figure 1 Block diagram of the host device in .

[0051] Reference Figure 2 , the host device 100 includes a processor 110 , a read only memory (ROM) 120 , a host memory 130 , a user interface (I / F) 140 , a storage interface (I / F) 150 , a memory controller 160 , and a bus 170 .

[0052] The bus 170 may refer to a transmission channel through which data is transmitted between the processor 110 , the ROM 120 , the host memory 130 , the user interface 140 , the storage interface 150 , and the memory controller 160 of the host device 100 .

[0053] ROM 120 may store various application programs. For example, an application program supporting storage protocols such as Advanced Technology Attachment (ATA), Small Computer System Interface (SCSI), Embedded Multimedia Card (eMMC), Universal Flash Storage (UFS) protocol, and NVMe may be stored in ROM 120.

[0054] The host memory 130 may temporarily store data or programs.

[0055] The storage interface 150 may include an interface supporting storage protocols such as SATA, SAS, eMMC, UFS, and NVMe. The host device 100 may perform an interface connection with the storage device 200 through the NVMe protocol.

[0056] The user interface 140 may be a physical or virtual medium, a computer program, etc. for exchanging information between the user and the host device 100, and includes physical hardware and logical software. For example, the user interface 140 may include an input device for allowing the user to manipulate the host device 100, and an output device for outputting the result of processing the user's input.

[0057] The processor 110 may control the overall operation of the host device 100. The processor 110 may generate a request (or command) for storing data in the storage device 200 or a request (or command) for reading data from the storage device 200, for example, by using an application stored in the ROM 120, and send the request to the storage device 200 via the storage interface 150.

[0058] The memory controller 160 may control the host memory 130 under the control of the processor 110. The memory controller 160 may allocate a portion of the host memory 130 as a host memory buffer, which may be accessed by the memory device 200 at a control line of the processor 110.

[0059] Figure 3 The embodiment according to the present invention is shown Figure 2Example of host memory in .

[0060] Reference Figure 3 , the host memory 130 includes a host region (HREG) 131 and a host memory buffer (HMB) 133. The host region 131 may be used by the host device 100, and the host memory buffer 133 may be used by the memory device 200.

[0061] The host memory buffer 133 may store metadata MTDT, such as a directory DIR1 and mapping tables MT1 ˜MTp that the storage controller 300 may load.

[0062] Each of the mapping tables MT1-MTp indicates a mapping relationship between a physical address and a logical address of a corresponding nonvolatile memory device included in the nonvolatile memory devices 410-4k0, and the directory DIR1 may store address information of a mapping table stored in a nonvolatile memory device. The storage controller 300 may map (convert) a logical address from the host device 100 into a physical address by referring to the metadata MTDT, and may perform a storage operation on at least one nonvolatile memory device based on the physical address.

[0063] The processor 110 may load source code stored in the main storage device 400 to the host area 131 in the host memory 130, and may run various software such as an operating system and applications by executing the code loaded to the host area 131. In addition, the processor 110 loads data stored in the storage device 200 and processes the data loaded to the host area 131. The processor 110 may store a portion of the data loaded to the host area 131 in the storage device 200, the portion of the data being determined to be retained for a long time.

[0064] Figure 4 The embodiment according to the present invention is shown Figure 1 Block diagram of the storage controller in .

[0065] Reference Figure 4 , the storage controller 300 includes: a processor 310 (such as a central processing unit (CPU)), a locality monitor 320, an error correction code (ECC) unit 330, a host interface (I / F) 340, a load controller 360, a non-volatile memory interface (NVM I / F) 350 and a bus 315.

[0066] The bus 315 may refer to a transmission channel through which data is transmitted between the processor 310 , the locality monitor 320 , the ECC unit 330 , the host interface 340 , the load controller 360 , and the nonvolatile memory interface 350 of the memory controller 300 .

[0067] The processor 310 may perform operations for data exchange between the host device 100 and the nonvolatile memory devices 410 ˜ 4 k0 . The processor 310 may execute firmware (F / W) 311 and a flash translation layer (FTL) 313 .

[0068] The host interface 340 is connected to the host device 100, and the non-volatile memory interface 350 is connected to the non-volatile storage devices 410-4k0. The processor 310 can communicate with the host device 100 via the host interface 340. The host interface 340 can be implemented using, for example, but not limited to, a SATA interface, a parallel advanced technology attachment (PATA) interface, a USB or SAS interface, an eMMC interface, a UFS interface, or an eMMC interface.

[0069] The processor 310 may communicate with the nonvolatile memory devices 410~4k0 through the nonvolatile memory interface 350. The nonvolatile memory interface 350 may be connected to each of the nonvolatile memory devices 410~4k0.

[0070] The ECC unit 330 may generate an error correction code (ECC) for data received from the host device 100 using various engines during a write operation. During a read operation, the ECC unit 330 may perform error detection and error correction on data read from the nonvolatile memory devices 410 ˜ 4 k0 and then provide the data to the host device 100.

[0071] The locality monitor 320 may monitor the locality of the physical address based on the host address HADDR (ie, logical address) received from the host device 100 , which may indicate access of the host device 100 to the main storage device 400 , and may provide the load controller 360 with locality information LIN indicating that the physical address has locality.

[0072] Here, locality indicates how often data is used, and when the same data is repeatedly used in a short time, or spatially close data is accessed in a short time, the data may be referred to as having high locality. The locality monitor 320 may determine data that is used many times or with a high frequency of use as having high locality, and data that is used few times or with a low frequency of use as having low locality. In this case, the locality information LIN may indicate high locality or low locality based on the frequency of use of the data.

[0073] The locality of data may also be referred to as the locality of a memory address storing the corresponding data. Therefore, the locality monitor 320 may determine a memory address that is accessed many times or with a high access frequency during a certain time period as having high locality, and may determine a memory address that is accessed few times or with a low access frequency as having low locality. In this case, the locality information LIN may indicate high locality or low locality based on the number of accesses to the memory address.

[0074] The load controller 360 may control loading of the directory and the mapping table to the host memory buffer 133 based on the locality information LIN and the size information HMSN associated with the size of the host memory buffer 133. The load controller 360 may generate a load mode signal LMS associated with controlling the loading of the directory and the mapping table, and may provide the load mode signal LMS to the nonvolatile memory devices 410-4k0 through the nonvolatile memory interface 350. The load controller 360 may include a register 363 storing a reference value.

[0075] Each nonvolatile storage device 410 ˜ 4k0 may receive a loading mode signal LMS, and may load a directory and a portion of a mapping table stored in the nonvolatile storage device to the host storage buffer 133 through the storage controller 300 based on a loading mode specified by the loading mode signal LMS among multiple loading modes.

[0076] Figure 5 The embodiment according to the present invention is shown Figure 4 A block diagram of an example of a loading controller in FIG.

[0077] Reference Figure 5 The load controller 360 includes a first comparator (comparator 1 ) 361 , a counter 362 , a register 363 , a second comparator (comparator 2 ) 364 , and a load mode signal generator 365 .

[0078] The first comparator 361 compares the size information HMSN with the first reference value SREF to output a first comparison signal CS1. The counter 362 outputs a count value CV by counting the number of misses MISS indicating that the logical address received from the host device 100 does not match any entry in the host storage buffer 133. The count value CV can be characterized as a miss rate of access requests to the host storage buffer 133. The second comparator 364 compares the count value CV with the second reference value CREF to output a second comparison signal CS2. The register 363 stores the first reference value SREF and the second reference value CREF, and provides the first reference value SREF to the first comparator 361 and the second reference value SREF to the second comparator 364.

[0079] The load mode signal generator 365 receives the first comparison signal CS1 , the second comparison signal CS2 , and the locality information LIN, and generates a load mode signal LMS based on the first comparison signal CS1 , the second comparison signal CS2 , and the locality information LIN.

[0080] When the first comparison signal CS1 indicates that the size information HMSN is less than the first reference value SREF (i.e., the size reference value), the load mode signal generator 365 may generate a load mode signal LMS that specifies a portion of the directories in the directory to be loaded preferentially in response to the first comparison signal CS1 and the locality information LIN. The portion of the directory may be associated with an address with high locality. When the first comparison signal CS1 indicates that the size information HMSN is equal to or greater than the first reference value SREF, the load mode signal generator 365 may generate a load mode signal LMS that specifies a merge load of at least one directory and a portion of the mapping table in the mapping table in response to the first comparison signal CS1 and the locality information LIN. The at least one directory may be associated with an address with high locality, the portion of the mapping table may be associated with an address with high locality, or the at least one directory and the portion of the mapping table may be associated with addresses with high locality, respectively. When the load mode signal LMS specifies merge loading, the storage controller 300 loads at least one directory and at least one mapping table to the host storage buffer 133 at a ratio of 1:N (N is a natural number greater than 2).

[0081] In an example embodiment, the storage controller 300 may determine a value of N based on the size information HMSN (or size) of the host storage buffer 133. In an example embodiment, the storage controller 300 may determine a value of N based on the locality information LIN and the size information HMSN of the host storage buffer 133. For example, the value of N related to the number of mapping tables associated with addresses having high locality may be determined based on the locality information LIN and / or the size information HMSN of the host storage buffer 133. That is, the storage controller 300 may determine a ratio of loading a directory and a mapping table to the host storage buffer 133 based on at least one of the locality information LIN and the size information HMSN of the host storage buffer 133. For example, if the number of mapping tables associated with addresses having high locality increases, the storage controller 300 may increase the value of N. For example, if the number of mapping tables associated with addresses having high locality decreases, the storage controller 300 may decrease the value of N.

[0082] When the second comparison signal CS2 indicates that the count value CV is equal to or greater than the second reference value CREF (i.e., the miss reference value), the load mode signal generator 365 may generate a load mode signal LMS specifying to update a portion of the loaded directories and a portion of the mapping tables in the mapping table in response to the second comparison signal CS2. When the load mode signal LMS specifies to update, each nonvolatile memory device 410-4k0 may load another portion of the directories or another portion of the mapping tables in the mapping table to the main memory buffer 133 through the memory controller 300.

[0083] The loading mode signal LMS can specify one of a plurality of loading modes. The plurality of loading modes may include a first loading mode, a second loading mode, and a third loading mode. As described above, the first loading mode can specify a portion of directories in a directory to be loaded first. As described above, the second loading mode can specify a portion of mapping tables in a merged loading of at least one directory and a mapping table. The third loading mode can specify a mapping table to be loaded first.

[0084] Figure 6 Shows Figure 1 An example of the operation of a storage system.

[0085] Reference Figures 1 to 6 , operation S10 represents a boot process (or boot sequence) of the storage system 10. Operations S11, S12, S13, S14, and S16 may be performed during operation S10. In operation S11, the processor 110 identifies the storage controller 300. That is, the processor 110 identifies the storage device 200. In operation S12, the storage controller 300 issues a request associated with using the host storage buffer 133 to the processor 110.

[0086] In operation S13, the processor 110 allocates (or assigns) a portion of the host memory 130 as the host storage buffer 133 by referring to the request of the storage controller 300. In operation S14, the processor 110 notifies the storage controller 300 of the allocation result and size information through a set feature command. In operation S16, the storage controller 300 loads at least one of (a) and (b) to the host storage buffer 133 based on the size information, wherein (a) is a portion of the directory in the directory, and (b) is at least a portion of the mapping table in the mapping table.

[0087] In operation S20, the host device 100 and the storage device 200 perform normal operations. Operations S21 and S23 may be performed in operation S20.

[0088] In operation S21, the host device 100 sends a command CMD and an address ADDR to the storage device 200. In operation S23, the storage controller 300 converts the address ADDR into a physical address by referring to at least a portion of the mapping table and a portion of the directory in the mapping table loaded into the host storage buffer 133, and performs a storage operation specified by the command CMD at a memory location specified by the physical address. According to the result of the storage operation, data DATA may be exchanged between the storage device 200 and the host device 100.

[0089] Fig. 7A Shows the storage Figure 1 The directory and mapping table in each non-volatile storage device in the.

[0090] Reference Fig. 7A , nonvolatile memory devices NVM1 ˜NVMk included in the main memory device 400 are shown.

[0091] For example, the directory DIR1 and the mapping tables MT11~MT1s may be stored in the meta area of ​​the nonvolatile memory device NVM1 among the nonvolatile memory devices NVM1~NVMk, the directory DIRg and the mapping tables MTg1~MTgs may be stored in the meta area of ​​the nonvolatile memory device NVMg among the nonvolatile memory devices NVM1~NVMk, and the directory DIRk and the mapping tables MTk1~MTks may be stored in the meta area of ​​the nonvolatile memory device NVMk among the nonvolatile memory devices NVM1~NVMk.

[0092] The mapping table MT11 may store the logical page numbers (logical addresses) LPN1-LPNj of the memory blocks in the nonvolatile memory device NVM1, the physical page numbers (physical addresses) PPN1-PPNj corresponding to the logical page numbers LPN1-LPNj, a bit map BM, and the first priority information PR11. The bit map BM may indicate the locality of the mapping table MT11 and may have a high / low value. The first priority information PR11 may indicate the access importance of the mapping table MT11.

[0093] The processor 310 of the memory controller 300 may determine a logic value of the bitmap BM and may determine a value of the first priority information PR11 based on access frequency and locality to a specific memory block during a program operation and a read operation of each memory block in each nonvolatile memory device NVM1~NVMk.

[0094] Figure 7B Shows Fig. 7A An example of a directory in .

[0095] Reference Figure 7B, the directory DIR1 may store address information MPPN1-MPPNs and second priority information PR21 of mapping tables MT11-MT1s, respectively. The address information MPPN1 may include physical address information of page PG2 of memory block BLK1 storing mapping table MT11. The processor 310 of the storage controller 300 may determine the value of the second priority information PR21 based on the bitmap BM and the first priority information of each mapping table MT11-MT1 stored according to the directory DIR1.

[0096] Figure 8 Shows Figure 1 Another example of operation of a storage system.

[0097] exist Figure 8 In the example, it is assumed that the size of the host storage buffer 133 is smaller than the first reference value.

[0098] and Figure 8 Operations associated with Figure 6 The operations associated with Figure 8 The associated operations also include operation S15, Figure 8 Operation S16a in Figure 6 Therefore, Figure 8 The startup process S10a in Figure 6 The following can be omitted Figure 8 in Figure 6 The same operation as described in the operation.

[0099] Reference Figure 8 , operation S10a represents a boot process of the storage system 10. Operations S11, S12, S13, S14, S15, and S16a may be performed during operation S10a. In operation S15, the storage controller 300 compares the size information HMSN of the host storage buffer 133 with the first reference value (SREF), and provides a loading mode signal LMS indicating that the size information HMSN is less than the first reference value to the main storage device 400. In operation S16a, the storage controller 300 preferentially loads a portion of the directories in the directory to the host storage buffer 133 based on the second priority information (PR21) of the directory.

[0100] Fig. 9 shows that when executing with Figure 8 The host memory buffer when associated with the operation.

[0101] Reference Fig. 9 , when the size of the host memory buffer 133 is smaller than the first reference value, the directories DIR1 ˜DIRg among the directories DIR1 ˜DIRk may be loaded into the host memory buffer 133 by the memory controller 300 .

[0102] Fig.10 Shows Figure 1 Another example of operation of a storage system.

[0103] exist Fig.10 In the embodiment, it is assumed that the size of the host storage buffer 133 is equal to or greater than the first reference value.

[0104] and Fig.10 Operations associated with Figure 6 The operations associated with Fig.10 The associated operations also include operation S15, Fig.10 Operation S16b in Figure 6 Therefore, Fig.10 The startup process S10b in Figure 6 The startup process S10 in is different. The following can be omitted Fig.10 in Figure 6 The operations are the same as in the description.

[0105] Reference Fig.10 , operation S10b represents a boot process of the storage system 10. Operations S11, S12, S13, S14, S15, and S16b may be performed during operation S10b. In operation S15, the storage controller 300 compares the size information HMSN of the host storage buffer 133 with a first reference value, and provides a loading mode signal LMS indicating that the size information HMSN is equal to or greater than the first reference value to the main storage 400. In operation S16b, the storage controller 300 loads at least one directory in the directory and a portion of the mapping tables in the mapping table to the host storage buffer 133 based on the priority information and the locality information LIN.

[0106] Fig.11 shows that when executing with Fig.10 The host memory buffer when associated with the operation.

[0107] Reference Fig.11, when the size of the host storage buffer 133 is equal to or greater than the first reference value, the directory DIR1 of the directories DIR1 to DIRk and some mapping tables MT21 to MT2q and MTg1 to MTgq may be loaded to the host storage buffer 133 by the storage controller. The directory DIR1 and the mapping tables MT21 to MT2q and MTg1 to MTgq may be loaded to the host storage buffer 133 at a ratio of 1:N (N is a natural number greater than 2). The storage controller 300 may adjust the value of N based on the size information HMSN and the locality information LIN. That is, the storage controller 300 may adjust the value of N according to the number of mapping tables associated with addresses having high locality at a given size of the host storage buffer 133. The number of mapping tables associated with addresses having high locality may be obtained from the locality information LIN.

[0108] The directory DIR1 and the mapping tables MT21 ˜ MT2q and MTg1 ˜ MTgq may be associated with different non-volatile memory devices, respectively. The directory DIR1 and the mapping tables MT21 ˜ MT2q and MTg1 ˜ MTgq may be independent of each other.

[0109] Fig.12 The embodiment according to the present invention is shown Figure 1 An example of multiple channels and ways of a main storage device in FIG.

[0110] Reference Fig.12 , the nonvolatile storage devices 410~4k0 are coupled to corresponding channel groups in a plurality of channel groups CHG1~CHGk. As shown in the figure, a plurality of nonvolatile storage devices 411~41m of the nonvolatile storage device 410 coupled to the channel group CHG1, a plurality of nonvolatile storage devices 421~42m of the nonvolatile storage 420 coupled to the channel group CHG2, ..., and a plurality of nonvolatile storage devices 4k1~4km of the nonvolatile storage 4k0 coupled to the channel group CHGk can form a plurality of ways: Way 1~Way m (Way1~Waym). ​​Here, m is a natural number greater than 2. That is, in each channel group CHG1~CHGk, m ways can include corresponding m nonvolatile storage devices 411~41m, 421~42m, ..., 4k1~4km.

[0111] A way indicates a unit for dividing nonvolatile memory devices sharing the same channel. Each nonvolatile memory device can be identified according to a channel number and a way number.

[0112] Fig.13 Shows Figure 1 A block diagram of the relationship between a storage controller and a nonvolatile memory device (ie, a nonvolatile memory device) in a storage device of FIG.

[0113] Reference Fig.13 The nonvolatile memory device 411 may perform an erase operation, a program operation, or a write operation under the control of the memory controller 300. The nonvolatile memory device 411 receives a command CMD, an address ADDR, and data DATA from the memory controller 300 through an input / output line to perform such an operation.

[0114] In addition, the nonvolatile memory device 411 receives a control signal CTRL through a control line, and receives power PWR from the memory controller 300 through a power line.

[0115] Fig.14 The embodiment according to the present invention is shown Fig.13 Block diagram of a non-volatile memory device in FIG.

[0116] Reference Fig.14 , the nonvolatile memory device 411 includes a memory cell array 420 , an address decoder 450 , a page buffer circuit 430 , a data input / output (I / O) circuit 440 , a control circuit 460 , and a voltage generator 470 .

[0117] The memory cell array 420 may be coupled to the address decoder 450 through a string selection line SSL, a plurality of word lines WL, and a ground selection line GSL. In addition, the memory cell array 420 may be coupled to the page buffer circuit 430 through a plurality of bit lines BL.

[0118] The memory cell array 420 may include a plurality of memory cells coupled to a plurality of word lines WL and a plurality of bit lines BL.

[0119] In some example embodiments, the memory cell array 420 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or a vertical structure). In this case, the memory cell array 420 may include a vertical cell string in a vertical direction such that at least one memory cell is located on another memory cell.

[0120] In other example embodiments, the memory cell array 420 may be a two-dimensional memory cell array formed on a substrate in a two-dimensional structure (or a horizontal structure).

[0121] Fig.15 Shows Fig.14 A block diagram of a memory cell array in a nonvolatile memory device.

[0122] Reference Fig.15 , the memory cell array 420 may include a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz extend along the first direction D1, the second direction D2, and the third direction D3. In an embodiment, the memory blocks BLK1 to BLKz are composed of Fig.14For example, the address decoder 450 may select a memory block BLK corresponding to a block address among the memory blocks BLK1 to BLKz.

[0123] Fig.16 Shows Fig.15 A circuit diagram of one of the memory blocks.

[0124] Fig.16 The memory block BLKi may be formed in a three-dimensional structure (or a vertical structure) on the substrate SUB. For example, a plurality of memory cell strings included in the memory block BLKi may be formed in a direction PD perpendicular to the substrate SUB.

[0125] Reference Fig.16 , the memory block BLKi may include memory cell strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 (hereinafter referred to as memory cell strings NS11 to NS33) coupled between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the memory cell strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 (hereinafter referred to as memory cells MC1 to MC8), and a ground selection transistor GST. Fig.16 , each of the memory cell strings NS11 to NS33 is illustrated as including eight memory cells MC1 to MC8. However, example embodiments are not limited thereto. In some example embodiments, each of the memory cell strings NS11 to NS33 may include any number of memory cells.

[0126] The string selection transistor SST may be connected to the corresponding string selection lines SSL1, SSL2, and SSL3. A plurality of memory cells MC1 to MC8 may be connected to the corresponding word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8 (hereinafter may be referred to as word lines WL to WL8), respectively. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL1, GSL2, and GSL3. The string selection transistor SST may be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

[0127] Word lines (eg, WL1) having the same height may be connected together, and ground selection lines GSL1 to GSL3 and string selection lines SSL1 to SSL3 may be separated. Fig.16, the memory block BLKi is shown to be coupled to eight word lines WL1 to WL8 and three bit lines BL1 to BL3. However, example embodiments are not limited thereto. In some example embodiments, the memory cell array 420 may be coupled to any number of word lines and bit lines.

[0128] Fig.17 Shows Fig.16 An example of a structure of a cell string CS (eg, memory cell string NS11) in a memory block of FIG.

[0129] Reference Fig.16 and Fig.17 , the pillars PL are disposed on the substrate SUB such that the pillars PL extend in a direction perpendicular to the substrate SUB to contact the substrate SUB. Fig.17 Each of the ground selection line GSL (e.g., ground selection line GSL1), word lines WL1 to WL8, and string selection line SSL (e.g., string selection line SSL1) shown in FIG. 1 may be formed of a conductive material, e.g., a metal material, parallel to the substrate SUB. The pillar PL may contact the substrate SUB through the conductive material forming the string selection line SSL, word lines WL1 to WL8, and ground selection line GSL.

[0130] exist Fig.17 A cross-sectional view taken along line AA' is also shown in FIG. In an embodiment, a cross-sectional view of a first memory cell MC1 corresponding to a first word line WL1 is shown. The pillar PL may include a cylindrical body BD. An air gap AG may be defined inside the body BD.

[0131] The body BD may include P-type silicon and may be a region where a channel will be formed. The pillar PL may also include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trapping layer CT surrounding the tunnel insulating layer TI. The blocking insulating layer BI may be disposed between the first word line WL and the pillar PL. The body BD, the tunnel insulating layer TI, the charge trapping layer CT, the blocking insulating layer BI, and the first word line WL may constitute a charge trapping transistor formed in a direction perpendicular to the substrate SUB or the upper surface of the substrate SUB. The string selection transistor SST, the ground selection transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

[0132] Return to reference Fig.14 , the control circuit 460 may receive a command (signal) CMD and an address (signal) ADDR from the storage controller 300, and control an erase cycle, a program cycle, and a read operation of the nonvolatile memory device 411 based on the command signal CMD and the address signal ADDR. A program cycle may include a program operation and a program verification operation. An erase cycle may include an erase operation and an erase verification operation.

[0133] For example, the control circuit 460 may generate a control signal CTL for controlling the voltage generator 470 based on the command signal CMD and generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 460 may provide the row address R_ADDR to the address decoder 450 and provide the column address C_ADDR to the data input / output circuit 440.

[0134] The address decoder 450 may be coupled to the memory cell array 420 through the string selection line SSL, the plurality of word lines WL, and the ground selection line GSL. During a program operation or a read operation, the address decoder 450 may determine one of the plurality of word lines WL as a first word line (i.e., a selected word line) based on the row address R_ADDR, and determine the remaining word lines of the plurality of word lines WL except the first word line as unselected word lines.

[0135] The voltage generator 470 may generate a word line voltage VWL based on the control signal CTL, which is required for the operation of the nonvolatile memory device 411. The voltage generator 470 may receive power PWR from the memory controller 300. The word line voltage VWL may be applied to a plurality of word lines WL through the address decoder 450.

[0136] For example, during an erase operation, the voltage generator 470 may apply an erase voltage to a well of a memory block and may apply a ground voltage to all word lines (i.e., all word lines) of the memory block. During an erase verification operation, the voltage generator 470 may apply an erase verification voltage to all word lines of the memory block or sequentially apply the erase verification voltage to the word lines word by word line.

[0137] For example, during a program operation, the voltage generator 470 may apply a program voltage to a first word line and may apply a program pass voltage to unselected word lines. In addition, during a program verification operation, the voltage generator 470 may apply a program verification voltage to a first word line and may apply a verification pass voltage to unselected word lines.

[0138] In addition, during a read operation, the voltage generator 470 may apply a read voltage to a first word line, and may apply a read pass voltage to unselected word lines.

[0139] The page buffer circuit 430 may be coupled to the memory cell array 420 through a plurality of bit lines BL. The page buffer circuit 430 may include a plurality of page buffers. In some example embodiments, one page buffer may be connected to one bit line. In other example embodiments, one page buffer may be connected to two or more bit lines.

[0140] The page buffer circuit 430 may temporarily store data to be programmed in a selected page or data read out from a selected page.

[0141] The data input / output circuit 440 may be coupled to the page buffer circuit 430 through the data line DL. During a program operation, the data input / output circuit 440 may receive data DATA from the memory controller 300 and provide the data DATA to the page buffer circuit 430 based on the column address C_ADDR received from the control circuit 460. During a read operation, the data input / output circuit 440 may provide the data DATA stored in the page buffer circuit 430 to the memory controller 300 based on the column address C_ADDR received from the control circuit 460.

[0142] In addition, the page buffer circuit 430 and the data input / output circuit 440 read data from the first region of the memory cell array 420 and write the read data to the second region of the memory cell array 420. That is, the page buffer circuit 430 and the data input / output circuit 440 may perform a copy-back operation. The page buffer circuit 430 and the data input / output circuit 440 may be controlled by the control circuit 460.

[0143] Fig.18 A flowchart of a method of operating a storage device according to an embodiment of the inventive concept is shown.

[0144] Reference Figures 1 to 18 , a method of operating a storage device 200 is provided, the storage device 200 includes a main storage device 400, wherein the main storage device 400 stores data and includes a plurality of nonvolatile memory devices (i.e., nonvolatile memory devices), and a storage controller 300 controls the main storage device 400. In operation S610, the storage controller 300 receives size information HMSN of a host storage buffer 133 included in the host device 100 that controls the storage device 200 from the host device 100. The host device 100 may allocate a portion of the host memory 130 as the host storage buffer 133 in response to a request from the storage controller 300, and may send the allocation result and the size information HMSN of the host storage buffer 133 to the storage controller 300.

[0145] In operation S620, the storage controller 300 may load at least one of (a) and (b) into the host storage buffer 133 based on at least one of the size information HMSN and the locality information LIN associated with the data access mode of the host device 100, wherein (a) is at least a portion of the mapping tables in the mapping table MT; and (b) is at least one directory in a portion of the directories in the directory DIR. As described above, the locality information LIN relates to the frequency of use of data and / or the number of accesses to the memory address, and is therefore associated with the access mode of the host device 100, or in other words, how the host device 100 accesses data in the storage device 200. The mapping tables MT are stored in the non-volatile memory device, and each mapping table MT represents a mapping relationship between a physical address and a logical address of the corresponding non-volatile memory device. The directory stores address information of the mapping table MT.

[0146] In operation S670 , the memory controller 300 performs a memory operation designated by the command CMD at a memory location designated by the address ADDR by referring to the host memory buffer 133 based on the command CMD and the address ADDR from the host device 100 .

[0147] Fig.19 Shows Fig.18 Flowchart of the operations of loading directories and mapping tables in .

[0148] Reference Fig.19 , operation S620 includes operations S630, S640 and S650.

[0149] In operation S630 , the load controller 360 of the memory controller 300 compares the size information HMSN of the host memory buffer 133 with the first reference value SREF and determines whether the size of the host memory buffer 133 is smaller than the first reference value SREF.

[0150] When the size of the host storage buffer 133 is smaller than the first reference value SREF (Yes in S630 ), in operation S640 , the storage controller 300 preferentially loads a portion of the directories to the host storage buffer 133 based on second priority information of the directories.

[0151] When the size of the host storage buffer 133 is equal to or greater than the first reference value SREF (No in S630), in operation S640, the storage controller 300 loads at least one directory in the directory and a portion of the mapping table in the mapping table into the host storage buffer 133 based on the locality information LIN, the first priority information of the mapping table, and the second priority information of the directory.

[0152] Therefore, when the size of the host storage buffer 133 cannot cover the entire address space of the mapping table of the main storage device 400 in the storage device 200, the storage controller 300 can dynamically load at least a portion of the mapping table and a portion of the directory to the host storage buffer 133 based on at least one of the size of the host storage buffer 133 and the locality information LIN associated with the data access mode. The storage controller 300 can perform a storage operation at a memory location specified by a physical address corresponding to a logical address by referring to the host storage buffer 133. The storage controller 300 can reduce the access time of accessing the mapping table.

[0153] Fig. 20 A block diagram of a memory system according to an embodiment of the inventive concept is shown.

[0154] Reference Fig. 20 , the storage system 10a includes a host device 100a and a storage device 200a.

[0155] Fig. 20 The storage system 10a and Figure 1 The storage system 10 is different in that: Fig. 20 The host device 100a in FIG. 100b does not use a portion of the host memory as a host memory buffer, and Fig. 20 The storage controller 300a in the embodiment performs a storage operation after loading a part of the directory and a part of the mapping table into the buffer memory included in the storage controller 300a based on the size and locality information of the buffer memory. Fig. 20 in Figure 1 The structure and function are the same as those in the description.

[0156] The storage device 200a includes a storage controller 300a and a main storage device 400. The main storage device 400 includes a plurality of nonvolatile storage devices 410-4k0. The storage device 200a may further include a DRAM 220. The DRAM 220 is connected to the storage controller 300a and the main storage device 400, and may temporarily store metadata stored in the nonvolatile storage devices 410-4k0.

[0157] Fig.21 The embodiment according to the present invention is shown Fig. 20 Block diagram of the storage controller in .

[0158] Reference Fig.21, the storage controller 300a includes a processor 310a, such as a central processing unit (CPU), a locality monitor 320, an ECC unit 330, a host interface (I / F) 340, a buffer memory 370, a nonvolatile memory interface (I / F) 350, and a bus 315. The processor 310a may include a load controller 360a.

[0159] In example embodiments, the load controller 360a may be included in the memory controller 300a as a separate component, rather than being included in the processor 310a.

[0160] The configuration and operation of the storage controller 300a may be substantially similar to Figure 4 Therefore, the following may be omitted. Fig.21 in Figure 4 The structure and function are the same as those in the description.

[0161] exist Fig.21 In the example, it is assumed that the size of the buffer memory 370 cannot cover the entire address space of the mapping table of the main storage device 400 in the storage apparatus 300a.

[0162] The locality monitor 320 may monitor the location of the physical address based on the host address HADDR (ie, logical address) received from the host device 100 a , and may provide the load controller 360 with locality information LIN indicating that the physical address has locality.

[0163] The load controller 360a may control loading of the directory and the mapping table to the buffer memory 370 based on the locality information LIN and the size information BMSN associated with the size of the buffer memory 370. The load controller 360a may generate a load mode signal LMS1 associated with controlling loading of the directory and the mapping table, and may provide the load mode signal LMS1 to the nonvolatile storages 400a-400k through the nonvolatile memory interface 350. The load controller 360a may include a register storing a reference value.

[0164] The load controller 360 a may compare the size information BMSN with a first reference value, and may generate a load mode signal LMS1 designating that a portion of the directories 371 are preferentially loaded into the buffer memory 370 in response to the size information BMSN being less than the first reference value.

[0165] The load controller 360a can compare the size information BMSN with the first reference value, and can generate a load mode signal LMS1 in response to the size information BMSN being equal to or greater than the first reference value, which specifies that a portion of the directory 371 and a portion of the mapping table 373 are merged and loaded into the buffer memory 370.

[0166] Therefore, when the size of a part or the whole of the buffer memory 370 cannot cover the entire address space of the mapping table of the main storage device 400 in the storage device 200a, the storage controller 300a can dynamically load at least a part of the mapping table and a part of the directory to the buffer memory 370 based on the size of the buffer memory 370 and at least one of the locality information LIN associated with the data access mode. The storage controller 300a can perform a storage operation at a memory location specified by a physical address corresponding to a logical address by referring to the buffer memory 370. The storage controller 300a can reduce the access time of accessing the mapping table.

[0167] Fig.22A Shown according to Figure 1 A graph of the access time to the mapping table versus the size of the main storage buffer in the storage system.

[0168] exist Fig.22A In the example above, we assume that N is 32.

[0169] exist Fig.22A , reference numeral 711 (first case) indicates the access time when a portion of the directory is loaded into the host storage buffer HMB (for example, the host storage buffer 133 in the host memory 130 of the host device 100), reference numeral 712 (second case) indicates the access time when the directory and the mapping table are loaded into the host storage buffer HMB at a ratio of 1:N based on the size and locality of the host storage buffer HMB, and reference numeral 713 (third case) indicates the access time when a portion of the mapping table is loaded into the host storage buffer HMB.

[0170] Reference Fig.22A , when the size of the host memory buffer HMB is less than the first reference size SREF11, the access time of the first case is shorter than the access time of the second case and the access time of the third case. When the size of the host memory buffer HMB is equal to or greater than the first reference size SREF11, the access time of the second case is shorter than the access time of the first case and the access time of the third case.

[0171] In addition, when the size of the host memory buffer HMB is larger than the second reference size SREF12, the access time of the second case and the access time of the third case are shorter than the access time of the first case.

[0172] Fig. 22B Shown according to Fig. 20 The size of the buffer memory in the storage system (eg, the buffer memory 370 in the storage controller 300a of the storage device 200a) and Fig.21 A graph showing the access time of a storage controller accessing a mapping table.

[0173] exist Fig. 22B In the example above, we assume that N is 32.

[0174] exist Fig. 22B In the figure, reference numeral 721 (first case) represents the access time when a portion of the directory is loaded into the buffer memory 370, reference numeral 722 (second case) represents the access time when the directory and the mapping table are loaded into the buffer memory 370 at a ratio of 1:N based on the size and locality of the buffer memory 370, and reference numeral 723 (third case) represents the access time when a portion of the mapping table is loaded into the buffer memory 370.

[0175] Reference Fig. 22B , when the size of the buffer memory 370 is smaller than the first reference size SREF21, the access time of the first case is shorter than the access time of the second case and the access time of the third case.

[0176] When the size of the buffer memory 370 is equal to or greater than the first reference size SREF21, the access time of the second case is substantially the same as the access time of the first case.

[0177] Fig.23 A block diagram of a system including a data storage device according to an embodiment of the inventive concept is shown.

[0178] Reference Fig.23 , the system 1000 includes a host device 2000 and a storage device 3000. For example, the host device 2000 may be an embedded multimedia card (eMMC), a solid state drive (SSD), or the like.

[0179] The host device 2000 may be configured to control data processing operations, such as data read operations and data write operations.

[0180] The host device 2000 may include a processor (CPU) 2100, a host memory (HMEM) 2200, a host controller interface (HCI) 2300, and a memory controller 2400 connected through a bus 20. The host memory 2200 may allocate a host memory buffer 2210 that stores a portion of a directory and a portion of a mapping table. An operating system (OS) and / or a host firmware (FW) 2110 may be executed by the processor 2100. The processor 2100 may execute the operating system and the host firmware 2110 to perform these operations. The memory controller 2400 may control the main memory 2200 under the control of the processor 2100. The memory controller 2400 may allocate a portion of the host memory 2200 as a host memory buffer 2210 that can be accessed by the storage device 3000 under the control of the processor 2100.

[0181] The host controller interface 2300 may interface with the storage device 3000. For example, the host controller interface 2300 is configured to issue a command CMD to the storage device 3000, receive a response RES to the command CMD from the storage device 3000, send write data to the storage device 3000, and receive read data from the storage device 3000.

[0182] The memory device 3000 may include a plurality of nonvolatile memory devices (NVMs) 3100 and a memory controller 3200 .

[0183] Alternatively, an external high voltage VPP may be provided to the nonvolatile memory device 3100. The memory controller 3200 may be connected to the nonvolatile memory device 3100 through a plurality of channels CH1 to CHi. The memory controller 3200 may include one or more processors CPU 3210, an ECC engine 3220, a host interface 3230, a load controller 3240, a nonvolatile memory interface 3250, and a locality monitor 3260 connected through a bus 30.

[0184] The processor 3210 is configured to control the overall operation of the storage controller 3200. For example, the processor 3210 may run firmware 3212 having a flash translation layer (FTL), and may include other firmware. The FTL may perform various functions such as address mapping, read calibration, error correction, and other functions.

[0185] As described above, when monitoring the locality of data, the locality monitor 3260 monitors the locality of data and provides the locality information to the load controller 3240 .

[0186] As described above, the load controller 3240 dynamically loads at least a portion of the mapping table and a portion of the directory to the host memory buffer 2210 based on at least one of the size and locality information of the host memory buffer 2210 .

[0187] The host interface 3230 may provide an interface connected to an external device such as the host device 2000. The nonvolatile memory interface 3250 may provide an interface connected to the nonvolatile memory device 3100. The host device 2000 and the memory device 3000 may be connected through the bus 15.

[0188] Fig.24 is a block diagram illustrating a mobile device according to an example embodiment.

[0189] Reference Fig.24 , the mobile device 4000 may include an application processor 4100 (including one or more application processors), a communication module 4200 , a display / touch module 4300 , a data storage device 4400 , and a mobile RAM 4500 .

[0190] The application processor 4100 controls the operation of the mobile device 4000. The communication module 4200 is implemented to perform wireless or wired communication with an external device. The display / touch module 4300 is implemented to display data processed by the application processor 4100 and / or receive data through a touch panel (not shown). The data storage device 4400 is used to store user data.

[0191] The data storage device 4400 may be, for example, an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash memory (UFS) device, etc. The data storage device 4400 may include a load controller 4410 that dynamically loads at least a portion of the mapping table and a portion of the directory into the host storage buffer 4510 in the mobile RAM 4500 as described above.

[0192] The mobile RAM 4500 temporarily stores data for processing operations of the mobile device 4000. For example, the mobile RAM 4500 may be, for example, a double data rate (DDR) synchronous DRAM (SDRAM), a low power DDR (LPDDR) SDRAM, a graphics DDR (GDDR) SDRAM, a Rambus DRAM, or a RAM. wait.

[0193] As described above, the storage controller can dynamically load at least a portion of the mapping table and a portion of the directory into the main memory buffer based on the size of the main memory buffer and at least one of the locality information associated with the data access pattern, and can reduce the access time of accessing the mapping table.

[0194] The present disclosure can be applied to various electronic devices including storage devices. For example, the present disclosure can be applied to the following systems: such as mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital televisions, set-top boxes, portable game consoles, navigation systems, etc.

[0195] The foregoing is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.

Claims

1. A storage device, comprising: a main storage device configured to store data and including a plurality of non-volatile memory devices; as well as a storage controller configured to control the primary storage device, wherein the storage controller is configured to load at least one of a portion of the directories in the directory to the host storage buffer in a first loading mode, and load at least a portion of the mapping tables in the mapping table and the at least one of the portion of the directories in the directory to the host storage buffer in a second loading mode, based on at least one of a size of the host storage buffer included in the external host device and locality information associated with a data access mode of the external host device, The mapping table is stored in the non-volatile memory device, and the mapping table indicates a mapping relationship between a physical address and a logical address of a corresponding non-volatile memory device in the non-volatile memory device, and The directory is configured to store address information of the mapping table stored in the non-volatile memory device.

2. The storage device according to claim 1, wherein: The mapping table is configured to store first priority information indicating access importance of the mapping table, and The directory is configured to store second priority information indicating an access importance of the directory.

3. The storage device according to claim 2, wherein: The storage controller is further configured to, in response to determining that the size of the host storage buffer is smaller than a reference value, preferentially load at least one directory among the portion of the directories into the host storage buffer based on the second priority information in the first loading mode.

4. The storage device according to claim 2, wherein: The storage controller is further configured to, in response to determining that the size of the host storage buffer is equal to or greater than a reference value, load both at least one of the directories in the portion of the directories and at least a portion of the mapping tables in the mapping tables into the host storage buffer based on the first priority information, the second priority information, and the locality information in the second loading mode.

5. The storage device according to claim 4, wherein: The at least one directory in the portion of the directories and the at least one portion of the mapping tables are associated with different nonvolatile memory devices in the plurality of nonvolatile memory devices.

6. The storage device according to claim 4, wherein: The storage controller is further configured to load at least one of the portion of the directories and at least a portion of the mapping tables into the host storage buffer at a ratio of 1:N in the second loading mode, where N is a natural number greater than 2.

7. The storage device according to claim 6, wherein: The memory controller is further configured to determine a value of N based on a size of the host memory buffer.

8. The storage device according to claim 1, wherein: The storage controller is further configured to: determining a load ratio of the directory and the mapping table based on a size of the host storage buffer and the locality information; as well as In the second loading mode, the at least one directory in the part of the directories and the at least one part of the mapping tables are loaded into the host storage buffer according to the determined loading ratio.

9. The storage device according to claim 8, wherein: The mapping table is configured to store first priority information indicating the access importance of the mapping table; The directory is configured to store second priority information indicating the access importance of the directory; as well as The storage controller is configured to select, in the second loading mode, the at least one directory of the portion of the directories and the at least one portion of the mapping tables to be loaded into the host storage buffer based on the first priority information and the second priority information.

10. The storage device according to claim 1, wherein: The storage controller comprises: a locality monitor configured to generate the locality information by monitoring a host access address indicating an access of the external host device to the main storage device; and A load controller is configured to control loading of the directory and the mapping table into the host memory buffer based on the locality information and size information associated with a size of the host memory buffer.

11. The storage device according to claim 10, wherein: The loading controller comprises: a first comparator configured to compare the size information with a first reference value to output a first comparison signal; a counter configured to output a count value by counting the number of misses, the miss being that the logical address received from the external host device does not match any of the entries in the host memory buffer; a second comparator configured to compare the count value with a second reference value to output a second comparison signal; a loading mode signal generator configured to generate a loading mode signal designating one of the first loading mode and the second loading mode based on the first comparison signal, the second comparison signal, and the locality information; and A register is configured to store the first reference value and the second reference value.

12. The storage device of claim 11, wherein the loading mode signal generator is configured to generate a loading mode signal specifying the first loading mode in response to the first comparison signal indicating that the size information is less than the first reference value, the first loading mode comprising preferentially loading at least one directory in the portion of the directories.

13. The storage device according to claim 11, wherein: The loading mode signal generator is configured to generate a loading mode signal specifying the second loading mode in response to the first comparison signal indicating that the size information is equal to or greater than the first reference value, the second loading mode including merge loading of at least one directory in the portion of the directories and at least a portion of the mapping tables in the mapping tables.

14. The storage device according to claim 1, wherein: The memory controller is further configured to execute the first loading mode and the second loading mode during a boot sequence of the memory device.

15. The storage device according to claim 14, wherein: The storage controller is further configured to, after the boot sequence is completed, perform the following operations: receiving commands and addresses from the external host device; searching for a physical address specified by the address by referring to the host memory buffer; and A storage operation specified by the command is performed in the storage area specified by the physical address.

16. A method for operating a storage device, the storage device comprising a main storage device for storing data and a storage controller for controlling the main storage device, the main storage device comprising a plurality of non-volatile storage devices, the method comprising: Receiving, by the storage controller, size information of a host storage buffer included in the external host device from an external host device controlling the storage device; The storage controller loads at least one of a portion of the directories in the directory into the host storage buffer in a first loading mode, and loads at least a portion of the mapping tables in the mapping table and the at least one of the portion of the directories in the directory into the host storage buffer in a second loading mode based on at least one of size information of the host storage buffer and locality information associated with a data access mode of the external host device, wherein the mapping table is stored in the non-volatile storage device, the mapping table indicating a mapping relationship between a physical address and a logical address of a corresponding non-volatile storage device in the non-volatile storage device, wherein the directory is configured to store address information of the mapping table; as well as A storage operation specified by the command is performed by the memory controller based on the command and the address received from the host device by referring to the host memory buffer in a storage area of ​​the nonvolatile memory device specified by the address.

17. A storage device comprising: a main storage device, the main storage device comprising a non-volatile storage device storing a directory and a mapping table, wherein the mapping table indicates a mapping relationship between a physical address and a logical address of a corresponding non-volatile storage device in the non-volatile storage device, and the directory stores address information of the mapping table stored in the non-volatile storage device; and a storage controller configured to control the main storage device in a plurality of modes and selectively load the directory and the mapping table from the nonvolatile memory device to the host storage buffer based on a size of a host storage buffer of an external host device and a count value indicating the number of misses in which a logical address received from the external host device does not match any of entries in the host storage buffer, Wherein, the multiple modes include a first mode, a second mode and a third mode, the first mode includes preferentially loading the directory from the non-volatile memory device to the host storage buffer, the second mode includes merging the directory and the mapping table from the non-volatile memory device and loading them into the host storage buffer, and the third mode includes preferentially loading the mapping table from the non-volatile memory device to the host storage buffer.

18. The storage device according to claim 17, wherein: The memory controller is further configured to select the first mode when a size of the host memory buffer is smaller than a size reference value.

19. The storage device according to claim 17, wherein: The memory controller is further configured to select the third mode when the count value is equal to or greater than a miss reference value.

20. The storage device of claim 17, wherein the storage controller is further configured to: during the second mode, load at least one of the directories and at least one of the mapping tables from the non-volatile memory device to the host storage buffer at a ratio of 1:N, where N is a natural number greater than 2.

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