Error correction code decoder and semiconductor memory device

Abstract

An error correction code (ECC) decoder for a semiconductor memory device is provided. The ECC decoder includes an ECC checker, a syndrome generator, and an error detection / correction circuit. The ECC checker generates characteristic information that represents first error information associated with a message bit in an input codeword read from a target page in a memory cell array. The syndrome generator performs an operation on the message bit and the parity check bit in the input codeword based on a parity check matrix, and outputs a syndrome vector representing second error information associated with the input codeword. The error detection / correction circuit generates a transmission codeword by selectively correcting the error bit in the input codeword based on the characteristic information and the syndrome vector, generates a flag signal indicating whether the transmission codeword includes an error bit, and outputs a transmission message based on the transmission codeword.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2018-0134853 filed on November 6, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments relate to a memory device, and more particularly, to an error correction code (ECC) decoder of a semiconductor memory device, a semiconductor memory device, and a memory system. Background Art

[0004] Semiconductor memory devices can be categorized into non-volatile memory devices such as flash memory devices and volatile memory devices such as DRAM. The high-speed operation and cost-effectiveness of DRAM make it suitable for system memory. However, due to the continued reduction in DRAM manufacturing design rules, bit errors in memory cells within DRAM may increase rapidly, and DRAM yields may decrease. Summary of the Invention

[0005] One aspect is to provide an error correction code (ECC) decoder of a semiconductor memory device that can enhance error detection capability without increasing parity check overhead.

[0006] Another aspect is to provide a semiconductor memory device capable of enhancing error detection capability without increasing parity check overhead.

[0007] Another aspect is to provide a memory system that can enhance error detection capability without increasing parity check overhead.

[0008] According to one aspect of one or more example embodiments, there is provided an error correction code (ECC) decoder of a semiconductor memory device, the ECC decoder including: an ECC checker configured to generate characteristic information representing first error information associated with a message bit in an input codeword read from a target page in a memory cell array; a syndrome generator configured to output a syndrome vector representing second error information associated with the input codeword by performing an operation on the message bit and parity bits in the input codeword based on a parity check matrix; and an error detection / correction circuit configured to generate a transmission codeword by selectively correcting the error bits in the input codeword based on the characteristic information and the syndrome vector, generate a flag signal indicating whether the transmission codeword includes the error bit, and output a transmission message based on the transmission codeword.

[0009] According to another aspect of one or more example embodiments, there is provided a semiconductor memory device including: a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines; an error correction code (ECC) engine configured to perform ECC encoding on a message received from outside the semiconductor memory device to generate an initial codeword, store the initial codeword in a target page in the memory cell array, generate feature information and a syndrome vector based on the initial codeword read from the target page, generate a transmission codeword by selectively correcting an error bit in the initial codeword based on the feature information and the syndrome vector, and generate a flag signal indicating whether the transmission codeword includes an error bit; and a control logic circuit configured to control the ECC engine based on a command and an address received from outside the semiconductor memory device.

[0010] According to another aspect of one or more example embodiments, a memory system is provided, comprising: a semiconductor memory device; and a memory controller configured to control the semiconductor memory device, wherein the semiconductor memory device comprises: a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines; an error correction code (ECC) engine configured to perform ECC encoding on a message received from the memory controller to generate an initial codeword, store the initial codeword in a target page in the memory cell array, generate feature information and a syndrome vector based on the initial codeword read from the target page, generate a transmission codeword by selectively correcting an error bit in the read initial codeword based on the feature information and the syndrome vector, and generate a flag signal indicating whether the transmission codeword includes an error bit; and a control logic circuit configured to control the ECC engine based on a command and an address received from the memory controller.

[0011] According to another aspect of one or more example embodiments, an error correction code (ECC) decoder is provided, comprising at least one microprocessor, the at least one microprocessor being configured to: generate characteristic information based on message bits in an input codeword read from a target page in a memory cell array; generate a syndrome vector from the input codeword by performing an operation on the message bits and parity bits in the input codeword based on a parity check matrix; and generate a transmission codeword by selectively correcting a first error bit in the input codeword based on the characteristic information and the syndrome vector, wherein the ECC decoder detects whether the first error bit occurs in the input codeword and detects whether a second error bit occurs in the input codeword based on the characteristic information and the syndrome vector, and generates a flag signal indicating whether the second error bit occurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram illustrating a memory system according to an example embodiment;

[0014] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of a memory controller in a memory system;

[0015] Figure 3 is a diagram showing a method according to an example embodiment Figure 2 A block diagram of an example of a system ECC engine in a memory controller;

[0016] Figure 4 It is a view used to describe the on-chip ECC level in terms of data bits and parity bits;

[0017] Figure 5 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of a semiconductor memory device in a memory system;

[0018] Figure 6 yes Figure 5 A circuit diagram of an example embodiment of a memory cell of a semiconductor memory device shown in FIG.

[0019] Figure 7 Show Figure 5 An example of a first bank array of a semiconductor memory device;

[0020] Figure 8 is a diagram showing a method according to an example embodiment Figure 5 A block diagram of an ECC engine in a semiconductor memory device;

[0021] Figure 9 is a diagram showing a method according to an example embodiment Figure 8 A block diagram of an ECC decoder in an ECC engine;

[0022] Figure 10 A parity check matrix of a first type implementing a second ECC is shown;

[0023] Figure 11 Shown in detail Figure 10 The first type of parity check matrix in ;

[0024] Figure 12A is a diagram showing a method according to an example embodiment Figure 9 A block diagram of an example of an error detection / correction circuit of an ECC decoder in FIG.

[0025] Figure 12B It shows that according to Figure 12A a table of characteristic information, syndrome vectors, and the number of error bits determined by the summation signal in the error detection / correction circuit;

[0026] Figure 13 is a diagram showing a method according to an example embodiment Figure 9 A flowchart of an example operation of an ECC decoder;

[0027] Figure 14 It shows that according to Figure 12A a table of characteristic information, syndrome vectors, and the number of error bits determined by the summation signal in the error detection / correction circuit;

[0028] Figure 15 A second type of parity check matrix implementing a second ECC is shown;

[0029] Figure 16 Shown in detail Figure 15 The second type of parity check matrix in ;

[0030] Figure 17A is a diagram showing a method according to an example embodiment Figure 9 A block diagram of another example of an error detection / correction circuit in;

[0031] Figure 17B It shows that according to Figure 17A a table of characteristic information, syndrome vectors, and the number of error bits determined by the selected elements in the error detection / correction circuit;

[0032] Figure 18 is a diagram showing a method according to an example embodiment Figure 9 A flowchart of another example operation of an ECC decoder;

[0033] Figure 19 It shows that according to Figure 17A a table of the number of error bits determined according to the characteristic information, the syndrome vector and the selected element in the error detection / correction circuit;

[0034] Figure 20 is a flowchart illustrating a method of operating a semiconductor memory device according to example embodiments;

[0035] Figure 21 is a flowchart illustrating a method of operating a memory system according to an example embodiment;

[0036] Figure 22 is a block diagram illustrating a semiconductor memory device according to example embodiments;

[0037] Figure 23 is adopted according to an example embodiment Figure 22A cross-sectional view of a three-dimensional (3D) chip structure of a semiconductor memory device; and

[0038] Figure 24 is a block diagram illustrating a memory system according to example embodiments. DETAILED DESCRIPTION

[0039] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown.

[0040] According to various example embodiments disclosed herein, message bits in a code include information associated with a system-level error correction code (ECC). An ECC decoder in a semiconductor memory device generates signature information based on the message bits, generates a syndrome vector based on a codeword, and detects / corrects error bits in the codeword based on the signature information and the syndrome vector. Consequently, the ECC decoder and semiconductor memory device can enhance error detection capabilities by detecting two error bits and correcting one error bit based on a single-error correction (SEC) code.

[0041] Figure 1 is a block diagram illustrating a memory system according to example embodiments.

[0042] Reference Figure 1 , the memory system 10 may include a memory controller 100 and a semiconductor memory device 200 .

[0043] The memory controller 100 may control the overall operation of the memory system 10. The memory controller 100 may control the overall data exchange between the host and the semiconductor memory device 200. For example, the memory controller 100 may write data to the semiconductor memory device 200 or read data from the semiconductor memory device 200 in response to a request from the host. In addition, the memory controller 100 may issue an operation command for controlling the semiconductor memory device 200 to the semiconductor memory device 200.

[0044] The memory controller 100 transmits a command CMD and an address ADDR to the semiconductor memory device 200 and exchanges a message CM(MSG) with the semiconductor memory device 200. The semiconductor memory device 200 transmits a flag signal FL to the memory controller 100.

[0045] In some embodiments, the semiconductor memory device 200 is a memory device including resistive memory cells, such as magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), phase change random access memory (PRAM), and ferroelectric random access memory (FRAM). In other exemplary embodiments, the semiconductor memory device 200 includes dynamic memory cells, such as dynamic random access memory (DRAM).

[0046] The memory controller 100 may include a system ECC engine 130 and a link ECC engine 160 , and the semiconductor memory device 200 may include a link ECC engine 213 , an ECC engine 400 , and a memory cell array (MCA) 300 .

[0047] In some example embodiments, the memory controller 100 may omit the chained ECC engine 160 , and the semiconductor memory device 200 may omit the chained ECC engine 213 .

[0048] The system ECC engine 130 performs first ECC encoding on data received from the host to generate a message MSG, and provides the message MSG to the link ECC engine 160. The link ECC engine 160 performs link ECC encoding on the message MSG to generate link parity and transmits the encoded message CM to the semiconductor memory device 200. The encoded message CM includes the link parity and the message MSG. Furthermore, the link ECC engine 160 may receive the encoded message CM from the semiconductor memory device 200, perform link ECC decoding on the encoded message CM provided from the semiconductor memory device 200 to recover the message MSG, and provide the message MSG to the system ECC engine 130. The system ECC engine 130 performs first ECC decoding on the message MSG to recover the data and provides the data to the host. The system ECC engine 130 may use a first ECC. In example embodiments, the first ECC may be a single parity code or a single error correction / double error detection (SEC-DED) code. In other example embodiments, the first ECC may be a code where the sum of all bits in the encoded message CM corresponds to an even number, for example.

[0049] The link ECC engine 213 performs link ECC decoding on the encoded message CM provided from the memory controller 100 to restore the message MSG, and provides the message MSG to the ECC engine 400. The ECC engine 400 performs ECC encoding on the message MSG based on the second ECC to generate parity bits, and stores the codeword including the message MSG and the parity bits in the target page in the memory cell array 300. In addition, the ECC engine 400 generates feature information and a syndrome vector based on the codeword read from the target page, selectively corrects error bits in the read codeword based on the feature information and the syndrome vector, and generates a flag signal indicating whether the transmission message to be sent to the memory controller 100 includes an error bit.

[0050] The link ECC engine 213 performs link ECC encoding on the transmission message and provides the encoded message CM to the memory controller 100 .

[0051] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of a memory controller in a memory system.

[0052] Reference Figure 2 , the memory controller 100 includes a central processing unit (CPU) 110, a host interface 120, a data register 125, a system ECC engine 130, a link ECC engine 160, a flag buffer 185, a command buffer 190, and an address buffer 195. The system ECC engine 130 includes an ECC encoder 140 and an ECC decoder 150. The link ECC engine 160 includes a link ECC encoder 170 and a link ECC decoder 180.

[0053] The host interface 120 receives a request REQ and data DTA from the host, and provides the data DTA to the data register 125. The data register 125 outputs the data to the system ECC engine 130 continuously (or sequentially).

[0054] The ECC encoder 140 performs first ECC encoding on the data to generate a message MSG1, and provides the message MSG1 to the concatenated ECC encoder 170. The concatenated ECC encoder 170 performs concatenated ECC encoding on the message MSG1 to output an encoded message CM1.

[0055] The link ECC decoder 180 performs link ECC decoding on the encoded message CM2 received from the semiconductor memory device 200 to generate a message MSG2, and provides the message MSG2 to the system ECC decoder 150. The system ECC decoder 150 performs first ECC decoding on the message MSG2 to recover the data DTA, and provides the data DTA to the CPU 110. The flag buffer 185 receives the flag signal FL from the semiconductor memory device 200, and provides the flag signal FL to the CPU 110.

[0056] The CPU 110 receives the data DTA and the flag signal FL, and determines how to process the data DTA based on the flag signal FL.

[0057] The command buffer 190 stores a command CMD corresponding to the request REQ and transmits the command CMD to the semiconductor memory device 200 under the control of the CPU 110. The address buffer 195 stores an address ADDR and transmits the address ADDR to the semiconductor memory device 200 under the control of the CPU 110.

[0058] Figure 3 is a diagram showing a method according to an example embodiment Figure 2 A block diagram of an example of a system ECC engine in FIG.

[0059] Reference Figure 3 , the system ECC engine 130 includes a memory 135 , an ECC encoder 140 , and an ECC decoder 150 .

[0060] Memory 135 may include a first ECC (ECC1) 137. First ECC 137 may be a single parity check code or a SEC-DED code. First ECC 137 may be a code in which the sum of all bits in the encoded message CM corresponds to an even number. Therefore, ECC encoder 140 may encode data DTA such that the sum of the message bits in message MSG1 indicates whether message MSG1 includes an error bit.

[0061] Figure 4 is a diagram for describing on-chip ECC levels according to data bits and parity bits.

[0062] exist Figure 4 In the figure, SEC stands for single error correction, DED stands for double error detection, and DEC stands for double error correction. Figure 4The parity bits and the corresponding size overhead (parity O / H) of the parity bits are shown. The parity bits correspond to Hamming codes or extended Hamming codes. The size overhead of the parity bits corresponds to the ratio of the parity bits of the parity data corresponding to the write data to the data bits of the write data.

[0063] like Figure 4 As shown, as the number of parity bits (referred to as the number of parity bits) increases relative to the same number of data bits (referred to as the number of data bits), that is, as the ratio of the number of parity bits to the number of data bits increases, the error detection and correction capability increases. As the number of data bits increases relative to the same error detection and correction capability, the corresponding number of parity bits increases, but the ratio of the number of parity bits to the number of data bits decreases.

[0064] Thus, as the ratio of the number of parity bits to the corresponding number of data bits increases, the error detection capability and / or error correction capability can be increased. Consequently, as the ratio of the number of parity bits to the corresponding number of data bits increases, the on-chip ECC level can be improved.

[0065] If the on-chip ECC level is set to a higher level than required, memory resources may be wasted and the size of the semiconductor memory device may increase. Conversely, if the on-chip ECC level is set to a lower level than required, error detection and correction capabilities may be reduced and the performance of the semiconductor memory device may be reduced.

[0066] Figure 5 is a diagram showing a method according to an example embodiment Figure 1 Block diagram of a semiconductor memory device in a memory system.

[0067] Reference Figure 5 The semiconductor memory device 200 includes a control logic circuit 210, an address register 220, a bank control logic 230, a row address multiplexer (RA MUX) 240, a column address (CA) latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier 285, an input / output (I / O) gating circuit (I / O gating) 290, a data input / output (I / O) buffer 295, a refresh counter 245, an ECC engine 400, a link ECC engine 213, and a flag buffer 287.

[0068] The memory cell array 300 includes first to eighth bank arrays 310 to 380. The row decoder 260 includes first to eighth bank row decoders 260 a to 260 h coupled to the first to eighth bank arrays 310 to 380, respectively, the column decoder 270 includes first to eighth bank column decoders 270 a to 270 h coupled to the first to eighth bank arrays 310 to 380, respectively, and the sense amplifiers 285 include first to eighth bank sense amplifiers 285 a to 285 h coupled to the first to eighth bank arrays 310 to 380, respectively.

[0069] The first to eighth bank arrays 310 to 380, the first to eighth bank row decoders 260a to 260h, the first to eighth bank column decoders 270a to 270h, and the first to eighth bank sense amplifiers 285a to 285h may form the first to eighth banks. Each of the first to eighth bank arrays 310 to 380 includes a plurality of memory cells MC coupled to word lines WL and bit lines BTL.

[0070] The address register 220 receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100 , and the control logic circuit 210 receives a command CMD from the memory controller 100 .

[0071] The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230 , may provide the received row address ROW_ADDR to the row address multiplexer 240 , and may provide the received column address COL_ADDR to the column address latch 250 .

[0072] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. In response to the bank control signal, one of the first to eighth bank row decoders 260a to 260h corresponding to the bank address BANK_ADDR may be activated, and one of the first to eighth bank column decoders 270a to 270h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal.

[0073] The row address multiplexer (RA MUX) 240 may receive a row address ROW_ADDR from the address register 220 and may receive a refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output one of the row address ROW_ADDR and the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to eighth bank row decoders 260a to 260h.

[0074] The activated one of the first to eighth bank row decoders 260a to 260h may decode the row address RA output from the row address multiplexer 240 and activate a word line corresponding to the row address RA. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address RA.

[0075] The column address latch 250 may receive a column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. In some embodiments, in burst mode, the column address latch 250 may generate a column address that is incremented from the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or generated column address to the first to eighth bank column decoders 270a to 270h.

[0076] An activated one of the first to eighth bank column decoders 270 a to 270 h may decode the column address COL_ADDR output from the column address latch 250 and may control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR.

[0077] The I / O gating circuit (I / O Gating) 290 includes a circuit system for gating input / output data. The I / O gating circuit (I / O Gating) 290 also includes a read data latch for storing data output from the first to eighth memory bank arrays 310 to 380, and a write driver for writing data to the first to eighth memory bank arrays 310 to 380.

[0078] The codeword CW to be read from one of the first to eighth memory bank arrays 310 to 380 may be sensed by a sense amplifier coupled to the one memory bank array from which data is to be read, and the codeword CW may be stored in a read data latch. The codeword CW stored in the read data latch of the I / O gating circuit (I / O Gating) 290 is ECC-decoded by the ECC engine 400 and may be provided to the memory controller 100 via the data I / O buffer 295.

[0079] The message MSG to be written to one of the first to eighth memory bank arrays 310 to 380 may be provided from the memory controller 100 to the data I / O buffer 295. The message MSG may be provided to the ECC engine 400. The ECC engine 400 performs ECC encoding on the message MSG to generate parity bits, and provides a codeword CW including the message MSG and the parity bits to the I / O gating circuit (I / O Gating) 290. The I / O gating circuit (I / O Gating) 290 may write the codeword CW to a target page in the one memory bank array through a write driver.

[0080] The ECC engine 400 can generate feature information and a syndrome vector about the codeword read from the target page, can generate a transmission codeword by selectively correcting error bits in the read codeword based on the feature information and the syndrome vector, and can generate a flag signal FL indicating whether the transmission codeword includes an error bit. When the ECC engine 400 performs ECC encoding and / or ECC decoding, the ECC engine 400 can use a second ECC represented by a parity check matrix. The second ECC can be an SEC code. Therefore, the ECC engine 400 can detect two error bits and can correct one error bit.

[0081] The flag buffer 287 receives the flag signal FL and transmits the flag signal FL to the memory controller 100 .

[0082] The control logic circuit 210 may control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 may generate a control signal for the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the memory controller 100 and a mode register 212 that sets an operation mode of the semiconductor memory device 200.

[0083] For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The control logic circuit 210 may generate a first control signal CTL1 to control the I / O gating circuit (I / O Gating) 290 and a second control signal CTL2 to control the ECC engine 400 .

[0084] Figure 6 yes Figure 5 0047] Circuit diagram of an example implementation of a memory cell shown in .

[0085] Reference Figure 6 Memory cell MC includes a cell capacitor CC and a transistor CT. Transistor CT may be a selection element (or a switching element) that connects / disconnects cell capacitor CC to / from bit line BTL according to the voltage of word line WL. Transistor CT may be coupled between cell capacitor CC, word line WL, and bit line BTL, and cell capacitor CC may be coupled between transistor CT and a plate voltage (not shown).

[0086] Figure 6 The memory cell MC is shown as being implemented with a dynamic memory cell. However, in some example embodiments, the memory cell MC may be implemented with a resistive memory cell.

[0087] Figure 7 Shown Figure 5 An example of a first memory bank array in a semiconductor memory device.

[0088] Reference Figure 7 The first memory bank array 310 includes a plurality of word lines WL1 to WLm (m is a natural number greater than 2), a plurality of bit lines BTL1 to BTLj (j is a natural number greater than 2), and a plurality of memory cells MC arranged near intersections between the word lines WL1 to WLm and the bit lines BTL1 to BTLj. In some example embodiments, each of the plurality of memory cells MC may include a dynamic random access memory (DRAM) cell structure. The plurality of word lines WL1 to WLm connected to the plurality of memory cells MC may be defined as rows of the first memory bank array 310, and the plurality of bit lines BTL1 to BTLj connected to the plurality of memory cells MC may be defined as columns of the first memory bank array 310.

[0089] Figure 8 is a diagram showing a method according to an example embodiment Figure 5 Block diagram of an ECC engine in a semiconductor memory device.

[0090] Reference Figure 8, the ECC engine 400 includes a memory 410, an ECC encoder 420, and an ECC decoder 430. The memory 410 stores a second ECC (ECC2) 415, and the ECC encoder 420 and the ECC decoder 430 are connected to the memory 410 and use the second ECC 415.

[0091] The ECC encoder 420 is connected to the memory 410 and performs ECC encoding on the message MSG based on the second ECC 415 to generate the parity bit PRT in a write operation. The ECC encoder 420 can provide the codeword CW including the message MSG and the parity bit PRT to the I / O gating circuit (I / O Gating) 290.

[0092] The ECC decoder 430 is connected to the memory 410, receives the codeword CW in a read operation, generates characteristic information representing first error information associated with message bits in a message MSG of the codeword CW based on the message bits, generates a syndrome vector indicating second error information associated with the codeword CW by performing an operation on the message bits and parity bits PRT based on the second ECC 415, selectively corrects the error bits in the codeword CW based on the characteristic information and the syndrome vector, and generates a flag signal FL indicating whether a transmission message to be sent to the memory controller 100 includes the error bits.

[0093] The second ECC (ECC2) 415 may be an SEC code. The ECC decoder 430 may detect two error bits and correct one error bit based on the SEC code. Therefore, the ECC decoder 430 may enhance error detection capability without increasing parity check overhead.

[0094] Although it is described that the ECC encoder 420 and the ECC decoder 430 are coupled to the memory 410 to use the second ECC (ECC2) 415, the second ECC (ECC2) 415 may be implemented with XOR gates within the ECC encoder 420 and the ECC decoder 430.

[0095] Figure 9 is a diagram showing a method according to an example embodiment Figure 8 Block diagram of the ECC decoder in the ECC engine.

[0096] Reference Figure 9 , the ECC decoder 430 includes a systematic ECC checker 440 , a syndrome generator 450 , and an error detection / correction circuit 460 .

[0097] The system ECC checker 440 may generate characteristic information CI representing first error information associated with the message bits in the codeword CW based on the message bits in the codeword CW. The syndrome generator 450 may output a syndrome vector SV representing second error information associated with the codeword CW by performing an operation on the message bits and parity check bits in the codeword CW based on the parity check matrix that implements the second ECC (ECC2) 415. The error detection / correction circuit 460 may selectively correct the error bits in the codeword CW based on the characteristic information CI and the syndrome vector SV, may generate a flag signal FL indicating whether the codeword CW includes an error bit, and may output the flag signal FL and a transmission message MSG′ to be sent to the memory controller 100 based on the codeword CW.

[0098] Figure 10 A first type of parity check matrix implementing the second ECC is shown.

[0099] Reference Figure 10 , the parity check matrix PCM1 may include a first part INP11 corresponding to the message bits and a second part PTP12 corresponding to the parity check bits. The parity check matrix PCM1 is stored in the memory 410 and can implement the second ECC (ECC2) 415. The first part INP11 may include a plurality of column vectors corresponding to the message bits, respectively, and each column vector may include a high-level element corresponding to an even number. The second part PTP12 may include a plurality of parity check column vectors corresponding to the parity check bits, respectively, and each parity check column vector may include a high-level element corresponding to an odd number. The parity check matrix PCM1 may include different column vectors and different row vectors.

[0100] Figure 11 Shown in detail Figure 10 The first type of parity check matrix in .

[0101] exist Figure 11 In FIG, it is assumed that the code word CW includes bits d0 to d11, the message MSG includes bits (message bits) d0 to d7, and the parity bits PRT include bits d8 to d11.

[0102] Figure 9 The system ECC checker 440 in FIG. 4 may perform a first modulo-two operation on the sum of the message bits d0 to d7 to output a result of the first modulo-two operation associated with the first error information as the characteristic information CI.

[0103] Reference Figure 11, each of the column vectors CV11 to CV18 corresponding to each of the message bits d0 to d7 includes a high-level element corresponding to an even number, and each of the parity column vectors PCV11 to PCV14 corresponding to each of the parity bits PRT including bits d8 to d11 includes a high-level element corresponding to an odd number. In addition, the row vectors in the row direction are different from each other, and the column vectors in the column direction are different from each other.

[0104] exist Figure 11 , the column vector CV18 corresponding to the message bit d7 includes all zero elements. Typically, the parity check matrix does not use a column vector with all zero elements, and the error detection / correction circuit 460 knows that Figure 3 The ECC encoder 140 in employs an even code, and thus the error detection / correction circuit 460 can determine whether an error bit occurs in the message bit d7 based on the characteristic information CI.

[0105] In addition, Figure 11 In , s0 to s3 represent the elements of the syndrome vector SV.

[0106] Figure 12A is a diagram showing a method according to an example embodiment Figure 9 A block diagram of an example of an error detection / correction circuit in FIG.

[0107] exist Figure 12A In, assuming Figure 9 The syndrome generator 450 includes the following: Figure 10 The first type of parity check matrix PCM1 in .

[0108] Reference Figure 12A , the error detection / correction circuit 460a includes an adder 470, an error detector 472, a modulus calculator 474, a data corrector 476, a message extractor 479 and a flag generator 478.

[0109] Adder 470 receives syndrome vector SV and generates a sum signal x by calculating the sum of each element of syndrome vector SV. Error detector 472 receives characteristic information CI and sum signal x and, based on whether the sum of sum signal x and characteristic information CI corresponds to zero, generates a detection signal DS indicating whether codeword CW includes an error bit. That is, error detector 472 adds sum signal x and characteristic information CI, determines whether the result is zero, and, if so, generates detection signal DS indicating that codeword CW does not include an error bit. Modulo calculator 474 receives characteristic information CI, sum signal x, and detection signal DS. In response to the sum of sum signal x and characteristic information CI being non-zero, it performs a second modulo-2 operation on the sum of sum signal x and characteristic information CI and generates modulo signal MS1 indicating whether the result of the second modulo-2 operation is zero. Data corrector 476 receives codeword CW, detection signal DS, and modulo signal MS1 and, based on detection signal DS and modulo signal MS1, selectively corrects codeword CW to provide transmission codeword CW′. The message extractor 479 extracts the transmission message MSG' from the transmission codeword CW' and outputs the transmission message MSG'.

[0110] The flag generator 478 receives the detection signal DS and the modulo signal MS1 and generates a flag signal FL1 indicating whether the transmission codeword CW′ includes an error bit based on the detection signal DS and the modulo signal MS1. The flag generator 478 may output the flag signal FL1 having a first logic level in response to the detection signal DS indicating that the codeword CW does not include an error bit.

[0111] The modulo calculator 474 may perform a second modulo-2 operation in response to the detection signal DS indicating that the codeword CW includes an error bit, and the data corrector 476 may correct the error bit in the codeword CW in response to the modulo signal MS1 indicating that the result of the second modulo-2 operation is non-zero to output a transmission codeword CW′. In this case, the flag generator 478 may output a flag signal FL1 having a first logic level in response to the detection signal DS and the modulo signal MS1 to indicate that the transmission message MSG′ does not include an error bit.

[0112] Modulo calculator 474 may perform a second modulo-2 operation in response to a detection signal indicating that codeword CW includes an error bit, and data corrector 476 may output transmission codeword CW′ without correcting the error bit in codeword CW in response to modulo signal MS1 indicating that the result of the second modulo-2 operation is zero. In this case, flag generator 478 may output flag signal FL1 having a second logic level in response to detection signal DS and modulo signal MS1 to indicate that transmission message MSG′ includes an uncorrectable error bit.

[0113] Figure 12B It shows that according to Figure 12AA table of characteristic information, syndrome vectors, and the number of error bits determined by the sum signal in the error detection / correction circuit.

[0114] Reference Figure 12A and Figure 12B , when the characteristic information CI is zero and the syndrome vector SV is a zero vector, the code word CW does not include an error bit. When the characteristic information CI is zero and the sum signal x is an odd number, the code word CW includes one error bit. When the characteristic information CI is zero and the sum signal x is a positive even number, the code word CW includes two error bits. When the characteristic information CI is high and the sum signal x is an odd number, the code word CW includes two error bits. When the characteristic information CI is high and the sum signal x is a positive even number, the code word CW includes one error bit.

[0115] When the codeword CW includes one error bit, the data corrector 476 corrects the error bit in the codeword CW to output a transmission codeword CW'. In this case, the flag signal FL1 has a first logic level (e.g., a low level). When the codeword CW includes two error bits, the data corrector 476 outputs the transmission codeword CW' without correcting the error bit in the codeword CW. In this case, the flag signal FL1 has a second logic level (e.g., a high level).

[0116] Figure 13 is a diagram showing a method according to an example embodiment Figure 9 Flowchart of an example operation of an ECC decoder.

[0117] Reference Figures 9 to 13In operation S110, the system ECC checker 440 generates characteristic information CI based on the message bits in the codeword CW read from the target page in the memory cell array. For example, the system ECC checker 440 performs a first modulo-2 operation on the sum of the message bits d0 to d7 to generate the characteristic information CI. In operation S112, the syndrome generator 450 generates a syndrome vector based on the message bits and parity check bits in the codeword CW. For example, the syndrome generator 450 performs an operation on the codeword CW using a first-type parity check matrix PCM1 to generate a syndrome vector SV. In operation S114, the adder 470 generates a sum signal x by calculating the sum of each element of the syndrome vector SV. In operation S120, the error detector 472 determines whether the sum of the sum signal x and the characteristic information CI is equal to zero. Based on whether the sum of the sum signal x and the characteristic information CI corresponds to zero, the error detector 472 generates a detection signal DS indicating whether the codeword CW includes an error bit. In operation S122, when the sum of the sum signal x and the characteristic information CI corresponds to zero ("Yes" in operation S120), the code word and the flag signal having a first logic level are output. Because the code word CW does not include an error bit, the flag generator 478 outputs the flag signal FL1 having a first logic level and the message extractor 479 outputs the transmission message MSG' based on the transmission code word CW'.

[0118] When the sum of the sum signal x and the characteristic information CI corresponds to non-zero ("No" in operation S120), the modulo calculator 474 performs a second modulo-2 operation on the sum of the sum signal x and the characteristic information CI to generate a modulo signal MS1. It is then determined whether the modulo signal MS1 is equal to zero (operation S130). When the modulo signal MS1 is zero ("Yes" in operation S130), the code word and a flag signal having a second logic level are output at operation S138. Since the code word CW includes an uncorrectable error bit, the flag generator 478 outputs a flag signal FL1 having a second logic level. The data corrector 476 outputs the transmission code word CW' without correcting the error bit in the code word CW, and the message extractor 479 outputs the transmission message MSG' based on the transmission code word CW'.

[0119] When the modulo signal MS1 is at a high level (i.e., non-zero) ("No" in operation S130), it indicates that the codeword CW includes a correctable error bit. The data corrector 476 selects the message bit corresponding to the non-zero element of the syndrome vector SV in operation S132, flips the selected message bit (operation S134), and outputs the corrected codeword and a flag signal with a first logic level (operation S136). That is, the data corrector 476 outputs the transmission codeword CW' by correcting the error bit in the codeword CW. The message extractor 479 outputs the transmission message MSG' based on the transmission codeword CW', and the flag generator 478 outputs the flag signal FL1 with a first logic level.

[0120] Figure 14 It shows that according to Figure 12A A table of characteristic information, syndrome vectors, and the number of error bits determined by the sum signal in the error detection / correction circuit.

[0121] like Figure 14 As shown, the number of error bits and the positions of the error bits can be detected based on the combination of the characteristic information CI, the syndrome vector SV and the sum signal x.

[0122] Therefore, the first type of parity check matrix PCM1 can represent a t (t is a natural number greater than zero) bit correction code, and the error detection / correction circuit 460a can correct t error bits in the code word CW and detect (t+1) error bits in the code word CW. For example, when t is 1, the first type of parity check matrix PCM1 represents an SEC code, and the error detection / correction circuit 460a corrects one error bit in the code word CW and detects two error bits in the code word CW. Therefore, the error detection / correction circuit 460a can perform SEC-DED.

[0123] Figure 15 A second type of parity check matrix implementing a second ECC is shown.

[0124] refer to Figure 15 , the parity check matrix PCM2 may include a first part INP21 corresponding to the message bit and a second part PTP22 corresponding to the parity check bit. The parity check matrix PCM2 is stored in the memory 410 and can implement the second ECC (ECC2) 415. The parity check matrix PCM2 includes a plurality of row vectors RV1 to RVo, and a row vector RVk among the plurality of row vectors RV1 to RVo has a first sub-part corresponding to the first part INP21 and a second sub-part corresponding to the second part PTP22. All elements in the first sub-part have a low level, and all elements in the second sub-part have a high level. The parity check matrix PCM2 may include different column vectors and different row vectors.

[0125] Figure 16 Shown in detail Figure 15 The second type of parity check matrix in .

[0126] exist Figure 16 In FIG, it is assumed that the code word CW includes bits d0 to d11, the message MSG includes bits (message bits) d0 to d7, and the parity bits PRT include bits d8 to d11.

[0127] Figure 9 The system ECC checker 440 in FIG. 4 may perform a first modulo-2 operation on the sum of the message bits d0 to d7 to output a result of the first modulo-2 operation associated with the first error information as the characteristic information CI.

[0128] Reference Figure 16 , the second type of parity check matrix PCM2 includes row vectors RV1 to RV4, and row vector RV1 (first row vector) has a first sub-portion including all zero elements and a second sub-portion including all non-zero elements. The first sub-portion corresponds to the first portion INP21, and the second sub-portion corresponds to the second portion PTP22. In addition, elements s0 to s3 of the syndrome vector SV can be generated based on the row vectors RV1 to RV4.

[0129] exist Figure 16 In the example, the column vector corresponding to the message bit d7 includes all zero elements. Typically, the parity check matrix does not use a column vector with all zero elements, and the error detection / correction circuit 460 knows that Figure 3 The ECC encoder 140 in employs an even code, and the error detection / correction circuit 460 can determine whether an error bit occurs in the message bit d7 based on the characteristic information CI.

[0130] Figure 17A is a diagram showing a method according to an example embodiment Figure 9 A block diagram of another example of an error detection / correction circuit in FIG.

[0131] exist Figure 17A In, assuming Figure 9 The syndrome generator 450 in the embodiment adopts Figure 15 The second type of parity check matrix PCM2 in .

[0132] Reference Figure 17A , the error detection / correction circuit 460b includes an adder 480, an error detector 482, a modulus calculator 484, a data corrector 486, a message extractor 489 and a flag generator 488.

[0133] Adder 480 receives syndrome vector SV and generates a sum signal x by calculating the sum of each element of syndrome vector SV. Error detector 482 receives characteristic information CI and sum signal x and, based on whether the sum of sum signal x and characteristic information CI corresponds to zero, generates a detection signal DS indicating whether codeword CW includes an error bit. That is, error detector 482 adds sum signal x and characteristic information CI, determines whether the result is zero, and, if the result is zero, generates detection signal DS indicating that codeword CW does not include an error bit. Modulo calculator 484 receives characteristic information CI, syndrome vector SV, and detection signal DS. In response to the sum of sum signal x and characteristic information CI being non-zero, it performs a second modulo-2 operation on the sum of the selected element in syndrome vector SV corresponding to row vector RVk and characteristic information CI, and generates modulo signal MS2 indicating whether the result of the second modulo-2 operation is zero. The data corrector 486 receives the codeword CW, the detection signal DS and the modulo signal MS2 and selectively corrects the codeword CW based on the detection signal DS and the modulo signal MS2 to provide a transmission codeword CW'. The message extractor 489 extracts the transmission message MSG' from the transmission codeword CW' and outputs the transmission message MSG'.

[0134] The flag generator 488 receives the detection signal DS and the modulo signal MS2 and generates a flag signal FL2 indicating whether the transmission codeword CW′ includes an error bit based on the detection signal DS and the modulo signal MS2.

[0135] The modulo calculator 484 may perform a second modulo-2 operation in response to the detection signal DS indicating that the codeword CW includes an error bit, and the data corrector 486 may correct the error bit in the codeword CW in response to the modulo signal MS2 indicating that the result of the second modulo-2 operation is non-zero to output a transmission codeword CW′. In this case, the flag generator 488 may output a flag signal FL2 having a first logic level in response to the detection signal DS and the modulo signal MS2 to indicate that the transmission message MSG′ does not include an error bit.

[0136] Modulo calculator 484 may perform a second modulo-2 operation in response to the detection signal indicating that codeword CW includes an error bit, and data corrector 486 may output transmission codeword CW′ without correcting the error bit in codeword CW in response to modulo signal MS2 indicating that the result of the second modulo-2 operation is zero. In this case, flag generator 488 may output flag signal FL2 having a second logic level in response to detection signal DS and modulo signal MS2 to indicate that transmission message MSG′ includes an uncorrectable error bit.

[0137] Figure 17B It shows that according to Figure 17A A table of characteristic information, syndrome vectors, and the number of error bits determined by the selected elements in the error detection / correction circuit.

[0138] Reference Figure 17A and Figure 17B , when the characteristic information CI is zero and the syndrome vector SV is a zero vector, the code word CW does not include an error bit. When the characteristic information CI is zero and the selected element s(k-1) is a high level, the code word CW includes one error bit. When the characteristic information CI is zero, the selected element s(k-1) is a high level, and the syndrome vector SV is not a zero vector, the code word CW includes two error bits. When the characteristic information CI is a high level and the selected element s(k-1) is a high level, the code word CW includes two error bits. When the characteristic information CI is a high level, the selected element s(k-1) is a low level, and the syndrome vector SV is not a zero vector, the code word CW includes one error bit.

[0139] Figure 18 is a diagram showing a method according to an example embodiment Figure 9 Flowchart of another example operation of an ECC decoder.

[0140] Reference Figure 9 and Figures 14 to 18 In operation S210, the system ECC checker 440 generates characteristic information CI based on the message bits in the codeword read from the target page in the memory cell array. For example, the system ECC checker 440 performs a first modulo-2 operation on the sum of the message bits d0 to d7 to generate the characteristic information CI. In operation S212, the syndrome generator 450 generates a syndrome vector based on the message bits and parity bits in the codeword. For example, the syndrome generator 450 performs an operation on the codeword CW using the second type of parity check matrix PCM2 to generate a syndrome vector SV. In operation S214, the adder 480 generates a sum signal x by calculating the sum of each element of the syndrome vector SV. In operation S220, the error detector 482 determines whether the sum of the characteristic information CI and the sum signal x is zero. Based on whether the sum of the sum signal x and the characteristic information CI corresponds to zero, the error detector 482 generates a detection signal DS indicating whether the codeword CW includes an error bit. When the sum of the sum signal x and the characteristic information CI corresponds to zero ("Yes" in operation S220), the code word and the flag signal having the first logic level are output in operation S222. Since the code word CW does not include an error bit, the flag generator 488 outputs the flag signal FL2 having the first logic level, and the message extractor 489 outputs the transmission message MSG' based on the transmission code word CW'.

[0141] When the sum of the sum signal x and the characteristic information CI corresponds to non-zero ("No" in operation S220), the modulo calculator 484 performs a second modulo-2 operation on the sum of the selected element s(k-1) and the characteristic information CI to generate a modulo signal MS2. The modulo calculator 484 determines whether the modulo signal MS2 is equal to zero (operation S230). When the modulo signal MS1 is zero ("Yes" in operation S230), the codeword and a flag signal having a second logic level are output. Since the codeword CW includes an uncorrectable error bit, the flag generator 488 outputs a flag signal FL2 having a second logic level. The data corrector 486 outputs the transmission codeword CW' without correcting the error bit in the codeword CW, and the message extractor 489 outputs the transmission message MSG' based on the transmission codeword CW'.

[0142] When the modulo signal MS2 is at a high level ("No" in operation S230), indicating that the codeword CW includes a correctable error bit, the data corrector 486 selects the message bit corresponding to the non-zero element of the syndrome vector SV in operation S232, flips the selected message bit in operation S234, and outputs the corrected codeword and a flag signal having a first logic level in operation S236. The data collector 486 outputs a transmission codeword CW' by correcting the error bit in the codeword CW. The message extractor 489 outputs a transmission message MSG' based on the transmission codeword CW', and the flag generator 488 outputs a flag signal FL2 having a first logic level.

[0143] Figure 19 It shows that according to Figure 17A A table of characteristic information, syndrome vectors, and the number of error bits determined by the selected elements in the error detection / correction circuit.

[0144] like Figure 19 As shown, the number of error bits and the positions of the error bits can be detected based on the characteristic information CI, the selected element s(k-1), and the combination of the characteristic information CI and the selected element s(k-1).

[0145] Therefore, the second type of parity check matrix PCM2 can represent a t-bit correction code, and the error detection / correction circuit 460b can correct t error bits in the codeword CW and detect (t+1) error bits in the codeword CW. For example, when t is 1, the second type of parity check matrix PCM2 represents an SEC code, and the error detection / correction circuit 460b corrects one error bit in the codeword CW and detects two error bits in the codeword CW. Therefore, the error detection / correction circuit 460a can perform SEC-DED.

[0146] Figure 20 is a flowchart illustrating a method of operating a semiconductor memory device according to example embodiments.

[0147] Reference Figures 5 to 20 In the method of operating the semiconductor memory device 200, a codeword CW is read from a target page of the memory cell array 300 (operation S310). The system ECC checker 440 generates characteristic information CI based on the message bits in the codeword CW (operation S320). The syndrome generator 450 generates a syndrome vector SV based on the message bits and parity bits in the codeword CW (operation S330). The error detection / correction circuit 460 selectively corrects the error bits in the codeword CW based on the characteristic information CI and the syndrome vector SV (operation S340) to output a transmission codeword CW'. The flag generator in the error detection / correction circuit 460 generates a flag signal FL indicating whether the transmission codeword CW' includes an error bit (operation S350). The transmission message and the flag signal are output (operation S360). The message extractor in the error detection / correction circuit 460 extracts the transmission message MSG' from the transmission codeword CW' and sends the transmission message MSG' and the flag signal FL to the memory controller 100.

[0148] Figure 21 is a flowchart illustrating a method of operating a memory system according to example embodiments.

[0149] Reference Figures 1 to 21In the method of operating the memory system 10, the memory controller 100 performs a first encoding to generate a message (operation S410). For example, the memory controller 100 performs a first encoding on the data DTA to generate a message MSG. The memory controller 100 transmits the message MSG to the semiconductor memory device 200, performs a second encoding on the message MSG to generate a codeword CW, and writes the codeword CW into a target page of the memory cell array 300 (operation S420). The codeword CW is read from the target page of the memory cell array 300 (operation S430). The system ECC checker 440 generates characteristic information CI based on the message bits in the codeword CW (operation S440). The syndrome generator 450 generates a syndrome vector SV based on the message bits and parity bits in the codeword CW (operation S450). The error detection / correction circuit 460 selectively corrects the error bits in the codeword CW based on the characteristic information CI and the syndrome vector SV (operation S460) to output a transmission codeword CW′. The flag generator in the error detection / correction circuit 460 generates a flag signal FL indicating whether the transmission codeword CW' includes an error bit (operation S470). A transmission message and the flag signal are output (operation S480). A message extractor in the error detection / correction circuit 460 extracts the transmission message MSG' from the transmission codeword CW' and transmits the transmission message MSG' and the flag signal FL to the memory controller 100. The memory controller 100 receives the transmission message and the flag signal and processes the transmission (operation S490). For example, the memory controller processes the error bit in the transmission message MSG' based on the flag signal FL.

[0150] Figure 22 is a block diagram illustrating a semiconductor memory device according to example embodiments.

[0151] Reference Figure 22 , a semiconductor memory device 600 may include a first group of dies 610 and a second group of dies 620 providing soft error analysis and correction functions in a stacked chip structure.

[0152] The first group of dies 610 may include at least one buffer die. The second group of dies 620 may include a plurality of memory dies 620-1 to 620-p stacked on the first group of dies 610 and transmitting data through a plurality of through silicon via (TSV) lines.

[0153] At least one of the memory dies 620-1 to 620-p may include a first type of ECC engine 622 that generates transmission parity bits (i.e., transmission parity data) based on transmission data to be sent to the first group of dies 610. The first type of ECC engine 622 may be referred to as a "unit core ECC engine." The first type of ECC engine 622 may employ Figure 8 Therefore, the first type ECC engine 622 can correct one error bit and detect two error bits by using the SEC code in ECC decoding.

[0154] The buffer die 610 may include a second type of ECC engine 612 that, when a transmission error is detected in transmission data received through the TSV lines, uses transmission parity bits to correct the transmission error and generates error-corrected data. The second type of ECC engine 612 may be referred to as a "via ECC engine."

[0155] With the above description, the data TSV line group 632 formed at one memory die 620-p may include 128 TSV lines L1 to Lp, and the parity TSV line group 634 may include 8 TSV lines L10 to Lq. The TSV lines L1 to Lp in the data TSV line group 632 and the parity TSV lines L10 to Lq in the parity TSV line group 634 may be connected to microbumps MCB formed between the memory dies 620-1 to 620-p, respectively.

[0156] At least one of the memory dies 620 - 1 through 620 - p may include DRAM cells, each DRAM cell including at least one access transistor and one storage capacitor.

[0157] The semiconductor memory device 600 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with a host through a data bus B10. The buffer die 610 may be connected to a memory controller through the data bus B10.

[0158] When an error is detected in read data from a high bandwidth memory (HBM) or stacked memory structure, the error is an error that occurs due to noise when data is transferred through TSVs.

[0159] According to an example embodiment, Figure 22 As shown, the cell core ECC engine 622 can be included in the memory die, and the through-hole ECC engine 612 can be included in the buffer die. Therefore, soft data faults can be detected and corrected. Soft data faults can include transmission errors caused by noise when data is transmitted through TSV lines.

[0160] Figure 23 is adopted according to an example embodiment Figure 22 A cross-sectional view of a 3D chip structure of a semiconductor memory device.

[0161] Figure 23A 3D chip structure 700 is shown in which the host and the HBM are directly connected without an intermediate layer.

[0162] Reference Figure 23 , a host die 710 such as a system on chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU) can be placed on a printed circuit board (PCB) 720 using flip chip bumps FB. Memory dies D11 to D14 can be stacked on the host die 710 to implement a system such as a CPU. Figure 22 The HBM structure of the memory die 620 in FIG. Figure 23 In, omitted Figure 22 The buffer die 610 or logic die in the host die 710 can be provided between the memory die D11 and the host die 710. To implement an HBM structure such as the memory die 620, TSV lines can be formed on the memory dies D11 to D14. The TSV lines can be electrically connected to the microbumps MCB placed between the memory dies.

[0163] Figure 24 is a block diagram illustrating a memory system according to example embodiments.

[0164] Reference Figure 24 , the memory system 800 may include a memory controller 810 and a semiconductor memory device 850 .

[0165] The memory controller 810 includes a first ECC engine 820 and a second ECC engine 830. The first ECC engine 820 may use a code such as a single parity check code or a SEC-DED code, in which the sum of all bits in the encoded message corresponds to an even number. The second ECC engine 830 may use a SEC code.

[0166] The memory controller 810 performs concatenated ECC encoding on the data by using the first ECC engine 820 and the second ECC engine 830 to generate a codeword CW and transmits the codeword CW to the semiconductor memory device 850. In addition, the first ECC engine 820 and the second ECC engine 830 perform concatenated ECC decoding on the codeword CW received from the semiconductor memory device 850 and correct error bits in the codeword CW to restore the data. The second ECC engine 830 may adopt Figure 9 The ECC decoder 430 in FIG.

[0167] In addition, the memory controller 810 transmits a command CMD and an address ADDR to the semiconductor memory device 850 .

[0168] The semiconductor memory device 850 includes a memory cell array (MCA) 860, and the codeword CW may be stored in the memory cell array 860. The memory cell array 860 may include dynamic memory cells or nonvolatile memory cells.

[0169] The present disclosure can be applied to a semiconductor memory device and a memory system that employ ECC.

[0170] The foregoing is illustrative of example embodiments and should not be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made to the example embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims.

Claims

1. An error correction code decoder for a semiconductor memory device, the error correction code decoder comprising: an error correction code checker configured to generate characteristic information representing first error information associated with a message bit in an input codeword read from a target page in a memory cell array; a syndrome generator configured to output a syndrome vector representing second error information associated with the input codeword by performing an operation on the message bits and parity check bits in the input codeword based on a parity check matrix; as well as An error detection / correction circuit is configured to generate a transmission codeword by selectively correcting an erroneous bit in the input codeword based on the feature information and the syndrome vector, generate a flag signal indicating whether the transmission codeword includes the erroneous bit, and output a transmission message based on the transmission codeword.

2. The error correction code decoder according to claim 1, wherein The parity check matrix includes: a first portion corresponding to the message bits; and The second part, which corresponds to the parity bit, The first part includes a plurality of column vectors, each column vector includes an even number of high-level elements, The second part includes a plurality of parity check column vectors, each parity check column vector includes an odd number of high-level elements, The parity check matrix corresponds to a first type of parity check matrix, the first type of parity check matrix includes a plurality of different row vectors and a plurality of different column vectors, and The error correction code checker is configured to perform a first modulo-2 operation on the first sum of the message bits to output a first result of the first modulo-2 operation associated with the first error information as the characteristic information.

3. The error correction code decoder according to claim 2, wherein: The error detection / correction circuit is configured to: generating a summation signal by calculating a second sum of elements of the syndrome vector; selectively performing a second modulo-2 operation on the third sum based on whether a third sum of the sum signal and the feature information corresponds to zero; selectively correcting the input codeword based on the summation signal and a second result of the second modulo-2 operation; as well as The flag signal is generated.

4. The error correction code decoder according to claim 2, wherein: The error detection / correction circuit comprises: an adder configured to generate a summation signal by calculating a second sum of elements of the syndrome vector; an error detector configured to generate a detection signal indicating whether the input codeword includes an error bit based on whether a third sum of the sum signal and the characteristic information corresponds to zero; a modulo calculator configured to, in response to the third sum being non-zero, perform a second modulo-2 operation on the third sum to generate a modulo signal indicating whether a second result of the second modulo-2 operation is zero; a data corrector configured to selectively correct the input codeword based on the sum signal and the modulo signal to generate the transmission codeword; a message extractor configured to extract a transmission message from the transmission codeword and output the transmission message; and A flag generator is configured to generate the flag signal indicating whether the transmission codeword includes an error bit based on the detection signal and the modulo signal.

5. The error correction code decoder according to claim 4, wherein The flag generator is configured to output the flag signal having a first logic level in response to the detection signal indicating that the transmission codeword does not include an error bit.

6. The error correction code decoder according to claim 4, wherein: the modulo calculator being configured to perform the second modulo-2 operation in response to the detection signal indicating that the transmission codeword includes the erroneous bit; The data corrector is configured to correct the erroneous bit in the input codeword in response to a modulo signal indicating that the second result of the second modulo-2 operation is non-zero, so as to generate the transmission codeword; and The flag generator is configured to output the flag signal having a first logic level in response to the detection signal and the modulo signal to indicate that the transmission message does not include an error bit.

7. The error correction code decoder according to claim 4, wherein: the modulo calculator being configured to perform the second modulo-2 operation in response to the detection signal indicating that the transmission codeword includes the erroneous bit; The data corrector is configured to output the transmission codeword without correcting the erroneous bit in the transmission codeword in response to a modulo signal indicating that the second result of the second modulo-2 operation is zero; and The flag generator is configured to output the flag signal having a second logic level in response to the detection signal and the modulo signal to indicate that the transmission message includes an error bit.

8. The error correction code decoder according to claim 1, wherein The parity check matrix includes: a first portion corresponding to the message bits; and The second part, which corresponds to the parity bit, wherein a first row vector among the plurality of row vectors of the parity check matrix includes a first subpart corresponding to the first part and a second subpart corresponding to the second part, all elements in the first subpart have a low level, and all elements in the second subpart have a high level, The parity check matrix corresponds to a second type of parity check matrix, the second type of parity check matrix including a plurality of different row vectors and a plurality of different column vectors, and The error correction code checker is configured to perform a first modulo-2 operation on the first sum of the message bits to output a first result of the first modulo-2 operation associated with the first error information as the characteristic information.

9. The error correction code decoder according to claim 8, wherein The error detection / correction circuit is configured to: generating a summation signal by calculating a second sum of elements of the syndrome vector; selectively performing a second modulo-2 operation on a third sum of the feature information and a selected element of the syndrome vector based on whether a fourth sum of the sum signal and the feature information corresponds to zero, the selected element corresponding to the first row vector; selectively correcting the input codeword based on the summation signal and a second result of the second modulo-2 operation; as well as The flag signal is generated.

10. The error correction code decoder according to claim 8, wherein The error detection / correction circuit comprises: an adder configured to generate a summation signal by calculating a second sum of elements of the syndrome vector; an error detector configured to generate a detection signal indicating whether the input codeword includes an error bit based on whether a third sum of the sum signal and the characteristic information corresponds to zero; a modulo calculator configured to, in response to the third sum being non-zero, perform a second modulo-2 operation on the feature information and a fourth sum of the selected elements to generate a modulo signal indicating that a second result of the second modulo-2 operation is zero; a data corrector configured to selectively correct the input codeword based on the detection signal and the modulo signal to generate the transmission codeword; a message extractor configured to extract a transmission message from the transmission codeword and output the transmission message; and A flag generator is configured to generate the flag signal indicating whether the transmission codeword includes an error bit based on the detection signal and the modulo signal.

11. The error correction code decoder according to claim 10, wherein: The flag generator is configured to output the flag signal having a first logic level in response to the detection signal indicating that the transmission codeword does not include an error bit.

12. The error correction code decoder of claim 10, wherein: the modulo calculator being configured to perform the second modulo-2 operation in response to the detection signal indicating that the transmission codeword includes the erroneous bit; The data corrector is configured to correct the erroneous bit in the input codeword in response to the modulo signal indicating that the second result of the second modulo-2 operation is non-zero, so as to generate the transmission codeword; and The flag generator is configured to output the flag signal having a first logic level in response to the detection signal and the modulo signal to indicate that the transmission message does not include an error bit.

13. The error correction code decoder of claim 10, wherein: the modulo calculator being configured to perform the second modulo-2 operation in response to the detection signal indicating that the transmission codeword includes the erroneous bit; The data corrector is configured to output the transmission codeword without correcting the erroneous bit in the transmission codeword in response to the modulo signal indicating that the second result of the second modulo-2 operation is zero; and The flag generator is configured to output the flag signal having a second logic level in response to the detection signal and the modulo signal to indicate that the transmission message includes an error bit.

14. The error correction code decoder of claim 1, wherein: The parity check matrix represents a t-bit correction code, where t is a natural number greater than zero; and The error detection / correction circuit is configured to correct t-bit errors in the input codeword and detect (t+1)-bit errors in the input codeword.

15. A semiconductor memory device comprising: a memory cell array comprising a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines; an error correction code engine configured to perform error correction code encoding on a message received from outside the semiconductor memory device to generate an initial codeword, store the initial codeword in a target page in the memory cell array, generate characteristic information and a syndrome vector based on the initial codeword read from the target page, generate a transmission codeword by selectively correcting an error bit in the initial codeword based on the characteristic information and the syndrome vector, and generate a flag signal indicating whether the transmission codeword includes an error bit; as well as A control logic circuit is configured to control the error correction code engine based on a command and an address received from outside the semiconductor memory device.

16. The semiconductor memory device according to claim 15, wherein The error correction code engine includes: an error correction code encoder configured to perform the error correction code encoding on the message; and An error correction code decoder comprising: an error correction code checker configured to generate the characteristic information based on the message bits in the read initial codeword, the characteristic information representing first error information associated with the message bits; a syndrome generator configured to output the syndrome vector by performing an operation on the message bits and parity bits in the initial codeword based on a parity check matrix, the syndrome vector representing second error information associated with the read initial codeword; and An error detection / correction circuit is configured to generate the transmission codeword by selectively correcting the erroneous bit in the read initial codeword based on the feature information and the syndrome vector, and is configured to generate the flag signal.

17. The semiconductor memory device according to claim 16, wherein Each of the plurality of memory cells comprises a dynamic memory cell; The parity check matrix represents a t-bit correction code, where t is a natural number greater than zero; and The error detection / correction circuit is configured to correct t-bit errors in the initial codeword and is configured to detect (t+1)-bit errors in the initial codeword.

18. The semiconductor memory device according to claim 15, further comprising: at least one buffer die; as well as a plurality of memory dies stacked on the at least one buffer die and transmitting data through a plurality of through silicon vias, wherein at least one of the plurality of memory dies includes the memory cell array and the error correction code engine, and the error correction code engine generates transmission parity bits using transmission data to be sent to the at least one buffer die, and The at least one buffer die includes a through-silicon via error correction code engine configured to correct a transmission error using the transmission parity bits in response to detecting a transmission error from the transmission data received through the plurality of through-silicon via lines.

19. An error correction code decoder comprising at least one microprocessor, wherein the at least one microprocessor is configured to: generating characteristic information based on message bits in an input codeword read from a target page in a memory cell array; generating a syndrome vector from the input codeword by performing an operation on the message bits and parity check bits in the input codeword based on a parity check matrix; as well as generating a transmission codeword by selectively correcting a first erroneous bit in the input codeword based on the characteristic information and the syndrome vector, The error correction code decoder detects whether the first error bit occurs in the input codeword and whether the second error bit occurs in the input codeword based on the feature information and the syndrome vector, and generates a flag signal indicating whether the second error bit occurs.

20. The error correction code decoder according to claim 19, wherein The parity check matrix includes: a plurality of message vectors, each message vector corresponding to one of the message bits; and a plurality of parity check vectors, each parity check vector corresponding to one of the parity check bits, and Each message vector includes high-level elements corresponding to even numbers, and each parity vector includes high-level elements corresponding to odd numbers.

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