Non-volatile memory devices and methods of programming therein

Abstract

In a method of programming in a nonvolatile memory device, a memory block including a plurality of stacks arranged in a vertical direction is provided, wherein the memory block includes cell strings, each of the cell strings including memory cells connected in series in the vertical direction between each of a source line and a bit line. A plurality of intermediate switching transistors arranged in a boundary portion between two adjacent stacks in the vertical direction is provided, wherein the intermediate switching transistors perform switching operations to control electrical connections of the cell strings, respectively. A boosting operation is performed to boost a voltage of a channel of the plurality of stacks while controlling the switching operations of the intermediate switching transistors during a programming operation with respect to the memory block. By controlling the switching operations of the intermediate switching transistors, programming voltage disturbance and pass voltage disturbance are reduced.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0135905 filed on November 7, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Apparatuses and methods according to example embodiments relate to semiconductor integrated circuits, and more particularly, to nonvolatile memory devices and methods of programming in nonvolatile memory devices. Background Art

[0004] Nonvolatile memory devices can retain stored data even when the power is turned off. While volatile memory devices are used as main memory for various devices, nonvolatile memory devices are used to store program codes and / or data in various electronic devices such as computers, mobile devices, etc.

[0005] Recently, three-dimensional nonvolatile memory devices such as vertical NAND memory devices have been developed to increase the integration and storage capacity of nonvolatile memory devices. As the integration and storage capacity increase, the disturbance to the memory cells increases while programming the memory cells. Summary of the Invention

[0006] Various example embodiments provide a method of programming in a nonvolatile memory device capable of reducing disturbance to memory cells during a programming operation.

[0007] Embodiments also provide a nonvolatile memory device capable of reducing disturbance to memory cells during a program operation.

[0008] According to one aspect of an example embodiment, a method for programming a nonvolatile memory device is provided. The method may include: providing a memory block including a plurality of stacks arranged in a vertical direction, each memory block including a plurality of cell strings, and each cell string including a plurality of memory cells connected in series in the vertical direction between a source line and each of a plurality of bit lines; providing a plurality of intermediate switching transistors arranged in a boundary portion between two adjacent stacks in the vertical direction, the intermediate switching transistors performing switching operations to respectively control electrical connections of the cell strings; and during a programming operation with respect to the memory block, performing a boosting operation to boost the voltage of a channel of the stack while controlling the switching operations of the intermediate switching transistors.

[0009] According to one aspect of example embodiments, a method for programming a memory block is provided, the memory block including a plurality of stacks connected in series in a vertical direction by forming a cell string between a bit line and a source line. The method may include: selecting a stack including memory cells to be programmed according to a program command from the stacks, the selected stack being separated from an erase stack including unprogrammed memory cells by a boundary portion including at least one intermediate switch; determining whether the number of word lines connected to previously programmed memory cells of the selected stack in the cell string is less than a predetermined number; and, in response to the determination, performing a dual boosting operation on the memory block. The dual boosting operation may include: a first boosting operation, which includes turning on the intermediate switch and applying a first pass voltage to word lines connected to memory cells of the erase stack in the cell string; and a second boosting operation, which includes turning off the intermediate switch and applying a second pass voltage to word lines connected to memory cells of the selected stack in the cell string, the word lines connected to memory cells of the selected stack in the cell string including word lines connected to memory cells to be programmed.

[0010] According to one aspect of an example embodiment, a nonvolatile memory device is provided, which may include: a memory block including a plurality of stacks arranged in a vertical direction, each memory block including a plurality of cell strings, each cell string including a plurality of memory cells connected in series in the vertical direction between a source line and each of a plurality of bit lines; a plurality of intermediate switching transistors arranged in a boundary portion between two adjacent stacks in the vertical direction, the intermediate switching transistors performing switching operations to respectively control electrical connections of the cell strings; and a control circuit configured to, during a programming operation with respect to the memory block, perform a boosting operation to boost the voltage of a channel of the stack while controlling the switching operations of the intermediate switching transistors.

[0011] The nonvolatile memory device and the method of programming in the nonvolatile memory device according to example embodiments can reduce program voltage disturbance and pass voltage disturbance, and thus can achieve double boosting of the channel voltage by controlling the switching operation of the intermediate switching transistor, thereby improving the performance and life of the nonvolatile memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Example embodiments of the present disclosure will be more clearly understood from the following detailed description with reference to the accompanying drawings.

[0013] Figure 1 is a flowchart illustrating a method of programming in a nonvolatile memory device according to example embodiments.

[0014] Figure 2is a block diagram illustrating a memory system according to example embodiments.

[0015] Figure 3 It shows Figure 2 A block diagram of an example embodiment of a nonvolatile memory device included in a memory system of FIG.

[0016] Figure 4 It shows Figure 3 A block diagram of a memory cell array included in a nonvolatile memory device.

[0017] Figure 5 It shows Figure 4 A perspective view of one of the storage blocks.

[0018] Figure 6 Reference Figure 5 A circuit diagram depicting the equivalent circuit of a memory block.

[0019] Figure 7A is a circuit diagram illustrating a structure of a memory cell array according to example embodiments.

[0020] Figure 7B and Figure 7C is shown with Figure 7A A three-dimensional diagram of a storage block corresponding to the structure.

[0021] Figure 8 is a cross-sectional view for describing example embodiments of a boundary portion included in a memory block according to example embodiments.

[0022] Figure 9 is a circuit diagram illustrating programming bias conditions for a three-dimensional flash memory device.

[0023] Figure 10 is a diagram illustrating a first programming scheme according to example embodiments.

[0024] Figure 11 is a diagram showing a method according to an example embodiment Figure 10 FIG. 5 is a timing diagram of a programming operation of a second stack of a first programming scheme.

[0025] Figure 12A is a diagram for describing pass voltage disturbance reduction in a nonvolatile memory device according to example embodiments.

[0026] Figure 12B is a diagram for describing program voltage disturbance reduction of a nonvolatile memory device according to example embodiments.

[0027] Figure 13A and Figure 13Bis a diagram for describing pass voltage disturb and program voltage disturb reduction in incremental step pulse programming (ISPP) of a nonvolatile memory device according to example embodiments.

[0028] Figure 14 is a diagram illustrating hot carrier injection that may be caused by a programming method in a nonvolatile memory device.

[0029] Figure 15 and Figure 16 is a flowchart illustrating a method of programming in a nonvolatile memory device according to example embodiments.

[0030] Figure 17 is a diagram showing a method according to an example embodiment Figure 10 FIG. 5 is a timing diagram of a programming operation of a second stack of a first programming scheme.

[0031] Figure 18 is a cross-sectional view illustrating a memory block divided into three stacks according to example embodiments.

[0032] Figure 19A and Figure 19B is a diagram showing a method according to an example embodiment Figure 10 The first programming scheme about Figure 18 FIG. 1 is a diagram of a programming operation of a stack of memory cell arrays.

[0033] Figure 20 is a diagram illustrating a second programming scheme according to example embodiments.

[0034] Figure 21 is a diagram showing a method according to an example embodiment Figure 20 FIG. 5 is a timing diagram of a programming operation of a first stack of a second programming scheme.

[0035] Figure 22A and Figure 22B is a diagram illustrating an example embodiment of a memory cell array included in a nonvolatile memory device.

[0036] Figure 23 is a block diagram illustrating a solid state disk or solid state drive (SSD) according to example embodiments. DETAILED DESCRIPTION

[0037] The embodiments described below are exemplary. Therefore, the present invention is not limited to the embodiments disclosed below and can be implemented in various other forms. Various embodiments will be described more fully below with reference to the accompanying drawings. In the drawings, like reference numerals represent like elements throughout. Repetitive descriptions may be omitted.

[0038] It should be understood that when an element or layer is referred to as being “above,” “on,” “on,” “connected to,” or “coupled to” another element or layer, it can be directly above, on, on, connected to, or coupled to another element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being “directly above,” “directly on,” “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0039] Spatially relative terms such as "below," "beneath," "lower," "above," "above," "upper," etc., may be used herein for purposes of simplicity of description to describe the relationship of one element or feature shown in the figures to another (or other) elements or features. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation beyond the orientation shown in the figures. For example, if the device in the figures is turned upside down, elements described as being "below" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the term "below" can encompass both the above and below directions. The device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0040] Figure 1 is a flowchart illustrating a method of programming in a nonvolatile memory device according to an embodiment.

[0041] refer to Figure 1 , providing a memory block including a plurality of stacks arranged in a vertical direction, wherein the memory block includes a plurality of cell strings, and each cell string includes a plurality of memory cells connected in series and arranged in a vertical direction between a source line and a plurality of bit lines (S100). The memory block or memory cell array can be divided into Figure 7A 、 Figure 7B and Figure 7C The two stacks described below will be referred to Figure 18 Three stacks are described, and four or more stacks may be arranged in the same manner.

[0042] A plurality of intermediate switching transistors are provided, which are arranged in a boundary portion between two adjacent stacks in a vertical direction, wherein the plurality of intermediate switching transistors perform switching operations to control electrical connections of the plurality of cell strings, respectively (S200). In some embodiments, as will be described below with reference to Figure 7A and Figure 7B As described above, the boundary portion may correspond to a gate layer. In other embodiments, as will be described below with reference to Figure 7C As described above, the boundary portion may correspond to two or more gate layers adjacent in the vertical direction. Figure 18 As described above, the boundary portion may correspond to two or more gate layers spaced apart in a vertical direction. Here, the gate layer may be formed thereon. Figure 5 The layers of conductive material 213 to 293, that is, the layers formed therein Figure 6 The gate layer of the gate lines GTL1 to GTL8.

[0043] While controlling the switching operations of the plurality of middle switching transistors during the programming operation, a boosting operation is performed to boost the voltages of the channels of the plurality of stacks (S300). Figure 11 etc., describe a boosting operation according to control of switching operations of a plurality of intermediate switching transistors.

[0044] As the number of word lines formed in vertically stacked gate layers increases to increase the density of each memory block, the pass voltage disturbance of memory cells connected to unselected word lines during programming operations increases. In addition, as the number of cell strings in each memory block increases, the program voltage disturbance of memory cells connected to a selected word line but included in unselected cell strings increases.

[0045] The nonvolatile memory device and the method for programming the nonvolatile memory device according to the embodiment can reduce program voltage disturbance and pass voltage disturbance. Therefore, the performance and life of the nonvolatile memory device can be improved by controlling the switching operation of the nonvolatile memory device to achieve double boosting of the channel voltage. Here, double boosting means boosting the channel voltage of the selected stack to be programmed twice by controlling the switching operation of the intermediate switching transistor and the timing of applying the pass voltage to each stack.

[0046] Figure 2 is a block diagram illustrating a memory system according to an embodiment.

[0047] refer to Figure 2 , the memory system 10 may include a memory controller 20 and at least one memory device 30 .

[0048] The memory device 30 may be a non-volatile memory device as described herein.The memory system 10 may include flash-based data storage media such as memory cards, universal serial bus (USB) memories, and solid-state drives (SSDs).

[0049] The nonvolatile memory device 30 can perform read operations, erase operations, and program operations or write operations under the control of the memory controller 20. The nonvolatile memory device 30 receives commands CMD, addresses ADDR, and data DATA from the memory controller 20 via input / output lines to perform such operations. In addition, the nonvolatile memory device 30 receives control signals CTRL from the memory controller 20 via control lines. In addition, the nonvolatile memory device 30 receives power PWR from the memory controller 20 via power lines.

[0050] Figure 3 It shows Figure 2 A block diagram of an embodiment of a non-volatile memory device included in a memory system.

[0051] refer to Figure 3 , the nonvolatile memory device 30 includes a memory cell array 100 , a page buffer circuit 410 , a data input / output circuit 420 , an address decoder 430 , a control circuit 450 , and a voltage generator 460 .

[0052] The memory cell array 100 may be coupled to the address decoder 430 through a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. In addition, the memory cell array 100 may be coupled to the page buffer circuit 410 through a plurality of bit lines BL.

[0053] The memory cell array 100 may include a plurality of memory cells coupled to a plurality of word lines WL and a plurality of bit lines BL. In some embodiments, the memory cell array 100 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or a vertical structure). In this case, the memory cell array 100 may include a plurality of vertically oriented NAND strings such that at least one memory cell is located above another memory cell.

[0054] The control circuit 450 may receive a command (signal) CMD and an address (signal) ADDR from the memory controller 20. The control circuit 450 may control an erase operation, a program operation, and a read operation of the nonvolatile memory device 30 based on the command signal CMD and the address signal ADDR. The erase operation may include performing a series of erase cycles, and the program operation may include performing a series of program cycles. Each program cycle may include a program operation and a program verification operation. Each erase cycle may include an erase operation and an erase verification operation. The read operation may include a normal read operation and a data recovery read operation.

[0055] For example, the control circuit 450 may generate a control signal CTL for controlling the voltage generator 460 based on the command signal CMD, generate a page buffer control signal PBC for controlling the page buffer circuit 410, and generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 450 may provide the row address R_ADDR to the address decoder 430 and provide the column address C_ADDR to the data input / output circuit 420.

[0056] The address decoder 430 may be coupled to the memory cell array 100 through a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. During a program operation or a read operation, the address decoder 430 may determine one of the plurality of word lines WL as a selected word line based on a row address R_ADDR, and determine the remaining word lines of the plurality of word lines WL except the selected word line as unselected word lines.

[0057] In addition, during a program operation or a read operation, the address decoder 430 may determine one of the plurality of string selection lines SSL as a selected string selection line based on the row address R_ADDR, and determine the remaining string selection lines of the plurality of string selection lines SSL except the selected string selection line as unselected string selection lines.

[0058] The voltage generator 460 may generate a word line voltage VWL based on the control signal CTL, which may be required to operate the memory cell array 100 of the nonvolatile memory device 30. The voltage generator 460 may receive power PWR from the memory controller 20. The word line voltage VWL may be applied to a plurality of word lines WL through the address decoder 430.

[0059] For example, during a program operation, the voltage generator 460 may apply a program voltage to a selected word line and a program pass voltage to unselected word lines. Additionally, during a program verify operation, the voltage generator 460 may apply a program verify voltage to a selected word line and a verify pass voltage to unselected word lines. Additionally, during a normal read operation, the voltage generator 460 may apply a read voltage to a selected word line and a read pass voltage to unselected word lines.

[0060] The page buffer circuit 410 can be coupled to the memory cell array 100 through a plurality of bit lines BL. The page buffer circuit 410 may include a plurality of buffers. In some embodiments, each buffer may be connected to one bit line. In other embodiments, each buffer may be connected to two or more bit lines.

[0061] The page buffer circuit 410 may temporarily store data to be programmed in a selected page of the memory cell array 100 or data read out from a selected page of the memory cell array 100 .

[0062] The data input / output circuit 420 may be coupled to the page buffer circuit 410 via a data line DL. During a program operation, the data input / output circuit 420 may receive program data DATA from the memory controller 20 and provide the program data DATA to the page buffer circuit 410 based on a column address C_ADDR received from the control circuit 450. During a read operation, the data input / output circuit 420 may provide read data DATA that has been read from the memory cell array 100 and stored in the page buffer circuit 410 to the memory controller 20 based on the column address C_ADDR received from the control circuit 450.

[0063] The address decoder 430 may include a channel initializer (CHI) 432. Typically, channel initialization is performed by connecting the string select line SSL and the bit line BL of the cell string. However, when the memory cell adjacent to the string select transistor is first programmed, channel initialization or channel precharge may not be performed by the string select transistor and the bit line SSL. The channel initializer 432 may determine the appropriate programming sequence and perform channel initialization based on the programming sequence. For example, the channel initializer 432 may determine the time point at which voltage is applied to the string select line SSL, the ground select line GSL, and the common source line.

[0064] The control circuit 450 may include an address scramble selector (ASS) 452. The address scramble selector 452 may store channel hole profile information about the cell strings included in the memory cell array 100. The channel hole profile may be defined during the manufacturing stage of the nonvolatile memory device 30. The address scramble selector 452 may select a word line WL corresponding to the received address ADDR from among a plurality of word lines WL based on the channel hole profile information. Address scrambling refers to a method of mapping memory cells included in a cell string to a word line WL.

[0065] Hereinafter, the first direction D1 refers to a direction perpendicular to the upper surface of the semiconductor substrate, and the second direction D2 and the third direction D3 refer to two directions parallel to the upper surface of the semiconductor substrate. For example, the second direction D2 and the third direction D3 may be perpendicular to each other. The first direction D1 may be referred to as the vertical direction, the second direction D2 may be referred to as the row direction, and the third direction D3 may be referred to as the column direction. The direction indicated by the arrow in the figure and the opposite direction may be considered to be the same direction.

[0066] Figure 4 It shows Figure 3A block diagram of a memory cell array included in a nonvolatile memory device, Figure 5 It shows Figure 4 A perspective view of one of the storage blocks.

[0067] refer to Figure 4 , the memory cell array 100 may include a plurality of memory blocks BLK1 to BLKz. In an embodiment, the memory blocks BLK1 to BLKz are composed of Figure 3 For example, the address decoder 430 may select a specific memory block BLK corresponding to a block address among the memory blocks BLK1 to BLKz.

[0068] refer to Figure 5 The memory block BLKi includes NAND strings or cell strings formed on a substrate in a three-dimensional structure (or vertical structure). The memory block BLKi includes a structure extending along a first direction D1, a second direction D2, and a third direction D3.

[0069] A substrate 111 is provided. For example, the substrate 111 may have a well of a first type (e.g., a first conductivity type). For example, the substrate 111 may have a p-well formed by implanting a Group 13 element such as boron (B). For example, the substrate 111 may have a pocket p-well disposed in an n-well. In an embodiment, the substrate 111 has a p-type well (or a p-type pocket well). However, the conductivity type of the substrate 111 is not limited to p-type.

[0070] A plurality of doping regions 311 to 314 extending along the second direction D2 are provided in / on the substrate 111. For example, the plurality of doping regions 311 to 314 may have a substrate 111 of a second type (e.g., a second conductivity type) different from the first type. In an embodiment, the first to fourth doping regions 311 to 314 have an n-type conductivity. However, the conductivity type of the first to fourth doping regions 311 to 314 is not limited to the n-type.

[0071] A plurality of insulating materials 112 extending along a second direction D2 are sequentially disposed along a first direction D1 in a region between the first doping region 311 and the second doping region 312 of the substrate 111. For example, the plurality of insulating materials 112 are disposed at specific intervals along the first direction D1. For example, the insulating materials 112 may include an insulating material such as an oxide layer.

[0072] A plurality of pillars 113 penetrating the insulating material in the first direction D1 are sequentially arranged in the third direction D3 on a region of the substrate 111. For example, the plurality of pillars 113 penetrate the insulating material 112 to contact the substrate 111.

[0073] For example, each pillar 113 may include a variety of materials. For example, the channel layer 114 of each pillar 113 may include a first type of silicon material. For example, the channel layer 114 of each pillar 113 may include the same type of silicon material as the substrate 111. In an embodiment, the channel layer 114 of each pillar 113 includes p-type silicon. However, the channel layer 114 of each pillar 113 is not limited to p-type silicon.

[0074] The inner material 115 of each pillar 113 may include an insulating material. For example, the inner material 115 of each pillar 113 may include an insulating material such as silicon oxide. In some examples, the inner material 115 of each pillar 113 may include an air gap.

[0075] An insulating layer 116 is disposed on a region between the first doping region 311 and the second doping region 312 along exposed surfaces of the insulating material 112 , the pillars 113 , and the substrate 111 .

[0076] A plurality of first conductive materials 211 to 291 are disposed on the surface of the insulating layer 116 in the region between the first doping region 311 and the second doping region 312. For example, the first conductive material 211 extending along the second direction D2 is disposed between the insulating material 112 adjacent to the substrate 111 and the substrate 111. More specifically, the first conductive material 211 extending along the second direction D2 is disposed between the insulating layer 116 and the substrate 111 at the bottom of the insulating material 112 adjacent to the substrate 111.

[0077] The first conductive material extending along the second direction D2 is disposed between the insulating layer 116 at the top of a specific insulating material in the insulating material 112 and the insulating layer 116 at the bottom of the specific insulating material in the insulating material 112. For example, a plurality of first conductive materials 221 to 281 extending along the second direction D2 are disposed between the insulating materials 112, and it can be understood that the insulating layer 116 is disposed between the plurality of insulating materials 112 and the first conductive materials 221 to 281. The first conductive materials 211 to 291 can be formed of a conductive metal. In some examples, the first conductive materials 211 to 291 can include a conductive material such as polysilicon.

[0078] The same structure as that on the first doping region 311 and the second doping region 312 may be provided in the region between the second doping region 312 and the third doping region 313. In the region between the second doping region 312 and the third doping region 313, a plurality of insulating materials 112 extending along the second direction D2, pillars 113 penetrating the plurality of insulating materials 112 along the first direction D1, an insulating layer 116 provided on exposed surfaces of the plurality of insulating materials 112 and the pillars 113, and a plurality of conductive materials 213 to 293 extending along the second direction D2 are provided.

[0079] Drains 320 are disposed on the plurality of pillars 113. Second conductive materials 331 to 333 extending along the third direction D3 are disposed on the drains 320. The second conductive materials 331 to 333 are spaced apart along the second direction D2. The second conductive materials 331 to 333 are connected to the drains 320 in corresponding regions. The drains 320 and the second conductive materials 331 to 333 extending along the third direction D3 can be connected via contact plugs. The second conductive materials 331 to 333 may include a metal material. The second conductive materials 331 to 333 may include a conductive material such as polysilicon.

[0080] The layer in which the first conductive material is formed corresponds to a gate layer and may form gate lines such as string selection lines SSL, word lines WL, middle switching lines MSL, USL and LSL, ground selection lines GSL, etc. The second conductive material may form bit lines BL.

[0081] Figure 6 Reference Figure 5 Circuit diagram of the equivalent circuit of the described memory block.

[0082] Figure 6 The memory block BLKi may be formed on a substrate in a three-dimensional structure (or vertical structure). For example, a plurality of NAND strings or cell strings included in the memory block BLKi may be formed in a first direction D1 perpendicular to the upper surface of the substrate.

[0083] refer to Figure 6 , the memory block BLKi may include NAND strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. Figure 6 , each of the NAND strings NS11 to NS33 is shown as including eight memory cells MC1 to MC8. However, embodiments are not limited thereto. In some embodiments, each of the NAND strings NS11 to NS33 may include any number of memory cells.

[0084] Each string selection transistor SST can be connected to a corresponding string selection line (one of SSL1 to SSL3). A plurality of memory cells MC1 to MC8 can be connected to corresponding gate lines GTL1 to GTL8, respectively. The gate lines GTL1 to GTL8 can be word lines, and some of the gate lines GTL1 to GTL8 can be pseudo word lines. In addition, some of the gate lines GTL1 to GTL8 can be intermediate switch lines, and the memory cells connected to the intermediate switch lines can be referred to as intermediate switch transistors or intermediate switches. Each ground selection transistor GST can be connected to a corresponding ground selection line (one of GSL1 to GSL3). Each string selection transistor SST can be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3), and each ground selection transistor GST can be connected to a common source line CSL.

[0085] Word lines (eg, WL1) of the same height may be generally connected together, and the ground selection lines GSL1 to GSL3 and the string selection lines SSL1 to SSL3 may be separated. Although not shown, the gate lines corresponding to the middle switch lines may be separated as described below. Figure 6 , the memory block BLKi is shown as being coupled to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, the embodiment is not limited thereto. Each memory block in the memory cell array 100 may be coupled to any number of word lines and any number of bit lines.

[0086] In the following, for ease of explanation, memory cells may be omitted, and only gate lines stacked in the vertical direction may be shown in the diagram of the memory block. The gate lines may include a string selection line SSL, a word line WL, a pseudo word line DWL, an intermediate switch line MSL, USL, and LSL, and a ground selection line GSL. The transistor driven by the intermediate switch line MSL, USL, and LSL may be referred to as an intermediate switch transistor or an intermediate switch. At least one of the intermediate switch lines MSL, USL, and LSL may also be a pseudo word line DWL, and at least one of the respectively connected intermediate switch transistors may be a pseudo transistor that is not connected to the bit line BL. For ease of illustration and description, in the following figures, only two, three, or four cell strings are connected to the same bit line BL. However, the embodiment is not limited thereto, and the number of cell strings may be determined differently.

[0087] Figure 7A is a circuit diagram showing the structure of a memory cell array according to an embodiment.

[0088] Figure 7B and Figure 7C It shows the corresponding Figure 7A A perspective view of the structure of a storage block.

[0089] For ease of explanation, Figure 7A A two-dimensional version of a memory block including cell strings connected to one bit line BL and one source line CSL is shown, but it should be understood that the memory block may have a plurality of cell strings as shown in FIG. Figure 5 and Figure 6 A three-dimensional structure of multiple bit lines is described.

[0090] refer to Figure 7A and Figure 7B , the memory block may include a plurality of cell strings STR1 to STRm connected between a bit line BL and a source line CSL. The cell strings STR1 to STRm may include two stacks ST1 and ST2, and a boundary portion BND therebetween. The cell strings STR1 to STRm may include string selection transistors SST1 to SSTm controlled by string selection lines SSL1 to SSLm, respectively, memory cells controlled by word lines WL, intermediate switching transistors MST1 to MSTm controlled by intermediate switching lines MSL, and ground selection transistors GST1 to GSTm controlled by ground selection lines GSL. Here, m is a natural number greater than 1. The intermediate switching line MSL may be a dummy word line DWL, and the intermediate switching transistors MST1 to MSTm may be dummy transistors not connected to the bit line BL. The memory cells connected to the word lines in the ends of the stacks ST1 and ST2 arranged in the first direction D1 may be dummy cells.

[0091] Figure 7A An embodiment in which the ground selection transistors GST1 to GSTm are connected to the same ground selection line GSL is shown. In other embodiments, the ground selection transistors may be connected to respective ground selection lines.

[0092] In some embodiments, as Figure 7A and Figure 7B As shown, the boundary portion BND may include a gate line MSL that simultaneously switches or activates the intermediate switching transistors MST1 to MSTm connected thereto. Figure 7C As shown, the boundary portion BND may include two gate lines MSL1 and MSL2, which simultaneously switch the intermediate switching transistors connected thereto. Even though not shown in the figure, the boundary portion BND may include three or more gate lines.

[0093] Figure 8 is a cross-sectional view for describing an embodiment of a boundary portion included in a memory block according to an embodiment.

[0094] refer to Figure 8 , the channel hole of each cell string STR may include a first sub-channel hole 610 and a second sub-channel hole 510. The channel hole may be referred to as Figure 5. The first sub-channel hole 610 may include a channel layer 611, an inner material 612, and an insulating layer 613. The second sub-channel hole 510 may include a channel layer 511, an inner material 512, and an insulating layer 513. The channel layer 611 of the first channel hole 610 may be connected to the channel layer 511 of the second sub-channel hole 510 via a P-type silicon pad SIP. The sub-channel holes 610 and 510 may be formed using a blocking line GTL5 having an appropriate etching rate. For example, the blocking line GTL5 may be formed of polysilicon, while the other gate lines GTL1 to GTL4 and GTL6 to GTL8 may be formed of a metal such as tungsten to achieve an appropriate etching rate.

[0095] The boundary portion BND may correspond to the barrier layer GTL5 used to form the plurality of sub-channel holes. Cells in the barrier layer GTL5 may not be suitable for storing data, and the barrier layer may serve as the boundary portion BND for forming an intermediate switching transistor. Embodiments are not limited to a single barrier layer boundary portion, and the boundary portion may include two or more gate layers.

[0096] Figure 9 is a circuit diagram illustrating programming bias conditions for a three-dimensional flash memory device.

[0097] For ease of description, Figure 9 Schematic diagram showing NAND strings NS11 and NS21 connected to a first bit line BL1 and NAND strings NS12 and NS22 connected to a second bit line BL2 among a plurality of NAND strings of a memory block BLK.

[0098] The first bit line BL1 may be a program bit line to which a program permission voltage (e.g., 0V) is applied, and the second bit line BL2 may be a program inhibition bit line to which a program inhibition voltage (such as a power supply voltage VCC) is applied. If NAND string NS21 is selected among NAND strings NS11 and NS21, during a program operation, a voltage of 0V may be applied to the first string selection line SSL1 (unselected string line), and the power supply voltage VCC may be applied to the second string selection line SSL2 (selected string line).

[0099] A voltage of 0 V may be applied to the ground selection lines GSL1 and GSL2. In addition, a voltage higher than 0 V (e.g., VCC) may be applied to the common source line CSL. A program voltage VPGM (e.g., 18 V) may be applied to a selected word line (e.g., WL5), and a pass voltage VPASS (e.g., 8 V) may be applied to unselected word lines (e.g., WL4 and WL6).

[0100] Under programming bias conditions, a voltage of 18 V can be applied to the gate of memory cell A, which has a channel voltage of 0 V. Since a strong electric field is formed between the gate and the channel of memory cell A, memory cell A can be programmed. However, since the channel voltage of memory cell B is VCC and a low electric field is formed between the gate and the channel, memory cell B may not be programmed. In addition, since the respective channels of memory cells C and D are in a floating state, their channel voltages may be increased to, for example, approximately 8 V, and therefore, memory cells C and D may not be programmed.

[0101] When the program voltage VPGM increases, the memory cell C of the unselected NAND string NS11 connected to the program permission bit line BL1 may be over-stressed and unintentionally programmed, which may be referred to as program voltage disturbance. In addition, when the pass voltage VPASS increases, the memory cells other than the memory cell A of the selected NAND string NS21 connected to the program permission bit line BL1 may be over-stressed and unintentionally programmed, which may be referred to as pass voltage disturbance.

[0102] Figure 10 is a diagram illustrating a first programming scheme according to an embodiment.

[0103] Figure 10 The diagram shows a cell string including a string selection transistor SST connected to a string selection line SSL, a ground selection transistor GST connected to a ground selection line GSL, and memory cells MC1 to MC12 connected to word lines WL1 to WL12, as well as the states of the memory cells. The cell string is connected between a bit line BL and a source line CSL. Figure 10 A non-limiting example of an MLC with 12 memory cells and storing two bits is shown.

[0104] refer to Figure 10 According to the first programming scheme, a programming operation can be performed in a downward direction from the top word line. In other words, as the data stored in the memory block increases, the data can be filled in the erased cells in a downward direction from the top to the bottom (T2B programming sequence). Unprogrammed memory cells MC1 to MC7 are in the erased state E0, and each of the programmed memory cells MC8 to MC12 can be in the erased state E0 and one of the programmed states P1, P2, and P3. For example, at least one of the memory cells MC2 to MC11 can be an intermediate switching transistor.

[0105] Figure 11 Is to show that according to Figure 10 FIG. 4 is a timing diagram of a programming operation performed on a second stack of cell strings of a first programming scheme.

[0106] Figure 111 shows the boosting operation of the middle switching transistor when the selected word line WLs corresponding to the programming address is included in the second stack ST2. In other words, the first stack ST1 corresponds to the erase stack, which indicates a stack in which all memory cells are in an erased state, and the second stack ST2 corresponds to the selected stack, which indicates a stack in which memory cells to be programmed are included.

[0107] Time interval T1-T2 is a precharge period PPC, time interval T2-T3 is a first boosting period PBST1, time interval T3-T4 is a second boosting period PBST2, and time interval T4-T5 is a program execution period PEXE, while a program voltage VPGM is applied to the selected word line WLs. Hereinafter, the on-voltage and off-voltage refer to voltage levels that turn on and off corresponding transistors.

[0108] When the bit line BL is a program inhibition bit line, a program inhibition voltage VINH may be applied to the bit line BL, and when the bit line BL is a program enablement bit line, a program enablement voltage VPER may be applied to the bit line BL.

[0109] During the precharge period PPC, a cutoff voltage VSOFF is applied to the selected string select line SSLs and the unselected string select line SSLu, a turn-on voltage VMON is applied to the middle switch line MSL, and a turn-on voltage VGON is applied to the ground select line GSL. The ground select transistor and the middle switch transistor are turned on, so the precharge voltage VPC of the source line CSL is applied to the channel CH of the first and second stacks ST1 and ST2. Thus, the precharge voltage VPC can be applied to the channels of the first and second stacks ST1 and ST2 before the boost operations of the first and second boost periods PBST1 and PBST2 are performed. During the precharge period PPC, an initial voltage Vo can be applied to the selected word line WLs and the unselected word lines WLu. The initial voltage Vo can have a voltage level capable of turning on erased memory cells. The programmed memory cells in the second stack ST2 are turned off, and the channel portion between the bit line BL and the programmed memory cells can be floated.

[0110] During the first boost period PBST1, the middle switch line MSL maintains the on-voltage VMON, the off-voltage VGOFF is applied to the ground select line GSL, and the channels of the first and second stacks ST1 and ST2 are floated. While the middle switch transistor is turned on, a first pass voltage VPASS1 is applied to the word line WLu(ST1) of the first stack ST1 corresponding to the erase stack. As a result, the channels CH of the first and second stacks ST1 and ST2 can be boosted to a first channel voltage VCH1. The first channel voltage VCH1 can be approximately expressed as the following equation 1.

[0111] VCH1=VPC+VBST1=VPC+VPASS1*N1 / [(N2-Np)+N1]…(1)

[0112] In Equation 1, VPC is a precharge voltage, VBST1 is a first boosting voltage, N1 is the number of word lines in the first stack ST1, N2 is the number of word lines in the second stack ST2, and Np is the number of word lines in the second stack ST2 corresponding to (or connected to) previously programmed memory cells. As shown in Equation 1, as the first boosting voltage VBST1 increases, the number Np increases.

[0113] During the second boost period PBST2, a pass voltage VSON is applied to the selected string select line SSLs, and a pass voltage VMOFF is applied to the middle switch line MSL, thereby electrically disconnecting the first stack ST1 and the second stack ST2 from each other. While the middle switch transistor is turned off, a second pass voltage VPASS2 is applied to the word lines WLu(ST2) and WLs(ST2) of the second stack ST2 corresponding to the selected stack. As a result, the channel CH of the first stack ST1 can maintain the first channel voltage VCH1, and the channel of the second stack ST2 can be further boosted to the second channel voltage VCH2. Although not shown, because the pass voltage VSON is applied to the selected string select line SSLs, the channel of the second stack ST2 in the selected cell string can have a program enable voltage VPER or a program inhibit voltage VINH depending on the bit line voltage. The second channel voltage VCH2 can be approximately expressed as Equation 2.

[0114] VCH2=VCH1+VBST2=VPC+VBST1+VBST2

[0115] =VPC+VPASS1*N1 / [(N2-Np)+N1]+VPASS2......(2)

[0116] In Equation 2, VBST2 is the second boosting voltage, and the second boosting voltage VBST2 corresponds to the second pass voltage VPASS2.

[0117] After the precharge period PPC, the off voltage VGOFF is applied to the ground selection line GSL to electrically disconnect the cell string from the source line CSL.

[0118] During the program execution period PEXE, the program voltage VPGM is applied to the selected word line WL(ST2) of the second stack ST2 corresponding to the selected stack, and the selected memory cells connected to the bit line BL to which the program enable voltage VPER is applied can be programmed.

[0119] As such, the boost operation according to the embodiment may include a first boost operation in a first boost period PBST1 and a second boost operation in a second boost period PBST2 , which may be referred to as a double boost.

[0120] During the first boosting period PBST1, a first boosting operation may be performed such that a first pass voltage VPASS1 is applied to a word line of an erase stack ST1 among the plurality of stacks ST1 and ST2 while a turn-on voltage VMON is applied to the middle switching line MSL so that the plurality of middle switching transistors are turned on. During the second boosting period PBST2, a second boosting operation may be performed such that after the first pass voltage VPASS1 is applied to the word line of the erase stack ST1, a second pass voltage VPASS2 is applied to a word line of a selected stack ST2 among the plurality of stacks ST1 and ST2 while a turn-off voltage VMOFF is applied to the middle switching line MSL so that the plurality of middle switching transistors are turned off.

[0121] During the first boosting period PBST1, while the first pass voltage VPASS1 is applied to the word line of the erase stack ST1, the channel of the erase stack ST1 and the channel of the selected stack ST2 are electrically connected to each other by turning on the plurality of intermediate switching transistors. Conversely, during the second boosting period PBST2, while the second pass voltage VPASS2 is applied to the word line of the selected stack ST2, the channel of the erase stack ST1 and the channel of the selected stack ST2 are electrically disconnected from each other by turning off the plurality of intermediate switching transistors.

[0122] Therefore, as shown in Equation 1 and Equation 2, the channel of the erase stack ST1 and the channel of the selected stack ST2 are boosted to the first channel voltage VCH1 by the first boosting operation, and only the channel of the selected stack ST2 is further boosted to the second channel voltage VCH2 by the second boosting operation. At time point T4 when the second boosting operation is completed, the second channel voltage VCH2 of the selected stack ST2 becomes higher than the first channel voltage VCH1 of the erase stack ST1.

[0123] Figure 12Ais a diagram for describing reduction of pass voltage disturbance in a nonvolatile memory device according to an embodiment, Figure 12B is a diagram for describing reduction of program voltage disturbance in a nonvolatile memory device according to an embodiment.

[0124] Figure 12A and Figure 12B The structure of a cell string connected between a bit line BL and a source line CSL is shown, wherein the cell string includes a vertically arranged string selection transistor SST connected to a string selection line SSL, a plurality of memory cells MC1 to MC12 respectively connected to word lines WL1 to WL12, an intermediate switching transistor MST connected to an intermediate switching line MSL, and a ground selection transistor GST connected to a ground selection line GSL. Figure 12A and Figure 12B The left part shows the situation according to the traditional scheme, Figure 12A and Figure 12B The right part of shows the situation according to an embodiment. Figure 12A and Figure 12B The cell string is a selected cell string so that the turn-on voltage VSON is applied to the string selection line SSL. The first stack ST1 corresponds to an erase stack in which all memory cells are in an erase state, and the second stack ST2 corresponds to a selected stack including memory cells currently to be programmed.

[0125] Figure 12A The figure shows the channel voltage of the cell string when the program enable voltage VPER is applied to the bit line BL. In conventional methods, the on-voltage VMON is applied to the middle switching line MSL corresponding to the dummy word line, turning on the middle switching transistor MST. Consequently, the channel voltage VCHc of the erase stack ST1 becomes equal to the channel voltage VCHc of the selected stack ST2. In this case, the voltage difference between the channel and gate of the memory cells MC1 to MC6 in the erase stack ST1 is the pass voltage VPASS. In contrast, with dual boosting according to an embodiment, the off-voltage VMOFF is applied to the middle switching line MSL, turning off the middle switching transistor MST. Consequently, the channel of the erase stack ST1 is boosted to the first channel voltage VCH1. In this case, the voltage difference between the channel and gate of the memory cells MC1 to MC6 in the erase stack ST1 is VPASS1 - VCH1. As a result, the dual boosting according to an embodiment can reduce or prevent pass voltage interference in the erase stack ST1.

[0126] Figure 12BFigure 2 shows the channel voltages of a cell string when the program-inhibit voltage VINH is applied to the bit line BL. In conventional methods, the on-voltage VMON is applied to the middle switching line MSL corresponding to the dummy word line, turning on the middle switching transistor MST. Consequently, the channel voltage VCHc of the erase stack ST1 becomes equal to the channel voltage VCHc of the selected stack ST2. In this case, the voltage difference between the channel and gate of the memory cell MC9 to which the program voltage VPGM is applied is VPGM - VCC - VPASS. In contrast, in the dual-boosting method according to an embodiment, the off-voltage VMOFF is applied to the middle switching line MSL, turning off the middle switching transistor MST. Consequently, the channel of the erase stack ST1 is boosted to a first channel voltage VCH1, the channels of the erased memory cells MC7 to MC9 of the selected stack ST2 are boosted to a second channel voltage VCH2, and the channels of the programmed memory cells MC10 to MC12 of the selected stack ST2 are boosted to a third channel voltage VCH3. In this case, the voltage difference between the channel and the gate electrode of the memory cell MC9 to which the program voltage VPGM is applied is VPGM-VCC-VBST-VPASS2. As a result, the program voltage disturbance of the memory cell MC9 to which the program voltage VPGM is applied can be reduced or prevented by the double boosting according to the embodiment.

[0127] Figure 13A and Figure 13B is a diagram for describing reduction of pass voltage disturb and program voltage disturb in incremental step pulse programming (ISPP) of a nonvolatile memory device according to an embodiment.

[0128] Figure 13A shows ISPP by conventional methods, Figure 13B FIG. 4 shows ISPP by double boost according to an embodiment. Figure 13A and Figure 13B , a plurality of program loops LOOP1 to LOOP7 may be sequentially performed until programming according to ISPP is completed. When the program loop is repeated, the voltage level of the program voltage VPGM may increase (eg, from 15V to 21V), and the second pass voltage VPASS2 may also increase.

[0129] exist Figure 13A and Figure 13B In , “yes” indicates a case where program voltage disturbance or pass voltage disturbance occurs, and “no” indicates a case where program voltage disturbance or pass voltage disturbance does not occur. Figure 13A In the case of , program voltage disturbance occurs when VPGM-VPASS2 is equal to or greater than 9V, and pass voltage disturbance occurs when VPASS is equal to or higher than 7V. Figure 13BIn the case of , program voltage disturbance occurs when VPGM-VPASS2-VBST is equal to or greater than 9 V, and pass voltage disturbance occurs when VPASS is equal to or higher than 7 V. Here, VBST is the above-mentioned boost voltage, and the boost voltage is assumed to be 2 V.

[0130] like Figure 13A and Figure 13B As shown, for a program loop in which program voltage disturbance does not occur using dual boosting according to an embodiment, the pass voltage VPASS2 can be reduced, thereby reducing the number of program loops in which pass voltage disturbance occurs. In addition, the number of program loops in which program voltage disturbance occurs can be reduced by boosting the voltage VBST.

[0131] Figure 14 is a diagram illustrating hot carrier injection that may be caused by a programming method in a nonvolatile memory device.

[0132] Figure 14 The hot carrier injection HCI that may occur in the above selected stack is shown. Figure 11 、 Figure 12A and Figure 12B As described above, with respect to the selected stack, an initial voltage (e.g., 0V) may be applied to word lines WL7 to WL12 during a first boosting period PBST1, and a second pass voltage VPASS2 may be applied to word lines WL7 to WL12 during a second boosting period PBST2. Because memory cells in the program state PS are turned off, channels corresponding to word lines WL10 to WL12, on which a programming operation has already been performed, may have a third channel voltage VCH3, and channels corresponding to word lines WL7 to WL9, on which a programming operation has not yet been performed, may have a second channel voltage VCH2. As described above with reference to Equations 1 and 2, the second channel voltage VCH2 increases as the number Np of word lines corresponding to previously programmed memory cells in the selected stack increases. Furthermore, as the number Np increases, the boosting effect of the program voltage VPGM may increase, and the second channel voltage VCH2 may excessively increase. If the difference between the second channel voltage VCH2 and the third channel voltage VCH3 exceeds a threshold value, the program state PS of the memory cell in the boundary region may be distorted due to hot carrier injection HCI. Figure 15 and Figure 16 As described, the double boost according to the embodiment can be controlled.

[0133] Figure 15 and Figure 16 is a flowchart illustrating a method of programming in a nonvolatile memory device according to an embodiment.

[0134] refer to Figure 2 、 Figure 3 and Figure 15 , the non-volatile memory device 30 may receive a program (PGM) command (S11) and prepare for a programming operation. The control circuit 450 of the non-volatile memory device 30 may determine the number of programming lines Np corresponding to the number of word lines corresponding to the previously programmed memory cells in the selected stack (S12). The control circuit 450 may control the boost operation based on the number of programming lines Np. For example, the control circuit 450 may compare the number of programming lines Np with a predetermined reference number Nr (S13). When the number of programming lines Np is less than the reference number Nr (S13: No), the control circuit 450 may perform a boost PGM using the above-described boost operation (S14). When the number of programming lines Np is greater than the reference number Nr (S13: Yes), the control circuit 450 may perform a normal PGM by omitting the boost operation (S15).

[0135] In this way, the boost operation can be controlled based on the number of programming lines Np to prevent the reference Figure 14 Hot carrier injection HCI as described.

[0136] refer to Figure 2 、 Figure 3 and Figure 16 , the non-volatile memory device 30 may receive a program (PGM) command (S21) and prepare for a programming operation. The control circuit 450 of the non-volatile memory device 30 may determine the number of programming lines Np, the precharge voltage VPC, and the first pass voltage VPASS1 corresponding to the number of word lines corresponding to the previously programmed memory cells in the selected stack (S22). The control circuit 450 may control a boost operation based on the number of programming lines Np, the precharge voltage VPC, and the first pass voltage VPASS1. For example, the control circuit 450 may determine whether hot carrier injection (HCl) occurs based on the number of programming lines Np, the precharge voltage VPC, and the pass voltage VPASS (S23). When it is determined that hot carrier injection (HCl) does not occur (S23: No), the control circuit 450 may perform a boost PGM using the above-described boost operation (S24). When it is determined that hot carrier injection (HCI) occurs (S23: Yes), the control circuit 450 may reduce at least one of the precharge voltage VPC and the first pass voltage VPASS1 (S25), and then the control circuit 450 may perform the boost PGM through the above-mentioned boost operation (S24). As described with reference to Equation 1, the first boosted voltage VBST1 may be reduced by reducing at least one of the precharge voltage VPC and the first pass voltage VPASS1.

[0137] Thus, when the number of programming lines Nr increases, the reference voltage VPC can be prevented from being reset by reducing at least one of the precharge voltage VPC and the first pass voltage VPASS1. Figure 14Hot carrier injection HCI as described.

[0138] Figure 17 Is to show that according to Figure 10 The timing diagram of the programming operation of the second stack of the cell string of the first programming scheme is shown in FIG. The precharge period PPC, the first boost period PBST1, the second boost period PBST2 and the program execution period PEXE are Figure 11 The same, so repeated description is omitted.

[0139] As reference Figure 11 、 Figure 12A and Figure 12B As described, the channel of the erase stack ST1 has a first channel voltage VCH1, and the channel of the selected stack ST2 has a further boosted second channel voltage VCH2. If the channels of the first stack ST1 and the second stack ST2 are electrically connected to each other, the voltage difference between the first channel voltage VCH1 and the second channel voltage VCH2 may cause hot carrier injection (HCl).

[0140] refer to Figure 17 , a recovery operation for initializing the word line voltage may be sequentially performed during a first recovery period PRCV1 of a time interval T5-T6 and a second recovery period PRCV2 of a time interval T6-T7.

[0141] During the first recovery period PRCV1, the voltage of the word line of the selected stack ST2 may decrease from the second pass voltage VPASS2 to an intermediate voltage Va that is lower than the second pass voltage VPASS2 and higher than the initial voltage Vo. After the voltage of the word line of the selected stack ST2 decreases to the intermediate voltage Va, the plurality of intermediate switching transistors may be turned on.

[0142] During the second recovery period PRCV2 , the voltage of the word line of the erase stack ST1 may decrease from the first pass voltage VPASS1 to the initial voltage Vo, and simultaneously, the voltage of the word line of the selected stack ST2 may decrease from the intermediate voltage Va to the initial voltage Vo.

[0143] As a result, during the first recovery period PRCV1, the channel voltage of the selected stack ST2 can be reduced first, the intermediate switching transistor is turned on to electrically connect the channels of the selected stack ST2 and the erase stack ST1, and then, during the second recovery period PRCV2, the channel voltage of the selected stack ST2 and the erase stack ST1 can be reduced for the second time.

[0144] In this way, hot carrier injection HCI may be prevented by performing a recovery operation to initialize word line voltages of the plurality of stacks ST1 and ST2 by controlling switching operations of the plurality of middle switching transistors.

[0145] Figure 18 is a cross-sectional view illustrating a memory block divided into three stacks according to an embodiment.

[0146] refer to Figure 18 The boundary portion BND may include a lower boundary portion BNDL and an upper boundary portion BNDU. The memory block MB may include a first stack body ST1 below the lower boundary portion BNDL, a second stack body ST2 between the lower boundary portion BNDL and the upper boundary portion BNDU, and a third stack body ST3 above the upper boundary portion BNDU.

[0147] The intermediate switching transistors may include a plurality of lower switching transistors disposed in the lower boundary portion BNDL and connected to the lower switching line LSL; and a plurality of upper switching transistors disposed in the upper boundary portion BNDU and connected to the upper switching line USL.

[0148] Figure 19A and Figure 19B It shows that according to Figure 10 The first programming scheme about Figure 18 The programming operation of the stack of memory cell arrays can be omitted. Figure 11 Duplicate description.

[0149] Figure 19A and Figure 19B The voltages during the above-described precharge period PPC, the first boosting period PBST1, and the second boosting period PBST2 are shown.

[0150] Figure 19A This corresponds to a case where a program operation is performed on the third stack ST3 according to the first programming scheme T2B. In this case, the first stack ST1 and the second stack ST2 correspond to the erase stack, and the third stack ST3 corresponds to the selected stack.

[0151] During the precharge period PPC and the first boost period PBST1, the on-voltages VLON and VUON are applied to the lower switch line LSL and the upper switch line USL, respectively. During the second boost period PBST2, the off-voltages VLOFF and VUOFF are applied to the lower switch line LSL and the upper switch line USL, respectively. Other voltages are referenced to Figure 11 By controlling the switching operations of the middle switching transistors MC4 and MC8 in this manner, the double boost as described above can be achieved with respect to the third stack ST3 corresponding to the selected stack.

[0152] Figure 19BThis corresponds to the case where a program operation is performed on the second stack ST2 according to the first programming scheme T2B. In this case, the first stack ST1 corresponds to the erase stack, and the second stack ST2 corresponds to the selected stack.

[0153] During the precharge period PPC and the first boost period PBST1, the on-voltages VLON and VUON are applied to the lower switch line LSL and the upper switch line USL, respectively. During the second boost period PBST2, the off-voltages VLOFF and VUOFF are applied to the lower switch line LSL and the upper switch line USL, respectively. Other voltages are referenced to Figure 11 By controlling the switching operations of the middle switching transistors MC4 and MC8 in this manner, the double boost as described above can be achieved for the second stack ST2 corresponding to the selected stack.

[0154] Figure 20 is a diagram showing a second programming scheme according to an embodiment. Figure 10 Duplicate description.

[0155] refer to Figure 20 According to the second programming scheme, a programming operation can be performed in an upward direction from the lowest word line. In other words, as the data stored in the memory block increases, the data can be filled in the erased cells in an upward direction from bottom to top (B2T programming order). The unprogrammed memory cells MC5 to MC12 are in the erased state E0, and each of the programmed memory cells MC1 to MC4 can be in the erased state E0 and one of the programmed states P1, P2, and P3. For example, at least one of the memory cells MC2 to MC11 can be an intermediate switching transistor.

[0156] Figure 21 It shows that according to Figure 20 The timing diagram of the programming operation of the first stack of the second programming scheme can be omitted. Figure 11 Duplicate description.

[0157] exist Figure 11 In the case of , the first stack body ST1 corresponds to the erased stack body, and the second stack body ST2 corresponds to the selected stack body. Figure 21 In the case of , the first stack ST1 corresponds to a selected stack, and the second stack ST2 corresponds to an erased stack.

[0158] Therefore, the first boosting operation may be performed by applying the first pass voltage VPASS1 to the word line of the second stack ST2 , and after the first boosting operation, the second boosting operation may be performed by applying the second pass voltage VPASS2 to the word line of the first stack ST1 .

[0159] In the second programming scheme, when a programming operation is performed on the first stack ST1 corresponding to the selected stack, a previously programmed memory cell may exist between the currently selected memory cell to be programmed and the source line CSL. Therefore, during the precharge period PPC, a precharge voltage VPC may be applied to the channels of the first and second stacks ST1 and ST2 by applying the precharge voltage VPC to the bit line BL, applying the turn-on voltage VSON to the string selection lines SSLs and SSLu, and applying the turn-on voltage VMON to the middle switching line MSL.

[0160] Figure 22A and Figure 22B is a diagram illustrating an embodiment of a memory cell array included in a nonvolatile memory device according to an embodiment.

[0161] Figure 22A and Figure 22B The structure shown is that both the bit lines BL and the source lines CSL are arranged above the memory cell arrays 700 and 800. For ease of explanation, one cell string is shown, and each of the memory cell arrays 700 and 800 may include multiple cell strings of the same configuration. Each cell string may include a string select transistor SST controlled by a string select line SSL, a memory cell MC controlled by a word line WL, an intermediate switch transistor controlled by an intermediate switch line MSL, and a ground select transistor GST controlled by a ground select line GSL.

[0162] refer to Figure 22A , the cell string may include a middle switching transistor MST arranged in a lowermost layer, and the memory cell array 700 may be divided into a first sub-array 710 and a second sub-array 720 .

[0163] refer to Figure 22B , the cell strings may include switching transistors MST arranged in the lowermost layer and the middle layer, and the memory cell array 800 may be divided into a first sub-array 810 , a second sub-array 820 , a third sub-array 830 , and a fourth sub-array 840 .

[0164] By applying the double boosting described above to the sub-array considered as the stack, program voltage disturbance and pass voltage disturbance can be reduced, thereby improving the performance and lifespan of the nonvolatile memory device.

[0165] Figure 23 is a block diagram illustrating a solid state disk or solid state drive (SSD) according to an embodiment.

[0166] refer to Figure 23 , the SSD 1000 includes a plurality of nonvolatile memory devices 1100 and an SSD controller 1200 .

[0167] The nonvolatile memory device 1100 may be optionally configured to receive a high voltage VPP. The nonvolatile memory device 1100 may be the nonvolatile memory device 30 described above. The nonvolatile memory device 1100 may implement the double boost described above by controlling the switching operation of the intermediate switching transistor based on a programmed address.

[0168] The SSD controller 1200 is connected to the nonvolatile memory device 1100 via a plurality of channels CH1 to CHi. The SSD controller 1200 includes one or more processors 1210, a buffer memory 1220, an error correction code (ECC) circuit 1230, a host interface 1250, and a nonvolatile memory (NVM) interface 1260. The buffer memory 1220 stores data for driving the SSD controller 1200. The buffer memory 1220 can buffer data used for programming operations. The ECC circuit 1230 calculates an error correction code value for the data to be programmed during a write operation and uses the error correction code value to correct errors in the read data during a read operation. During a data recovery operation, the ECC circuit 1230 corrects errors in the data recovered from the nonvolatile memory device 1100.

[0169] As described above, the nonvolatile memory device and the method of programming the nonvolatile memory device according to the embodiment can reduce program voltage disturbance and pass voltage disturbance, thereby improving the performance and life of the nonvolatile memory device by controlling the switching operation of the intermediate switching transistor to achieve double boosting of the channel voltage.

[0170] The present invention can be applied to non-volatile memory devices and systems including non-volatile memory devices. For example, the present invention can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, notebook computers, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, and the like.

[0171] The above is an illustration of an embodiment and should not be construed as limiting thereof. Although various embodiments have been described, it will be readily apparent to those skilled in the art that many modifications may be made to the embodiments without departing substantially from the concept of the present invention.

Claims

1. A method of programming a non-volatile memory device, the method comprising the steps of: providing a memory block including a plurality of stacks arranged in a vertical direction, each memory block including a plurality of cell strings, and each cell string including a plurality of memory cells connected in series in the vertical direction between a source line and each of a plurality of bit lines; providing a plurality of intermediate switching transistors arranged in a boundary portion between two adjacent stack bodies in the vertical direction, the intermediate switching transistors performing switching operations to respectively control electrical connections of the cell strings; as well as During a program operation on the memory block, a boosting operation is performed to boost the voltage of the channel of the stack while controlling the switching operation of the middle switching transistor. The step of performing the boost operation includes: applying a first pass voltage to a word line of an erase stack in the stack while turning on the middle switch transistor, the erase stack representing a stack in which all memory cells are in an erased state; After applying the first pass voltage to the word line of the erase stack, a second pass voltage is applied to the word line of a selected stack in the stack while turning off the middle switching transistor, the selected stack representing the stack including the memory cell to be programmed.

2. The method according to claim 1, wherein while applying the first pass voltage to a word line of the erase stack, electrically connecting a channel of the erase stack and a channel of the selected stack to each other by turning on the middle switch transistor; and Wherein, while applying the second pass voltage to the word line of the selected stack, the channel of the erase stack and the channel of the selected stack are electrically disconnected from each other by turning off the middle switch transistor.

3. The method according to claim 1, wherein After applying the second pass voltage to the word line of the selected stack, the channel of the selected stack is boosted to a voltage higher than the voltage to which the channel of the erase stack is boosted.

4. The method according to claim 1, wherein The step of performing the boost operation further includes: Before applying the first pass voltage to the word line of the erase stack, a precharge voltage is applied to the channel of the selected stack and the channel of the erase stack while turning on the middle switching transistor.

5. The method according to claim 1, further comprising the steps of: performing a recovery operation to initialize a word line voltage of the stack by controlling the switching operation of the middle switching transistor, in, The steps of performing the recovery operation include: reducing a voltage of a word line of the selected stack from the second pass voltage to an intermediate voltage that is lower than the second pass voltage and higher than an initial voltage; and After the voltage of the word line of the selected stack decreases to the intermediate voltage, the intermediate switching transistor is turned on.

6. The method according to claim 5, wherein: The step of performing the recovery operation further includes: The voltage of the word line of the erase stack is reduced from the first pass voltage to the initial voltage, and at substantially the same time, the voltage of the word line of the selected stack is reduced from the intermediate voltage to the initial voltage.

7. The method of claim 1, further comprising the steps of: The boosting operation is controlled based on a number of program lines corresponding to a plurality of word lines connected to previously programmed memory cells in the selected stack.

8. The method of claim 7, wherein: The steps of controlling the boost operation include: In response to determining that the programming line number is less than a reference number, performing the boosting operation; and In response to determining that the programming line number is greater than the reference number, the boosting operation is omitted.

9. The method of claim 7, wherein: The steps of controlling the boost operation include: As the number of the programming lines increases, the first pass voltage is reduced.

10. The method of claim 7, wherein: The step of performing the boost operation further includes: Before applying the first pass voltage to the word line of the erase stack, a precharge voltage is applied to the channel of the selected stack and the channel of the erase stack while turning on the middle switch transistor, and The step of controlling the boost operation includes: As the number of programming lines increases, the precharge voltage is reduced.

11. The method according to claim 1 , further comprising the steps of: executing a programming scheme such that the programming operation is performed in a downward direction starting from the uppermost word line, in, The stacked bodies include a first stacked body below the boundary portion and a second stacked body above the boundary portion, and The boosting operation is performed in response to determining that the program operation on the second stack is performed, and the boosting operation is omitted in response to determining that the program operation on the first stack is performed.

12. The method according to claim 11, further comprising the steps of: Before performing the boosting operation, a precharge voltage is applied to the channel of the stack through the source line.

13. The method of claim 1, wherein: Also includes the steps: executing a programming scheme such that the programming operation is performed in an upward direction starting from a lowest word line of the stack, wherein the stacked body comprises a first stacked body below the boundary portion and a second stacked body above the boundary portion, and The boosting operation is performed in response to determining that the program operation on the first stack is performed, and the boosting operation is omitted in response to determining that the program operation on the second stack is performed.

14. The method of claim 13, further comprising the steps of: Before performing the boosting operation, a precharge voltage is applied to the channel of the stack through the bit line.

15. The method of claim 1, wherein: The boundary portion includes a lower boundary portion and an upper boundary portion, wherein the stacking body comprises a first stacking body below the lower boundary portion, a second stacking body between the lower boundary portion and the upper boundary portion, and a third stacking body above the upper boundary portion, and The intermediate switch transistors include a plurality of lower switch transistors arranged in the lower boundary portion and a plurality of upper switch transistors arranged in the upper boundary portion.

16. A method for programming a memory block, the memory block comprising a plurality of stacks connected in series in a vertical direction by forming cell strings between bit lines and source lines, the method comprising the steps of: selecting a stack including memory cells to be programmed according to a program command from the stacks, the selected stack being separated from an erase stack including unprogrammed memory cells by a boundary portion including at least one intermediate switch; determining whether the number of word lines connected to previously programmed memory cells of the selected stack in the cell string is less than a predetermined number; In response to the determination result, performing a double boost operation on the memory block, The dual boost operation includes: a first boosting operation including turning on the middle switch and applying a first pass voltage to a word line connected to a memory cell of an erase stack in the cell string; and A second boosting operation, the second boosting operation including turning off the intermediate switch and applying a second pass voltage to word lines connected to memory cells of a selected stack in the cell string, the word lines connected to memory cells of the selected stack in the cell string including word lines connected to memory cells to be programmed.

17. The method of claim 16, wherein: In the first boosting operation, the channel of the selected stack and the channel of the erase stack are boosted to a first channel voltage, and in the second boosting operation, only the channel of the selected stack among the selected stack and the erase stack is boosted to a second channel voltage, the second channel voltage being greater than the first channel voltage, and The method further includes the step of: reducing the first channel voltage and the second channel voltage in response to determining that the difference between the first channel voltage and the second channel voltage is greater than a threshold.

18. The method of claim 16, wherein: The intermediate switch includes a dummy memory cell.

19. A non-volatile memory device comprising: a memory block including a plurality of stacks arranged in a vertical direction, each memory block including a plurality of cell strings, each cell string including a plurality of memory cells connected in series in the vertical direction between a source line and each of a plurality of bit lines; a plurality of intermediate switching transistors arranged in a boundary portion between two adjacent stacked bodies in the vertical direction, the intermediate switching transistors performing switching operations to respectively control electrical connections of the cell strings; as well as a control circuit configured to perform a boosting operation to boost the voltage of the channel of the stack while controlling the switching operation of the middle switching transistor during a programming operation with respect to the memory block, The boost operation includes: a first boosting operation including turning on the intermediate switch and applying a first pass voltage to word lines connected to memory cells of erase stacks in the plurality of cell strings; and A second boosting operation includes turning off the middle switch and applying a second pass voltage to a word line connected to a memory cell of a selected stack among the plurality of cell strings.

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