Electronic panel, electronic panel testing device and electronic panel testing method

Abstract

An electronic panel, an electronic panel test device and an electronic panel test method are disclosed. The test device includes: a plurality of signal test pads electrically connected to pads of an input sensing unit; a power test pad electrically connected to a power pattern of a display unit; the test circuit is configured to apply a test signal to the signal test pad; the voltage generator is configured to generate a sensing power supply voltage; and the ripple controller is configured to change a voltage level of the sensing power supply voltage to apply the sensing power supply voltage to the power test pad.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0136736, filed on November 8, 2018, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Aspects of some example embodiments of the present disclosure relate to apparatus for testing electronic panels. Background Art

[0004] Organic light-emitting display devices display images using organic light-emitting diodes as self-luminous elements, and have attracted much attention as next-generation display devices because they have relatively excellent brightness and color purity. Organic light-emitting display devices include red pixels, green pixels, and blue pixels to form a display panel, and display various color images through the display panel.

[0005] The organic light emitting display device includes an electronic panel including a display unit that displays an image and an input sensing unit that senses an external input and outputs information about the location and intensity of the external input. When manufacturing the organic light emitting display device, a process of testing whether the electronic panel of the organic light emitting display device operates normally (or as expected) may be performed.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] Aspects of some example embodiments of the present disclosure relate to an apparatus for testing an electronic panel. For example, some example embodiments of the present disclosure relate to a testing apparatus for testing an electronic panel including an input sensing unit.

[0008] Some example embodiments of the present disclosure include a testing device capable of testing an operating state of an input sensing unit according to an operating environment of a display unit.

[0009] Some example embodiments of the present disclosure include an electronic panel including a panel for testing an operation state of an input sensing unit.

[0010] Some example embodiments of the present disclosure include a testing method capable of testing an operating state of an input sensing unit according to an operating environment of a display unit.

[0011] According to some example embodiments of the inventive concept, a test device includes: a signal test pad, a power test pad, a test circuit, a voltage generator, and a ripple controller, the signal test pad is electrically connected to a pad of an input sensing unit, the power test pad is electrically connected to a power pattern of a display unit, the test circuit applies a test signal to the signal test pad, the voltage generator generates a sensing power voltage, and the ripple controller changes a voltage level of the sensing power voltage to apply the sensing power voltage to the power test pad.

[0012] According to some example embodiments, the ripple controller provides ripple noise to a sensing power supply voltage, and applies the sensing power supply voltage including the ripple noise to a power supply test pad.

[0013] According to some example embodiments, the signal test pads include a test transmission signal pad and a test reception signal pad.

[0014] According to some example embodiments, the test circuit outputs a test transmission signal to a test transmission signal pad, and receives a test reception signal from a test reception signal pad.

[0015] According to some example embodiments, the test circuit further outputs a switch signal in synchronization with the test transmission signal to select a voltage level of the sensing power supply voltage.

[0016] According to some example embodiments, the test circuit further outputs a switch signal to select a voltage level of the sensing power supply voltage.

[0017] According to some example embodiments, a ripple controller changes a voltage level of a sense power supply voltage in response to a switching signal.

[0018] According to some example embodiments, the ripple controller includes a plurality of current controllers connected in parallel between a first node receiving a sense power supply voltage and a second node receiving a second voltage and operating in response to a switching signal.

[0019] According to some example embodiments, each of the current controllers includes a resistor and a transistor, the resistor including one end connected to a first node and the other end, and the transistor including a first electrode connected to the other end of the resistor, a second electrode connected to the second node, and a gate electrode receiving a corresponding switching signal among the switching signals.

[0020] According to some example embodiments of the present invention, an electronic panel includes: a display unit and an input sensing unit, the display unit includes a display area and a peripheral area adjacent to the display area, and the input sensing unit is located on the display unit to sense an external input applied to the sensing area overlapping the display area. The display unit includes a power pad and a power pattern, the power pad is located in the peripheral area to receive a power supply voltage, and the power pattern is located in the peripheral area and electrically connected to the power pad. The input sensing unit includes a sensing pad and a power line, the sensing pad is located in a non-sensing area around the sensing area and receives a sensing power supply voltage, and the power line is located in the non-sensing area and electrically connected to the sensing pad. The power line is electrically connected to the power pattern.

[0021] According to some example embodiments, the power line overlaps the power pattern when viewed in a plan view.

[0022] According to some example embodiments, a display unit includes a plurality of pixels located in a display area. Each of the pixels includes a transistor and an organic light-emitting device, the transistor including a semiconductor pattern, a control electrode spaced apart from the semiconductor pattern, an input electrode connected to the semiconductor pattern, and an output electrode located on the same layer as the input electrode and connected to the semiconductor pattern and covered by an insulating layer, and the organic light-emitting device is located on the insulating layer and includes a first electrode, a second electrode located on the first electrode, and a light-emitting layer located between the first electrode and the second electrode, and the power pattern is located on the same layer as the output electrode.

[0023] According to some example embodiments, the power pattern is electrically connected to the second electrode.

[0024] According to some example embodiments, the insulating layer includes a first layer, a second layer, and a third layer, the first layer being between the first electrode and the output electrode to cover the output electrode, the second layer being on the first layer, and the third layer being on the second layer, and the first electrode being on the third layer.

[0025] According to some example embodiments, the power pattern receives a power voltage via a power pad during a normal mode, and receives a sensing power voltage via a sensing pad and a power line during a test mode.

[0026] According to some example embodiments, during the test mode, the sensed power voltage includes ripple noise.

[0027] According to some example embodiments, the input sensing unit further includes a sensing signal pad located in the non-sensing region and receiving a test transmission signal, and receives the test transmission signal during the test mode.

[0028] According to some example embodiments of the present invention, in a testing method of a testing device including a signal test pad electrically connected to a pad of an input sensing unit and a power test pad electrically connected to a power pattern of a display unit, the method includes: outputting a test transmission signal to a first pad among the signal test pads; generating a sensing power supply voltage; changing a voltage level of the sensing power supply voltage; and receiving a test transmission signal from a second pad among the signal test pads.

[0029] According to some example embodiments, the changing of the voltage level of the sensing power supply voltage includes changing the voltage level of the sensing power supply voltage in synchronization with the test transmission signal.

[0030] According to some example embodiments, sensing the change in the voltage level of the power supply voltage includes adding ripple noise to the sensing power supply voltage.

[0031] Therefore, according to some example embodiments, the test device can test the operating state of the input sensing unit when the power supply voltage is supplied to the display unit. For example, since the input sensing unit can be characteristically tested according to the change in the voltage level of the power supply voltage, a defect of the input sensing unit can be detected relatively easily. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects of some example embodiments of the present disclosure will become more apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0033] Figure 1 are exploded perspective views respectively showing some components of an electronic panel according to some example embodiments of the present disclosure;

[0034] Figure 2 is a plan view showing a display panel according to some example embodiments of the present disclosure;

[0035] Figure 3A It is shown Figure 2 A cross-sectional view of the region XX shown in ;

[0036] Figure 3B It is shown Figure 2 A cross-sectional view of the region YY shown in ;

[0037] Figure 4 is a perspective view showing a test circuit board connected to a display unit of an electronic panel in a testing operation;

[0038] Figure 5 is a perspective view showing a test circuit board connected to an input sensing unit of an electronic panel in a testing operation;

[0039] Figure 6 is along Figure 5The line II' of FIG. 1 is taken to show a cross-sectional view of the electronic panel;

[0040] Figure 7 is a block diagram illustrating a configuration of a second test circuit board according to some example embodiments of the present disclosure;

[0041] Figure 8 It is shown Figure 7 A circuit diagram of a ripple controller circuit configuration shown in;

[0042] Fig. 9 It is shown Figure 7 A timing diagram of the operation of the second test circuit board shown in ; and

[0043] Fig.10 is a flowchart illustrating a testing method of a testing device according to some example embodiments of the present disclosure. DETAILED DESCRIPTION

[0044] It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected to or coupled to the other element or layer, or intervening elements or layers may be present.

[0045] Throughout the specification, the same reference numerals refer to the same elements.In the drawings, the thicknesses of layers, films, and regions are exaggerated for clarity.

[0046] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] It should be understood that although the terms first, second, etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teaching of the present disclosure, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part. Unless otherwise clearly indicated in the context, the singular form "a (a)", "an (an)" and "the (the)" as used herein are also intended to include plural forms.

[0048] Spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” etc. may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as shown in the figures.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense.

[0050] It should also be understood that when the terms “include” and / or “including” are used in this specification, they indicate the presence of stated features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or clusters thereof.

[0051] Hereinafter, the present disclosure will be explained in detail with reference to the accompanying drawings.

[0052] Figure 1 are exploded perspective views respectively illustrating some components of an electronic panel according to some example embodiments of the present disclosure. Figure 2 is a plan view showing a display panel according to some example embodiments of the present disclosure. Figure 3A It is shown Figure 2 A cross-sectional view of the region XX shown in FIG. Figure 3B It is shown Figure 2 A cross-sectional view of region YY shown in FIG.

[0053] Reference Figure 1 and Figure 2 , the electronic panel 100 includes a display unit 110 and an input sensing unit 120. Figure 1 , for convenience of explanation, the display unit 110 and the input sensing unit 120 are separated from each other.

[0054] The display unit 110 may include a display area DA and a peripheral area NDA. The display area DA may generate and display an image. The peripheral area NDA is arranged adjacent to the display area DA. The peripheral area NDA surrounds the edge of the display area DA, however, this is only an example. According to some example embodiments, the peripheral area NDA may be arranged adjacent to a portion of the edge of the display area DA or may be omitted, and the embodiments are not limited thereto.

[0055] The display unit 110 may generate an image and display the image through the display area DA. The display unit 110 may include a base substrate BS and pixels PX. The display area DA and the peripheral area NDA may be areas provided by the base substrate BS. The base substrate BS may include an insulating substrate. For example, the base substrate BS may include a glass substrate, a plastic substrate, or a combination thereof.

[0056] The pixels PX are arranged in the display area DA. The pixels PX are arranged in the first direction D1 and the second direction D2 and are spaced apart from each other in a matrix form. Each of the pixels PX receives an electrical signal and emits light to form an image.

[0057] Each of the pixels PX is connected to a signal line. The signal line includes a gate line GL, a data line DL, and a power line PL.

[0058] The gate lines GL extend in the first direction D1 and are arranged in the second direction D2 while being spaced apart from each other. The gate lines GL apply gate signals to the pixels PX.

[0059] The data lines DL are insulated from the gate lines GL while crossing the gate lines GL. In the present exemplary embodiment, the data lines DL extend in the second direction D2 and are arranged in the first direction D1 while being spaced apart from each other. The data lines DL apply data signals to the pixels PX.

[0060] The power lines PL may be insulated from the gate lines GL and the data lines DL. In the present exemplary embodiment, the power lines PL extend in the first direction D1 and are arranged in the second direction D2 while being spaced apart from each other. The power lines PL apply a first power signal to the pixels PX.

[0061] Each of the pixels PX includes a first transistor TR1, a second transistor TR2, a capacitor CP, and a light emitting device OLD. The first transistor TR1 is turned on in response to a gate signal applied thereto through a corresponding gate line among the gate lines GL to apply a data signal applied thereto through a corresponding data line among the data lines DL to the capacitor CP.

[0062] The capacitor CP is charged with a voltage corresponding to a potential difference between the first power voltage ELVDD supplied from the power line PL and the data signal. The second transistor TR2 is turned on by the voltage charged in the capacitor CP to supply the first power voltage ELVDD applied thereto through the power line PL to the light emitting device OLD.

[0063] The light emitting device OLD may generate light in response to an electrical signal or may control the amount of light. For example, the light emitting device OLD may include an organic light emitting device, a quantum dot light emitting device, an electrophoresis device, or an electrowetting device.

[0064] The light emitting device OLD is connected to the power terminal VSS to receive a second power voltage ELVSS different from the first power voltage ELVDD. A driving current corresponding to the difference between the electrical signal provided from the second transistor TR2 and the second power voltage ELVSS flows through the light emitting device OLD, and the light emitting device OLD can generate light corresponding to the driving current.

[0065] Meanwhile, according to some example embodiments of the present disclosure, the pixel PX may include electronic components having various configurations and arrangements, and the embodiments are not limited thereto.

[0066] The signal lines GL, DL and PL are positioned on the base substrate BS. The signal lines GL, DL and PL include gate lines GL, data lines DL and power lines PL. The gate lines GL, data lines DL and power lines PL may transmit electric signals different from each other.

[0067] The gate line GL extends in the first direction D1. The gate line GL is provided in plural, and the gate lines GL are arranged in the second direction D2 and are spaced apart from each other. For convenience of explanation, one gate line GL is shown as an example.

[0068] Meanwhile, the display unit 110 includes a gate driving circuit GV mounted on the base substrate BS to apply an electrical signal to the gate line GL.

[0069] The gate drive circuit GV may include at least one drive transistor TR-D and a plurality of wires CL and VIN. The drive transistor TR-D has the same structure as the second transistor TR2, however, it should not be limited thereto or thereby. That is, the drive transistor TR-D may have a different structure from the second transistor TR2. The wires CL and VIN are connected to the drive transistor TR-D to form an electronic circuit. The gate drive circuit GV may be connected to the gate line GL.

[0070] The first power pattern PP1 is positioned in the peripheral area NDA. The first power pattern PP1 has a quadrilateral shape defined by long sides extending in the first direction D1 and short sides extending in the second direction D2. The second power pattern PP2 is positioned in the peripheral area NDA. When viewed in a plan view, the first power pattern PP1 and the second power pattern PP2 are spaced apart from each other. The shapes and arrangements of the first power pattern PP1 and the second power pattern PP2 may be changed in various ways without limitation. Figure 1 and Figure 2 .

[0071] A plurality of display pads PDD, PDP1, and PDP2 are positioned in the peripheral area NDA. The area of ​​the peripheral area NDA where the display pads PDD, PDP1, and PDP2 are positioned may be defined as a first pad area PA1. A circuit board may be coupled to the first pad area PA1 to drive the pixel PX. In addition, in a test operation, a test circuit board may be coupled to the first pad area PA1. The circuit board or the test circuit board is electrically connected to the electronic panel 100 via the display pads PDD, PDP1, and PDP2 positioned in the first pad area PA1.

[0072] The display pads PDD, PDP1, and PDP2 may include a data pad PDD and power pads PDP1 and PDP2.

[0073] The power pad PDP1 is connected to the first power pattern PP1, and the power pad PDP2 is connected to the second power pattern PP2. The first power pattern PP1 may receive a first power voltage ELVDD provided from the outside via the power pad PDP1. The second power pattern PP2 may receive a second power voltage ELVSS provided from the outside via the power pad PDP2.

[0074] The input sensing unit (or input sensor) 120 is positioned on the display unit (or display or display panel) 110. The input sensing unit 120 senses the external input to obtain information about the position and strength of the external input. The input sensing unit 120 may include a sensing insulating layer SS, a sensing electrode SE, a plurality of sensing lines SL1 and SL2, and a plurality of sensing pads PDT and PDP3.

[0075] The input sensing unit 120 may include a sensing area SA and a non-sensing area NSA. The sensing area SA is an area capable of sensing an external input. The sensing area SA may overlap with the display area DA.

[0076] The non-sensing area NSA is positioned adjacent to the sensing area SA. The non-sensing area NSA surrounds the edge of the sensing area SA, however, this is merely exemplary. According to some example embodiments, the non-sensing area NSA may be positioned adjacent to a portion of the edge of the sensing area SA or may be omitted, however, embodiments are not limited thereto.

[0077] The sensing electrode SE is positioned in the sensing area SA. The sensing electrode SE includes a first sensing electrode SP1 and a second sensing electrode SP2 that receive different electrical signals from each other. The sensing electrode SE may acquire information about an external input based on a change in capacitance between the first sensing electrode SP1 and the second sensing electrode SP2.

[0078] The first sensing electrode SP1 extends in the first direction D1. The first sensing electrode SP1 is provided in plurality, and the first sensing electrodes SP1 are arranged in the second direction D2 and spaced apart from each other. The second sensing electrode SP2 extends in the second direction D2. The second sensing electrode SP2 is provided in plurality, and the second sensing electrodes SP2 are arranged in the first direction D1 and spaced apart from each other.

[0079] The first sensing line SL1 and the second sensing line SL2 and the sensing pads PDT and PDP3 are positioned in the non-sensing area NSA. The sensing pad PDT is connected to the first sensing line SL1 and the second sensing line SL2. The first sensing line SL1 connects the first sensing electrode SP1 and the sensing pad PDT to transmit an electrical signal provided from the outside to the first sensing electrode SP1 via the sensing pad PDT. The second sensing line SL2 connects the second sensing electrode SP2 and the sensing pad PDT to transmit an electrical signal provided from the second sensing electrode SP2 to the outside via the sensing pad PDT.

[0080] The area in which the sensing pads PDT and PDP3 are positioned in the non-sensing area NSA may be defined as a second pad area PA2. A circuit board for driving the first sensing electrode SP1 and the second sensing electrode SP2 may be coupled to the second pad area PA2. In addition, in a test operation, a test circuit board may be coupled to the second pad area PA2. The circuit board or the test circuit board is electrically connected to the electronic panel 100 via the sensing pads PDT and PDP3 positioned in the second pad area PA2.

[0081] Meanwhile, in the present exemplary embodiment, the sensing pad PDP3 may be electrically connected to the second power pattern PP2 of the display unit 110. That is, the sensing pad PDP3 and the display unit 110 are positioned on different layers from each other but may be electrically connected to each other.

[0082] Reference Figures 2 to 3B , the base substrate BS may be an insulating substrate. For example, the base substrate BS may include a plastic substrate or a glass substrate. An auxiliary layer BL is positioned on the base substrate BS to cover the entire surface of the base substrate BS. The auxiliary layer BL includes an inorganic material. The auxiliary layer BL includes a barrier layer and / or a buffer layer. Accordingly, the auxiliary layer BL prevents or reduces the oxygen or moisture entering through the base substrate BS from penetrating into the pixel PX and reduces the surface energy of the base substrate BS, so that the pixel PX is relatively stably formed on the base substrate BS.

[0083] The pixels PX may be arranged in the display area DA. In some example embodiments, as shown by way of example Figure 2 Each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may include an organic material and / or an inorganic material and may have a single layer structure or a multi-layer structure.

[0084] The second transistor TR2 is positioned on the base substrate BS and includes a control electrode CE, an input electrode IE, an output electrode OE, and a semiconductor pattern SP. The control electrode CE is positioned apart from the semiconductor pattern SP with the first insulating layer 10 interposed therebetween, and is connected to one electrode of the capacitor CP. Each of the input electrode IE and the output electrode OE is positioned on the second insulating layer 20, and is connected to the semiconductor pattern SP after penetrating the first insulating layer 10 and the second insulating layer 20. The input electrode IE is connected to the other electrode of the capacitor CP, and the output electrode OE is connected to the light emitting device OLD.

[0085] The light emitting device OLD is connected to the second transistor TR2 and the power supply terminal VSS. The light emitting device OLD includes a first electrode E1, a light emitting layer EL, and a second electrode E2. The first electrode E1 is positioned on the third insulating layer 30 and is connected to the second transistor TR2 after penetrating the third insulating layer 30. The light emitting layer EL covers the first electrode E1 exposed by the fourth insulating layer 40. The light emitting layer EL may include a light emitting material that generates light in response to a potential difference. For example, the light emitting layer EL may include an organic light emitting material or a quantum dot.

[0086] The second electrode E2 is positioned on the light emitting layer EL. The second electrode E2 is formed on the entire surface of the display area DA. The second electrode E2 extends from the display area DA to the peripheral area NDA and is connected to the connection pattern E-CNT. The connection pattern E-CNT may correspond to the power supply terminal VSS.

[0087] The power terminal VSS applies the second power voltage ELVSS to the light emitting device OLD. The second power voltage ELVSS may have a different potential from the first power voltage ELVDD. The light emitting device OLD generates light corresponding to the potential difference between the data signal supplied from the second transistor TR2 and the second power voltage ELVSS supplied from the power terminal VSS and emits light.

[0088] The gate drive circuit GV may include at least one drive transistor TR-D and a plurality of wires CL and VIN. The drive transistor TR-D has the same structure as the second transistor TR2, however, it should not be limited thereto or thereby. That is, the drive transistor TR-D may have a different structure from the second transistor TR2. The wires CL and VIN are connected to the drive transistor TR-D to form an electronic circuit. The gate drive circuit GV may be connected to the gate line GL.

[0089] The gate lines GL extend from the display area DA and are connected to a gate driving circuit GV positioned in the peripheral area NDA The gate driving circuit GV applies electrical signals (eg, gate signals) to the pixels PX respectively via the gate lines GL.

[0090] According to some example embodiments, one gate drive circuit GV is shown, however, the gate drive circuit GV may be provided in plurality. In an embodiment having a plurality of gate drive circuits GV, the gate drive circuits GV may be positioned or arranged so that they are spaced apart from each other with the display area DA interposed therebetween in the first direction D1. In addition, according to some example embodiments, the gate drive circuit GV is positioned directly on the base substrate BS, however, the embodiments are not limited thereto or thereby. That is, the gate drive circuit GV may be provided after being mounted on a separate circuit board. In this case, the gate drive circuit GV may be connected to the display unit 110 via a conductive adhesive member. The gate drive circuit GV according to some example embodiments of the present disclosure may be provided in various ways, however, the embodiments are not limited thereto.

[0091] The first conductive pattern CP1 connects the data line DL and the data pad PDD. The first conductive pattern CP1 includes a plurality of line patterns extending in the second direction D2 and arranged in the first direction D1 while being spaced apart from each other.

[0092] According to some example embodiments, the first conductive pattern CP1 may be positioned on a different layer from the data line DL. For example, the first conductive pattern CP1 may be positioned on the same layer as the control electrode CE (e.g., the gate line GL). In this case, the data line connection terminal DL-P extending from the data line DL may be connected to the first conductive pattern CP1 positioned between the first insulating layer 10 and the second insulating layer 20 via a contact hole CH defined by the second insulator layer 20.

[0093] However, this is only an example, and the first conductive pattern CP1 may be positioned on the same layer as the data line DL. For example, the first conductive pattern CP1 may be formed integrally with the data line DL and provided as a part of the data line DL, or may be connected to each of the data lines DL via a separate bridge pattern. According to some example embodiments of the present disclosure, as long as the first conductive pattern CP1 is connected to the data line DL, the first conductive pattern CP1 may have various shapes, and the embodiments are not limited thereto.

[0094] The first power pattern PP1 is positioned in the peripheral area NDA and connected to a power line PL extending from the display area DA. The power line PL is connected to the first power pattern PP1 to apply a first power voltage ELVDD of the same potential to each of the pixels PX.

[0095] The second power pattern PP2 is connected to the light emitting device OLD to provide a second power signal. The connection pattern E-CNT extends to the second power pattern PP2 to electrically connect the second electrode E2 and the second power pattern PP2. The power terminal VSS of each of the pixels PX may be a terminal substantially connected to the second pattern CP22. The second pattern CP22 may apply a second power voltage ELVSS of substantially the same potential to each of the pixels PX.

[0096] According to some example embodiments, the second conductive pattern CP2 is arranged on a different layer from the first conductive pattern CP1. According to some example embodiments, the second conductive pattern CP2 may be positioned above the first conductive pattern CP1. When viewed in a plan view, the second conductive pattern CP2 may be arranged to overlap with the first conductive pattern CP1 in the fan-out area FOA.

[0097] The second conductive pattern CP2 and the first conductive pattern CP1 are insulated from each other while intersecting each other in the fan-out area FOA. The first conductive pattern CP1 may be insulated from each of the first pattern CP21 and the second pattern CP22 while intersecting the first pattern CP21 and the second pattern CP22 of the second conductive pattern CP2. This will be described in more detail later.

[0098] The encapsulation layer TFE is positioned on the fourth insulating layer 40 to encapsulate the light emitting device OLD. The encapsulation layer TFE may include a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL2 sequentially stacked in the third direction D3, however, this is only an example. That is, the encapsulation layer TFE may also include an inorganic layer and an organic layer, and at least one of the first inorganic layer IOL1, the organic layer OL, and the second inorganic layer IOL2 may be omitted.

[0099] According to some example embodiments, the organic layer OL extends to a region where the gate driving circuit GV is located and does not overlap the first and second conductive patterns CP21 and CP22. However, according to some example embodiments, when viewed in a plan view, the organic layer OL may extend to a region where the organic layer OL overlaps the second conductive pattern CP2, but embodiments are not limited thereto.

[0100] The pads PDD, PDP1, and PDP2 may be positioned in the first pad area PA1. The pads PDD, PDP1, and PDP2 are arranged in the first direction D1 and are spaced apart from each other. The first pad area PA1 may be an area to which a circuit board is connected. The pads PDD, PDP1, and PDP2 may receive signals provided from the circuit board, respectively.

[0101] Each of the data pads PDD is connected to the first conductive pattern CP1. The data pads PDD may be data pads that respectively apply data signals provided from the circuit board to the data lines DL.

[0102] According to some example embodiments, the data pad PDD may be arranged on a different layer from the first conductive pattern CP1. For example, the data pad PDD may be arranged on the second insulating layer 20 and may be connected to the first conductive pattern CP1 after penetrating the second insulating layer 20, however, this is only an example. The data pad PDD may be arranged on the same layer as the first conductive pattern CP1 and may be formed integrally with the first conductive pattern CP1.

[0103] Meanwhile, the first and second power patterns PP1 and PP2 may receive the first and second power voltages ELVDD and ELVSS through the first and second power pads PDP1 and PDP2 arranged in the first pad area PA1, respectively.

[0104] Figure 4 is a perspective view showing a test circuit board connected to a display unit of an electronic panel in a test operation.

[0105] Reference Figure 4 , the active area AA may include Figure 1 2 , a display area DA of the display unit 110 and a sensing area SA of the input sensing unit 120 are shown in FIG. The sensing area SA may overlap with the display area DA.

[0106] The first test circuit board 400 may be implemented by a flexible printed circuit board (FPCB) and may include a pad portion disposed on a lower surface of one end thereof The pad portion of the first test circuit board 400 may be connected to the first pad area PA1 of the display unit 110 .

[0107] According to some example embodiments, the first test circuit board 400 may include a test circuit for testing the display unit 110. The test circuit of the first test circuit board 400 may provide a driving signal to drive the light emitting device OLD disposed on the display unit 110. In addition, according to some example embodiments, when the driving signal is provided to the display unit 110, color characteristics (such as color coordinates, efficiency, and current consumption) of the light emitting device OLD may be measured using a colorimeter or a spectrometer, and an image quality test (such as a flicker test) may be performed by the test circuit of the first test circuit board 400.

[0108] When the test operation on the display unit 110 is completed, a test operation on the input sensing unit 120 may be performed.

[0109] Figure 5 is a perspective view showing a test circuit board connected to an input sensing unit of an electronic panel in a test operation.

[0110] Reference Figure 5The second test circuit board 500 (or test device) may be implemented by a flexible printed circuit board (FPCB) and may include a pad portion positioned on a lower surface of one end thereof. The pad portion of the second test circuit board 500 may be connected to the second pad area PA2 of the input sensing unit 120.

[0111] The second test circuit board 500 may include a sensing test circuit 510 for testing the input sensing unit 120. The sensing test circuit 510 may test the sensing electrodes SE and the sensing lines SL1 and SL2 (see Figure 1 ) performs characteristic and defect test operations. The sensing test circuit 510 may be implemented by an integrated circuit (IC).

[0112] like Figure 3A As shown in FIG. 1 , the second electrode E2 electrically connected to the second power pattern PP2 is arranged above the display unit 110 and is located adjacent to the input sensing unit 120. When the voltage level of the second power voltage ELVSS supplied to the second power pattern PP2 is changed, the sensing characteristics of the input sensing unit 120 may be changed. For example, when an image displayed by the display unit 110 is changed from a white image to a black image or vice versa, the amount of change in the consumption current of the display unit 110 may increase. The change in the consumption current causes a change in the voltage level of the second power voltage ELVSS, thereby causing a ripple on the second power voltage ELVSS.

[0113] When the capacitance between the sensing electrode SE and the second electrode E2 changes due to a change in the voltage level of the second power voltage ELVSS, the capacitance between the first sensing electrode SP1 and the second sensing electrode SP2 changes, and thus information about an external input may be distorted.

[0114] Accordingly, in a test operation regarding the input sensing unit 120 , the test operation may be performed on the input sensing unit 120 after the first test circuit board 400 is connected to the display unit 110 , and substantially simultaneously, the second test circuit board 500 may be connected to the input sensing unit 120 .

[0115] However, it may be physically difficult to simultaneously connect the first test circuit board 400 and the second test circuit board 500 to the electronic panel 100 , and there may be a difficulty that may require a change in a test operation of the related art.

[0116] The second test circuit board 500 according to some example embodiments outputs the second power voltage ELVSS to apply the second power voltage ELVSS to the second power pattern PP2 of the display unit 110. For example, the second power voltage ELVSS may include ripple noise caused by the operation characteristics of the display unit 110. Accordingly, a test operation on characteristics and defects of the input sensing unit 120 may be performed in a state in which the ripple noise is included in the second power voltage ELVSS.

[0117] like Figure 1 and Figure 5 As shown in , the second power line VSL electrically connected to the sensing pad PDP3 is positioned in the non-sensing area NSA of the input sensing unit 120 .

[0118] Figure 6 is along Figure 5 The line II' of FIG. 8 is taken to show a cross-sectional view of the electronic panel.

[0119] Reference Figure 6 , the second power line VSL may be connected to the second power pattern PP2 through a contact hole CH1 formed through the third insulating layer 30 and the fourth insulating layer 40 of the display unit 110. When viewed in a plan view, the second power line VSL may overlap the second power pattern PP2.

[0120] Reference Figure 5 and Figure 6 , the second power voltage ELVSS provided from the sensing test circuit 510 of the second test circuit board 500 may be applied to the second power pattern PP2 via the second power line VSL.

[0121] Accordingly, the sensing test circuit 510 may test the operating state of the input sensing unit 120 while supplying the second power voltage ELVSS to the display unit 110. For example, since the input sensing unit 120 may be characteristically tested according to a change in the voltage level of the second power voltage ELVSS, a defect in the input sensing unit 120 may be detected relatively easily.

[0122] Figure 7 is a block diagram showing a configuration of a second test circuit board according to some example embodiments of the present disclosure. Figure 7 In the present invention, only circuit components associated with some example embodiments of the present disclosure are shown and described, however, the embodiments of the present disclosure are not limited thereto or thereby.

[0123] Reference Figure 7 The second test circuit board 500 includes a sensing test circuit 510, a signal test pad STP and a power test pad PTP. The signal test pad STP includes test transmission signal pads TX1 to TXi and test reception signal pads RX1 to RXj.

[0124] The sensing test circuit 510 includes a test circuit 610 , a voltage generator 620 , and a ripple controller 630 .

[0125] The test circuit 610 outputs a test transmission signal to the test transmission signal pads TX1 to TXi, and receives a test reception signal from the test reception signal pads RX1 to RXj.

[0126] The voltage generator 620 generates the sensing power supply voltage S_ELVSS. The voltage generator 620 may also generate a voltage required for the operation of the test circuit 610. The voltage generator 620 may be implemented by a DC-DC converter.

[0127] The ripple controller 630 changes the voltage level of the sensing power supply voltage S_ELVSS and outputs the sensing power supply voltage S_ELVSS to the power supply test pad PTP. According to some example embodiments, the ripple controller 630 may output the sensing power supply voltage S_ELVSS including ripple noise to the power supply test pad PTP. In addition, the ripple controller 630 may change the voltage level of the sensing power supply voltage S_ELVSS in synchronization with one of the test transmission signals provided to the test transmission signal pads TX1 to TXi.

[0128] According to some example embodiments, the ripple controller 630 may change the voltage level of the sensing power supply voltage S_ELVSS in response to the switching signals SW1 to SWk from the test circuit 610. The test circuit 610 may output the switching signals SW1 to SWk in synchronization with one of the test transmission signals supplied to the test transmission signal pads TX1 to TXi.

[0129] Figure 8 It is shown Figure 7 The circuit configuration of the ripple controller is shown in the circuit diagram.

[0130] Reference Figure 8 , the ripple controller 630 includes a plurality of current controllers 810 to 830. The current controllers 810 to 830 are connected in parallel between the first node N1 and the second node N2, and operate in response to the switching signals SW1 to SWk.

[0131] The first node N1 may receive the sensing power supply voltage S_ELVSS, and the second node N2 may receive the ground voltage (or the second voltage).

[0132] Each of the current controllers 810 to 830 includes a resistor and a switching transistor. One end of the resistor R1 of the current controller 810 is connected to the first node N1. The switching transistor ST1 of the current controller 810 includes a first electrode connected to the other end of the resistor R1, a second electrode connected to the second node N2, and a gate electrode receiving the switching signal SW1. One end of the resistor R2 of the current controller 820 is connected to the first node N1. The switching transistor ST2 of the current controller 820 includes a first electrode connected to the other end of the resistor R2, a second electrode connected to the second node N2, and a gate electrode receiving the switching signal SW2. One end of the resistor Rk of the current controller 830 is connected to the first node N1. The switching transistor STk of the current controller 830 includes a first electrode connected to the other end of the resistor Rk, a second electrode connected to the second node N2, and a gate electrode receiving the switching signal SWk.

[0133] When the switching transistors ST1 to STk in the current controllers 810 to 830 are turned on / off in response to the switching signals SW1 to SWk, the resistance between the first node N1 and the second node N2 changes, and as a result, the amount of current between the first node N1 and the second node N2 changes. As described above, the voltage level of the sensing power supply voltage S_ELVSS can be changed by controlling the on / off of the switching transistors ST1 to STk.

[0134] Fig. 9 It is shown Figure 7 0 is a timing diagram of the operation of the second test circuit board shown in .

[0135] Reference Figures 7 to 9 , the test circuit 610 outputs the test transmission signal to the test transmission signal pads TX1 to TXi. Fig. 9 Only the test transmission signal provided to the test transmission signal pad TX1 is illustrated, however, the test circuit 610 may sequentially or substantially simultaneously transmit the test transmission signals to the test transmission signal pads TX1 to TXi.

[0136] The test circuit 610 outputs the switch signals SW1 to SWk at the transition points of the test transmission signals output to the test transmission signal pad TX1. The test circuit 610 can control the output sequence and pulse width of the switch signals SW1 to SWk, and thus can change the voltage level of the sensing power supply voltage S_ELVSS in various ways.

[0137] For example, when the image displayed by the display unit 110 changes from a white image to a black image or vice versa, the amount of change in the consumption current of the display unit 110 may increase. When it is assumed that the image displayed by the display unit 110 changes from a white image to a black image, the voltage level of the second power pattern PP2 of the display unit 110 may become lower than a normal level (e.g., about -3 volts). When it is assumed that the image displayed by the display unit 110 changes from a black image to a white image, the voltage level of the second power pattern PP2 of the display unit 110 may become higher than a normal level (e.g., about -3 volts).

[0138] The test circuit 610 may output the switching signals SW1 to SWk by considering the change in voltage level so that the voltage level of the sensing power supply voltage S-ELVSS of the display unit 110 changes to a level lower or higher than a normal level (eg, about -3 volts).

[0139] In addition, the test circuit 610 may output switch signals SW1 to SWk so that the voltage level of the sensing power supply voltage S_ELVSS changes in an activation period in which a test transmission signal is output to the test transmission signal pad TX1 , thereby more accurately testing characteristics of the input sensing unit 120 .

[0140] Fig.10 1 is a flowchart illustrating a test method of a test device according to some example embodiments of the present disclosure. Figures 1 to 7 The test method is described with reference to the electronic panel 100 and the second test circuit board 500 shown in FIG. 1 , however, the test method according to the present disclosure is not limited thereto or thereby.

[0141] Reference Fig.10 , test circuit 610 (refer to Figure 7 ) outputs the test transmission signal to the test transmission signal pads TX1 to TXi (1010).

[0142] Voltage generator 620 (see Figure 7 ) generates a sensing power supply voltage S_ELVSS (1020).

[0143] Ripple controller 630 (refer to Figure 7 ) changes the ripple noise of the sensing power supply voltage S_ELVSS (1030). The sensing power supply voltage S_ELVSS is provided to the input sensing unit 120 via the power test pad PTP. The sensing power supply voltage S_ELVSS provided via the sensing pad PDP3 of the input sensing unit 120 is provided to the second power pattern PP2 of the display unit 110 via the second power line VSL.

[0144] The test circuit 610 receives the test reception signal from the test reception signal pads RX1 to RXj (1040).

[0145] According to the above test method, a test operation of characteristics and defects of the input sensing unit 120 can be performed while the sensing power supply voltage S_ELVSS is provided to the second power pattern PP2 of the display unit 110. For example, since ripple noise is included in the sensing power supply voltage S_ELVSS, the test accuracy of the input sensing unit 120 can be improved.

[0146] Although various aspects of some example embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these example embodiments, but rather that a person of ordinary skill in the art may make various changes and modifications within the spirit and scope of the present disclosure as claimed below. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined according to the appended claims and their equivalents.

Claims

1. A testing device, comprising: a plurality of signal test pads electrically connected to pads of an input sensing unit; a power supply test pad electrically connected to a power supply pattern of a display unit; a test circuit configured to apply a test signal to the signal test pad; a voltage generator configured to generate a sensing supply voltage; as well as A ripple controller is configured to change the voltage level of the sensing power supply voltage to apply the sensing power supply voltage to the power supply test pad, wherein the ripple controller applies the sensing power supply voltage including ripple noise to the power supply test pad so that the voltage level of the sensing power supply voltage is changed to a level lower or higher than a normal level.

2. The testing device according to claim 1, wherein: The ripple controller is configured to provide the ripple noise to the sensing supply voltage.

3. The testing device according to claim 1, wherein: The signal test pads include a test transmission signal pad and a test reception signal pad.

4. The testing device according to claim 3, wherein: The test circuit is configured to output a test transmission signal to the test transmission signal pad and receive a test reception signal from the test reception signal pad.

5. The testing device according to claim 4, wherein: The test circuit is further configured to output a switch signal in synchronization with the test transmission signal to select the voltage level of the sensing power supply voltage.

6. The testing device according to claim 1, wherein: The test circuit is also configured to output a switch signal to select the voltage level of the sense supply voltage.

7. The testing device according to claim 6, wherein: The ripple controller is configured to change the voltage level of the sensing supply voltage in response to the switching signal.

8. The testing device according to claim 6, wherein: The ripple controller includes a plurality of current controllers connected in parallel between a first node configured to receive the sense power supply voltage and a second node configured to receive a second voltage and operated in response to the switching signal.

9. The testing device according to claim 8, wherein: Each of the current controllers comprises: a resistor including one end connected to the first node and another end; and A transistor includes a first electrode connected to the other end of the resistor, a second electrode connected to the second node, and a gate electrode receiving a corresponding one of the switching signals.

10. An electronic panel comprising: a display unit, the display unit comprising a display area and a peripheral area adjacent to the display area; as well as an input sensing unit, the input sensing unit being located on the display unit and configured to sense an external input applied to a sensing area overlapping the display area, the display unit comprising: a power pad located in the peripheral region and configured to receive a power voltage; and a power pattern located in the peripheral region and electrically connected to the power pad, the input sensing unit comprising: a sensing pad located in a non-sensing area around the sensing area and configured to receive a sensing supply voltage; and A power line is located in the non-sensing area and is electrically connected to the sensing pad, wherein the power line is electrically connected to the power pattern, wherein during a test mode, the sensing power supply voltage includes ripple noise so that a voltage level of the sensing power supply voltage changes to a level lower or higher than a normal level.

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