Chip packaging structure
By designing a chip packaging structure including chips, tube bases, insulated brackets and caps, the problem of poor optical chip packaging is solved, and the chip is well packaged and stable in performance is achieved.
Patent Information
- Application Number
- CN201911421936.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2019-12-31
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2039-12-31
AI Technical Summary
The prior art is difficult to effectively package optical chips, especially because the special structure of the chip cannot be directly packaged, resulting in poor packaging that affects chip performance.
A chip packaging structure is designed, including chips, tube bases, insulated brackets and caps. There is a storage space in the insulating bracket, and the chip is installed in this space. A light-through hole is provided on the insulating bracket so that light rays illuminate to the photosensitive area. The conductive connector connects the chip electrode and the tube seat pin. The cap is installed on the tube seat to protect the packaging structure.
It realizes good packaging of optical chips, ensures stable performance of the chip, can effectively introduce external light and connect electrodes, solving the problem of poor chip packaging.
Smart Images

Figure CN111162130B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip technology, and in particular to a chip packaging structure. Background Art
[0002] An optical chip is a chip that converts optical signals into electrical signals and is used to detect weak photon signals. Based on application requirements and performance considerations, the chip design has a photosensitive area and a ring-shaped N electrode on one side of the chip, and a circular P electrode on the other side of the chip. During packaging, due to the special structure of the chip, the chip cannot be directly packaged in a conventional way. Summary of the invention
[0003] In order to solve the deficiencies of the prior art or at least partially solve the deficiencies of the prior art, an embodiment of the present invention provides a chip packaging structure, which can ensure good packaging of the chip.
[0004] An embodiment of the present invention provides a chip packaging structure, including:
[0005] A chip, wherein a first surface of the chip is provided with a first electrode and a photosensitive area, and a second surface of the chip is provided with a second electrode;
[0006] A tube holder, the tube holder being provided with a first pin for connecting to the first electrode and a second pin for connecting to the second electrode;
[0007] an insulating support, the insulating support being mounted on the tube holder, the insulating support being provided with a housing space, the chip being mounted in the housing space, a light-through hole being provided at one end of the insulating support away from the tube holder, the photosensitive area facing the light-through hole, so that light emitted from the light-through hole to the housing space is irradiated onto the photosensitive area, a first conductive connector and a second conductive connector being provided on the insulating support, the two ends of the first conductive connector and the second conductive connector respectively extending into the housing space and outside the insulating support, the two ends of the first conductive connector being respectively connected to the first electrode and the first pin, and the two ends of the second conductive connector being respectively connected to the second electrode and the second pin;
[0008] A sealing cap is installed on the tube seat and covers the outside of the insulating bracket. The sealing cap is provided with a light window corresponding to the light-through hole.
[0009] Optionally, the insulating support includes an upper wall located between the light window and the accommodating space, and the light through hole passes through the upper wall.
[0010] Optionally, the first surface of the chip is mounted on the upper wall, the first conductive connector and the second conductive connector are arranged through the upper wall, the first electrode is in contact with one end of the first conductive connector, and the second electrode is connected to one end of the second conductive connector through a wire.
[0011] Optionally, the other end of the first conductive connector is connected to the first pin via a wire, and the other end of the second conductive connector is connected to the second pin via a wire.
[0012] Optionally, the first conductive connector includes a first soldering pad and a first slurry portion, the first soldering pad is fixed on a side of the upper wall facing the accommodating space, the first soldering pad is in contact with the first electrode, the first slurry portion passes through the upper wall and is connected to the first soldering pad, the upper wall is provided with a first grouting hole for accommodating the first slurry portion, and the first slurry portion is formed by injecting conductive slurry into the first grouting hole.
[0013] Optionally, the second conductive connector includes a second conductive connector and a second slurry portion, the second soldering pad is fixed on a side of the upper wall facing the accommodating space, the second soldering pad is connected to the second electrode through a wire, the second slurry portion passes through the upper wall and is connected to the second soldering pad, a second grouting hole for accommodating the second slurry portion is provided on the upper wall, and the second slurry portion is formed by injecting conductive slurry into the second grouting hole.
[0014] Optionally, the insulating bracket further includes a lower wall arranged opposite to the upper wall and a transverse wall connecting the upper wall and the lower wall, the accommodating space is enclosed by the upper wall, the lower wall and the transverse wall, and the lower wall is fastened to the tube seat.
[0015] Optionally, glue is filled between the lower wall and the tube seat to fasten the lower wall and the tube seat.
[0016] Optionally, the cross-sections of the light window, the light through hole and the photosensitive area are circular, the light window, the light through hole and the photosensitive area are concentrically arranged, and the first electrode is annular, and the first electrode surrounds the periphery of the first electrode.
[0017] Optionally, the packaging structure is a TO packaging structure.
[0018] Beneficial effects of the present invention:
[0019] The chip packaging structure of the present invention fixes the chip through an insulating bracket, and external light is sequentially projected onto the photosensitive area through the light window and the light hole, the first electrode is connected to the first pin on the tube holder through the first conductive connector, and the second electrode is connected to the second pin on the tube holder through the second conductive connector. The chip packaging structure of the present invention realizes good chip packaging and ensures chip performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The advantages of the above and / or additional aspects of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0021] Figure 1 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present invention;
[0022] Figure 2 is a schematic structural diagram of a chip according to an embodiment of the present invention;
[0023] Figure 3 It is a schematic diagram of the back structure of the chip according to an embodiment of the present invention.
[0024] in Figures 1 to 3 The corresponding relationship between the reference numerals and the component names is as follows:
[0025] 1. Chip; 100. First surface; 101. Photosensitive area; 102. First electrode; 110. Second surface; 111. Second electrode; 2. Tube seat; 20. First pin; 21. Second pin; 3. Insulating bracket; 3000. Accommodating space; 3100. Upper wall; 3200. Horizontal wall; 3300. Lower wall; 30. Light hole; 31. First conductive connection; 310. First soldering pad; 311. First conductive paste portion; 32. Second conductive connection; 320. Second soldering pad; 321. Second conductive paste portion; 4. Sealing cap; 40. Light window. DETAILED DESCRIPTION
[0026] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.
[0027] Figure 1 A schematic diagram showing the structure of a chip packaging structure according to an embodiment of the present invention is shown. Figure 2 FIG. 1 is a schematic diagram showing the structure of a chip according to an embodiment of the present invention. Figure 3 The back structure diagram of the chip of the embodiment of the present invention is shown. Figures 1 to 3 , an embodiment of the present invention provides a chip packaging structure, including:
[0028] A chip 1, wherein a first surface 100 of the chip 1 is provided with a photosensitive region 101 and a first electrode 102, and a second surface 110 of the chip 1 is provided with a second electrode 111;
[0029] A tube socket 2, on which a first pin 20 for connecting to the first electrode 102 and a second pin 21 for connecting to the second electrode 111 are provided;
[0030] An insulating bracket 3, the insulating bracket 3 is used to fix the chip 1, the insulating bracket 3 is installed on the tube base 2, a containing space 3000 is provided in the insulating bracket 3, the chip 1 is installed in the containing space 3000, a light hole 30 is provided at one end of the insulating bracket 3 away from the tube base 2, the photosensitive area 101 of the chip 1 faces the light hole 30, so that the light emitted from the light hole 30 into the containing space 3000 hits the photosensitive area 101, and a first conductive connector 31 and a second conductive connector 32 are provided on the insulating bracket 3, one end of the first conductive connector 31 and the second conductive connector 32 extends to the containing space 3000, and the other end extends to the outside of the insulating bracket 3, wherein one end of the first conductive connector 31 is connected to the first electrode 102, the other end of the first conductive connector 31 is connected to the first pin 20, one end of the second conductive connector 32 is connected to the second electrode 111, and the other end of the second conductive connector 32 is connected to the second pin 21;
[0031] The sealing cap 4 is mounted on the tube base 2 and is covered outside the insulating bracket 3 . The sealing cap 4 is provided with a light window 40 corresponding to the light-through hole 30 .
[0032] After packaging, the chip 1 is fixed by the insulating bracket 3, and the external light is sequentially transmitted through the light window 40 and the light hole 30 to hit the photosensitive area 101. The first electrode 102 of the chip 1 located in the accommodating space 3000 is connected to the first pin 20 located on the tube seat 2 through the first conductive connector 31 and the second conductive connector 31, and the second electrode 111 of the chip 1 located in the accommodating space 3000 is connected to the second pin 21 located on the tube seat 2, thereby realizing the packaging of the chip.
[0033] In one embodiment, the insulating bracket 3 includes an upper wall 3100, which is located between the accommodating space 3000 and the light window 40, wherein the light hole 30 is arranged on the upper wall 3100, and the light hole 30 passes through the upper wall 3100 to connect the accommodating space 3000 with the light window 40 located on the upper part of the upper wall 3100.
[0034] In one embodiment, the first conductive connector 31 and the second conductive connector 32 are arranged on the upper wall 3100 of the insulating bracket 3, and the first conductive connector 31 and the second conductive connector 32 respectively pass through the upper wall 3100, wherein one end of the first conductive connector 31 is connected to the first electrode 102 of the chip 1, and the other end of the first conductive connector 31 is connected to the first pin 20 on the tube seat 2, one end of the second conductive connector 32 is connected to the second electrode 111 of the chip 1, and the other end of the second conductive connector 32 is connected to the second pin 21 on the tube seat 2.
[0035] In one embodiment, the first surface of the chip 1 faces the upper wall 3100, and the first surface of the chip 1 is mounted on the side of the upper wall 3100 facing the accommodating space 3000, wherein the photosensitive area 101 corresponds to the position of the light-through hole 30, the first electrode 102 corresponds to the position of the first conductive connector 31, and the first electrode 102 is in contact with the first conductive connector 31, and the second electrode 111 is connected to the second conductive connector 32 through a wire.
[0036] Optionally, the first conductive connector 31 includes a first pad 310 and a first conductive paste portion 311. The first pad 310 is disposed on the side of the upper wall 3100 facing the accommodating space 3000. The first pad 310 contacts the first electrode 101 of the chip 1. The first conductive paste portion 311 penetrates the upper wall 3100, one end of which is connected to the first pad 310, and the other end is connected to the first pin 20 on the socket 2 through a wire. In one embodiment, the first conductive paste portion 311 is formed by conductive paste injection, such as: a first injection hole for conductive paste injection is pre-opened on the upper wall 3100, and conductive paste is injected into the first injection hole to form the first conductive paste portion 311.
[0037] Optionally, the second conductive connector 32 is located on the extension line of the chip 1, so as to facilitate the connection between the second conductive connector 32 and the second electrode 111 on the second surface 110 of the chip 1. The second conductive connector 32 includes a second pad 320 and a second conductive paste portion 321. The second pad 320 is provided on the side of the upper wall 3100 facing the accommodating space 3000. The second pad 320 is connected to the second electrode 111 of the chip 2 through a wire. The second conductive paste portion 321 penetrates the upper wall 3100, one end of which is connected to the second pad 320, and the other end is connected to the second pin 21 on the tube seat 2 through a wire. In this embodiment, the second conductive paste portion 321 is formed by conductive paste grouting, and the forming process is: a second grouting hole for conductive paste grouting is opened in advance on the upper wall 3100, and conductive paste is grouted into the second grouting hole to form the second conductive paste portion 321.
[0038] In one embodiment of the present invention, the insulating support 3 also includes a horizontal wall 3200, which is located between the upper wall 3100 and the tube seat 2. The upper wall 3100, the horizontal wall 3200, and the tube seat 2 are mutually enclosed to form the accommodating space 3000, which is fastened to the insulating support 3 through the lower part of the horizontal wall 3200. Optionally, the lower part of the horizontal wall 3200 is glued to the insulating support 3.
[0039] Optionally, the transverse wall 3200 and the upper wall 3100 are integrally formed, and the material of the transverse wall 3200 and the upper wall 3100 is ceramic.
[0040] In an alternative embodiment of the present invention, the insulating support 3 further includes a transverse wall 3200 and a lower wall 3300, the lower wall 3300 is arranged opposite to the upper wall 3100, the transverse wall 3200 is arranged between the upper wall 3100 and the lower wall 3300, and is used to connect the upper wall 3100 with the lower wall 3300, the upper wall 3100, the transverse wall 3200 and the lower wall 3300 are mutually enclosed to form the accommodating space 3000, and the lower wall 3300 is fastened to the tube seat 2. Optionally, glue 3400 is filled between the lower wall 3300 and the tube seat 2, and the lower wall 3300 and the tube seat 2 are glued together by the glue.
[0041] Optionally, the upper wall 3100 , the transverse wall 3200 and the lower wall 3300 are integrally formed, and the material of the upper wall 3100 , the transverse wall 3200 and the lower wall 3300 is ceramic.
[0042] In one embodiment of the present invention, the cross-sections of the light window 40, the light hole 30 and the photosensitive area 101 are circular, and the light window 40, the light hole 30 and the photosensitive area 101 are concentrically arranged. In one embodiment, the cross-sectional diameters of the light window 40, the light hole 30 and the photosensitive area 101 are equal; the light window 40 is a lens with a collimating function to optimize the path of light and improve the utilization rate of light.
[0043] Optionally, the first electrode 101 is in a ring shape, and the first electrode 101 surrounds the periphery of the photosensitive region 101 .
[0044] Optionally, the second electrode 111 is disposed on the entire surface of the second surface 110 of the chip 1 .
[0045] In the embodiment of the present invention, the chip packaging structure adopts a TO packaging structure.
[0046] In the embodiment of the present invention, the first electrode 101 is an N electrode, the second electrode 111 is a P electrode, the first pin 20 is connected to the negative electrode of the external power supply, and the second pin 21 is connected to the positive electrode of the external power supply.
[0047] In the description of the present invention, it should be noted that the terms "upper", "lower", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0048] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the inside of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0049] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A chip packaging structure, characterized in that: include: A chip, wherein a first surface of the chip is provided with a first electrode and a photosensitive area, and a second surface of the chip is provided with a second electrode; A tube holder, the tube holder being provided with a first pin for connecting to the first electrode and a second pin for connecting to the second electrode; an insulating support, the insulating support being mounted on the tube holder, the insulating support being provided with a housing space, the chip being mounted in the housing space, a light-through hole being provided at one end of the insulating support away from the tube holder, the photosensitive area facing the light-through hole, so that light emitted from the light-through hole to the housing space is irradiated onto the photosensitive area, a first conductive connector and a second conductive connector being provided on the insulating support, the two ends of the first conductive connector and the second conductive connector respectively extending into the housing space and outside the insulating support, the two ends of the first conductive connector being respectively connected to the first electrode and the first pin, and the two ends of the second conductive connector being respectively connected to the second electrode and the second pin; A sealing cap, which is mounted on the tube seat and covers the outside of the insulating bracket, and is provided with a light window corresponding to the light-through hole; The insulating bracket includes an upper wall located between the light window and the accommodating space, and the light hole passes through the upper wall; the insulating bracket also includes a lower wall arranged opposite to the upper wall and a transverse wall connecting the upper wall and the lower wall, the accommodating space is enclosed by the upper wall, the lower wall and the transverse wall, and the lower wall is fastened to the tube seat; wherein, the first surface of the chip is mounted on the upper wall, the first conductive connector and the second conductive connector are arranged through the upper wall, the first electrode is in contact with one end of the first conductive connector, and the other end of the first conductive connector is connected to the first pin through a wire; the second electrode is connected to one end of the second conductive connector through a wire, and the other end of the second conductive connector is connected to the second pin through a wire.
2. The chip packaging structure according to claim 1, characterized in that: The first conductive connecting member includes a first soldering pad and a first slurry portion. The first soldering pad is fixed on a side of the upper wall facing the accommodating space. The first soldering pad contacts the first electrode. The first slurry portion passes through the upper wall and is connected to the first soldering pad. The upper wall is provided with a first grouting hole for accommodating the first slurry portion. The first slurry portion is formed by injecting conductive slurry into the first grouting hole.
3. The chip packaging structure according to claim 1, characterized in that: The second conductive connecting member includes a second soldering pad and a second slurry portion. The second soldering pad is fixed on a side of the upper wall facing the accommodating space. The second soldering pad is connected to the second electrode through a wire. The second slurry portion passes through the upper wall and is connected to the second soldering pad. A second grouting hole for accommodating the second slurry portion is provided on the upper wall. The second slurry portion is formed by injecting conductive slurry into the second grouting hole.
4. The chip packaging structure according to claim 1, characterized in that: Glue is filled between the lower wall and the tube seat to fasten the lower wall and the tube seat.
5. The chip packaging structure according to claim 1, characterized in that: The cross-sections of the light window, the light through hole and the photosensitive area are circular, the light window, the light through hole and the photosensitive area are concentrically arranged, and the first electrode is annular, and the first electrode surrounds the periphery of the photosensitive area.
6. The chip packaging structure according to claim 1, characterized in that: The packaging structure is a TO packaging structure.
Citation Information
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