Amplifier, tail current stabilization method, input receiver, and chip

Abstract

The present invention provides an amplifier, a tail current stabilization method, an input receiver, and a chip. The amplifier includes a first transistor, a second transistor, and a temperature control unit. The gate of the first transistor is connected to a bias voltage. One end of the first transistor is connected to the source of the input pair transistor, and the other end is grounded. The first transistor is used to generate a first tail current. One end of the second transistor is connected between the connection line of the source of the first transistor and the input pair transistor, and the other end of the second transistor is grounded. The second transistor is used to generate a second tail current. The temperature control unit is connected to the gate of the second transistor. The temperature control unit is used to adjust the voltage applied to the gate of the second transistor according to the detected temperature of the first transistor, so that the sum of the first tail current and the second tail current remains a constant value. By adjusting the second tail current, the present invention maintains the stability of the overall tail current, thereby weakening or eliminating the influence of the temperature of the first transistor on the tail current, and stabilizing the working state of the amplifier circuit at the required performance.

Description

Technical Field

[0001] The present invention relates to semiconductor memories, and particularly to an amplifier, a tail current stabilization method, an input receiver, and a chip. Background Art

[0002] In an input receiver of a dynamic random access memory (DRAM), a smaller input signal is amplified into a rail-to-rail full swing signal through two-stage input buffers so that the internal circuit can work properly. The two-stage input buffers are amplifiers with different structures.

[0003] However, since the current of the MOS transistor is affected by temperature changes, the tail current of the amplifier will change with temperature changes, resulting in a difference between the static operating voltage of the amplifier and the expected value, thereby affecting the performance of the amplifier and causing a certain error between the performance of the input receiver and the expected value. Summary of the Invention

[0004] The present invention provides an amplifier, a tail current stabilization method, an input receiver, and a chip to alleviate or solve at least one technical problem in the prior art.

[0005] In a first aspect, an embodiment of the present invention provides an amplifier, including:

[0006] A first transistor, the gate of the first transistor is connected to a bias voltage (EN), one end of the first transistor is connected to the source (U) of an input pair transistor, the other end of the first transistor is grounded (GND), and the first transistor is used to generate a first tail current;

[0007] A second transistor, one end of the second transistor is connected between the source connection line of the first transistor and the input pair transistor, the other end of the second transistor is grounded, and the second transistor is used to generate a second tail current;

[0008] A temperature control unit, the temperature control unit is connected to the gate of the second transistor, and the temperature control unit is used to adjust the voltage applied to the gate of the second transistor according to the temperature of the first transistor detected by a temperature sensor, so that the sum of the first tail current and the second tail current remains a constant value.

[0009] In an implementation manner, it further includes a differential unit, and the differential unit includes:

[0010] A first resistor, one end of the first resistor is connected to a power supply voltage (VCC);

[0011] A second resistor, one end of the second resistor is connected to a power supply voltage;

[0012] A third transistor, the drain of the third transistor is connected to the other end of the first resistor, and the gate of the third transistor is connected to an input voltage;

[0013] A fourth transistor, the drain of the fourth transistor is connected to the other end of the second resistor, the gate of the fourth transistor is connected to a reference voltage (Vref), and the connection point of the source of the third transistor and the source of the fourth transistor serves as the source of the input pair transistor and is connected to the drain of the first transistor;

[0014] A first amplification output terminal, the first amplification output terminal is arranged on the connection line between the first resistor and the third transistor;

[0015] A second amplification output terminal, the second amplification output terminal is arranged on the connection line between the second resistor and the fourth transistor.

[0016] In one embodiment, it further includes an operational amplification unit, and the operational amplification unit includes:

[0017] A fifth transistor, the gate of the fifth transistor is connected to the first amplification output terminal;

[0018] A sixth transistor, the gate of the sixth transistor is connected to the second amplification output terminal, and the connection point of the source of the fifth transistor and the source of the sixth transistor serves as the source of the input pair transistor and is connected to the drain of the first transistor;

[0019] A seventh transistor, the source of the seventh transistor is connected to the power supply voltage, and the drain of the seventh transistor is connected to the drain of the fifth transistor;

[0020] An eighth transistor, the source of the eighth transistor is connected to the power supply voltage, the drain of the eighth transistor is connected to the drain of the sixth transistor, the gate of the eighth transistor is connected to the gate of the seventh transistor, and the gate of the eighth transistor is short-circuited to the drain;

[0021] A third amplification output terminal, the third amplification output terminal is arranged on the connection line between the fifth transistor and the seventh transistor.

[0022] In one embodiment, the first transistor is an NMOS transistor, the drain of the first transistor is connected to the source of the input pair transistor, and the source of the first transistor is grounded.

[0023] In one embodiment, the second transistor is an NMOS transistor. The drain of the second transistor is connected between the drain of the first transistor and the source connection line of the input pair transistors, and the source of the second transistor is grounded.

[0024] In a second aspect, an embodiment of the present invention provides a method for stabilizing the tail current of an amplifier, including:

[0025] Detecting the temperature of the first transistor;

[0026] When there is a temperature change in the first transistor, adjusting the voltage applied to the gate of the second transistor according to the temperature change, so that the sum of the second tail current and the first tail current remains a constant value.

[0027] In one embodiment, the method of adjusting the voltage applied to the gate of the second transistor according to the temperature change when there is a temperature change in the first transistor includes:

[0028] When the temperature change causes the first tail current of the first transistor to increase, reducing the voltage applied to the gate of the second transistor to reduce the second tail current generated by the second transistor;

[0029] When the temperature change causes the first tail current of the first transistor to decrease, increasing the voltage applied to the gate of the second transistor to increase the second tail current generated by the second transistor.

[0030] To achieve the above object, in a third aspect of this embodiment, an input receiver is provided, including the amplifier as described in any one of the above embodiments.

[0031] To achieve the above object, in a fourth aspect of this embodiment, an input receiver is provided, including an output buffer with two stages. The output buffer with two stages is composed of the above two amplifiers with different structures. Among them, the first amplified output terminal is connected to the gate of the fifth transistor, and the second amplified output terminal is connected to the gate of the sixth transistor;

[0032] The amplifier further includes:

[0033] A bias transistor, one end of the bias transistor is respectively connected to the source of the third transistor, the source of the fourth transistor and the drain of the second transistor, the other end of the bias transistor is connected to the drain of the first transistor, and the gate of the bias transistor is applied with a bias voltage.

[0034] To achieve the above object, in a fifth aspect of this embodiment, a chip is provided, and the chip includes the input receiver as described above.

[0035] The present invention weakens or eliminates the influence of the temperature of the first transistor on the tail current by generating and regulating the second tail current, thereby maintaining the stability of the overall tail current, making the operating state of the amplifier circuit stable at the desired performance, and weakening or eliminating the change of the output of the input receiver with temperature.

[0036] The above summary is only for the purpose of the specification and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will become apparent by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In the drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in accordance with the present invention and should not be regarded as limiting the scope of the present invention.

[0038] Figure 1 Circuit diagram of the amplifier in the embodiment of the present invention

[0039] Figure 2 Circuit diagram of the differential unit in the amplifier in the embodiment of the present invention;

[0040] Figure 3 Circuit diagram of the operational amplifier unit in the amplifier in the embodiment of the present invention;

[0041] Figure 4 Another circuit diagram of the amplifier in the embodiment of the present invention;

[0042] Figure 5 Flowchart of the method for stabilizing the tail current of the amplifier in the embodiment of the present invention;

[0043] Figure 6 Another flowchart of the method for stabilizing the tail current of the amplifier in the embodiment of the present invention;

[0044] Reference Numerals:

[0045] 100 First transistor;

[0046] 210 Second transistor;

[0047] 220 Temperature control unit;

[0048] 230 Temperature sensor;

[0049] 300 Differential unit;

[0050] 310 First resistor;

[0051] 320 Second resistor;

[0052] 330 The third transistor;

[0053] 340 The fourth transistor;

[0054] 350 The first amplified output terminal;

[0055] 360 The second amplified output terminal;

[0056] 400 The operational amplifier unit;

[0057] 410 The fifth transistor;

[0058] 420 The sixth transistor;

[0059] 430 The seventh transistor;

[0060] 440 The eighth transistor;

[0061] 450 The third amplified output terminal;

[0062] 500 The bias transistor. Detailed implementation manners

[0063] In the following, only some exemplary embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present invention. Therefore, the drawings and the description are considered to be exemplary in nature rather than restrictive.

[0064] In the first aspect of this embodiment, an amplifier is provided.

[0065] See Figure 1 As shown, the amplifier includes: a first transistor 100, a second transistor 210, and a temperature control unit 220.

[0066] The gate of the first transistor 100 is connected to a bias voltage. One end of the first transistor 100 is connected to the source of the input pair transistor, and the other end of the first transistor 100 is grounded. The first transistor 100 is used to generate a first tail current. The first transistor 100 has a characteristic that varies with temperature, and the generated first tail current will change with the change of temperature.

[0067] One end of the second transistor 210 is connected between the connection line of the first transistor 100 and the source of the input pair transistor, and the other end of the second transistor 210 is grounded. The second transistor 210 is used to generate a second tail current.

[0068] The temperature control unit 220 is connected to the gate of the second transistor 210. The temperature control unit 220 is configured to adjust the voltage applied to the gate of the second transistor 210 according to the temperature of the first transistor 100 detected by the temperature sensor 230, so that the sum of the first tail current and the second tail current remains constant. The temperature sensor 230 is an existing internal unit, which can reduce the area of the amplifier. For example, when the amplifier is applied to a semiconductor memory, the temperature sensor 230 can be a unit inside the semiconductor memory for controlling the self-refresh frequency. Herein, the constant value includes but is not limited to the set operating current range or an accurate numerical value. For example, a constant value within an error range is allowed.

[0069] In this way, when the temperature of the first transistor 100 changes, the temperature control unit 220 generates an adjustment based on the temperature change and adjusts the voltage applied to the gate of the second transistor 210 to generate a second tail current. Thus, when the first tail current changes, the overall tail current of the amplifier (the sum of the first tail current and the second tail current) can be maintained stable, thereby ensuring the stability of the amplifier performance.

[0070] Further, the first transistor 100 is an NMOS transistor. The drain of the first transistor 100 is connected to the source of the input pair transistor, and the source of the first transistor 100 is grounded.

[0071] Further, the second transistor 210 is an NMOS transistor. The drain of the second transistor 210 is connected between the drain of the first transistor 100 and the source of the input pair transistor, and the source of the second transistor 210 is grounded.

[0072] In this embodiment, when the first transistor 100 is affected by temperature changes, by adjusting the conduction voltage applied to the gate of the second transistor 210, it is ensured that the sum of the second tail current generated by the second transistor 210 and the first tail current remains constant, so that the tail current of the amplifier is not affected by temperature, and the low-end drive of the NMOS transistor is adopted to ensure the power of the amplifier.

[0073] In one embodiment, as shown in Figure 2 the amplifier further includes a differential unit 300.

[0074] The differential unit 300 includes: a first resistor 310, a second resistor 320, a third transistor 330, a fourth transistor 340, a first amplified output terminal 350, and a second amplified output terminal 360.

[0075] One end of the first resistor 310 is connected to the power supply voltage. One end of the second resistor 320 is connected to the power supply voltage. The drain of the third transistor 330 is connected to the other end of the first resistor 310, and the gate of the third transistor 330 is connected to the input voltage. The drain of the fourth transistor 340 is connected to the other end of the second resistor 320, the gate of the fourth transistor 340 is connected to the reference voltage, and the connection point of the sources of the third transistor 330 and the fourth transistor 340 serves as the source of the input pair transistors and is connected to the drain of the first transistor 100. The first amplified output terminal 350 is disposed on the connection line between the first resistor 310 and the third transistor 330. The second amplified output terminal 360 is disposed on the connection line between the second resistor 320 and the fourth transistor 340.

[0076] In one embodiment, referring to Figure 3 as shown, the amplifier further includes an operational amplifier unit 400.

[0077] The operational amplifier unit 400 includes: a fifth transistor 410, a sixth transistor 420, a seventh transistor 430, an eighth transistor 440, and a third amplified output terminal 450.

[0078] Referring to Figure 4 as shown, the gate of the fifth transistor 410 is connected to the first amplified output terminal 350. The gate of the sixth transistor 420 is connected to the second amplified output terminal 360, and the connection point of the sources of the fifth transistor 410 and the sixth transistor 420 serves as the source of the input pair transistors and is connected to the drain of another first transistor 100. The source of the seventh transistor 430 is connected to the power supply voltage, and the drain of the seventh transistor 430 is connected to the drain of the fifth transistor 410. The source of the eighth transistor 440 is connected to the power supply voltage, the drain of the eighth transistor 440 is connected to the drain of the sixth transistor 420, the gate of the eighth transistor 440 is connected to the gate of the seventh transistor 430, and the gate and the drain of the eighth transistor 440 are short-circuited. The third amplified output terminal 450 is disposed on the connection line between the fifth transistor 410 and the seventh transistor 430.

[0079] Both of the two different amplifier circuit structures in this embodiment maintain the stability of the overall tail current by generating and regulating the second tail current, thereby weakening or eliminating the influence of the temperature of the first transistor 100 on the tail current, and making the working state of the amplifier circuit stable at the required performance.

[0080] The second aspect of this embodiment provides a method for stabilizing the tail current of an amplifier.

[0081] See Figure 5 as shown, the method for stabilizing the tail current of an amplifier includes:

[0082] Step S110: Detect the temperature of the first transistor 100.

[0083] Step S120: When there is a temperature change in the first transistor 100, according to the temperature change, adjust the voltage applied to the gate of the second transistor 210 so that the sum of the second tail current and the first tail current remains a constant value.

[0084] The sum of the second tail current and the first tail current is the overall tail current of the amplifier. In this way, when the first tail current changes with temperature, the second tail current is controlled by the temperature control unit 220 so that the sum of the first tail current and the second tail current remains stable. Then, the overall tail current of the amplifier is a constant value, ensuring the stability of the amplifier performance.

[0085] Further, as shown in Figure 6 The method of adjusting the voltage applied to the gate of the second transistor 210 according to the temperature change when there is a temperature change in the first transistor 100 in step S120 includes:

[0086] Step S121: When the temperature change causes the first tail current of the first transistor 100 to increase, reduce the voltage applied to the gate of the second transistor 210 to reduce the second tail current generated by the second transistor 210.

[0087] Step S122: When the temperature change causes the first tail current of the first transistor 100 to decrease, increase the voltage applied to the gate of the second transistor 210 to increase the second tail current generated by the second transistor 210.

[0088] In this embodiment, by inversely adjusting the gate voltage applied to the second transistor 210 with temperature change, the magnitude of the second tail current is controlled, maintaining the sum of the first tail current and the second tail current as a constant value. Furthermore, the overall tail current of the amplifier is a constant value, ensuring the stability of the amplifier performance and being unaffected by temperature.

[0089] In the third aspect of this embodiment, an input receiver is provided.

[0090] The input receiver includes the amplifier in any of the above embodiments.

[0091] The input receiver in this embodiment includes the above amplifier. The amplifier maintains the stability of the overall tail current by generating and adjusting the second tail current, thereby weakening or eliminating the influence of the temperature of the first transistor 100 on the tail current, stabilizing the operating state of the amplifier circuit at the required performance, weakening or eliminating the change of the output of the input receiver with temperature. When the amplifier operates stably, the operating state of the input receiver is stabilized at the required performance and is not affected by temperature.

[0092] In the fourth aspect of this embodiment, an input receiver is provided. As shown in Figure 4As shown, the input receiver includes an output buffer with two stages, and the output buffer of the two stages is respectively composed of amplifiers with two different structures in the above embodiments. Among them, the first amplified output terminal 350 is connected to the gate of the fifth transistor 410, and the second amplified output terminal 360 is connected to the gate of the sixth transistor 420.

[0093] Furthermore, the amplifier further includes a bias transistor 500.

[0094] One end of the bias transistor 500 is respectively connected to the source of the third transistor 330, the source of the fourth transistor 340, and the drain of the second transistor 210. The other end of the bias transistor 500 is connected to one end of the first transistor 100, and the gate of the bias transistor 500 is connected to a bias voltage.

[0095] In this embodiment, the input receiver amplifies a smaller input signal into a rail-to-rail full swing signal through two-stage amplifiers, enabling the internal circuit to work properly. The working state of the amplifier circuit is stable at the required performance, ensuring that the performance of the input receiver is not affected by temperature.

[0096] The fifth aspect of this embodiment provides a chip. The chip includes the input receiver in the above embodiment.

[0097] The input receiver in the chip of this embodiment is not affected by temperature in terms of performance, thereby improving the performance of the chip.

[0098] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various changes or substitutions, and these should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

[0099] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0100] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0101] In the present invention, unless otherwise clearly defined and limited, the terms such as "mounted", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or a communication connection; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0102] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature.

[0103] The above disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, the components and settings of specific examples are described above. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and / or the use of other materials.

Claims

1. An amplifier, characterized in that, it comprises: a first transistor, the gate of the first transistor is connected to a bias voltage, one end of the first transistor is connected to the source of the input pair transistor, the other end of the first transistor is grounded, the first transistor is used to generate a first tail current, and the first tail current generated by the first transistor will change with the change of temperature; a second transistor, one end of the second transistor is connected between the connection line of the first transistor and the source of the input pair transistor, the other end of the second transistor is grounded, and the second transistor is used to generate a second tail current; a temperature control unit, the temperature control unit is connected to the gate of the second transistor, and the temperature control unit is used to adjust the voltage applied to the gate of the second transistor according to the temperature of the first transistor detected by the temperature sensor, so that the sum of the first tail current and the second tail current remains a constant value; wherein, the input pair transistor includes a first-stage input pair transistor and a second-stage input pair transistor, both the first-stage input pair transistor and the second-stage input pair transistor have their respective corresponding first transistors and second transistors, a bias transistor is connected in series between the source of the first-stage input pair transistor and the corresponding first transistor, the drain of the bias transistor is connected to the drain of the second transistor, and the gate of the bias transistor is connected to a bias voltage; no bias transistor is provided between the second-stage input pair transistor and the corresponding first transistor.

2. The amplifier according to claim 1, characterized in that, it further comprises a differential unit, and the differential unit includes: a first resistor, one end of the first resistor is connected to the power supply voltage; a second resistor, one end of the second resistor is connected to the power supply voltage; a third transistor, the drain of the third transistor is connected to the other end of the first resistor, and the gate of the third transistor is connected to the input voltage; a fourth transistor, the drain of the fourth transistor is connected to the other end of the second resistor, the gate of the fourth transistor is connected to the reference voltage, and the connection point of the source of the third transistor and the source of the fourth transistor is used as the source of the input pair transistor and is connected to the drain of the first transistor; a first amplified output terminal, the first amplified output terminal is arranged on the connection line between the first resistor and the third transistor; a second amplified output terminal, the second amplified output terminal is arranged on the connection line between the second resistor and the fourth transistor.

3. The amplifier according to claim 2, characterized in that, it further comprises an operational amplifier unit, and the operational amplifier unit includes: a fifth transistor, the gate of the fifth transistor is connected to the first amplified output terminal; a sixth transistor, the gate of the sixth transistor is connected to the second amplified output terminal, and the connection point of the source of the fifth transistor and the source of the sixth transistor is used as the source of the input pair transistor and is connected to the drain of the first transistor; a seventh transistor, the source of the seventh transistor is connected to the power supply voltage, and the drain of the seventh transistor is connected to the drain of the fifth transistor; The eighth transistor, the source of the eighth transistor is connected to the power supply voltage, the drain of the eighth transistor is connected to the drain of the sixth transistor, the gate of the eighth transistor is connected to the gate of the seventh transistor, and the gate and the drain of the eighth transistor are short-circuited; The third amplified output terminal is disposed on the connection line between the fifth transistor and the seventh transistor.

4. The amplifier according to any one of claims 1-3, characterized in that the first transistor is an NMOS transistor, the drain of the first transistor is connected to the source of the input pair transistor, and the source of the first transistor is grounded.

5. The amplifier according to claim 4, characterized in that the second transistor is an NMOS transistor, the drain of the second transistor is connected between the drain of the first transistor and the connection line of the source of the input pair transistor, and the source of the second transistor is grounded.

6. An input receiver, characterized in that it includes the amplifier according to any one of claims 1-5.

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