High PSRR Reference Circuit

Abstract

The high power supply rejection ratio reference circuit has a simple and reasonable structural design, which can reduce power consumption and investment cost. The circuit comprises a startup circuit module, a bandgap reference circuit module, and a pre-regulation circuit module. The input end of the pre-regulation circuit module is connected to a voltage source VDD. The pre-regulation circuit module is used to form an internal stable voltage, generate a pre-regulated voltage source Vreg, and supply power to the bandgap reference circuit module. The startup circuit module is respectively connected to the bandgap reference circuit module and the pre-regulation circuit module. The bandgap reference circuit module adopts a current mode structure of a self-biased current mirror.

Description

Technical Field

[0001] The invention relates to the technical field of power supply, and in particular to a high power supply rejection ratio reference circuit. Background Art

[0002] In recent years, with the widespread application of portable electronic products and wireless communication systems, higher requirements have been put forward for the stability of the power supply voltage within a certain range. In particular, with the increasing complexity and perfection of circuit integration, circuit structure and function, higher requirements have been put forward for the circuit design of low-voltage, low-power, low-temperature coefficient and high power supply rejection ratio (PSRR) bandgap reference source. The bias current of the traditional bandgap reference circuit is generated by an additional bias circuit, and in order to enhance the power supply rejection ratio, an additional enhancement circuit needs to be added to the reference circuit. The use of additional bias circuits and enhancement circuits not only increases the structural complexity of the entire power supply, but also easily generates additional power consumption, making the investment cost higher. Therefore, it is an urgent problem to invent a high-performance bandgap reference circuit with a simple circuit structure, low power consumption, low cost, low temperature coefficient and high power supply rejection ratio. At the same time, the reference circuit also needs to be compatible with the standard CMOS process. Summary of the invention

[0003] In view of the problems of complex structure, high power consumption and high investment cost of the reference circuit in the prior art, the present invention provides a high power supply rejection ratio reference circuit, which has a simple and reasonable structural design, can reduce power consumption and investment cost, and can greatly improve the power supply rejection ratio.

[0004] A high power supply rejection ratio reference circuit comprises a startup circuit module and a bandgap reference circuit module, and is characterized in that it also comprises a pre-regulation circuit module, wherein the input end of the pre-regulation circuit module is connected to a voltage source VDD, the pre-regulation circuit module is used to form an internal stable voltage, generate a pre-regulated voltage source Vreg, and supply power to the bandgap reference circuit module, the startup circuit module is respectively connected to the bandgap reference circuit module and the pre-regulation circuit module, and the bandgap reference circuit module adopts a current mode structure of a self-biased current mirror.

[0005] It is further characterized in that the startup circuit includes a MOS tube MS1, the source of the MOS tube MS1 is respectively connected to the source of the MOS tube MS2, the source of the MOS tubes MP1, MP2, MP3, MP4, MP5, MP6, the drain of the MOS tubes MP7, MN10, and one end of the capacitor Cc, the drain of the MOS tube MS1 is respectively connected to the gate of the MOS tube MS2 and one end of the capacitor Cs, and the drain of the MOS tube MS2 is respectively connected to the drain and gate of the MOS tubes MP1 and MN1, and the gate of the MOS tubes MN2, MN6, and MP6;

[0006] The bandgap reference circuit module includes the MOS tubes MP1, MP2, MP3, MP4, MN1, MN2, MN3, MN4, MN5, MN6, and MN7. The gate of the MOS tube MP1 is respectively connected to the gate and drain of the MOS tube MP2, the drains of the MOS tubes MN2 and MN6, the gate of the MOS tube MP3, the gate of the MOS tube MP4, and the gate of the MOS tube MP5. The source of the MOS tube MN1 is connected to the emitter of the triode QB1. The source of the MOS tube MN2 is connected to one end of the resistor R1. The resistor R 1, the other end is connected to the emitter of the transistor QB2, the source of the MOS transistor MN6 is respectively connected to the drains of the MOS transistors MN3 and MN4, the source of the MOS transistor MN3 is connected to one end of the resistor R2, the source of the MOS transistor MN4 is respectively connected to the emitter of the transistor QB3 and the source of the MOS transistor MN5, the base of the MOS transistor MN5 is respectively connected to the drain of the MOS transistor MN5, the gate of the MOS transistor MN7, and the drain of the MOS transistor MP3, and the source of the MOS transistor MN7 is respectively connected to one end of the capacitor C1, one end of the resistor R5, and the drain of the MOS transistor MP4;

[0007] The pre-regulation circuit module includes the MOS transistors MP5, MP6, MP7, and MP8. The drain of the MOS transistor MP5 is respectively connected to the drain and gate of the MOS transistor MN8, the gate of MN9, and the gate of the MOS transistor MN11. The drain of the MOS transistor MP6 is respectively connected to the other end of the capacitor Cc, the gate of the MOS transistor MN10, and the drain of the MOS transistor MN9. The drain of the MOS transistor MN11 is respectively connected to the gate of the MOS transistor MP7, the gate and the drain of the MOS transistor MP8. The source of the MOS transistor MP7 and the source of MP8 are connected to the voltage source VDD. The source of the MOS transistor MN11, the source of the MOS transistors MN8 and MN9, the other end of the resistor R5, the other end of the capacitor C1, the base and collector of the transistor QB3, the other end of the resistor R2, the base and collector of the transistor QB2, the base and collector of the transistor QB1, the other end of the capacitor Cs, and the gate of the MOS transistor MS1 are connected and grounded.

[0008] The above structure of the present invention can achieve the following beneficial effects: the voltage source VDD does not directly supply power to the voltage reference core, but is connected to the pre-regulation circuit module, and a stable voltage regulator Vreg is formed through the pre-regulation circuit module, and the bandgap reference circuit module is powered by the regulator Vreg. This power supply method is equivalent to adding a first-level regulator Vreg between the output reference voltage and the input voltage source VDD. The regulator Vreg generated by the pre-regulation circuit module also has a certain degree of suppression capability for power supply ripple. Therefore, the power supply voltage is first suppressed before reaching the bandgap reference circuit module, and is finally applied to the LDO system. The overall power supply suppression performance of the system is the product of the power supply suppression ratio of the pre-regulator and the power supply suppression ratio of the introduced error amplifier negative feedback loop, so that the power supply suppression ratio of the system can be greatly improved. It can be seen that the bandgap reference circuit module adopts a current mode structure of a self-biased current mirror through a voltage regulator power supply, and it does not need to use an additional bias circuit and an enhancement circuit to achieve the effect of enhancing the power supply suppression ratio. The reduction of additional bias circuits and enhancement circuits makes the structure of the entire circuit device simple, while reducing the circuit power consumption and the circuit complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a circuit structure block diagram of the present invention;

[0010] Figure 2 is a circuit schematic diagram of the present invention;

[0011] Figure 3 It is the power supply rejection ratio simulation curve of the present invention. DETAILED DESCRIPTION

[0012] See Figure 1 A high power supply rejection ratio reference circuit includes a startup circuit module 1, a bandgap reference circuit module 2, and a pre-regulation circuit module 3. The input end of the pre-regulation circuit module 3 is connected to a voltage source VDD. The pre-regulation circuit module 3 is used to form an internal stable voltage, generate a pre-regulated voltage source Vreg, and supply power to the bandgap reference circuit module 2. The startup circuit module 1 is connected to the bandgap reference circuit module 2 and the pre-regulation circuit module 3 respectively. When the startup circuit module 1 starts working, it stretches the reference voltage source so that the self-biased amplifier circuit works normally. The bandgap reference circuit module 2 adopts a current mode structure based on a self-biased current mirror.

[0013] See Figure 2The start-up circuit 1 includes a MOS tube MS1, the source of the MOS tube MS1 is respectively connected to the source of the MOS tube MS2, the source of the MOS tubes MP1, MP2, MP3, MP4, MP5, MP6, the drain of the MOS tubes MP7, MN10, and one end of the capacitor Cc, the drain of the MOS tube MS1 is respectively connected to the gate of the MOS tube MS2 and one end of the capacitor Cs, and the drain of the MOS tube MS2 is respectively connected to the drain and gate of the MOS tubes MP1 and MN1, and the gate of the MOS tubes MN2, MN6, and MP6;

[0014] The bandgap reference circuit module 2 includes MOS tubes MP1, MP2, MP3, MP4, MN1, MN2, MN3, MN4, MN5, MN6, and MN7. The gate of MOS tube MP1 is respectively connected to the gate and drain of MOS tube MP2, the drains of MOS tubes MN2 and MN6, the gate of MOS tube MP3, the gate of MOS tube MP4, and the gate of MOS tube MP5. The source of MOS tube MN1 is connected to the emitter of triode QB1. The source of MOS tube MN2 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the emitter of triode QB2. The source of MOS tube MN6 is respectively connected to the drains of MOS tubes MN3 and MN4. The source of MOS tube MN3 is connected to one end of resistor R2. The source of MOS tube MN4 is respectively connected to the emitter of triode QB3 and the source of MOS tube MN5. The base of MOS tube MN5 is respectively connected to the drain of MOS tube MN5, the gate of MOS tube MN7, and the drain of MOS tube MP3. The source of MOS tube MN7 is respectively connected to one end of capacitor C1, one end of resistor R5, and the drain of MOS tube MP4.

[0015] The pre-regulation circuit module 3 includes MOS transistors MP5, MP6, MP7, and MP8. The drain of MOS transistor MP5 is respectively connected to the drain and gate of MOS transistor MN8, the gate of MN9, and the gate of MOS transistor MN11. The drain of MOS transistor MP6 is respectively connected to the other end of capacitor Cc, the gate of MOS transistor MN10, and the drain of MOS transistor MN9. The drain of MOS transistor MN11 is respectively connected to the gate of MOS transistor MP7, the gate and drain of MP8. The source of MOS transistor MP7 and the source of MP8 are connected to the voltage source VDD. The source of MOS transistor MN11, the source of MOS transistor MN8 and MN9, the other end of resistor R5, the other end of capacitor C1, the base and collector of transistor QB3, the other end of resistor R2, the base and collector of transistor QB2, the base and collector of transistor QB1, the other end of capacitor Cs, and the gate of MOS transistor MS1 are connected.

[0016] Figure 2In the embodiment, the MOS tubes MS1, MS2 and capacitor Cs in the startup circuit 1 force the injection of current into the self-bias circuit composed of the MOS tubes MN1, MN2, MP1 and MP2 in the bandgap reference circuit module 2. After the voltage source VDD is powered on, the gate of the MOS tube MS1 is grounded, and the MOS tube MS1 is in the on state, gradually charging the capacitor Cs. In the initial state, there is no charge on the capacitor Cs, the MOS tube MS2 is turned on, and the startup current flows from the MOS tube MS2 into the self-bias circuit, so that it gets rid of the zero point state and enters the normal working point; as the MOS tube MS1 charges the capacitor Cs, the voltage on the capacitor Cs increases, that is, the gate voltage of the MOS tube MS2 gradually rises, and when it is close to the voltage regulator source Vreg, the MOS tube MS2 is turned off. After the circuit works normally, the startup circuit no longer works and no longer consumes any static power consumption, so it can play a role in reducing power consumption;

[0017] The self-biased current mirror composed of MOS tubes MN1, MN2, MP1 and MP2 in the bandgap reference circuit module 2 works together with transistors QB1, QB2 and resistor R1 to generate a current I PTAT MOS tubes MN3, MN4, MN6, transistor QB3 and resistor R2 are used to generate current I CTAT The two currents I PTAT ,I CTAT The MOS tube MP2 is combined and mirrored to the MOS tube MP4 branch, and converted to generate a reference voltage Vref ( Figure 2 The voltage at the source of MOS tube MN7, drain of MP4, and resistor connection point in the middle); and the current mirrored to the MOS tube MP3 branch provides gate bias voltage to MOS tubes MN3 and MN4 respectively through voltage conversion of MOS tube MN5, and at the same time, triode QB3 obtains part of the bias current. MOS tube MN7 plays a role of fine-tuning of negative feedback: when the current of MOS tube MP4 branch increases, the corresponding potential of the source terminal of MOS tube MN7 is increased, so that the current flowing into the load resistor of MOS tube MN7 decreases; on the contrary, if the current of MP4 branch decreases, the source terminal potential of MOS tube MN7 decreases, and the current of its branch increases. Since the change of output voltage has a greater impact on the change of current in MOS tube MN7, the current of MOS tube MN7 can only account for a very small proportion of the total output current, that is, it plays a small negative feedback regulation role to maintain the stability of the output. The voltage pre-regulation circuit is composed of MOS tubes MP5, MP6, MP7, MP8, MN8, MN9, MN10, MN11 and capacitor Cc on the right. Figure 2There is a low-resistance AC path from node D to ground, so the influence of power supply noise on node D is effectively suppressed. The reference core circuit is powered through node D, so the noise superimposed on the reference voltage by the power supply is suppressed even lower. The circuit can provide a reference voltage for other module circuits in the system that is independent of power supply voltage, temperature, and process, which has an important impact on the static and noise performance of the system.

[0018] Where: Reference voltage generation principle:

[0019] The current-mode voltage reference is a weighted addition of two voltages with opposite temperature coefficients. By adding two currents with opposite temperature coefficients, a current with a zero temperature coefficient is obtained, which is then converted into a voltage on a resistor. Finally, a reference voltage of different values ​​is output according to the circuit requirements.

[0020] The current generation principle in the bandgap reference circuit of this embodiment is as follows:

[0021] Positive temperature coefficient current, I PTAT The current can be converted from the PTAT voltage on the zero temperature coefficient resistor R1. The PTAT voltage is calculated by ΔV BE Provides, ΔV BE Refers to the V of the first bipolar transistor Q1 and the second bipolar transistor Q2 BE Voltage difference.

[0022]

[0023]

[0024] V BEQB3 is the V of transistor QB3 BE voltage, due to V BE The negative temperature coefficient is not fixed, and the negative temperature coefficient current I CTAT Only with approximate I CTAT characteristic.

[0025] V REF =(I PTAT +I CTAT )R 5

[0026] ΔV BE / R 1 The PTAT current and V BEQB3 / R 2 The CTAT (Complementary PTAT) currents are coupled together and transmitted to the output stage through the PMOS current mirror of the MOS tube MP2, and are converted into a reference output voltage Vref through the resistor R5.

[0027] This reference circuit can be used in LDO systems, and can also be used in power products such as DC-DC or ADC to provide high-precision reference voltage. Figure 3 When the voltage source VDD is 3.3V, the PSRR (power supply rejection ratio) simulation result of the reference voltage source Vref is: Figure 3 The vertical axis represents the PSRR value of the reference voltage Vref, and the horizontal axis represents the frequency range of 10 0 HZ~10 8 HZ, the curve shows the change of power supply rejection ratio, ranging from -110dB to -30dB. Figure 3 It can be seen from the figure that the PSRR can reach -103dB when the low frequency is 100HZ. Under normal circumstances, when the PSRR reaches 60dB or more, the suppression effect is better. The existing patent provides a high power supply rejection ratio reference circuit, for example, the patent name is: a self-biased high power supply rejection ratio reference circuit, and the patent number is CN105955328B. It can solve the problem of complex circuit and high power consumption caused by the need to add bias circuit and power supply rejection ratio enhancement circuit to the existing bandgap reference. However, it can be seen from its specification and drawings that it needs to set a current amplifier and a modulation amplifier for amplification and adjustment. The startup circuit also includes a startup branch. The circuit structure is more complicated than that of the present application, and the power supply rejection ratio can reach 77dB. The present application can achieve current adjustment through a pre-regulation circuit. After adopting the reference circuit in the present application, the power supply rejection ratio can reach 103dB, which is far more than 77dB. Therefore, the use of the circuit device can well suppress the influence of the power supply voltage, and at the same time can further simplify the circuit structure, reduce energy consumption, and save costs.

Claims

1. A high power supply rejection ratio reference circuit, comprising a startup circuit module, a bandgap reference circuit module, It is characterized in that It also includes a pre-regulation circuit module, the input end of the pre-regulation circuit module is connected to a voltage source VDD, the pre-regulation circuit module is used to form an internal stable voltage, generate a pre-regulated voltage source Vreg, and supply power to the bandgap reference circuit module, the startup circuit module is respectively connected to the bandgap reference circuit module and the pre-regulation circuit module, and the bandgap reference circuit module adopts a current mode structure of a self-biased current mirror; The startup circuit includes a MOS transistor MS1, the source of the MOS transistor MS1 is respectively connected to the source of the MOS transistor MS2, the source of the MOS transistors MP1, MP2, MP3, MP4, MP5, MP6, the drain of the MOS transistors MP7 and MN10, and one end of the capacitor Cc, the drain of the MOS transistor MS1 is respectively connected to the gate of the MOS transistor MS2 and one end of the capacitor Cs, and the drain of the MOS transistor MS2 is respectively connected to the drain and gate of the MOS transistors MP1 and MN1, and the gate of the MOS transistors MN2, MN6, and MP6; The bandgap reference circuit module includes the MOS tubes MP1, MP2, MP3, MP4, MN1, MN2, MN3, MN4, MN5, MN6, and MN7. The gate of the MOS tube MP1 is respectively connected to the gate and drain of the MOS tube MP2, the drains of the MOS tubes MN2 and MN6, and the gates of the MOS tubes MP3, MP4, and MP5. The source of the MOS tube MN1 is connected to the emitter of the triode QB1. The source of the MOS tube MN2 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the emitter of the triode QB2. The source of the MOS tube MN6 is respectively connected to the drains of the MOS tubes MN3 and MN4. The source of the MOS tube MN3 is connected to one end of the resistor R2. The source of the MOS tube MN4 is respectively connected to the emitter of the triode QB3 and the source of the MOS tube MN5. The base of the MOS tube MN5 is respectively connected to the drain of the MOS tube MN5, the gate of the MOS tube MN7, and the drain of the MOS tube MP3. The source of the MOS tube MN7 is respectively connected to one end of the capacitor C1, one end of the resistor R5, and the drain of the MOS tube MP4. The self-biased current mirror composed of MOS tubes MN1, MN2, MP1 and MP2 in the bandgap reference circuit module works together with transistors QB1, QB2 and resistor R1 to generate current I PTAT MOS tubes MN3, MN4, MN6, transistor QB3 and resistor R2 are used to generate current I CTAT ; Two currents I PTAT ,I CTAT The signals are merged and mirrored through MOS tube MP2 and output to MOS tube MP4 branch, and converted to generate reference voltage Vref on resistor R5; The current mirrored to the MOS tube MP3 branch provides gate bias voltage to MOS tubes MN3 and MN4 respectively through voltage conversion of MOS tube MN5, and transistor QB3 obtains part of the bias current; MOS tube MN7 plays a role of fine-tuning negative feedback: when the current of the MOS tube MP4 branch increases, the corresponding potential of the source terminal of MOS tube MN7 is increased, so that the current flowing into the load resistor of MOS tube MN7 decreases; conversely, if the current of MP4 branch decreases, the source terminal potential of MOS tube MN7 decreases, and the current of its branch increases. Since the output voltage change has a greater impact on the change of the current in MOS tube MN7, the current of MOS tube MN7 can only account for a very small proportion of the total output current, that is, it plays a small negative feedback regulation role to maintain the stability of the output.

2. A high power supply rejection ratio reference circuit according to claim 1, It is characterized in that The pre-regulation circuit module includes the MOS transistors MP5, MP6, MP7, and MP8. The drain of the MOS transistor MP5 is respectively connected to the drain and gate of the MOS transistor MN8, the gate of MN9, and the gate of the MOS transistor MN11. The drain of the MOS transistor MP6 is respectively connected to the other end of the capacitor Cc, the gate of the MOS transistor MN10, and the drain of the MOS transistor MN9. The drain of the MOS transistor MN11 is respectively connected to the gate of the MOS transistor MP7, the gate and the drain of the MOS transistor MP8. The source of the MOS transistor MP7 and the source of MP8 are connected to the voltage source VDD. The source of the MOS transistor MN11, the source of the MOS transistor MN8, the source of MN9, the other end of the resistor R5, the other end of the capacitor C1, the base and collector of the transistor QB3, the other end of the resistor R2, the base and collector of the transistor QB2, the base and collector of the transistor QB1, the other end of the capacitor Cs, and the gate of the MOS transistor MS1 are connected and grounded.

Images