Semiconductor device and method for manufacturing the same

Abstract

The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a substrate; a body region located on the surface of the substrate; a doped region extending from the body region surface into the body region; a gate stack located on the surface of the body region; and a conductive channel, including a trench passing through the body region and contacting the substrate, and a conductive material filled in the trench, the conductive channel being separated from the doped region, wherein a channel is formed between the doped region and the conductive channel, and the substrate and the doped region are electrically connected through the conductive channel and the channel. The semiconductor device forms a conductive channel by filling the trench with conductive material. Since the trench is no longer used to form a trench gate, the etching quality requirements for the trench are reduced, thereby reducing the etching difficulty. Furthermore, the gate stack formed on the surface of the body region replaces the trench gate, thereby making the threshold voltage of the device more stable.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Trench VDMOS (vertical double-diffused metal oxide semiconductor field-effect transistor) forms its gate by growing a gate dielectric layer on the trench sidewalls and then filling it with conductive material. This trench gate structure significantly improves the planar area utilization of power devices, enabling larger device channel widths and current densities per unit area, thereby achieving greater current conduction capability. Currently, trench VDMOS is widely used in a variety of applications, including motor speed control, inverters, power supplies, electronic switches, audio equipment, and automotive electronics.

[0003] Trench VDMOS is also called UMOS because it contains a U-shaped trench structure. Figure 1 FIG. 1 shows a schematic diagram of the structure of a UMOS device in the prior art. Figure 1 As shown, a typical UMOS device includes a substrate 10, an epitaxial layer 11, a body region 12, a U-shaped trench, a source region 15, a contact hole 16, and a channel 17. A gate dielectric layer 13 is formed on the sidewalls of the U-shaped trench, and a conductive material serving as a gate conductor 14 is filled in the U-shaped trench.

[0004] In traditional UMOS manufacturing processes, due to limitations in etching technology, the outer profile and sidewall roughness of the U-shaped trench are difficult to control. Furthermore, after dry etching to form the U-shaped trench, a series of complex processes, including rounding etching, sacrificial oxidation, and acid cleaning, are required, further increasing the difficulty of controlling the outer profile and sidewall roughness of the U-shaped trench. Furthermore, since the gate dielectric layer 13 is grown on the sidewalls of the U-shaped trench, it is affected by the oxidizing atmosphere, sidewall roughness, and crystal orientation (atomic density), making it difficult to form a high-quality gate dielectric layer 13 with uniform thickness.

[0005] Furthermore, since the channel 17 of the UMOS device extends longitudinally (through the thickness of the body region 12) in the body region 12, it is easily affected by the longitudinal impurity concentration gradient in the body region 12. Consequently, the doping concentration of the channel 17 is poorly uniform, resulting in instability in the channel resistance Rch and the threshold voltage Vt. This, in turn, makes it difficult to control the on-resistance of the device, significantly increasing the difficulty in process development and device manufacturing. Summary of the Invention

[0006] In view of this, the present invention provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device has lower manufacturing difficulty and higher consistency.

[0007] According to one aspect of the present invention, a semiconductor device is provided, comprising: a substrate; a body region located on a surface of the substrate; a doped region extending from the surface of the body region into the body region; a gate stack comprising a gate dielectric layer and a gate conductor layer, the gate dielectric layer covering the surface of the body region, the gate conductor layer being located on the gate dielectric layer; and a conductive channel comprising a trench passing through the body region and in contact with the substrate, and a conductive material filled in the trench, the conductive channel being separated from the doped region, wherein the body region is of a first doping type, the substrate, the conductive channel and the doped region are of a second doping type, the first doping type being opposite to the second doping type, the gate conductor layer receiving a control voltage, and the substrate and the doped region being connected via the conductive channel and a channel between the doped region and the conductive channel.

[0008] Preferably, the channel is close to the surface of the body region.

[0009] Preferably, the gate conductor corresponds to at least a body region between the doped region and the conductive channel.

[0010] Preferably, it also includes: an interlayer dielectric layer, covering the gate dielectric layer and the gate conductor layer; a first conductive plug, passing through the interlayer dielectric layer and the gate dielectric layer, and contacting the doped region and the body region respectively; a second conductive plug, passing through the interlayer dielectric layer and contacting the gate conductor layer; a source electrode, located on the surface of the interlayer dielectric layer and contacting the first conductive plug; and a gate electrode, located on the surface of the interlayer dielectric layer and contacting the second conductive plug.

[0011] Preferably, the conductive channel extends from the surface of the body region to the surface of the substrate or into the substrate.

[0012] Preferably, on a cross section perpendicular to the thickness direction of the body region, a plurality of the doped regions are arranged in an array in the body region, and each of the doped regions is surrounded by the conductive channel, wherein the channel between each of the doped regions and the conductive channel is in the shape of a U-shape; or, on a cross section perpendicular to the thickness direction of the body region, a plurality of the doped regions are rectangular and are arranged in parallel in the body region along the long side direction of the rectangle, and at least one conductive channel is separated between two adjacent doped regions, wherein the channel between each of the doped regions and the conductive channel is rectangular.

[0013] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a body region on a surface of a substrate; forming a doped region extending from the surface of the body region into the body region; forming a conductive channel, comprising forming a trench passing through the body region and contacting the substrate, and filling the trench with a conductive material, wherein the trench is separated from the doped region; and forming a gate stack on the surface of the body region, comprising forming a gate dielectric layer on the surface of the body region and forming a gate conductor layer located on the gate dielectric layer, wherein the body region is of a first doping type, the substrate, the conductive channel and the doped region are of a second doping type, the first doping type being opposite to the second doping type, the gate conductor layer receiving a control voltage, and the substrate and the doped region being connected through the conductive channel and a channel between the doped region and the conductive channel.

[0014] Preferably, it also includes: forming an interlayer dielectric layer covering the gate dielectric layer and the gate conductor layer; forming a first conductive plug passing through the interlayer dielectric layer, the gate dielectric layer and the doped region, the first conductive plug being in contact with the doped region and the body region below the doped region, respectively; forming a second conductive plug passing through the interlayer dielectric layer, the second conductive plug being in contact with the gate conductor layer; forming a source electrode on the surface of the interlayer dielectric layer, the source electrode being in contact with the first conductive plug; and forming a gate electrode on the surface of the interlayer dielectric layer, the gate electrode being in contact with the second conductive plug.

[0015] Preferably, the step of forming the body region includes: forming an epitaxial layer serving as the body region on the surface of the substrate, wherein the doping type of the substrate is opposite to the doping type of the epitaxial layer; or, forming an epitaxial layer on the surface of the substrate, and then injecting dopant impurities into the epitaxial layer to form the body region, and controlling the junction depth of the body region to be equal to the thickness of the epitaxial layer, wherein the doping type of the substrate is the same as the doping type of the epitaxial layer.

[0016] Preferably, before forming the trench, dopant impurities are implanted into the epitaxial layer to form the body region; or, after forming the gate dielectric layer, dopant impurities are implanted into the epitaxial layer to form the body region; or, after forming the conductive channel, dopant impurities are implanted into the epitaxial layer to form the body region, and then the gate dielectric layer is formed.

[0017] Compared to the technical solution in conventional UMOS devices, which forms a trench gate structure by growing a gate dielectric layer on the trench sidewalls and filling the trench with a conductive material, the semiconductor device and the manufacturing method thereof provided by the embodiments of the present invention have the following advantages:

[0018] 1. A conductive channel is formed by forming a trench in the body region and filling the trench with a conductive material, and a gate dielectric layer is formed on the surface of the body region, replacing the trench gate structure in the existing technology. The adverse effects of the trench outer profile and the roughness of the sidewall on the device performance parameters are eliminated, thereby greatly reducing the requirements for the trench etching quality, reducing the difficulty of device processing and manufacturing, and helping to improve the consistency of device performance.

[0019] 2. Since the gate dielectric layer is formed on the surface of the body region, the thickness uniformity and quality of the gate dielectric layer are better controlled, so it is easier to obtain a high-quality gate dielectric layer, making the threshold voltage of the device more stable.

[0020] 3. Since the gate stack is a planar gate structure, the channel is adjacent to the gate dielectric layer and close to the surface of the body region, making the channel doping concentration more uniform and easier to control, avoiding the influence of the longitudinal concentration gradient of impurities in the acceptor region on the channel doping concentration, thereby making the channel resistance Rch stable and easy to control, and making the threshold voltage Vt of the device more stable.

[0021] 4. By forming a conductive channel through the body region and forming a gate stack on the surface of the body region, after the gate stack receives the control voltage, a channel is formed between the doped region and the conductive channel. The substrate and the doped region are connected through the conductive channel and the channel, which reduces the on-resistance of the device and makes the on-resistance easier to control, further improving the performance and consistency of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0023] Figure 1 The figure shows a schematic structural diagram of a UMOS device in the prior art.

[0024] Figure 2a FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

[0025] Figure 2b Shown Figure 2a Schematic cross-sectional view of a semiconductor device in FIG.

[0026] Figure 2c Schematic cross-sectional views of semiconductor devices according to other embodiments of the present invention are shown.

[0027] Figures 3a to 3p The diagram shows cross-sectional views at various stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by similar reference numerals throughout the various figures. For clarity, parts in the figures are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps may be depicted in a single figure.

[0029] It should be understood that when describing a device structure, when a layer or region is referred to as being "on" or "above" another layer or region, this may mean that it is directly above the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" the other layer or region. To describe the situation of being directly above another layer or region, this document will use the expressions "directly above" or "above and adjacent to"

[0030] Figure 2a FIG. 1 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention. Figure 2a As shown, the semiconductor device of the embodiment of the present invention includes: a substrate 101, a body region 120, a conductive channel 130, a gate stack 140, a doped region 150, an interlayer dielectric layer 160, a first conductive plug 171, a second conductive plug 172, a source electrode 181 and a gate electrode 182.

[0031] The body region 120 is located on the surface of the substrate 101 (in the semiconductor field, of the two surfaces of the substrate 101, the surface used to form the epitaxial layer 110 is generally called the front surface, and the other surface is called the back surface). The conductive channel 130 passes through the body region 120 and contacts the substrate 101. The depth of the conductive channel 130 is no less than the junction depth of the body region 120. In this embodiment, the conductive channel 130 extends from the surface of the body region 120 into the substrate 101. In some other embodiments, the conductive channel 130 may only contact the front surface of the substrate 101. The doped region 150 extends from the surface of the body region 120 into the body region 120, and the conductive channel 130 and the doped region 150 are separated by the body region 120.

[0032] The body region 120 has a first doping type, and the substrate 101, the conductive channel 130, and the doped region 150 have a second doping type, where the first doping type is opposite to the second doping type. The second doping type is selected from one of P-type doping and N-type doping, and the first doping type is selected from the other of P-type doping and N-type doping.

[0033] In this embodiment, the first doping type is selected from P-type doping, and the second doping type is selected from N-type doping. In other embodiments, the first doping type is selected from N-type doping, and the second doping type is selected from P-type doping.

[0034] The gate stack 140 specifically includes a gate dielectric layer 141 and a gate conductor layer 142, which are stacked together. The gate dielectric layer 141 covers the surface of the body region 120, and the gate conductor layer 142 is located on the gate dielectric layer 141. The gate conductor layer 142 is located above the conductive channel 130 and extends along the gate dielectric layer 141 to both sides of the conductive channel 130 to cover the body region 120 between the doped region 150 and the conductive channel 130. The gate stack 140, or more precisely, the gate conductor layer 142, receives a control voltage to form a channel 190 between the doped region 150 and the conductive channel 130. The substrate 101 and the doped region 150 are electrically connected through the conductive channel 130 and the channel 190. The channel 190 is adjacent to the gate dielectric layer 141 and close to the surface of the body region 120.

[0035] An interlayer dielectric layer (ILD) 160 covers the gate dielectric layer 141 and the gate conductor layer 142. A first conductive plug 171 penetrates the interlayer dielectric layer 160 and the gate dielectric layer 141 and contacts both the doped region 150 and the body region 120. That is, the first conductive plug 171 penetrates the interlayer dielectric layer 160, the gate dielectric layer 141, and the doped region 150 and contacts the body region 120 below the doped region 150. A second conductive plug 172 penetrates the interlayer dielectric layer 160 and contacts the gate conductor layer 142. In this embodiment, the second conductive plug 172 penetrates the interlayer dielectric layer 160 and contacts the surface of the gate conductor layer 142 away from the body region 120; in other embodiments, the second conductive plug 172 penetrates the interlayer dielectric layer 160 and enters the gate conductor layer 142.

[0036] The source electrode 181 is located on the surface of the interlayer dielectric layer 160 and contacts the first conductive plug 171. The gate electrode 182 is located on the surface of the interlayer dielectric layer 160 and contacts the second conductive plug 172. Of course, the source electrode 181 and the gate electrode 182 are not in direct contact.

[0037] Figure 2b Shown Figure 2a The cross-sectional view of the semiconductor device in FIG. 1 is a schematic view of a cross-sectional view of the source connection region S. Figure 2a The cross-sectional view corresponding to the gate connection region G is taken along the position indicated by arrow A. Figure 2a The image is taken along the position indicated by arrow B.

[0038] like Figure 2a and 2bAs shown, in a cross section perpendicular to the thickness of the body region 120, multiple doped regions 150 are arranged in an array within the body region 120, each doped region 150 being surrounded and enclosed by a conductive channel 130. A channel 190 between each doped region 150 and the conductive channel 130 is shaped like a U-shaped channel to increase current density. Multiple doped regions 150 can be connected to a common source electrode 181 via a first conductive plug 171. The gate conductor layer 142 can be connected to a common gate electrode 182 via multiple second conductive plugs 172.

[0039] It should be noted that Figure 2b In the embodiment, there are four doped regions 150 arranged in a 2×2 array. In a specific implementation, the number of doped regions 150 in each cell can reach hundreds of thousands or even millions. The arrangement can be reasonably set according to product performance requirements and will not be further described here.

[0040] like Figure 2c As shown, in some other embodiments, in a cross section perpendicular to the thickness direction of the body region 120, the multiple doped regions 150 are rectangular and arranged parallel to the long sides of the rectangle in the body region 120, with at least one conductive channel 130 between each adjacent doped region 150. The channel 190 between each doped region 150 and the conductive channel 130 is rectangular. Each doped region 150 is connected to multiple uniformly arranged first conductive plugs 171, and the multiple doped regions 150 are connected to the same source electrode 181 through the first conductive plugs 171. Multiple gate conductor layers 142 are connected to the same gate electrode 182 through corresponding second conductive plugs 172.

[0041] It should be noted that Figure 2c In the embodiment, there are two doping regions 150 arranged in parallel. In a specific implementation, the number of doping regions 150 in each cell can reach hundreds of thousands or even millions. The arrangement can be reasonably set according to the product performance requirements, which will not be described in detail here.

[0042] Figures 3a to 3p The cross-sectional views of the method for manufacturing a semiconductor device according to an embodiment of the present invention at various stages are shown. Figures 3a to 3p The method for manufacturing the semiconductor device of the present invention will be described in detail.

[0043] In this embodiment, the body region 120 can be manufactured in the following two ways:

[0044] In one implementation, such as Figure 3a As shown, an epitaxial layer 110 is formed on the surface of the substrate 101; Figure 3bAs shown, the epitaxial layer 110 is doped to form a body region 120 on the front surface of the substrate 101. This embodiment does not particularly limit the formation process of the epitaxial layer 110 and the body region 120. The epitaxial layer 110 can be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or other processes. The body region 120 can be formed by implanting dopant impurities into the epitaxial layer 110 and then annealing to ensure that the junction depth of the body region 120 is the same as the thickness of the epitaxial layer 110.

[0045] The substrate 101 and the epitaxial layer 110 have the same doping type, for example, both are N-type doped, and the doping concentration of the epitaxial layer 110 is lower than the doping concentration of the substrate 101. In this embodiment, P-type doping is used when implanting into the epitaxial layer 110. The doping impurity used may be, for example, boron (B), and the implantation dose is generally not greater than E14cm -2 Order of magnitude.

[0046] Optionally, the step of implanting P-type dopant impurities into the epitaxial layer 110 to form the body region 120 may be performed before or after the gate dielectric layer 141 is formed. For example, after the gate dielectric layer 141 is formed, dopant impurities are implanted into the epitaxial layer 110 to form the body region 120. For another example, after the conductive channel 130 is formed, dopant impurities are implanted into the epitaxial layer 110 to form the body region 120, and then the gate dielectric layer 141 is formed.

[0047] In another implementation, reference Figure 3b Alternatively, the body region 120 can be directly obtained by performing an epitaxial growth process on the front surface of the substrate 110. Of course, the doping type of the substrate 101 is opposite to that of the body region 120 (or epitaxy). For example, an N-type substrate with P-type epitaxy. Of course, epitaxial wafers that meet this requirement can also be purchased directly from commercial sources.

[0048] Since the channel 190 is formed within the body region 120 and close to the surface of the body region 120 when the device is formed and turned on, the doping concentration of the channel region can be monitored by the sheet resistance after implantation and annealing. In the embodiment of the present invention, whether the body region 120 is formed by doping the epitaxial layer 110 with impurities or directly forming the body region 120 using the epitaxial layer 110, there is no need to consider the longitudinal concentration gradient of the doping impurities in the body region 120. Only the uniformity of the doping impurities on the surface of the body region 120 needs to be controlled, thereby reducing the difficulty of the doping process and making the channel resistance Rch and threshold voltage Vt stable and easy to control after the device is turned on.

[0049] Furthermore, a mask 102 is formed on the surface of the body region 120, such as Figure 3c shown.

[0050] In this step, for example, a non-metallic dielectric layer is first formed on the surface of the body region 120 using a thin film growth process, and then the non-metallic dielectric layer is patterned using an etching process to form a mask 102 having a plurality of windows 103. In this embodiment, the material of the mask 102 includes, but is not limited to, insulating materials such as silicon oxide and silicon nitride.

[0051] Furthermore, the body region 120 is anisotropically etched through the through window 103 to form a plurality of trenches 104 passing through the body region 120, as shown in FIG. Figure 3d shown.

[0052] In this step, the anisotropic etching method may be, for example, ion milling, plasma etching, reactive ion etching, or laser ablation. By controlling the etching time and etching rate, the depth of the trench 104 is ensured to be no less than the junction depth of the body region 120. In this embodiment, the trench 104 may be a U-shaped trench as used in conventional UMOS, with the bottom of the trench 104 passing through the body region 120 and extending into the substrate 101.

[0053] However, the embodiment of the present invention is not limited thereto, and those skilled in the art may set other depths of the trench 104 as needed, for example, the bottom of the trench 104 is located on the front surface of the substrate 101 .

[0054] Since the trench 104 will be filled with a conductive material to form a conductive path in subsequent steps, the shape and edge flatness of the trench 104 will not significantly affect the quality of the device. Therefore, during the step of forming the trench 104, the inner surface of the trench 104 does not need to be perfectly flat, thereby reducing the difficulty of controlling the etching process.

[0055] Furthermore, a polysilicon layer 105 is deposited on the surface of the mask 102 and in the trench 104, as shown in FIG. Figure 3e shown.

[0056] In this step, for example, a CVD process is used to form the polysilicon layer 105, and thermal diffusion, ion implantation and subsequent annealing can be used to dope the polysilicon layer 105 with a concentration not less than E18cm -3 In this embodiment, the polysilicon layer 105 is, for example, in-situ N-type doped, with an impurity concentration of 1E19 cm -3 , the deposition thickness of the polysilicon layer 105 is not less than 1000 angstroms.

[0057] However, the embodiments of the present invention are not limited thereto, and those skilled in the art may flexibly adjust the parameters of the polysilicon layer 105 according to the filling effect of the trench 104 .

[0058] Furthermore, the polysilicon layer 105 is reversely etched, and the surface height of the polysilicon layer 105 after etching is not lower than the interface between the body region 120 and the mask 102, for example Figure 3f In the embodiment, the surface of the polysilicon layer 105 after etching is substantially flush with the surface of the body region 120 ; in other embodiments, the surface of the polysilicon layer 105 after etching is slightly higher than the surface of the body region 120 but does not exceed the surface of the mask 102 .

[0059] Further, the mask 102 is removed to expose the surface of the body region 120 again, as shown in FIG. Figure 3g As shown, the polysilicon layer 105 in the trench 104 and the trench 104 together serve as a conductive channel 130 . The outer contour of the conductive channel 130 is U-shaped, extending from the surface of the body region 120 to the substrate 101 .

[0060] Furthermore, a gate dielectric layer 141 is formed on the surface of the body region 120, as shown in FIG. Figure 3h shown.

[0061] In this step, for example, a thin film growth process is used to form the gate dielectric layer 141. The material of the gate dielectric layer 141 includes but is not limited to silicon oxide, and the thickness is not less than 30 angstroms.

[0062] However, the embodiment of the present invention is not limited thereto, and those skilled in the art may flexibly adjust the thickness of the gate dielectric layer 141 according to different requirements of the device threshold voltage Vt.

[0063] Furthermore, a gate conductor layer 142 is formed on the surface of the gate dielectric layer 141, such as Figure 3i shown.

[0064] In this step, for example, a polysilicon layer is first deposited on the surface of the gate dielectric layer 141 using a CVD process. The thickness of the polysilicon layer is not less than 1000 angstroms, and the doping type of the polysilicon layer is N-type with a doping concentration of not less than 1E19 cm -3 The polysilicon layer is then patterned using photolithography and etching processes to form a gate conductor layer 142 . The gate dielectric layer 141 and the gate conductor layer 142 together constitute a gate stack 140 .

[0065] In this embodiment, the gate conductor layer 142 is located above the conductive channel 130 and extends along the gate dielectric layer 141 to both sides of the conductive channel 130 by a predetermined length, covering the channel 190 and the conductive channel 130 .

[0066] However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings for the thickness and doping concentration of the polysilicon layer as needed.

[0067] In some other embodiments, the gate conductor layer 142 may also be made of conductive materials such as metals and metal oxides.

[0068] Furthermore, a doping region 150 is formed extending from the surface of the body region 120 into the body region 120, such as Figure 3j shown.

[0069] In this step, a self-aligned implantation process is first used to implant N-type dopant impurities into the body region 120. The gate conductor layer 142 made of polysilicon serves as a masking layer. Annealing is then performed to diffuse the dopant impurities from the surface of the body region 120 into the body region 120, forming a doped region 150. In this embodiment, the doped region 150 serves as the source region of the device. The N-type dopant impurity is arsenic (As) with an implantation dose of not less than E15cm. -2 .

[0070] However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings for the doping impurities and doping concentration of the doping region 150 as needed, and reasonably adjust the annealing conditions according to actual needs.

[0071] Furthermore, an interlayer dielectric layer 160 is formed to cover the gate dielectric layer 141 and the gate conductor layer 142. Figure 3k shown.

[0072] In this step, an insulating material, such as silicon oxide or silicon nitride, is first deposited on the surfaces of the gate dielectric layer 141 and the gate conductor layer 142 using a thin film growth process, for example. The insulating material is then planarized using, for example, chemical mechanical polishing (CMP) to form the interlayer dielectric layer 160. In this embodiment, the thickness of the planarized interlayer dielectric layer 160 is no less than 1000 angstroms.

[0073] However, the embodiment of the present invention is not limited thereto, and those skilled in the art may make other settings for the material and thickness of the interlayer dielectric layer 160 as needed.

[0074] Furthermore, anisotropic etching is used to form a first contact hole 106 passing through the interlayer dielectric layer 160, the gate dielectric layer 141 and the doped region 150, and a second contact hole 107 passing through the interlayer dielectric layer 160, as shown in FIG. Figure 3l shown.

[0075] In this step, the anisotropic etching method includes, for example, ion milling, plasma etching, reactive ion etching, and laser ablation. By controlling the etching rate and etching time, the bottom of the first contact hole 106 passes through the doped region 150 and enters the body region 120. Similarly, by controlling the etching rate and etching time, the bottom of the second contact hole 107 reaches the gate conductor layer 142 or passes through the gate conductor layer 142. When forming the second contact hole 107, the gate dielectric layer 141 can serve as an etch stop layer, and the second contact hole 107 may also pass through the surface of the gate dielectric layer 141 to the middle of the gate dielectric layer 141.

[0076] Furthermore, a first conductive plug 171 is formed through the interlayer dielectric layer 160, the gate dielectric layer 141 and the doped region 150, and a second conductive plug 172 is formed through the interlayer dielectric layer 160, as shown in FIG. Figure 3m shown.

[0077] In this step, a metal material, such as titanium, titanium nitride, tungsten, or copper, is filled into the first contact hole 106 and the second contact hole 107, respectively, using, for example, a CVD or PVD process. The bottom of the first conductive plug 171 extends through the doped region 150 into the body region 120 below the doped region 150. The bottom of the second conductive plug 172 reaches the gate conductor layer 142, or it can penetrate the gate conductor layer 142 to reach the surface or center of the gate dielectric layer 141.

[0078] Furthermore, a source electrode 181 and a gate electrode 182 are formed on the surface of the interlayer dielectric layer 160, wherein the source electrode 181 contacts the first conductive plug 171, and the gate electrode 182 contacts the second conductive plug 172. Figure 3n shown.

[0079] In this step, a metal layer is first deposited on the surface of the interlayer dielectric layer 160 using a PVD process, for example. The material of the metal layer is, for example, aluminum, copper, silver, aluminum-copper alloy, aluminum-silicon-copper alloy, etc. An etching process is then used to form an opening 108 in the metal layer, thereby separating the metal layer into a source electrode 181 and a gate electrode 182.

[0080] Preferably, a drain electrode (not shown) may be formed on the back side of the substrate 101. Of course, before forming the drain electrode on the back side of the substrate 101, the back side of the substrate 101 may be thinned according to actual needs.

[0081] In some other embodiments, if the gate conductor layer 142 is formed of a metal material, after the gate conductor layer 142 is formed, Figure 3h After the steps shown in FIG. 1 , a doped region 150 is formed in the body region 120, as shown in FIG. Figure 3o Then, a metal gate conductor layer 142 is formed on the gate dielectric layer 141, as shown. Figure 3pFor subsequent steps, refer to Figures 3k to 3n , I will not go into details here.

[0082] A control voltage is externally connected to the gate electrode 182, and the gate conductor layer 142 receives the control voltage, forming a channel 190 between the doped region 150 and the conductive channel 130. The substrate 101 and the doped region 150 are electrically connected through the conductive channel 130 and the channel 190. Current flows sequentially through the substrate 101, the longitudinal conductive channel 130, the channel 190, the doped region 150, and the longitudinal first conductive plug 171 to reach the source electrode 181. Figure 2a shown.

[0083] The manufacturing method of the semiconductor device mentioned in the embodiment of the present invention is particularly suitable for manufacturing low-voltage (operating voltage not greater than 100V) NMOS devices. The manufacturing principle of the PMOS device is the same, and the doping type in the corresponding structure is directly switched. However, the N-type doping and P-type doping methods of polysilicon are different. N-type doping mostly adopts in-situ polycrystalline doping, that is, growing N-type doped polycrystalline silicon. P-type doping is limited by the processing means. Generally, polysilicon is deposited first, and then boron is injected and annealed to achieve P-type doping. In addition, the formation of N-type polysilicon can also be achieved by phosphorus implantation and annealing, and in-situ N-type polycrystalline deposition is the preferred solution.

[0084] like Figure 1 As shown, the on-resistance of a conventional UMOS device includes: substrate resistance Rsub, epitaxial resistance Repi, accumulation region resistance Racc, channel resistance Rch, source resistance Rsc, and hole contact resistance Rcon. After the device is turned on, the vertically flowing current (direction of the arrow) must pass through the entire device, particularly through a high-resistance region—the epitaxial layer 11. The epitaxial resistance Repi has a very large resistance, resulting in a very high on-resistance.

[0085] According to an embodiment of the present invention, a semiconductor device and a method for manufacturing the same, such as Figure 2a As shown, by forming a conductive channel 130 that passes through the body region 120 and contacts the substrate 101, the epitaxial resistor Repi, originally connected in series with the traditional UMOS device, is eliminated, thereby reducing the overall on-resistance of the device. Because the conductive channel 130 is made of in-situ doped polysilicon and serves only as a low-resistance conductive path to direct current from the drain electrode on the back side of the substrate 101 to the front side, the vertical flow of current between the source electrode 181 and the drain electrode of the VDMOS is not altered, thereby ensuring efficient utilization of the device's planar area. Because the gate stack 140 is formed on the surface of the body region 120, it replaces the trench gate structure used in the prior art, thus avoiding problems such as the U-shaped trench profile and sidewall roughness affecting the gate oxidation quality.

[0086] Furthermore, since the gate dielectric layer 141 is only formed on the surface of the body region 120, the thickness uniformity and quality of the gate dielectric layer 141 are better controlled; in addition, the body region 120 is a semiconductor material with a single crystal orientation, so the thickness uniformity and quality of the gate dielectric layer 141 can be better controlled, thereby making the threshold voltage Vt more stable and the on-resistance value easier to control.

[0087] Furthermore, since the gate stack 140 is a planar gate structure, the channel 190 formed when the device is operating is adjacent to the gate dielectric layer 141 and close to the surface of the body region 120, thereby making the resistance of the channel 190 more uniform and easier to control, avoiding the resistance of the channel 190 being easily affected by the longitudinal concentration gradient of impurities in the body region 120, thereby making the channel resistance Rch stable and easy to control, and at the same time making the on-resistance and threshold voltage Vt of the device more stable.

[0088] Furthermore, when forming the polysilicon gate conductor layer, only one polysilicon deposition and photolithography step is added compared to conventional processes. However, during the implantation step of the doped region 150, an automated alignment process can be used, saving one photolithography mask, without significantly increasing the overall number of photolithography steps. Furthermore, the entire device manufacturing process, in all steps, can be completed using existing process technologies, making the device fabrication process easily integrated with existing semiconductor processes and readily applicable.

[0089] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0090] The above descriptions describe embodiments of the present invention. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Those skilled in the art may make various substitutions and modifications without departing from the scope of the present invention, and such substitutions and modifications are intended to fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; a body region located on the surface of the substrate; a doped region extending from a surface of the body region into the body region; a gate stack, comprising a gate dielectric layer and a gate conductor layer, wherein the gate dielectric layer covers a surface of the body region, and the gate conductor layer is located on the gate dielectric layer; as well as A conductive channel, comprising a trench passing through the body region and contacting the substrate and a conductive material filled in the trench, wherein the conductive channel is separated from the doped region, wherein the dose of the doping impurity in the body region is not greater than E14cm -2 , and the conductive path has a value not less than E18cm -3 The impurity concentration, The body region is of a first doping type, the substrate, the conductive channel, and the doping region are of a second doping type, and the first doping type is opposite to the second doping type. In a cross section perpendicular to the thickness direction of the body region, a plurality of the doped regions are arranged in an array in the body region, each of the doped regions is surrounded by the conductive channel, wherein a channel between each of the doped regions and the conductive channel is in a U-shaped channel. The gate conductor layer receives a control voltage, and the substrate and the doping region are electrically connected via the conductive channel and a channel between the doping region and the conductive channel.

2. The semiconductor device according to claim 1, wherein The channel is close to the surface of the body region.

3. The semiconductor device according to claim 1 or 2, wherein: The gate conductor corresponds to at least a body region between the doped region and the conductive channel.

4. The semiconductor device according to claim 1 or 2, wherein: Also includes: an interlayer dielectric layer, covering the gate dielectric layer and the gate conductor layer; a first conductive plug passing through the interlayer dielectric layer and the gate dielectric layer and contacting the doped region and the body region respectively; a second conductive plug passing through the interlayer dielectric layer and contacting the gate conductor layer; a source electrode, located on a surface of the interlayer dielectric layer and in contact with the first conductive plug; as well as The gate electrode is located on the surface of the interlayer dielectric layer and contacts the second conductive plug.

5. The semiconductor device according to claim 1 or 2, wherein: The conductive channel extends from the surface of the body region to the surface of the substrate.

6. The semiconductor device according to claim 1 or 2, wherein: The conductive channel extends from the surface of the body region into the substrate, and a top surface of the conductive channel is flush with a top surface of the body region.

7. A method for manufacturing a semiconductor device, characterized in that: include: forming a body region on a surface of the substrate; forming a doped region extending from a surface of the body region into the body region; Forming a conductive channel, including forming a trench passing through the body region and contacting the substrate, and filling the trench with a conductive material, wherein the trench is separated from the doped region, wherein the dose of the doping impurity in the body region is not greater than E14cm -2 , and the conductive path has a value not less than E18cm -3 impurity concentration; and forming a gate stack on the surface of the body region, including forming a gate dielectric layer on the surface of the body region and forming a gate conductor layer on the gate dielectric layer; The body region is of a first doping type, the substrate, the conductive channel, and the doping region are of a second doping type, and the first doping type is opposite to the second doping type. In a cross section perpendicular to the thickness direction of the body region, a plurality of the doped regions are arranged in an array in the body region, each of the doped regions is surrounded by the conductive channel, wherein a channel between each of the doped regions and the conductive channel is in a U-shaped channel. The gate conductor layer receives a control voltage, and the substrate and the doping region are electrically connected via the conductive channel and a channel between the doping region and the conductive channel.

8. The manufacturing method according to claim 7, characterized in that Also includes: forming an interlayer dielectric layer covering the gate dielectric layer and the gate conductor layer; forming a first conductive plug passing through the interlayer dielectric layer, the gate dielectric layer and the doped region, wherein the first conductive plug is in contact with the doped region and a body region below the doped region respectively; forming a second conductive plug passing through the interlayer dielectric layer, wherein the second conductive plug contacts the gate conductor layer; forming a source electrode on a surface of the interlayer dielectric layer, wherein the source electrode is in contact with the first conductive plug; as well as A gate electrode is formed on the surface of the interlayer dielectric layer, and the gate electrode is in contact with the second conductive plug.

9. The manufacturing method according to claim 7 or 8, characterized in that: The step of forming the body region comprises: forming an epitaxial layer as the body region on the surface of the substrate, wherein the doping type of the substrate is opposite to the doping type of the epitaxial layer; Alternatively, an epitaxial layer is formed on the surface of the substrate, and then dopant impurities are implanted into the epitaxial layer to form the body region, and the junction depth of the body region is controlled to be equal to the thickness of the epitaxial layer, wherein the doping type of the substrate is the same as the doping type of the epitaxial layer.

10. The manufacturing method according to claim 9, characterized in that: Before forming the trench, implanting dopant impurities into the epitaxial layer to form the body region; or, After forming the gate dielectric layer, implanting dopant impurities into the epitaxial layer to form the body region; or, After forming the conductive channel, dopant impurities are implanted into the epitaxial layer to form the body region, and then the gate dielectric layer is formed.

Images