Semiconductor device

Abstract

A semiconductor device is disclosed, comprising: a substrate having a first region and a second region adjacent to each other in a first direction; and first to third gate electrodes extending from the first region toward the second region. Each of the first region and the second region includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. A first signal is applied to the first gate electrode and the third gate electrode. A second signal, which is an inverted signal of the first signal, is applied to the second gate electrode. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned with each other in the first direction and connected to each other.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2018 - 0143562, filed on November 20, 2018, and Korean Patent Application No. 10 - 2019 - 0038256, filed on April 2, 2019, with the Korean Intellectual Property Office, the entire contents of both patent applications being incorporated herein by reference. Technical field

[0003] The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a field - effect transistor. Background art

[0004] Semiconductor devices are widely used in the electronics industry because of their small size, multi - functionality, and / or low manufacturing cost. Semiconductor devices can include semiconductor memory devices that store logic data, semiconductor logic devices that process operations of logic data, and hybrid semiconductor devices having both memory and logic elements. With the advanced development of the electronics industry, semiconductor devices have increasingly required high integration. For example, semiconductor devices have increasingly required high reliability,

[0005] high speed, and / or multi - functionality. Semiconductor devices have gradually become more complex and integrated to meet these required characteristics. Summary of the invention

[0006] The present disclosure provides a semiconductor device including a highly integrated field - effect transistor.

[0007] According to an exemplary embodiment of the inventive concept, a semiconductor device includes: a substrate including a first region and a second region adjacent to the first region in a first direction; and a first gate electrode, a second gate electrode, and a third gate electrode extending from the first region toward the second region. Each of the first region and the second region includes a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) region and an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) region. Each of the first gate electrode, the second gate electrode, and the third gate electrode extends in the first direction such that each of the first gate electrode, the second gate electrode, and the third gate electrode extends longitudinally in the first direction. Each of the PMOSFET region and the NMOSFET region may extend longitudinally in a second direction different from the first direction. The second gate electrode is interposed between the second gate electrode and the third gate electrode in a second direction different from the first direction. The first gate electrode and the third gate electrode are configured to receive a first signal. The second gate electrode is configured to receive a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gate of the first region and the first gate of the second region are aligned in the first direction and connected to each other.

[0008] According to an exemplary embodiment of the inventive concept, a semiconductor device includes: a flip-flop unit located on a substrate, the flip-flop unit including a first region including a master latch and a second region including a slave latch, the second region being adjacent to the first region in a first direction; and a first gate electrode, a second gate electrode, and a third gate electrode extending from the first region toward the second region and sequentially arranged in a second direction different from the first direction. Each of the first gate electrode, the second gate electrode, and the third gate electrode extends in the first direction. The first gate electrode and the third gate electrode are applied with a clock signal. The second gate electrode is applied with a clock inverted signal that is an inverted signal of the clock signal. The second gate electrode includes a second gate that is a gate of a PMOS transistor of the first region, a gate of an NMOS transistor of the first region, a gate of an NMOS transistor of the second region, and a gate of a PMOS transistor of the second region.

[0009] According to an exemplary embodiment of the inventive concept, a semiconductor device includes a first flip-flop unit and a second flip-flop unit adjacent to each other in a first direction on a substrate; and first, second, and third gate electrodes extending from the first flip-flop unit toward the second flip-flop unit and sequentially arranged in a second direction different from the first direction. Each of the first, second, and third gate electrodes extends in the first direction. A scan enable signal is applied to the first gate electrode and the third gate electrode. A scan enable inverse signal is applied to the second gate electrode. The second gate electrode includes a second gate that is a gate of a PMOS transistor of the first flip-flop unit, a gate of an NMOS transistor of the first flip-flop unit, a gate of an NMOS transistor of the second flip-flop unit, and a gate of a PMOS transistor of the second flip-flop unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 FIG. shows a plan view of a logic region of a semiconductor device presenting some example embodiments according to the inventive concept.

[0011] Figure 2 FIG. shows a logic circuit diagram of a flip-flop of a semiconductor device presenting some example embodiments according to the inventive concept.

[0012] Figure 3 FIG. shows Figure 2 an equivalent circuit diagram of a first portion shown in

[0013] Figure 4 FIG. shows Figure 2 an equivalent circuit diagram of a second portion or a third portion shown in

[0014] Figure 5 FIG. shows a plan view of a first region and a second region of a semiconductor device presenting some example embodiments according to the inventive concept.

[0015] Figure 6 FIG. shows a plan view of a first region and a second region of a semiconductor device presenting some example embodiments according to the inventive concept.

[0016] Figure 7 FIG. shows a plan view of a semiconductor device presenting some example embodiments according to the inventive concept.

[0017] Figure 8A , Figure 8B , Figure 8C and Figure 8D FIGS. respectively show cross-sectional views taken along lines I-I', II-II', III-III', and IV-IV' of Figure 7 .

[0018] Figure 9A plan view showing a first region, a second region, and a third region of a semiconductor device presenting some example embodiments according to the inventive concept is shown.

[0019] Figure 10 A plan view showing a first region and a second region of a semiconductor device presenting some example embodiments according to the inventive concept is shown.

[0020] Figure 11 A plan view showing a semiconductor device presenting some example embodiments according to the inventive concept is shown.

[0021] Figure 12A and Figure 12B respectively show cross-sectional views taken along line I-I' and line II-II' of Figure 11 . Detailed Description

[0022] Figure 1 A plan view showing a logic region of a semiconductor device presenting some example embodiments according to the inventive concept is shown.

[0023] Referring to Figure 1 , a plurality of flip-flop units FF1 to FF4 may be disposed on a logic region of a substrate 100. The flip-flop units FF1 to FF4 may be two-dimensionally arranged on the logic region of the substrate 100. The flip-flop units FF1 to FF4 may include a first flip-flop unit FF1, a second flip-flop unit FF2, a third flip-flop unit FF3, and a fourth flip-flop unit FF4. The second flip-flop unit FF2 may be adjacent to the first flip-flop unit FF1 in a second direction D2. The third flip-flop unit FF3 may be adjacent to the first flip-flop unit FF1 in a first direction D1. The fourth flip-flop unit FF4 may be adjacent to the third flip-flop unit FF3 in the second direction D2. The first direction D1 may be different from the second direction D2.

[0024] Figure 2 A logic circuit diagram of a flip-flop of a semiconductor device presenting some example embodiments according to the inventive concept is shown. Figure 3 Shows Figure 2 an equivalent circuit diagram of a first portion shown in Figure 4 Shows Figure 2 an equivalent circuit diagram of a second portion or a third portion shown in

[0025] Referring to Figures 1 to 4 , each of the flip-flop units FF1 to FF4 may include Figure 2The trigger circuit. The first trigger unit FF1 will be described representatively below. The first trigger unit FF1 may include a first part P01 to a fourth part P04. For example, the first part P01 may be a core circuit that performs a scan function and a trigger function. The first part P01 may select one of an external input signal D and a scan input signal SI according to a scan enable signal SE and may provide the selected signal to a first node N1 as an output signal of the first part P01. The first part P01 may be referred to as a multiplexer (or mux), a scan multiplexer (or scan mux), or a selector.

[0026] Each of the second part P02 and the third part P03 may be a buffer. The second part P02 may include a master latch, and the third part P03 may include a slave latch. The master latch of the second part P02 may latch the output signal of the first part P01 based on a clock signal CLK. The slave latch of the third part P03 may latch the output of the master latch based on the clock signal CLK and provide an output signal Q. The fourth part P04 may include a clock circuit having a connection to the trigger and receiving an external clock signal CK.

[0027] Return reference Figure 2 and Figure 3 , the first part P01 may include a first element E1 and a second element E2. The scan input signal SI is input to the first element E1, and the external input signal D is input to the second element E2. The first element E1 and the second element E2 may be connected in parallel to the first node N1.

[0028] The first element E1 may include a first transistor to a fourth transistor connected in series. The first transistor to the fourth transistor may be sequentially arranged between a VDD terminal and a VSS terminal. Each of the first transistor and the second transistor may be a P-type metal oxide semiconductor (PMOS) transistor, and each of the third transistor and the fourth transistor may be an N-type metal oxide semiconductor (NMOS) transistor. The scan input signal SI may be input to the first transistor and the third transistor, a scan enable inverse signal ( / SE) may be input to the second transistor, and the scan enable signal SE may be input to the fourth transistor.

[0029] The second element E2 may include a first transistor to a fourth transistor connected in series. The first transistor to the fourth transistor may be sequentially arranged between the VDD terminal and the VSS terminal. The first transistor and the second transistor may be PMOS transistors, and the third transistor and the fourth transistor may be NMOS transistors. The external input signal D may be input to the second transistor and the third transistor, the scan enable signal SE may be input to the first transistor, and the scan enable inverse signal ( / SE) may be input to the fourth transistor.

[0030] Return reference Figure 2 and Figure 4 The second part P02 may include a third element E3, a fourth element E4, and a fifth element E5 disposed between the first node N1 and the second node N2. The fourth element E4 and the fifth element E5 may be connected in parallel between the third element E3 and the second node N2. The clock signal CLK and the clock inverse signal / CLK may be input to each of the third element E3 and the fourth element E4.

[0031] The third part P03 may be configured to include elements substantially the same as the third element E3, the fourth element E4, and the fifth element E5 of the second part P02. The third element E3, the fourth element E4, and the fifth element E5 of the third part P03 may be disposed between the second node N2 and the third node N3.

[0032] The second part P02 may include a master latch, and the third part P03 may include a slave latch. Although the following description relates to the second part P02, the description may also be equivalently or similarly applied to the third part P03.

[0033] The third element E3 may include a first transistor to a fourth transistor connected in series. The first transistor to the fourth transistor may be sequentially disposed between the VDD terminal and the VSS terminal. The first transistor and the second transistor may be PMOS transistors, and the third transistor and the fourth transistor may be NMOS transistors. The first transistor and the fourth transistor may receive signals from the first node N1. The clock signal CLK may be input to the second transistor, and the clock inverse signal / CLK may be input to the third transistor.

[0034] The fourth element E4 may include a first transistor to a fourth transistor connected in series. The first transistor to the fourth transistor may be sequentially disposed between the VDD terminal and the VSS terminal. The first transistor and the second transistor may be PMOS transistors, and the third transistor and the fourth transistor may be NMOS transistors. The first transistor and the fourth transistor may be connected to the second node N2. The clock inverse signal / CLK may be input to the second transistor, and the clock signal CLK may be input to the third transistor.

[0035] Table 1 below is a timing table of a flip-flop according to some example embodiments of the inventive concept.

[0036] [Table 1]

[0037] D[n] SI SE CK Q[n + 1] 1 X 0 Low → High 1 0 X 0 Low → High 0 X X X High → Low Q[n] X 1 1 Low → High 1 X 0 1 Low → High 0

[0038] When the external input D[n] is logic high and the scan enable signal SE is invalid, the external output Q[n+1] can turn logic high when the external clock signal CK changes from low to high. When the external input D[n] is logic low and the scan enable signal SE is invalid, the external output Q[n+1] can turn logic low when the external clock signal CK changes from low to high. When the external input D[n], the scan enable signal SE, and the scan input signal SI are all absent, the external output Q[n+1] can maintain its value Q[n+1] from the previous cycle when the external clock signal CK changes from high to low. When the external input D[n] is absent and both the scan enable signal SE and the scan input signal SI are valid, the external output Q[n+1] can turn logic high when the external clock signal CK changes from low to high. When the external input D[n] is absent, the scan enable signal SE is valid, and the scan input signal SI is invalid, the external output Q[n+1] can turn logic low when the external clock signal CK changes from low to high.

[0039] Figure 5 A plan view showing a first region and a second region of a semiconductor device presenting some example embodiments according to the inventive concept is shown.

[0040] Referring to Figure 1 and Figure 5 and

[0041] A plurality of gates GA1, GA2, and GA3 may extend in a first direction D1 while crossing the NMOSFET region NR and the PMOSFET region PR. The gates GA1, GA2, and GA3 may include a first gate GA1, a second gate GA2, and a third gate GA3 arranged in a second direction D2.

[0042] For example, the first gate GA1 may cross the NMOSFET region NR without crossing the PMOSFET region PR. The second gate GA2 may cross both the NMOSFET region NR and the PMOSFET region PR. The third gate GA3 may cross the PMOSFET region PR without crossing the NMOSFET region NR. The second gate GA2 may be disposed between the first gate GA1 and the third gate GA3.

[0043] The first signal A can be applied to the first gate GA1. The first signal A can be applied to the third gate GA3. The second signal A' can be applied to the second gate GA2. The second signal A' can be an inversion signal of the first signal A.

[0044] The first gate contact GC1, the second gate contact GC2, and the third gate contact GC3 can be electrically connected to the first gate GA1, the second gate GA2, and the third gate GA3, respectively. For example, the first region R1 can include three gates GA1, GA2, and GA3 and three gate contacts GC1, GC2, and GC3 respectively connected to the three gates GA1, GA2, and GA3. The second region R2 can include three gates GA1, GA2, and GA3 and three gate contacts GC1, GC2, and GC3 respectively connected to the three gates GA1, GA2, and GA3.

[0045] In a specific embodiment, the first region R1 can be Figure 1 , Figure 2 and Figure 4 a part of the second part P02 (e.g., the master latch) of the first flip - flop unit FF1 shown in Figure 1 , Figure 2 and Figure 4 The second region R2 can be a part of the third part P03 (e.g., the slave latch) of the first flip - flop unit FF1 shown in

[0046] For example, the first gate GA1 of the first region R1 can be the gate of the third transistor included in the fourth element E4 of the second part P02 shown in Figure 4 . The first gate GA1 of the second region R2 can include the gate of the third transistor included in the fourth element E4 of the third part P03 shown in Figure 4 . The second gate GA2 of the first region R1 can be the gate of the third transistor included in the third element E3 of the second part P02 shown in Figure 4 and the gate of the second transistor included in the fourth element E4 of the second part P02 shown in Figure 4 . The second gate GA2 of the second region R2 can include the gate of the third transistor included in the third element E3 of the third part P03 shown in Figure 4 and the gate of the second transistor included in the fourth element E4 of the third part P03 shown in Figure 4 . The third gate GA3 of the first region R1 can beFigure 4 The gate of the second transistor in the third element E3 of the second part P02 shown in. The third gate GA3 of the second region R2 may be included in, for example, Figure 4 The gate of the second transistor in the third element E3 of the third part P03 shown in.

[0047] In other embodiments, the first region R1 may be Figure 1 , Figure 2 and Figure 4 The second part P02 or the third part P03 of the second flip - flop unit FF2 shown in. The second region R2 may be Figure 1 , Figure 2 and Figure 4 The second part P02 or the third part P03 of the second flip - flop unit FF2 shown in.

[0048] In other embodiments, the first region R1 may be Figure 1 , Figure 2 and Figure 4 The first part P01 (e.g., the scan multiplexer) of the first flip - flop unit FF1 shown in. The second region R2 may be Figure 1 , Figure 2 and Figure 4 The first part P01 (e.g., the scan multiplexer) of the second flip - flop unit FF2 shown in. The first signal A applied to the first gate GA1 and the third gate GA3 may be the scan enable signal SE. The second signal A' applied to the second gate GA2 may be the scan enable inverse signal / SE. The scan enable inverse signal / SE may be the inverse signal of the scan enable signal SE.

[0049] For example, the first gate GA1 of the first region R1 may be the gate of the fourth transistor in the first element E1 of the first part P01 of the first flip - flop unit FF1 shown in, for example, Figure 3 . The first gate GA1 of the second region R2 may be the gate of the fourth transistor in the first element E1 of the first part P01 of the second flip - flop unit FF2 shown in, for example, Figure 3 . The second gate GA2 of the first region R1 may be the gate of the fourth transistor in the second element E2 of the first part P01 of the first flip - flop unit FF1 shown in, for example, Figure 3 and the gate of the second transistor in the first element E1 of the first part P01 of the first flip - flop unit FF1 shown in, for example, Figure 3 . The second gate GA2 of the second region R2 may be the gate of the fourth transistor in the second element E2 of the first part P01 of the second flip - flop unit FF2 shown in, for example, Figure 3 and the gate of the second transistor in the first element E1 of the first part P01 of the second flip - flop unit FF2 shown in, for example, Figure 3The gate of the second transistor in the first element E1 of the first part P01 of the second flip-flop unit FF2 shown. The third gate GA3 of the first region R1 can be the gate of the first transistor in the second element E2 of the first part P01 of the first flip-flop unit FF1 shown in Figure 3 The gate of the first transistor in the second element E2 of the first part P01 of the first flip-flop unit FF1 shown. The third gate GA3 of the second region R2 can be the gate of the first transistor in the second element E2 of the first part P01 of the second flip-flop unit FF2 shown in Figure 3 The gate of the first transistor in the second element E2 of the first part P01 of the second flip-flop unit FF2 shown.

[0050] The first gate contact GC1 and the third gate contact GC3 of the first region R1 and the first gate contact GC1 and the third gate contact GC3 of the second region R2 can be electrically connected to one or more first upper lines to which a first signal A is applied. Accordingly, the first gate GA1 and the third gate GA3 can be commonly applied with the first signal A applied from the one or more first upper lines.

[0051] The second gate contact GC2 of the first region R1 and the second gate contact GC2 of the second region R2 can be electrically connected to one or more second upper lines to which a second signal A' is applied. Accordingly, the second gate GA2 can be commonly applied with the second signal A' applied from the one or more second upper lines.

[0052] Figure 6 A plan view showing a first region and a second region of a semiconductor device presenting some example embodiments according to the inventive concept is shown. In the following embodiments, detailed descriptions of technical features that are repetitive with those discussed above Figure 5 will be omitted, and their differences will be discussed in detail.

[0053] Referring to Figures 1 to 4 and Figure 6 , the flip-flop according to the inventive concept can include a first region R1 and a second region R2 on a substrate. The second region R2 can be adjacent to the first region R1 in a first direction D1. The second region R2 of the present embodiment can be disposed adjacent to the first region R1 in a manner in which Figure 5 the second region R2 is inverted.

[0054] The first signal A can be commonly applied to the first gate GA1 of the first region R1 and the first gate GA1 of the second region R2. The first gate GA1 of the first region R1 and the first gate GA1 of the second region R2 can be connected to constitute a single first gate electrode.

[0055] The second signal A' can be commonly applied to the second gate GA2 of the first region R1 and the second gate GA2 of the second region R2. The second gate GA2 of the first region R1 and the second gate GA2 of the second region R2 can be connected to constitute a single second gate electrode.

[0056] The first gate contact GG1 and the second gate contact GC2 can be electrically connected to the first gate GA1 and the second gate GA2, respectively. The third gate contact GC3 can be electrically connected to the third gate GA3 in the first region R1. The fourth gate contact GC4 can be electrically connected to the third gate GA3 in the second region R2.

[0057] Since a single first gate electrode is composed of the first gate GA1 in the first region R1 and the first gate GA1 in the second region R2, the first region R1 and the second region R2 can be commonly applied with a first signal A through a single first gate contact GC1.

[0058] Since a single second gate electrode is composed of the second gate GA2 in the first region R1 and the second gate GA2 in the second region R2, the first region R1 and the second region R2 can be commonly applied with a second signal A' through a single second gate contact GC2.

[0059] The first gate contact GC1, the third gate contact GC3, and the fourth gate contact GC4 can be electrically connected to each other through one or more first upper lines applying the first signal A. The first gate GA1 and the third gate GA3 can be commonly applied with the first signal A applied from the one or more first upper lines. The second gate GA2 can be commonly applied with a second signal A' applied from one or more second upper lines.

[0060] For Figure 5 the embodiment shown in Figure 6 it may be necessary to have six gate electrodes and six gate contacts to apply the first signal A and the second signal A' to the first region R1 and the second region R2. For Figure 6 the embodiment shown in

[0061] Figure 7 it may be necessary to have four gate electrodes and four gate contacts to apply the first signal A and the second signal A' to the first region R1 and the second region R2. Thus, the placement change of the first region R1 and the second region R2 can reduce the number of gate electrodes and gate contacts. The number of upper lines for wiring can also be reduced due to the reduction in the number of gate contacts that should be electrically connected to the upper lines. This result can simplify the design of the connection lines for wiring. Additionally, this result can reduce the area of the connection lines for wiring, and thus, the semiconductor device can improve the integration degree. Figure 8A , Figure 8B , Figure 8C and Figure 8D respectively show cross-sectional views taken along Figure 7 the lines I-I', II-II', III-III', and IV-IV'. Figure 7 and Figures 8A to 8DThe semiconductor device shown therein can be an example in which Figures 2 to 4 and Figure 6 flip-flops are implemented on a substrate.

[0062] Referring to Figure 6 、 Figure 7 and Figures 8A to 8D , a substrate 100 can be provided. For example, the substrate 100 can be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate. A device isolation layer ST that defines a PMOSFET region PR and an NMOSFET region NR can be provided on the substrate 100. The PMOSFET region PR and the NMOSFET region NR can be defined by a second trench TR2 on the upper part of the substrate 100. The device isolation layer ST can fill the second trench TR2. For example, the device isolation layer ST can include a silicon oxide layer.

[0063] The PMOSFET region PR and the NMOSFET NR can be arranged in a first direction D1. Each of the PMOSFET region PR and the NMOSFET region NR can extend in a second direction D2 different from the first direction D1. For example, the longitudinal direction of each of the PMOSFET region PR and the NMOSFET region NR can be parallel to the second direction D2. The PMOSFET region PR and the NMOSFET region NR can be arranged in the first direction D1 in the following order: PMOSFET region PR, NMOSFET region NR, NMOSFET region NR, and PMOSFET region PR. Adjacent PMOSFET region PR and NMOSFET region NR can be spaced apart from each other in the first direction D1 through the device isolation layer ST.

[0064] The PMOSFET region PR can be provided with a plurality of first active patterns FN1 extending in the second direction D2 thereon. The NMOSFET region NR can be provided with a plurality of second active patterns FN2 extending in the second direction D2 thereon. The first active patterns FN1 and the second active patterns FN2 can be vertical protruding portions of the substrate 100. In an exemplary embodiment, the first active patterns FN1 and the second active patterns FN2 can grow epitaxially from the substrate 100, or can be patterned using an etching process. The first active patterns FN1 and the second active patterns FN2 can be arranged along the first direction D1.

[0065] For example, three first active patterns FN1 can extend side by side in the second direction D2 on the PMOSFET region PR. For example, three second active patterns FN2 can extend side by side in the second direction D2 on the NMOSFET region NR. The number and shape of the first active patterns FN1 and the second active patterns FN2 located on the PMOSFET region PR and the NMOSFET region NR respectively are exemplary and are not limited to the number and shape shown.

[0066] A plurality of first trenches TR1 may be defined between a pair of first active patterns FN1 and between a pair of second active patterns FN2. The first trenches TR1 may be disposed adjacent to each other in a first direction D1. The device isolation layer ST may also fill the first trenches TR1.

[0067] The upper portions of the first active pattern FN1 and the second active pattern FN2 may be higher than the top surface of the device isolation layer ST. The upper portions of the first active pattern FN1 and the second active pattern FN2 may protrude vertically with respect to the device isolation layer ST. The upper portion of each of the first active pattern FN1 and the second active pattern FN2 may be shaped to be similar to a fin protruding from the device isolation layer ST.

[0068] The upper portion of each first active pattern FN1 may include a first channel region CH1 and a first source / drain region SD1. The first source / drain region SD1 may be a p-type impurity region. Each first channel region CH1 may be interposed between a pair of first source / drain regions SD1. The upper portion of each second active pattern FN2 may include a second channel region CH2 and a second source / drain region SD2. The second source / drain region SD2 may be an n-type impurity region. Each second channel region CH2 may be interposed between a pair of second source / drain regions SD2.

[0069] The first source / drain region SD1 and the second source / drain region SD2 may be epitaxial patterns formed by a selective epitaxial growth process. The top surfaces of the first source / drain region SD1 and the second source / drain region SD2 may be higher than the top surfaces of the first channel region CH1 and the second channel region CH2.

[0070] For example, each first source / drain region SD1 may include a semiconductor element having a lattice constant greater than that of the semiconductor element of the substrate 100. As a result, the first source / drain region SD1 may provide a first channel region CH1 having compressive stress. For example, the second source / drain region SD2 may include the same semiconductor element as the semiconductor element of the substrate 100. For example, the first source / drain region SD1 may include silicon-germanium, and the second source / drain region SD2 may include silicon.

[0071] When viewed in cross-section along the first direction D1, each first source / drain region SD1 may have a cross-section different from that of each second source / drain region SD2 (see Figure 8D ).

[0072] Multiple gate electrodes GE may include a first gate electrode GE1, a second gate electrode GE2, and a third gate electrode GE3. The gate electrodes GE may be arranged to cross the first active pattern FN1 and the second active pattern FN2 and extend in a first direction D1. Each gate electrode GE may have a linear shape. The gate electrodes GE may be spaced apart from each other in a second direction D2. The gate electrodes GE may be arranged at regular intervals in the second direction D2.

[0073] The gate electrodes GE may be vertically stacked with the first channel region CH1 and the second channel region CH2. Each gate electrode GE may be disposed on the top surface and opposite sidewalls of the first channel region CH1 and the second channel region CH2 (see Figure 8C ). The gate electrodes GE may include, for example, one or more of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a metal (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0074] A pair of gate spacers GS may be disposed on opposite sidewalls of each gate electrode GE. The gate spacers GS may extend along the gate electrode GE in the first direction D1. The top surface of the gate spacers GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS may be coplanar with the top surface of a gate capping layer GP to be discussed below. For example, the gate spacers GS may include one or more of SiCN, SiCON, and SiN. For another example, the gate spacers GS may include a multi-layer composed of one or more of SiCN, SiCON, and SiN.

[0075] A gate dielectric layer GI may be interposed between the gate electrode GE and the first channel region CH1 and the second channel region CH2. Each gate dielectric layer GI may extend along the bottom surface of the corresponding one of the gate electrodes GE. Each gate dielectric layer GI may cover the top surface and opposite sidewalls of each of the first channel region CH1 and the second channel region CH2. The gate dielectric layer GI may include a high-k dielectric material having a dielectric constant higher than that of a silicon oxide layer. For example, the high-k dielectric material may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0076] A gate capping layer GP may be disposed on each gate electrode GE. The gate capping layer GP may extend along the gate electrode GE in the first direction D1. The gate capping layer GP may include a material having an etching selectivity with respect to a first interlayer dielectric layer 110 and a second interlayer dielectric layer 120 to be discussed below. For example, the gate capping layer GP may include one or more of SiON, SiCN, SiCON, and SiN.

[0077] The gate cut pattern GCP can be set to separate the gate electrode GE. The gate cut pattern GCP can be used to cut the gate electrode GE. For example, the gate cut pattern GCP can separate one gate electrode GE into two gate electrodes GE. The gate cut pattern GCP can include a dielectric material such as silicon oxide or silicon nitride.

[0078] A first interlayer dielectric layer 110, a second interlayer dielectric layer 120, and a third interlayer dielectric layer 130 can be sequentially stacked on the substrate 100 on the substrate 100. Each of the first interlayer dielectric layer 110, the second interlayer dielectric layer 120, and the third interlayer dielectric layer 130 can include a silicon oxide layer or a silicon oxynitride layer.

[0079] At least one active contact AC can be disposed between a pair of gate electrodes GE, which penetrates the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 and has an electrical connection with a first source / drain region SD1 and a second source / drain region SD2 between the pair of gate electrodes GE. Each active contact AC can have a linear shape extending in a first direction D1. For example, at least one active contact AC can be connected to a plurality of first source / drain regions SD1. For example, at least one active contact AC can be connected to a plurality of second source / drain regions SD2.

[0080] At least one of the plurality of gate contacts GC that penetrates the second interlayer dielectric layer 120 and the gate capping layer GP and has an electrical connection with at least one gate electrode GE can be disposed on at least one gate electrode GE. When viewed in a plane, the gate contact GC can be disposed between the PMOSFET region PR and the NMOSFET region NR. The gate contact GC can be vertically stacked with the device isolation layer ST that fills the second trench TR2 between the PMOSFET region PR and the NMOSFET region NR.

[0081] The active contact AC and the gate contact GC can include the same conductive material. The active contact AC and the gate contact GC can include at least one metal material, such as aluminum, copper, tungsten, molybdenum, and cobalt.

[0082] A first metal layer can be disposed in the third interlayer dielectric layer 130. The first metal layer can include interconnect lines IL and vias VI. Some of the interconnect lines IL can be used as a power supply line VDD, and some of the interconnect lines IL can be used as a ground line VSS. The interconnect lines IL can extend in a second direction D2. The power supply line VDD can be adjacent to the PMOSFET region PR. The ground line VSS can be adjacent to the NMOSFET region NR.

[0083] A via VI for electrically connecting the interconnect line IL and the active contact AC may be provided between the interconnect line IL and the active contact AC. The interconnect line IL and the via VI may include the same conductive material. For example, the interconnect line IL and the via VI may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, and cobalt.

[0084] Although not shown, additional metal layers (e.g., a second metal layer, a third metal layer, a fourth metal layer, etc.) may be provided on the first metal layer. The additional metal layers may include upper lines provided on the interconnect line IL. The first metal layer and the additional metal layers may allow the logic units of the semiconductor device to be connected to each other according to a designed circuit.

[0085] The semiconductor device according to some example embodiments of the inventive concept may include the first region R1 and the second region R2 discussed above with reference to Figure 6 The first region R1 and the second region R2 may be adjacent to each other in the first direction D1.

[0086] In a specific embodiment, each of the first region R1 and the second region R2 may include a master latch (e.g., the second part P02) of the first flip-flop unit FF1 and a slave latch (e.g., the third part P03) of the first flip-flop unit FF1.

[0087] In other embodiments, the first region R1 may include a master latch or a slave latch of the first flip-flop unit FF1, and the second region R2 may include a master latch or a slave latch of the second flip-flop unit FF2. The second flip-flop unit FF2 may be adjacent to the first flip-flop unit FF1 in the first direction D1.

[0088] In other embodiments, the first region R1 may include a scan multiplexer (e.g., the first part P01) of the first flip-flop unit FF1, and the second region R2 may include a scan multiplexer (e.g., the first part P01) of the second flip-flop unit FF2.

[0089] The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may be disposed on the first region R1 and the second region R2. The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may extend from the first region R1 in the first direction D1 toward the second region R2. The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may be arranged sequentially along the second direction D2. For example, each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may extend in the longitudinal direction of each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3. The longitudinal direction may be parallel to the first direction, and the first direction is different from the second direction of the longitudinal direction of each of the PMOSFET region PR and the NMOSFET region NR included in each of the first region R1 and the second region R2. The first region R1 and the second region R2 may be arranged in the first direction D1.

[0090] The first gate electrode GE1 may include a pair of gate cut patterns GCP and a first gate GA1 located between the pair of gate cut patterns GCP. The first gate GA1 may cross the NMOSFET region NR of the first region R1 and the NMOSFET region NR of the second region R2. For example, the first gate GA1 may be commonly connected to the NMOS transistor of the first region R1 and the NMOS transistor of the second region R2.

[0091] The second gate electrode GE2 may include a second gate GA2 that crosses the PMOSFET region PR and the NMOSFET region NR of the first region R1 and also crosses the PMOSFET region PR and the NMOSFET region NR of the second region R2. For example, the second gate GA2 may be commonly connected to the PMOS transistor of the first region R1, the NMOS transistor of the first region R1, the NMOS transistor of the second region R2, and the PMOS transistor of the second region R2.

[0092] The third gate electrode GE3 may include a third gate GA3 on the first region R1, a third gate GA3 on the second region R2, a dummy gate DE, and a pair of gate cut patterns GCP. The third gate GA3 on the first region R1 may cross the PMOSFET region PR of the first region R1, and the third gate GA3 on the second region R2 may cross the PMOSFET region PR of the second region R2. For example, the third gate GA3 on the first region R1 may be connected to the PMOS transistor of the first region R1, and the third gate GA3 on the second region R2 may be connected to the PMOS transistor of the second region R2. The dummy gate DE may cross the NMOSFET region NR of the first region R1 and the NMOSFET region NR of the second region R2.

[0093] One of the pair of gate cutting patterns GCP may be inserted between the dummy gate DE and the third gate GA3 on the first region R1. The other of the pair of gate cutting patterns GCP may be inserted between the dummy gate DE and the third gate GA3 on the second region R2. The third gate GA3 on the first region R1, the dummy gate DE, and the third gate GA3 on the second region R2 may be aligned with each other in the first direction D1. The pair of gate cutting patterns GCP may separate the dummy gate DE from the third gate GA3.

[0094] The gate contact GC may include a first gate contact GC1, a second gate contact GC2, and a third gate contact GC3. The first gate contact GC1 and the second gate contact GC2 may be respectively disposed on the first gate GA1 and the second gate GA2. The third gate contact GC3 may be disposed on the third gate GA3 of the first region R1, and the fourth gate contact GC4 may be disposed on the third gate GA3 of the second region R2.

[0095] The interconnection line IL may be disposed on the first gate contact GC1 to the fourth gate contact GC4. For example, the first gate contact GC1 and the third gate contact GC3 may be commonly connected to a single interconnection line IL. The interconnection line IL and the first gate contact GC1 to the fourth gate contact GC4 may provide a first signal A to the first gate GA1 and the third gate GA3, and may also provide a second signal A', which is an inverted signal of the first signal A, to the second gate GA2.

[0096] When the first region R1 and the second region R2 respectively include a master latch and a slave latch, the first signal A may be a clock signal CLK, and the second signal A' may be a clock inverted signal / CLK. When the first region R1 and the second region R2 include scan multiplexers of adjacent flip-flop units, the first signal A may be a scan enable signal SE, and the second signal A' may be a scan enable inverted signal / SE.

[0097] Figure 9 A plan view showing a first region, a second region, and a third region of a semiconductor device presenting some example embodiments according to the inventive concept is shown. In the following embodiments, detailed descriptions of technical features that are repetitive with the technical features discussed above will be omitted, and their differences will be discussed in detail. Figure 6 discussed will be omitted, and their differences will be discussed in detail.

[0098] Referring to Figures 1 to 4 and Figure 9, the flip-flop of the inventive concept may include a first region R1 and a second region R2, and further include a third region R3 on a substrate. The first region R1, the second region R2, and the third region R3 may be arranged in a first direction D1. The third region R3 may be adjacent to the second region R2 in the first direction D1. The third region R3 may have a shape that is substantially the same as or similar to the shape of the first region R1.

[0099] The second signal A' may be commonly applied to the second gate GA2 of the first region R1 and the second region R2 and the second gate GA2 of the third region R3. The second gates GA2 of the first region R1, the second region R2, and the third region R3 may be connected to each other to form a single second gate electrode.

[0100] The first signal A may be commonly applied to the third gate GA3 of the second region R2 and the third gate GA3 of the third region R3, the first gate GA1 of the first region R1, and the first gate GA1 of the second region R2. The third gate GA3 of the second region R2 and the third gate GA3 of the third region R3 may be connected to each other to form a single third gate electrode. The first signal A may also be applied to the third gate GA3 of the first region R1 spaced apart from the third gate GA3 of the second region R2 and the third gate GA3 of the third region R3. The first signal A may also be applied to the first gate GA1 of the third region R3 spaced apart from the first gate GA1 of the first region R1 and the first gate GA1 of the second region R2.

[0101] The first gate contact GC1 may be electrically connected to the first gate GA1 of the first region R1. The second gate contact GC2 may be electrically connected to the second gate GA2 of the first region R1, the second region R2, and the third region R3. The third gate contact GC3 may be electrically connected to the third gate GA3 of the first region R1. The fourth gate contact GC4 may be electrically connected to the third gate GA3 of the second region R2 and the third region R3. The fifth gate contact GC5 may be electrically connected to the first gate GA1 of the third region R3.

[0102] The first gate contact GC1, the third gate contact GC3, the fourth gate contact GC4, and the fifth gate contact GC5 may be electrically connected to each other through one or more first upper lines. The first signal A applied from the one or more first upper lines may be commonly applied to the first gate GA1 and the third gate GA3. The second signal A' from one or more second upper lines may be commonly applied to the second gate contact GC2.

[0103] In a particular embodiment, five gate electrodes and five gate contacts may be required to apply the first signal A and the second signal A' to the first region R1, the second region R2, and the third region R3. Thus, the number of gate electrodes and gate contacts can be reduced compared to a case where the first region R1, the second region R2, and the third region R3 are spaced apart independently of each other.

[0104] Figure 10 A plan view showing a first region and a second region of a semiconductor device presenting some example embodiments according to the inventive concept is shown. In the following embodiments, detailed descriptions of technical features that are repetitive of the technical features discussed above will be omitted, and their differences will be discussed in detail. Figure 6 A detailed description of technical features that are repetitive of the technical features discussed above will be omitted, and their differences will be discussed in detail.

[0105] Referring to Figures 1 to 4 and Figure 10 , the jumper JP can be disposed on the first region R1 and the second region R2. The jumper JP can be disposed on the first gate GA1 of the PMOSFET region PR on the first region R1, and can also be disposed on the first gate GA1 of the PMOSFET region PR on the second region R2. The jumper JP can be disposed on the third gate GA3 of the NMOSFET region NR on the first region R1, and can also be disposed on the third gate GA3 of the NMOSFET region NR on the second region R2.

[0106] The jumper JP can be electrically connected to the source region SR and the drain region DR located on the opposite side of the gate electrode. For example, the jumper JP on the first gate GA1 of the PMOSFET region PR on the first region R1 can be electrically connected to the source region SR and the drain region DR located on the opposite side of the first gate GA1.

[0107] Since the jumper JP electrically connects the source region SR and the drain region DR of the transistor, the effect of substantially omitting the transistor may occur. For example, a transistor having the jumper JP may no longer operate as a transistor. The gate electrode under the jumper JP may be similar to a dummy gate that does not have the function of a gate of a transistor. For example, the jumper JP can be used to cut off (delete) the gate electrode.

[0108] The semiconductor device can include a patterned first gate GA1 and a third gate GA3 (see Figure 6 ). Therefore, a patterning process may be required to pattern the first gate GA1 and the third gate GA3. For example, referring to Figure 7 and Figures 8A to 8D , the first gate electrode GE1 can be patterned to form a pair of gate cut patterns GCP to implement the first gate GA1. In a particular embodiment, when the jumper JP is used, patterning of the first gate GA1 and the third gate GA3 may not be required.

[0109] In a particular embodiment, when the third gate GA3 of the first region R1 is separated from the third gate GA3 of the second region R2, a third gate contact GC3 may be required to be disposed on the third gate GA3 of the first region R1 and a fourth gate contact GC4 may also be disposed on the third gate GA3 of the second region R2 (see Figure 6)。In other embodiments, the third gate GA3 may continuously extend from the first region R1 toward the second region R2. The third gate GA3 in the first region R1 and the third gate GA3 in the second region R2 may be connected to each other to form a single third gate electrode, and as a result, the fourth gate contact GC4 may be omitted. For example, three gate electrodes and three gate contacts may be required to apply the first signal A and the second signal A' to the first region R1 and the second region R2 (see Figure 10 )。

[0110] Figure 11 FIG. shows a plan view of a semiconductor device presenting some example embodiments according to the inventive concept. Figure 12A and Figure 12B show cross-sectional views taken along line I-I' and line II-II', respectively. Figure 11 of Figure 11 、 Figure 12A and Figure 12B The semiconductor device shown in may be an example in which the flip-flops of Figures 2 to 4 and Figure 10 are implemented on a substrate. In the following embodiments, detailed descriptions of technical features that are repetitive of those discussed previously with reference to Figure 7 and Figures 8A to 8D will be omitted, and their differences will be discussed in detail.

[0111] Referring to Figure 10 、 Figure 11 、 Figure 12A and Figure 12B , compared with the exemplary embodiment of Figure 7 , the gate cut pattern GCP may be omitted. The jumper JP may be disposed on the first gate GA1 of the PMOSFET region PR on the first region R1, and may also be disposed on the first gate GA1 of the PMOSFET region PR on the second region R2. The jumper JP may be disposed on the third gate GA3 of the NMOSFET region NR on the first region R1, and may also be disposed on the third gate GA3 of the NMOSFET region NR on the second region R2.

[0112] The jumper JP may be disposed in the second interlayer dielectric layer 120. The gate capping layer GP may separate the jumper JP from the gate electrode GE. The jumper JP may be disposed on a pair of active contacts AC on the opposite side of the gate electrode GE. The jumper JP may electrically connect the pair of active contacts AC to each other. The jumper JP may be used to render the transistor thereunder inoperable. For example, the jumper JP may include the same metal material as the metal material of the active contact AC.

[0113] According to the inventive concept, a semiconductor device may be configured such that gate electrodes on a plurality of regions are formed as a single gate electrode to commonly apply a signal to the plurality of regions. The number of upper lines for wiring may be reduced due to the reduction in the number of gate electrodes and gate contacts. As a result, the area of connection lines for wiring may be reduced, and thus the semiconductor device may have improved integration.

[0114] Although the present invention has been described in conjunction with some exemplary embodiments of the inventive concept shown in the drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and basic features of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and changes can be made without departing from the scope and spirit of the inventive concept.

Claims

1. A semiconductor device, comprising: A substrate, which includes a first region and a second region adjacent to the first region in a first direction; And A first gate electrode, a second gate electrode, and a third gate electrode extending from the first region toward the second region, Wherein each of the first region and the second region includes a P-type metal-oxide-semiconductor field-effect transistor region and an N-type metal-oxide-semiconductor field-effect transistor region adjacent to the P-type metal-oxide-semiconductor field-effect transistor region in the first direction, Wherein each of the first gate electrode, the second gate electrode, and the third gate electrode extends in the first direction such that each of the first gate electrode, the second gate electrode, and the third gate electrode extends longitudinally in the first direction, Wherein each of the P-type metal-oxide-semiconductor field-effect transistor region and the N-type metal-oxide-semiconductor field-effect transistor region extends longitudinally in a second direction different from the first direction, Wherein the second gate electrode is inserted between the first gate electrode and the third gate electrode in the second direction, Wherein the first gate electrode and the third gate electrode are configured to receive a first signal, and the second gate electrode is configured to receive a second signal that is an inverted signal of the first signal, Wherein the first gate electrode includes a first gate of the first region and a first gate of the second region, and the first gate of the first region and the first gate of the second region are aligned and connected to each other in the first direction, Wherein the third gate electrode includes a third gate of the first region and a third gate of the second region, Wherein the third gate of the first region and the third gate of the second region are spaced apart from each other in the first direction, and The first signal is commonly applied to the third gate of the first region and the third gate of the second region.

2. The semiconductor device according to claim 1, further comprising: A gate contact electrically connected to the first gate electrode, Wherein the first signal is commonly applied to the first gate of the first region and the first gate of the second region through the gate contact.

3. The semiconductor device according to claim 1, wherein, The first gate of the first region and the first gate of the second region respectively include the gate of the N-type metal-oxide-semiconductor transistor of the first region and the gate of the N-type metal-oxide-semiconductor transistor of the second region.

4. The semiconductor device according to claim 1, further comprising: A gate contact electrically connected to the second gate electrode, Wherein the second gate electrode includes a second gate of the first region and a second gate of the second region, the second gate of the first region and the second gate of the second region are aligned and connected to each other in the first direction, and Wherein the second signal is commonly applied to the second gate of the first region and the second gate of the second region through the gate contact.

5. The semiconductor device according to claim 4, wherein, The second gates of the first region and the second region include the gate of the P-type metal-oxide-semiconductor transistor of the first region, the gate of the N-type metal-oxide-semiconductor transistor of the first region, the gate of the N-type metal-oxide-semiconductor transistor of the second region, and the gate of the P-type metal-oxide-semiconductor transistor of the second region.

6. The semiconductor device according to claim 1, further comprising: A first gate contact and a second gate contact electrically connected to the third gate electrode, wherein, the first signal is applied to a third gate of the first region through the first gate contact, and wherein, the first signal is applied to a third gate of the second region through the second gate contact.

7. The semiconductor device according to claim 1, wherein, The third gate electrode further includes: a dummy gate located between the third gate of the first region and the third gate of the second region; a first gate cut pattern located between the third gate of the first region and the dummy gate; and a second gate cut pattern located between the third gate of the second region and the dummy gate.

8. The semiconductor device according to claim 1, further comprising: a first jumper located on the third gate electrode of an N-type metal oxide field effect transistor region on the first region, wherein the first jumper connects a first source / drain region of the N-type metal oxide field effect transistor on the first region to a second source / drain region of the N-type metal oxide field effect transistor on the first region; and a second jumper located on the third gate electrode of an N-type metal oxide field effect transistor region on the second region, wherein the second jumper connects a first source / drain region of the N-type metal oxide field effect transistor on the second region to a second source / drain region of the N-type metal oxide field effect transistor on the second region.

9. The semiconductor device according to claim 1, wherein, The first region includes a master latch of a flip-flop unit, and the second region includes a slave latch of the flip-flop unit.

10. The semiconductor device according to claim 1, wherein, The substrate includes a first flip-flop unit and a second flip-flop unit adjacent to the first flip-flop unit in the first direction, the first region includes a scan multiplexer of the first flip-flop unit, and the second region includes a scan multiplexer of the second flip-flop unit.

11. A semiconductor device, comprising: a flip-flop unit located on a substrate, the flip-flop unit including a first region including a master latch and a second region including a slave latch, the second region being adjacent to the first region in a first direction; and a first gate electrode, a second gate electrode, and a third gate electrode extending from the first region toward the second region and sequentially arranged in a second direction different from the first direction, a first gate contact overlapping with and electrically connected to the first gate electrode; a second gate contact overlapping with and electrically connected to the second gate electrode; wherein each of the first gate electrode, the second gate electrode, and the third gate electrode extends in the first direction, wherein a clock signal is applied to the first gate electrode and the third gate electrode, and a clock inverted signal, which is an inverted phase signal of the clock signal, is applied to the second gate electrode, and wherein the second gate electrode includes gates of P-type metal oxide semiconductor transistors in the first region, gates of N-type metal oxide semiconductor transistors in the first region, gates of N-type metal oxide semiconductor transistors in the second region, and gates of P-type metal oxide semiconductor transistors in the second region, wherein the clock signal is commonly applied to the first gate electrode through the first gate contact; and Among them, the clock inverted signal is commonly applied to the P-type metal oxide semiconductor transistors in the first region, the N-type metal oxide semiconductor transistors in the first region, the N-type metal oxide semiconductor transistors in the second region, and the P-type metal oxide semiconductor transistors in the second region through the second gate contact.

12. The semiconductor device according to claim 11, wherein, The second gate electrode has a straight shape.

13. The semiconductor device according to claim 11, wherein, The first gate electrode includes the gates of the N-type metal oxide semiconductor transistors in the first region and the gates of the N-type metal oxide semiconductor transistors in the second region.

14. The semiconductor device according to claim 11, wherein, The third gate electrode includes the third gate in the first region and the third gate in the second region. Among them, the third gate in the first region includes the gates of the P-type metal oxide semiconductor transistors in the first region, and the third gate in the second region includes the gates of the P-type metal oxide semiconductor transistors in the second region, and Among them, the third gate in the first region and the third gate in the second region are spaced apart from each other in the first direction.

15. A semiconductor device, comprising: A first flip-flop unit and a second flip-flop unit adjacent to each other in the first direction on a substrate; And A first gate electrode, a second gate electrode, and a third gate electrode extending from the first flip-flop unit toward the second flip-flop unit and sequentially arranged in a second direction different from the first direction. Among them, each of the first gate electrode, the second gate electrode, and the third gate electrode extends in the first direction. Among them, a scan enable signal is applied to the first gate electrode and the third gate electrode, and a scan enable inverted signal, which is an inverted signal of the scan enable signal, is applied to the second gate electrode, and Among them, the second gate electrode connects the gates of the P-type metal oxide semiconductor transistors in the first flip-flop unit, the gates of the N-type metal oxide semiconductor transistors in the first flip-flop unit, the gates of the N-type metal oxide semiconductor transistors in the second flip-flop unit, and the gates of the P-type metal oxide semiconductor transistors in the second flip-flop unit and extends in the first direction without a gate cut pattern. The first gate electrode connects the gates of the N-type metal oxide semiconductor transistors in the first flip-flop unit and the gates of the N-type metal oxide semiconductor transistors in the second flip-flop unit, and does not include the gates of the P-type metal oxide semiconductor transistors in the first flip-flop unit and the gates of the P-type metal oxide semiconductor transistors in the second flip-flop unit.

16. The semiconductor device according to claim 15, wherein, The third gate electrode includes the gates of the P-type metal oxide semiconductor transistors in the first flip-flop unit and the gates of the P-type metal oxide semiconductor transistors in the second flip-flop unit, and does not include the gates of the N-type metal oxide semiconductor transistors in the first flip-flop unit and the gates of the N-type metal oxide semiconductor transistors in the second flip-flop unit, and Among them, the second gate electrode has a straight shape.

17. The semiconductor device according to claim 15, wherein, The scan enable signal is commonly applied to the gates of the N-type metal oxide semiconductor transistors in the first flip-flop unit and the gates of the N-type metal oxide semiconductor transistors in the second flip-flop unit.

18. The semiconductor device according to claim 15, wherein, The third gate electrode further includes two gate cutting patterns and a dummy gate located between the two gate cutting patterns, and wherein the dummy gate extends from the N-type metal oxide semiconductor transistor of the first flip-flop unit to the N-type metal oxide semiconductor transistor of the second flip-flop unit.

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