Method of manufacturing vertical memory device

Abstract

In a method of fabricating a vertical memory device, a first sacrificial layer including nitride is formed on a substrate. A mold including alternating and repetitive stacks of insulating layers and second sacrificial layers is formed on the first sacrificial layer. The insulating layers and the second sacrificial layers include first oxides and second oxides, respectively. A trench is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A trench connection pattern is formed to fill the first gap. The second sacrificial layers are replaced with gate electrodes.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0148338, filed on November 27, 2018, with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a method for manufacturing a vertical memory device. Background Technology

[0004] To connect channels to a substrate in a VNAND flash memory device, channel vias can be formed using a die to expose the upper surface of the substrate. The die includes insulating and sacrificial layers alternately stacked on the substrate. The exposed upper surface of the substrate can be used as a seed to perform a selective epitaxial growth (SEG) process to form a semiconductor pattern, and channels can be formed on the semiconductor pattern. However, semiconductor patterns can have characteristic distributions, such as height distributions, and especially in COP structures where circuit patterns can be formed below the memory cell array, using a polysilicon layer as a seed to perform an SEG process on the circuit pattern can make uniform semiconductor pattern formation difficult. Summary of the Invention

[0005] An example embodiment provides a method for manufacturing a vertical memory device with improved characteristics.

[0006] According to some embodiments of the present invention, a method for manufacturing a vertical memory device is provided. In this method, a first sacrificial layer comprising a nitride may be formed on a substrate. A mold may be formed on the first sacrificial layer, the mold comprising alternating and repeatedly stacked insulating and second sacrificial layers. The insulating and second sacrificial layers may respectively comprise a first oxide and a second oxide. A channel may be formed through the mold and the first sacrificial layer. An opening may be formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer may be removed through the opening to form a first gap. A channel connection pattern may be formed to fill the first gap. A second sacrificial layer may be replaced by a gate electrode.

[0007] According to some embodiments of the present invention, a method for manufacturing a vertical memory device is provided. In this method, a mold comprising alternating and repeatedly stacked insulating layers and a first sacrificial layer may be formed on a substrate. The insulating layer may comprise silicon oxide, and the first sacrificial layer may comprise germanium oxide or germanium-doped silicon oxide. Channels may be formed through the mold. Openings may be formed through the mold to expose the upper surface of the substrate. The first sacrificial layer may be removed through the openings to form a first gap. A gate electrode may be formed in the first gap.

[0008] According to some embodiments of the present invention, a method for manufacturing a vertical memory device is provided. In this method, a first sacrificial layer comprising a nitride may be formed on a substrate. A mold comprising alternating and repeatedly stacked insulating and second sacrificial layers may be formed on the first sacrificial layer. The insulating layer may comprise silicon oxide, and the second sacrificial layer may comprise germanium oxide or germanium-doped silicon oxide. Channels may be formed through the mold and the first sacrificial layer. Openings may be formed through the mold and the first sacrificial layer to expose the upper surface of the substrate. The first sacrificial layer may be removed through the openings to form gaps. Channel connection patterns may be formed to fill the gaps. The second sacrificial layer may be replaced by a gate electrode.

[0009] In a method for manufacturing a vertical memory device, when a first sacrificial layer for forming a channel connection pattern is removed by extending through an opening in a mold comprising an insulating layer and a second sacrificial layer, the first sacrificial layer may comprise a material with high etch selectivity relative to the insulating layer and the second sacrificial layer of the mold, thus preventing the formation of an etch stop pattern covering the sidewalls of the opening. Therefore, the channel connection pattern can be formed with a reduced number of processes.

[0010] Specifically, when the gate electrode is formed by removing the second sacrificial layer, the second sacrificial layer may not include nitrides, so no CN residues are generated during the removal of the second sacrificial layer, and the characteristics of the channel are prevented from degrading. Attached Figure Description

[0011] Figures 1 to 16 These are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device according to an example embodiment; and

[0012] Figures 17 to 21 This is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to an example embodiment. Detailed Implementation

[0013] It should be noted that although not specifically described in this regard, aspects of the inventive concept described in one embodiment may be incorporated into different embodiments. That is, features of all and / or any embodiment may be combined in any manner and / or combination. These and other objects and / or aspects of the inventive concept are described in detail in the following description. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When appearing after a list of elements, expressions such as "at least one of" modify the entire list of elements without modifying any individual element in the list.

[0014] The above and other aspects and features of the vertical memory device and its manufacturing method according to the exemplary embodiments will become readily understood from the following detailed description with reference to the accompanying drawings. Hereinafter, a direction substantially perpendicular to the upper surface of the substrate may be defined as a first direction, and two directions substantially parallel to the upper surface of the substrate and intersecting each other may be defined as a second direction and a third direction, respectively. In the exemplary embodiment, the second direction and the third direction may be substantially perpendicular to each other. It will be understood that although the terms first, second, third, etc., are used herein to describe various elements, and the elements should not be limited by these terms; rather, these terms are used only to distinguish one element from another. Therefore, the first element discussed may be referred to as the second element without departing from the scope of the inventive concept.

[0015] Figures 1 to 16 These are plan and cross-sectional views illustrating a method of manufacturing a vertical memory device according to an example embodiment. Specifically, Figure 1 , Figure 4 , Figure 7 and Figure 15 It is a floor plan, and Figures 2 to 3 , Figures 5 to 6 , Figures 8 to 14 and Figure 16 These are cross-sectional views taken along line A-A' of the corresponding plan view.

[0016] Reference Figure 1 and Figure 2 The pad 110 and the first sacrificial layer 120 may be stacked sequentially on the substrate 100. The pad 110 and the first sacrificial layer 120 may be partially removed to form a support pattern 130 on the substrate 100, and a support layer 140 may be formed on the first sacrificial layer 120 and the support pattern 130.

[0017] The substrate 100 may include silicon, germanium, silicon-germanium, or group II or IV compounds such as GaP, GaAs, and GaSb. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0018] The padding layer 110 may include an oxide, such as silicon oxide, and the first sacrificial layer 120 may include a nitride, such as silicon nitride.

[0019] In an example embodiment, the support pattern 130 and support layer 140 may comprise a material having etch selectivity relative to the first sacrificial layer 120, such as doped or undoped polysilicon. However, the support pattern 130 and support layer 140 may be formed by forming amorphous silicon and annealing the amorphous silicon to comprise polysilicon. In some embodiments, the support pattern 130 and support layer 140 may be formed such that the amorphous silicon may be crystallized by the heat generated by the deposition process of other layers.

[0020] The support pattern 130 can be formed by the following steps: partially removing the pad 110 and the first sacrificial layer 120 to form a first opening and filling the first opening. Therefore, the upper surface of the support pattern 130 may have a height substantially coplanar with the upper surface of the structure including the pad 110 and the first sacrificial layer 120. The sidewalls of the support pattern 130 may contact the sidewalls of the pad 110 and the first sacrificial layer 120.

[0021] The support pattern 130 may overlap with the area where the second opening 290 may be formed, which will refer to Figure 7 and Figure 8 As shown. The second opening 290 may extend in the second direction, and a plurality of second openings 290 may be formed in the third direction. Therefore, one or more support patterns 130 may be formed in the second direction, and a plurality of support patterns 130 may be formed in the third direction.

[0022] Reference Figure 3 The insulating layer 160 and the second sacrificial layer 170 may be alternately and repeatedly formed on the support layer 140 to form a mold.

[0023] The insulating layer 160 may include an oxide, such as silicon oxide, and the second sacrificial layer 170 may include a material different from the materials of the insulating layer 160 and the first sacrificial layer 120. In an example embodiment, the second sacrificial layer 170 may include a material having etch selectivity relative to the silicon oxide of the insulating layer 160 and the silicon nitride of the first sacrificial layer 120, respectively. Therefore, the second sacrificial layer 170 may include, for example, germanium oxide (GeO2) or germanium-doped silicon oxide (Ge-doped SiO2).

[0024] Specifically, when the second sacrificial layer 170 includes germanium oxide, the first etch selectivity of the second sacrificial layer 170 relative to the insulating layer 160 including, for example, silicon oxide may be greater than the second etch selectivity of the first sacrificial layer 120 including, for example, silicon nitride relative to the insulating layer 160 including silicon oxide.

[0025] For example, the insulating layer 160 and the second sacrificial layer 170 can be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0026] Reference Figure 4 and Figure 5 The first interlayer insulating layer 180 can be formed on the uppermost insulating layer 160, and a channel hole 190 can be formed through the first interlayer insulating layer 180, the mold, the support layer 140, the first sacrificial layer 120 and the pad layer 110 by a dry etching process.

[0027] The first interlayer insulating layer 180 may include oxides, such as silicon oxide.

[0028] In an example embodiment, a dry etching process may be performed until the upper surface of the substrate 100 is exposed, and the upper part of the substrate 100 may also be removed during the dry etching process.

[0029] In an example embodiment, a plurality of channel holes 190 may be formed in each of the second and third directions, thus defining a channel hole array. The channel holes may be arranged in multiple rows and columns, staggered from each other in the second direction, such as... Figure 4 As shown. In some embodiments, the channel aperture may be aligned in both the second direction and the third direction.

[0030] Reference Figure 6 The charge storage structure 230, the channel 240, the filling pattern 250 and the capping pattern 260 can be formed in the channel hole 190.

[0031] Specifically, the charge storage structure layer and the channel layer can be formed sequentially in... Figure 5 The sidewalls of the channel hole 190, the exposed upper surface of the substrate 100, and the upper surface of the first interlayer insulating layer 180 are all exposed. A fill layer may be formed on the channel layer to fill the remaining portion of the channel hole 190. The fill layer, channel layer, and charge storage structure layer may be planarized until the upper surface of the first interlayer insulating layer 180 is exposed.

[0032] In an example embodiment, the planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0033] Through a planarization process, charge storage structures 230 and channels 240 can be formed in sequence on the sidewalls of the channel hole 190 and the upper surface of the substrate 100, and the filling pattern 250 can fill the inner space formed through the channel 240.

[0034] As the channel hole 190 forming the channel 240 can define the channel hole array, the channel 240 in the channel hole 190 can also define the channel array.

[0035] In an example embodiment, the charge storage structure 230 may include a first barrier pattern 200, a charge storage pattern 210, and a tunnel insulating pattern 220 stacked in sequence. For example, the first barrier pattern 200, the charge storage pattern 210, and the tunnel insulating pattern 220 may each include silicon oxide, silicon nitride, and silicon oxide, respectively.

[0036] For example, the channel 240 may include undoped polysilicon, and the filling pattern 250 may include oxides, such as silicon oxide.

[0037] The top of the fill pattern 250, the channel 240 and the charge storage structure 230 can be removed to form a recess. A capping layer can be formed on the first interlayer insulating layer 180 to fill the recess, and the capping layer can be planarized until the upper surface of the first interlayer insulating layer 180 is exposed to form a capping pattern 260.

[0038] Reference Figure 7 and Figure 8 The second interlayer insulating layer 270 can be formed on the first interlayer insulating layer 180 and the capping pattern 260. The second opening 290 can be formed by dry etching through the first interlayer insulating layer 180 and the second interlayer insulating layer 270, the mold, the support layer 140, the first sacrificial layer 120 and the pad layer 110.

[0039] In an example embodiment, a dry etching process may be performed until the upper surface of the substrate 100 is exposed, and / or the upper surface of the support pattern 130 may also be exposed. Additionally, the upper portions of the substrate 100 and the support pattern 130 may be removed during the dry etching process. With the formation of the second opening 290, the first sacrificial layer 120, as well as the mold's insulating layer 160 and the second sacrificial layer 170, may be exposed.

[0040] In an example embodiment, the second opening 290 may extend in the second direction, and a plurality of second openings 290 may be formed in the third direction. With the formation of the second openings 290, the insulating layer 160 may become an insulating pattern 165 extending in the second direction, and the second sacrificial layer 170 may become a second sacrificial pattern 175 extending in the second direction.

[0041] Reference Figure 9 The first sacrificial layer 120 exposed through the second opening 290 can be removed to form the first gap 310.

[0042] Therefore, the sidewalls of the support pattern 130 and a portion of the sidewalls of the charge storage structure 230 can be exposed through the first gap 310.

[0043] In an example embodiment, the first sacrificial layer 120 can be removed by a wet etching process using a solution comprising phosphoric acid or sulfuric acid. During the wet etching process, the insulating pattern 165 and the second sacrificial pattern 175 of the mold can be exposed through the second opening 290. However, each of the insulating pattern 165 comprising, for example, silicon oxide and the second sacrificial pattern 175 comprising, for example, germanium oxide, may be etch-selective relative to the first sacrificial layer 120, and therefore may not be damaged by the wet etching process. Therefore, it is not necessary to form an etch stop pattern to protect the mold by covering the sidewalls of the second opening 290 before the wet etching process, thus simplifying the process.

[0044] In an example embodiment, when the first gap 310 is formed by a wet etching process, the mold may not collapse due to the support pattern 130 and the support layer 140.

[0045] The portion of the charge storage structure 230 exposed through the first gap 310 can be removed to expose the outer wall of the channel 240 covered by the charge storage structure 230. The pad 110 on the substrate 100 can also be removed.

[0046] The exposed portions of the charge storage structure 230 can be removed, for example, by a wet etching process. The charge storage structure 230 and the pad layer 110 can have a thin thickness, so that other layers of the mold, such as the insulating pattern 165, can be avoided when performing the wet etching process.

[0047] The wet etching process can be isotropic, so not only the portion of the charge storage structure 230 exposed through the first gap 310, but also the portion of the charge storage structure 230 whose contact support layer 140 faces the outer sidewall of the channel 240 can be partially removed. However, the portion of the charge storage structure 230 whose contact support layer 140 is on the upper sidewall and the portion of the charge storage structure 230 that is adjacent to the sidewall of the support layer 140 and contacts the channel 240 can be retained.

[0048] Through a wet etching process, the portion of the charge storage structure 230 that passes through the upper part of the substrate 100 can be separated from the portion that passes through the mold.

[0049] Reference Figure 10 A channel connection layer 320 can be formed to fill the first gap 310. According to some embodiments, the channel connection layer 320 can partially fill the first gap 310.

[0050] The channel connection layer 320 can fill the first gap 310 and can also be formed on the sidewalls and bottom of the second opening 290 and on the upper surface of the second interlayer insulation layer 270.

[0051] For example, the channel connection layer 320 may include polysilicon doped with n-type impurities.

[0052] Reference Figure 11 The channel connection layer 320 may be partially removed to form a channel connection pattern 325 in the first gap 310.

[0053] In an example embodiment, the channel connection pattern 325 can be formed by removing a portion of the channel connection layer 320 in the second opening 290 through a back etching process.

[0054] As the channel connection pattern 325 is formed, the channels 240 forming the channel array can be connected to each other.

[0055] Impurities can be implanted in the upper portion of the substrate 100 exposed through the second opening 290 to form an impurity region 105. In an example embodiment, the impurity region 105 may contact the lower surface of the channel connection pattern 325, and thus be electrically connected to the channel connection pattern 325 comprising doped polysilicon.

[0056] Reference Figure 12 The second sacrificial pattern 175 exposed through the second opening 290 can be removed to form a second gap 340 at one or more horizontal heights between the insulating patterns 165, and the outer wall of the first blocking pattern 200 can be partially exposed through the second gap 340.

[0057] In an example embodiment, the second sacrificial pattern 175 can be removed by a wet etching process using an etching solution comprising SC1 (a mixture of NH4OH:H2O2:H2O). The second sacrificial pattern 175 may comprise a material that is etch-selective relative to an insulating pattern 165 comprising, for example, silicon oxide, and a channel connection pattern 325 comprising, for example, polysilicon, and a support layer 140. It may be, for example, germanium oxide (GeO2) or germanium-doped silicon oxide (Ge-doped SiO2), so that the insulating pattern 165, the channel connection pattern 325, and the support layer 140 exposed by the second opening 290 may not be damaged during the wet etching process.

[0058] Specifically, germanium oxide included in the second sacrificial pattern 175 may have a higher etch selectivity relative to silicon oxide included in the insulating pattern 165, which may be greater than the etch selectivity of silicon nitride relative to silicon oxide. Therefore, the second sacrificial pattern 175 can be removed more easily with less damage to the insulating pattern 165 of the mold during a wet etching process compared to the second sacrificial pattern 175 including silicon nitride.

[0059] The second sacrificial pattern 175 may include oxides instead of nitrides, thus preventing the generation of carbon nitride (CN) residues that could occur when etching the second sacrificial pattern 175, which includes nitrides. Therefore, the characteristics of adjacent layer structures (e.g., channel 240) may not be degraded due to CN residues.

[0060] Reference Figure 13 The second barrier pattern 350 may be formed on the exposed outer wall of the first barrier pattern 200, the inner wall of the second gap 340, the surface of the insulating pattern 165, the upper surface of the substrate 100, the upper surface of the support pattern 130, and the upper surface of the second interlayer insulating layer 270, and the gate electrode layer may be formed on the second barrier pattern 350.

[0061] The gate electrode layer may include a gate barrier layer and a gate conductive layer stacked in sequence. The gate electrode layer may include a low-resistance metal, such as tungsten, titanium, tantalum, platinum, etc., and the gate barrier layer may include a metal nitride, such as titanium nitride, tantalum nitride, etc.

[0062] The gate electrode layer may be partially removed to form a gate electrode in each of the second gaps 340. In an example embodiment, the gate electrode layer may be partially removed by a wet etching process, so that the gate electrode may completely or partially fill each of the second gaps 340.

[0063] The gate electrode can extend in the second direction, and multiple gate electrodes can be formed in the third direction. That is, the gate electrodes, each extending in the second direction, can be spaced apart from each other through the second opening 290.

[0064] In an example embodiment, gate electrodes may be formed at a plurality of horizontal heights spaced apart from each other in a first direction, and gate electrode structures may be formed at the gate electrodes at the plurality of horizontal heights. The gate electrode structures may include at least one first gate electrode 382, ​​a plurality of second gate electrodes 384, and at least one third gate electrode 386. The number of horizontal heights at which the first to third gate electrodes 382, ​​384, and 386 are formed may vary depending on the number of horizontal heights of the second sacrificial layer 170.

[0065] Reference Figure 14 The spacer layer can be formed on the second barrier pattern 350 and anisotropically etched to form spacers 390 on the sidewall of the second opening 290, so that the upper surface of the second barrier pattern 350 can be partially exposed.

[0066] The portion of the second barrier pattern 350 not covered by the spacer 390 can be etched, and the portion of the second barrier pattern 350 on the upper surface of the second interlayer insulating layer 270 can also be etched. Additionally, the upper portions of the substrate 100 and the support pattern 130 can be removed.

[0067] A conductive layer may be formed on the upper surface of the substrate 100, the upper surface of the support pattern 130, the spacer 390, and the second interlayer insulating layer 270 to fill the remainder of the second opening 290, and may be planarized until the upper surface of the second interlayer insulating layer 270 is exposed to form a common source line (CSL) 400. The CSL 400 may include a metal, such as tungsten.

[0068] In an example embodiment, the CSL 400 may extend in a first direction or a second direction. The lower surface of the CSL 400 may be covered by the substrate 100, that is, by the impurity region 105 and / or the support pattern 130. Therefore, current generated by a voltage applied from the CSL 400 may flow through the impurity region 105 and the channel connection pattern 325 to the channel 240. The CSL 400 may extend through the bottom of the spacer 390.

[0069] Reference Figure 15 and Figure 16 After a third interlayer insulating layer 410 is formed on the second interlayer insulating layer 270, CSL 400, spacer 390, and second blocking pattern 350, a contact plug 420 can be formed through the second interlayer insulating layer 270 and the third interlayer insulating layer 410 to contact the upper surface of the capping pattern 260. A fourth interlayer insulating layer 430 can be formed on the third interlayer insulating layer 410 and the contact plug 420, and a bit line 440 can be formed through the fourth interlayer insulating layer 430 to contact the upper surface of the contact plug 420.

[0070] As described above, a vertical memory device can be manufactured by the following steps: forming a first sacrificial layer 120 comprising a first insulating material on a substrate 100; forming a mold having an alternating and repetitively stacked insulating layer 160 and a second sacrificial layer 170, the insulating layer 160 and the second sacrificial layer 170 comprising a second insulating material and a third insulating material different from the first insulating material, respectively; forming a channel 240 through the mold and the first sacrificial layer 120; forming a second opening 290 through the mold and the first sacrificial layer 120 to expose the upper surface of the substrate 100; removing the first sacrificial layer 120 through the second opening 290 to form a first gap 310; forming a channel connection pattern 325 to fill the first gap 310; and replacing the second sacrificial layer 170 with a gate electrode.

[0071] In an example embodiment, the first sacrificial layer 120 may include a material having etch selectivity relative to the insulating pattern 165 and the second sacrificial pattern 175 of the mold. For example, the first sacrificial layer 120 may include silicon oxide having high etch selectivity relative to silicon oxide and germanium oxide respectively included in the insulating pattern 165 and the second sacrificial pattern 175.

[0072] In an example embodiment, the first sacrificial layer 120 can be removed by a wet etching process using an etching solution comprising phosphoric acid or sulfuric acid, wherein the etching selectivity of phosphoric acid or sulfuric acid relative to the first sacrificial layer 120 is greater than that relative to the insulating pattern 165 and the second sacrificial pattern 175. Therefore, the insulating pattern 165 and the second sacrificial pattern 175 exposed through the second opening 290 can be removed without damaging them during the wet etching process. Thus, the first sacrificial layer 120 can be removed without an etching stop pattern on the sidewall of the second opening 290.

[0073] In an example embodiment, the second sacrificial pattern 175 may include a material having etch selectivity relative to the insulating pattern 165 and the channel connection pattern 325 replacing the first sacrificial layer 120. For example, the second sacrificial pattern 175 may include germanium oxide, which may have high etch selectivity relative to the silicon oxide of the insulating pattern 165 and the polysilicon of the channel connection pattern 325, respectively.

[0074] In an example embodiment, the second sacrificial pattern 175 can be removed by a wet etching process using a solution comprising SC1. During the wet etching process, the etching selectivity of the solution relative to the second sacrificial pattern 175 may be greater than the etching selectivity relative to the insulating pattern 165 and the channel connection pattern 325, so the insulating pattern 165 and the channel connection pattern 325 may not be damaged during the wet etching process.

[0075] Specifically, germanium oxide included in the second sacrificial pattern 175 can have a higher etch selectivity relative to silicon oxide included in the insulating pattern 165, which can be greater than the etch selectivity of the second sacrificial pattern 175 including silicon nitride relative to silicon oxide. Therefore, the damage to the insulating pattern 165 of the mold during the wet etching process can be very small.

[0076] Furthermore, the second sacrificial pattern 175 may comprise oxides rather than nitrides, thus preventing the formation of carbon nitride (CN) residues that would occur if the second sacrificial pattern 175 comprised nitrides. Consequently, the characteristics of adjacent layer structures (e.g., channel 240) may not be degraded due to CN residues.

[0077] Figures 17 to 21 This is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to an example embodiment. The method may include, with reference to... Figures 1 to 16 The processes shown are essentially the same or similar, so a detailed description of them is omitted in this article.

[0078] Reference Figure 17 The circuit pattern can be formed on the substrate 500, and the first lower interlayer insulating layer 560 and the second lower interlayer insulating layer 630 can be formed on the substrate 500 to cover the circuit pattern.

[0079] The vertical memory device may have a cell-over-periphery (COP) structure. That is, the circuit pattern area and the cell array area may be vertically stacked on the substrate 500. The substrate 500 may include a field region having an isolation pattern 510 thereon and an active region.

[0080] The circuit pattern may include transistors, lower contact plugs, lower wiring, lower vias, etc. In an example embodiment, a transistor including the lower gate structure 550 and a lower impurity region 505 may be formed on the upper part of the active region of the substrate 500 adjacent to the lower gate structure 550. The lower gate structure 550 may include a lower gate insulating pattern 520, a lower gate electrode 530, and a lower gate mask 540 stacked sequentially on the substrate 500.

[0081] A first lower interlayer insulating layer 560 may be formed on a substrate 500 to cover the transistor, and a lower contact plug 570 may extend through the first lower interlayer insulating layer 560 to contact the lower impurity region 505.

[0082] A first lower wiring 580 may be formed on a first lower interlayer insulating layer 560 to contact the upper surface of the lower contact plug 570. A first lower via 590, a second lower wiring 600, a second lower via 610, and a third lower wiring 620 may be stacked sequentially on the first lower wiring 580.

[0083] A second lower interlayer insulating layer 630 may be formed on the first lower interlayer insulating layer 560 to cover the first to third lower wirings 580, 600 and 620, as well as the first lower via 590 and the second lower via 610. The second lower interlayer insulating layer 630 may be merged with the first lower interlayer insulating layer 560.

[0084] Reference Figure 18 The bottom pattern 700 can be formed on the second lower interlayer insulating layer 630.

[0085] A bottom pattern 700 can be formed by forming an underlayer and patterning the underlayer on the second lower interlayer insulating layer 630 to remain on a given region, for example, on a cell array region on the substrate 500. The bottom pattern 700 may include a semiconductor material, such as polysilicon.

[0086] Executable and Reference Figure 1 and Figure 2 The processes shown are essentially the same or similar.

[0087] Therefore, the pad 110 and the first sacrificial layer 120 can be stacked sequentially on the bottom pattern 700, the support pattern 130 extending through the pad 110 and the first sacrificial layer 120 can be formed on the bottom pattern 700, and the support layer 140 can be formed on the first sacrificial layer 120 and the support pattern 130.

[0088] Reference Figure 19 Executable and reference Figures 3 to 9 The processes shown are essentially the same or similar.

[0089] Therefore, as referenced Figures 3 to 9 The discussion and further discussion herein include the following: a mold for sequentially stacked insulating layers 160 and second sacrificial layers 170 may be formed on a support layer 140; a channel 240 extending through the mold and a charge storage structure 230 covering the lower surface and sidewalls of the channel 240 may be formed; a second opening 290 extending through the mold, support layer 140, and first sacrificial layer 120 to expose the upper surface of the bottom pattern 700 may be formed, and the first sacrificial layer 120 and a portion of the charge storage structure 230 may be removed through the second opening 290. Additionally, an impurity region 105 may be formed on the upper portion of the bottom pattern 700 exposed through the second opening 290.

[0090] Reference Figure 20 Executable and reference Figure 10 and Figure 11 The processes shown are substantially the same or similar, thus forming a channel connection pattern 325 that fills the first gap 310 so that the channels 240 can be connected to each other.

[0091] Reference Figure 21 Executable and reference Figures 12 to 16 The processes shown are essentially the same or similar to those used to complete the fabrication of the vertical memory device.

[0092] The vertical memory device may have a COP structure, so that a bottom pattern 700, including, for example, polysilicon, may be formed above the circuit pattern, a mold may be formed on the bottom pattern 700, and a channel 240 may be formed through the mold.

[0093] The bottom pattern 700 may not include single-crystal semiconductor material. Therefore, a SEG process using the bottom pattern 700 as a seed may not form a semiconductor pattern with uniform characteristics, and the channel 240 may not be uniformly connected to the bottom pattern 700 through this semiconductor pattern. However, according to the example embodiment, the channels 240 on the bottom pattern 700 can be connected to each other by a channel connection pattern 325 that can be formed by removing the first sacrificial layer 120, so no semiconductor pattern can be formed by the SEG process.

[0094] While exemplary embodiments have been specifically shown and described, one of those skilled in the art will understand that changes in form and detail may be made thereto without departing from the spirit and scope of the claims.

Claims

1. A method for manufacturing a vertical memory device, the method comprising: A first sacrificial layer is formed on a substrate, wherein the first sacrificial layer comprises a nitride; A mold is formed on the first sacrificial layer, the mold comprising alternating and repeatedly stacked insulating layers and a second sacrificial layer, wherein the insulating layer comprises a first oxide and the second sacrificial layer comprises germanium oxide or germanium-doped silicon oxide; Forming channels through the mold and the first sacrificial layer; An opening is formed through the mold and the first sacrificial layer to expose the upper surface of the substrate; The first sacrificial layer is removed through the opening to form a first gap; A channel connection pattern is formed in the first gap; as well as Replace the second sacrificial layer with a gate electrode. The channel connection pattern includes polycrystalline silicon doped with impurities. Prior to forming the mold, the method further includes: A support pattern is formed, the upper surface of which is coplanar with the upper surface of the first sacrificial layer, wherein the support pattern comprises a material different from the first sacrificial layer; and A support layer is formed on the first sacrificial layer and the support pattern, wherein the support layer comprises undoped or doped polysilicon.

2. The method according to claim 1, in, The insulating layer comprises silicon oxide.

3. The method according to claim 1, wherein, The first sacrificial layer comprises silicon nitride.

4. The method according to claim 1, wherein, Forming the channel connection pattern includes: A channel connection layer is formed in the first gap and on the sidewall of the opening; and Remove a portion of the channel connection layer from the opening.

5. The method according to claim 1, further comprising: Prior to forming the channel, a charge storage structure is formed, wherein the charge storage structure is located on the outer wall of the channel. After removing the first sacrificial layer, the portion of the charge storage structure exposed through the first gap is removed.

6. The method according to claim 5, wherein, The charge storage structure includes a tunnel insulation pattern, a charge storage pattern, and a blocking pattern stacked sequentially on the outer wall of the trench.

7. The method according to claim 6, in, The tunnel insulation pattern and the barrier pattern comprise silicon oxide, and The charge storage pattern includes silicon nitride.

8. The method according to claim 1, wherein, Replacing the second sacrificial layer with the gate electrode includes: The second sacrificial layer is removed through the opening to form a second gap; and The gate electrode is formed in the second gap.

9. A method for manufacturing a vertical memory device, the method comprising: A mold is formed on a substrate, the mold comprising alternating and repeatedly stacked insulating layers and a first sacrificial layer, wherein the insulating layer comprises silicon oxide and the first sacrificial layer comprises germanium oxide or germanium-doped silicon oxide; Forming channels through the mold; An opening is formed through the mold to expose the upper surface of the substrate; The first sacrificial layer is removed through the opening to form a first gap; and A gate electrode is formed in the first gap. Prior to forming the mold, the method further includes: A second sacrificial layer is formed on the substrate. A support pattern is formed, the upper surface of which is coplanar with the upper surface of the second sacrificial layer, wherein the support pattern comprises a material different from the second sacrificial layer; and A support layer is formed on the second sacrificial layer and the support pattern, wherein the support layer comprises undoped or doped polysilicon.

10. The method according to claim 9, in, The channel extends through the mold and the second sacrificial layer, and The opening extends through the mold and the second sacrificial layer.

11. The method according to claim 10, wherein, The second sacrificial layer comprises silicon nitride.

12. The method of claim 10, further comprising, before forming the first gap: The second sacrificial layer is removed through the opening to form a second gap; as well as A channel connection pattern is formed in the second gap.

13. The method according to claim 12, wherein, Forming the channel connection pattern includes: A channel connection layer is formed in the second gap and on the sidewall of the opening; and Remove a portion of the channel connection layer from the opening.

14. The method of claim 12, further comprising: Spacers are formed on the gate electrode; A conductive layer is formed on the upper surface of the substrate and on the spacer; as well as The conductive layer is planarized to form a common source electrode.

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