Display device

Abstract

The present disclosure relates to a display device, which includes: a display part, which includes a plurality of pixels arranged on a substrate; a plurality of dams, which are in a first peripheral part adjacent to the display part, the plurality of dams extend in a longitudinal direction of the first peripheral part and are arranged in a direction intersecting the longitudinal direction, the plurality of dams include a stack of a first organic insulating layer and a second organic insulating layer; and a blocking part, which is arranged between the plurality of dams and corresponds to a removed portion of the first organic insulating layer and the second organic insulating layer.

Description

Technical Field

[0001] Embodiments relate to a display device. Background Art

[0002] Display devices such as liquid crystal display (LCD) devices, organic light emitting display (OLED) devices, and electrophoretic display devices may include electric field generating electrodes and electro-optical active layers. For example, an organic light emitting display device may include an organic light emitting layer as an electro-optical active layer. The electric field generating electrodes may be connected to a switching element such as a thin film transistor to receive a data signal, and the electro-optical active layer may display an image by converting such a data signal into an optical signal. Summary of the invention

[0003] The present disclosure is directed to providing a display device for blocking external air.

[0004] An embodiment relates to a display device, which includes: a display portion, the display portion including a plurality of pixels arranged on a substrate; a plurality of dams, the plurality of dams being in a first peripheral portion adjacent to the display portion, the plurality of dams extending in a longitudinal direction of the first peripheral portion and arranged in a direction intersecting the longitudinal direction, the plurality of dams including a stack of a first organic insulating layer and a second organic insulating layer; and a blocking portion, the blocking portion being disposed between the plurality of dams and corresponding to removed portions of the first organic insulating layer and the second organic insulating layer.

[0005] In an example embodiment, at least one power supply voltage line that transmits a power supply voltage applied to the plurality of pixels may be disposed in the first peripheral portion, the at least one power supply voltage line may include a first source metal pattern and a second source metal pattern connected to the first source metal pattern through a contact hole formed in the first organic insulating layer, and the second organic insulating layer may be on the second source metal pattern.

[0006] In example embodiments, the plurality of dams may include at least one first dam disposed in a dam area adjacent to the display portion, a second dam disposed adjacent to the first dam, and a third dam disposed adjacent to the second dam.

[0007] In example embodiments, the first dam, the second dam, and the third dam may be on the at least one power supply voltage line, and may partially overlap the at least one power supply voltage line.

[0008] In example embodiments, the blocking portion may be disposed in a region between the first dam and the second dam in which the at least one power supply voltage line is not formed.

[0009] In example embodiments, the blocking portion may be disposed in a region between the second dam and the third dam in which the at least one power supply voltage line is not formed.

[0010] In an example embodiment, each of the plurality of pixels may include a pixel circuit including: a transistor including an active pattern, a gate electrode, a source electrode, and a drain electrode; an organic light emitting diode connected to the transistor, the organic light emitting diode including a pixel electrode, a light emitting layer, and a common electrode; and a pixel defining layer including an opening in which the light emitting layer is disposed, wherein the first organic insulating layer and the second organic insulating layer may be disposed between the source electrode and the pixel electrode.

[0011] In example embodiments, each of the first dam, the second dam, and the third dam may have a first height, and the first height may correspond to a stacking thickness of the first source metal pattern, the first organic insulating layer, the second source metal pattern, the second organic insulating layer, and the pixel defining layer.

[0012] In example embodiments, the first dam having a first height and a stepped portion having a second height lower than the first height may be disposed in the dam area, and wherein the stepped portion may be adjacent to the display portion, and the first dam may be adjacent to the second dam.

[0013] In example embodiments, the second height of the stepped portion may correspond to a stack thickness of the first source metal pattern or the second source metal pattern, the first organic insulation layer, and the pixel defining layer.

[0014] In example embodiments, a plurality of first dams having a first height and a step portion having a second height lower than the first height and disposed between the plurality of first dams may be disposed in the dam region.

[0015] In example embodiments, the second height of the stepped portion may correspond to a stack thickness of the first source metal pattern, the first organic insulation layer, and the second source metal pattern.

[0016] In example embodiments, the second height of the stepped portion may correspond to a stack thickness of the first source metal pattern or the second source metal pattern, the first organic insulation layer, and the pixel defining layer.

[0017] In example embodiments, the display device may further include an encapsulation layer on the common electrode of the display portion.

[0018] In example embodiments, the encapsulation layer may be sequentially stacked with an inorganic layer, an organic layer, and an inorganic layer.

[0019] In an example embodiment, the display device may further include: a first touch electrode of a touch sensor on the encapsulation layer of the display portion; a second touch electrode of the touch sensor on the first touch electrode of the display portion; and an interlayer insulating layer between the first touch electrode and the second touch electrode.

[0020] In example embodiments, the substrate may include a plurality of plastic layers.

[0021] In example embodiments, the display device may further include: a pad portion located at the first peripheral portion and including a plurality of pads connected to an external circuit film; and a bent portion located at the first peripheral portion between the display portion and the pad portion.

[0022] In example embodiments, the plurality of dams are disposed between the display portion and the bending portion.

[0023] In example embodiments, the display device may further include a valley portion provided in a second peripheral portion surrounding the display portion except for the first peripheral portion and corresponding to removed portions of the first and second organic insulating layers in the second peripheral portion.

[0024] According to an example embodiment, the display device includes: a plurality of dams to prevent the organic layer of the encapsulation layer from flowing to the edge portion of the display device; and a blocking portion in a region between the plurality of dams, from which the organic layer is removed. Therefore, external air such as moisture and oxygen can be prevented from flowing into the display portion inside the display device through the organic layer and the inorganic layer formed on the edge portion of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the accompanying drawings, in which:

[0026] Figure 1 A plan view showing a display device according to an example embodiment;

[0027] Figure 2 Show Figure 1 A pixel circuit diagram of a pixel of a display device;

[0028] Figure 3 Show Figure 1 A cross-sectional view of a display device including a display portion and a second peripheral portion;

[0029] Figure 4 Shown with Figure 1 An enlarged view of a portion A corresponding to the first peripheral portion in FIG.

[0030] Figure 5 Shown along Figure 4 A cross-sectional view of the display device taken along line II' in FIG.

[0031] Figure 6 Show Figure 1 A plan view of a first organic insulating layer and a second organic insulating layer in a portion A of FIG.

[0032] Figure 7 According to an example embodiment, Figure 1 A plan view of a first organic insulating layer and a second organic insulating layer in a portion A of FIG.

[0033] Figure 8 a cross-sectional view showing a display device according to an example embodiment; and

[0034] Fig. 9 A cross-sectional view of a display device according to example embodiments is shown. DETAILED DESCRIPTION

[0035] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and fully convey the example implementations to those skilled in the art. In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Throughout the text, the same reference numerals represent the same elements.

[0036] Figure 1 is a plan view illustrating a display device according to example embodiments. Figure 2 It is shown Figure 1 A pixel circuit diagram of a pixel of a display device.

[0037] refer to Figure 1 , the display device may include a display portion DA for displaying an image and a first peripheral portion PA1 and a second peripheral portion PA2 as a non-display portion surrounding the display portion DA.

[0038] A plurality of pixels may be arranged in the display portion DA, and each pixel may include a pixel circuit.

[0039] refer to Figure 2 , the pixel circuit PC may include an organic light emitting diode OLED, first to seventh transistors T1 to T7 , and a storage capacitor CST.

[0040] In this example embodiment, the anode of the organic light emitting diode OLED is connected to the first transistor T1 through the sixth transistor T6. The cathode of the organic light emitting diode OLED may be connected to the second power supply voltage ELVSS. The organic light emitting diode OLED may generate light of predetermined brightness corresponding to the current applied from the first transistor T1.

[0041] The first power voltage ELVDD may be set to a voltage higher than the second power voltage ELVSS so that current may flow through the organic light emitting diode OLED.

[0042] The seventh transistor T7 may be connected between the initialization voltage VINT and the anode of the organic light emitting diode OLED. The gate electrode of the seventh transistor T7 may be connected to the (i+1)th scan line Sli+1 or the (i-1)th scan line S1i-1 ("i" is a natural number). When the scan signal is applied to the (i+1)th scan line Sli+1 or the (i-1)th scan line S1i-1, the seventh transistor T7 may be turned on, and the seventh transistor T7 supplies the initialization voltage VINT to the anode of the organic light emitting diode OLED. The initialization voltage VINT may be set to a voltage lower than the data voltage.

[0043] The sixth transistor T6 may be connected between the first transistor T1 and the organic light emitting diode OLED. A gate electrode of the sixth transistor T6 may be connected to the i-th emission control line E1i. When an emission control signal is applied to the i-th emission control line E1i, the sixth transistor T6 may be turned on.

[0044] The fifth transistor T5 may be connected between the first power supply voltage ELVDD and the first transistor T1. A gate electrode of the fifth transistor T5 may be connected to the i-th emission control line E1i. When an emission control signal is applied to the i-th emission control line E1i, the fifth transistor T5 may be turned on.

[0045] The first electrode of the first transistor T1 is connected to the first power supply voltage ELVDD through the fifth transistor T5, and the second electrode of the first transistor T1 is connected to the anode of the organic light emitting diode OLED through the sixth transistor T6. The gate electrode of the first transistor T1 may be connected to the first node N1. Therefore, the first transistor T1 may control the amount of current flowing from the first power supply voltage ELVDD to the second power supply voltage ELVSS via the organic light emitting diode OLED corresponding to the voltage of the first node N1.

[0046] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be connected to the i-th scan line S1i. Therefore, when the scan signal is supplied to the i-th scan line S1i, the third transistor T3 is turned on and the second electrode of the first transistor T1 is electrically connected to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in a diode manner.

[0047] The fourth transistor T4 may be connected between the first node N1 and the initialization voltage VINT. The gate electrode of the fourth transistor T4 may be connected to the (i-1)th scan line S1i-1. Therefore, when the scan signal is applied to the (i-1)th scan line S1i-1, the fourth transistor T4 is turned on and applies the initialization voltage VINT to the first node N1.

[0048] The second transistor T2 may be connected between the mth data line Dm and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the i-th scan line S1i. Therefore, when a scan signal is applied to the i-th scan line S1i, the second transistor T2 is turned on and the first electrode of the first transistor T1 is electrically connected to the m-th data line Dm.

[0049] The storage capacitor CST may be connected between the first power voltage ELVDD and the first node N1. Therefore, the storage capacitor CST may store the data voltage and a voltage corresponding to the threshold voltage of the first transistor T1.

[0050] The first peripheral portion PA1 may correspond to a lower region or an upper region of the display portion DA.

[0051] A first power supply voltage line VL1 and a second power supply voltage line VL2 may be provided in the first peripheral portion PA1. The first power supply voltage line VL1 is configured to transmit a first power supply voltage ELVDD to the pixel circuit PC. The second power supply voltage line VL2 is configured to transmit a second power supply voltage ELVSS to the pixel circuit PC.

[0052] The first peripheral portion PA1 may include a dam portion DMA, a barrier portion BP, a bent portion BDA, and a pad portion PDA.

[0053] The dam portion DMA may include a plurality of dams, for example, dams DM1, DM2, and DM3. The plurality of dams DM1, DM2, and DM3 may block the organic material of the encapsulation layer used to seal the display portion DA from flowing toward the edge portion of the substrate. The plurality of dams DM1, DM2, and DM3 may prevent the formation of an edge tail of the organic material.

[0054] The edge tail refers to an edge portion of the organic layer that flows outwardly beyond the edge portion of the inorganic layer. Generally, in order to form an encapsulation layer, when the organic layer and the inorganic layer are formed, a pattern may be formed by placing a mask corresponding to the layer on a substrate. At this time, the organic layer may penetrate into the gap between the mask and the substrate to form the edge tail. The edge tail may cause external air such as oxygen or moisture to penetrate into the display portion DA.

[0055] In the present example embodiment, the blocking portion BP is a portion in which an organic layer (made of an organic material) is removed to prevent external air such as moisture or oxygen from penetrating through the organic layer.

[0056] The barrier portion BP may be formed in a region between the plurality of dams DM1 , DM2 , and DM3 .

[0057] In example embodiments, the blocking portion BP may be formed in a region between the first dam DM1 and the second dam DM2 .

[0058] In another embodiment, the barrier portion BP may be formed in a region between the second dam DM2 and the third dam DM3 .

[0059] The bending portion BDA is a region in which the display device may be bent by, for example, a module assembling process. The display device may include a flexible substrate, and the display device may be bent in the bending portion BDA.

[0060] The pad portion PDA may include a plurality of pads disposed in an edge portion of the first peripheral portion PA1 and connected to a plurality of signal lines arranged in the display device. The plurality of pads may be connected to an external circuit film such as a chip on film (COF) during module assembly.

[0061] The second peripheral portion PA2 may be a region surrounding the display portion DA except the first peripheral portion PA1. For example, the second peripheral portion PA2 may include an upper region of the display portion DA facing the first peripheral portion PA1 and left and right regions of the display portion DA.

[0062] The first power voltage line VL1 may be provided in the second peripheral portion PA2.

[0063] The second peripheral portion PA2 may include a valley portion VA.

[0064] The valley portion VA may be formed corresponding to a region where the first power voltage line VL1 is formed. The valley portion VA may be a region where an organic layer is removed to prevent external air such as moisture or oxygen from penetrating into the display portion DA through an insulating film made of an organic material.

[0065] Figure 3 It is shown Figure 1 A cross-sectional view of a display device showing a display portion and a first peripheral portion.

[0066] refer to Figure 1 , Figure 2 and Figure 3 , on the substrate 110, the display device may include a display portion DA and a second peripheral portion PA2.

[0067] The substrate 110 may include a first transparent plastic layer, a colored plastic layer, and a second transparent plastic layer stacked in sequence. For example, the plastic layer may be formed of a material selected from the group consisting of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate (PAR), polycarbonate (PC), polyetherimide (PEI), polyethersulfone (PS), etc.

[0068] The display part DA may include a pixel area PXA having a transistor TR connected to an organic light emitting diode OLED, a first touch electrode XE, and a second touch electrode YE.

[0069] The display device may further include a buffer layer 111 , a gate insulating layer 113 , a first interlayer insulating layer 116 , a first organic insulating layer 121 , a second organic insulating layer 122 , a pixel defining layer 123 , an encapsulation layer 130 , a planarization layer 141 , a second interlayer insulating layer 143 , and a passivation layer 145 .

[0070] The transistor TR may include an active pattern AC, a gate electrode GE, a source electrode SE, and a drain electrode DE. The gate electrode GE may be a gate metal pattern patterned from a gate metal layer, and the source electrode SE and the drain electrode DE may be source metal patterns patterned from a source metal layer.

[0071] The gate insulating layer 113 may be disposed between the active pattern AC and the gate electrode GE. The first interlayer insulating layer 116 may be disposed between the gate electrode GE and the source electrode SE or the drain electrode DE.

[0072] The organic light emitting diode OLED may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE. The pixel electrode PE may be connected to the drain electrode DE of the transistor TR through a contact hole formed in the first organic insulating layer 121 and the second organic insulating layer 122. In the opening formed in the pixel defining layer 123, the light emitting layer EL may be on the pixel electrode PE. In the display portion DA, the common electrode CE may be on the light emitting layer EL. The pixel defining layer 123 may include an organic material such as an acrylic resin, an epoxy resin, a polyimide resin, and a polyester resin.

[0073] The encapsulation layer 130 may be on the common electrode CE.

[0074] The encapsulation layer 130 may seal the light emitting layer EL and the common electrode CE to prevent moisture and / or oxygen from penetrating from the outside. The encapsulation layer 130 may include a plurality of encapsulation layers. The encapsulation layer 130 may include an inorganic layer 131, an organic layer 132, and an inorganic layer 133 stacked in sequence. The inorganic layers 131 and 133 may include inorganic materials such as aluminum oxide, silicon oxide, and silicon nitride. The organic layer 132 may include an organic material and may have a thickness for planarization.

[0075] Among the multiple encapsulation layers, the encapsulation layer located at the top may be an inorganic layer or an organic layer. When the uppermost encapsulation layer is an inorganic layer, the encapsulation layer 130 may well block moisture. The inorganic layer included in the encapsulation layer 130 may cover the organic layer disposed below the inorganic layer so that the organic layer is not exposed to the outside. The organic layer of the encapsulation layer 130 may be covered by the inorganic layer to prevent external air from penetrating through the organic layer.

[0076] The encapsulation layer 130 may cover the entire surface of the display portion DA, and may cover a portion of the first peripheral portion PA1 and the second peripheral portion PA2.

[0077] The planarization layer 141 may be on the encapsulation layer 130 to planarize the upper surface of the substrate 110 .

[0078] The first touch electrode XE may be on the planarization layer 141 , and may be a first electrode of a touch sensor.

[0079] The second touch electrode YE may be a second electrode of the touch sensor.

[0080] A second interlayer insulating layer 143 may be disposed between the first touch electrode XE and the second touch electrode YE.

[0081] A passivation layer 145 may be on the second touch electrode YE.

[0082] The second peripheral portion PA2 may include a valley portion VA defined in a region in which the first power voltage line VL1 is formed.

[0083] The first power supply voltage line VL1 may include a first portion a1, a second portion a2, and a third portion a3 along a width direction intersecting the longitudinal direction. The first portion a1 may be on the second organic insulating layer 122 of the second peripheral portion PA2. The second portion a2 may be connected to the first portion a1 and on the substrate 110 in a valley region from which the first organic insulating layer 121 and the second organic insulating layer 122 are removed. The third portion a3 may be connected to the second portion a2 and on the second organic insulating layer 122 of the second peripheral portion PA2.

[0084] The pixel defining layer 123 may be on the first portion a1 and the third portion a3 of the first power voltage line VL1. The pixel defining layer 123 may be removed corresponding to the valley portion VA.

[0085] The valley portion VA of the second peripheral portion PA2 may block external air such as moisture and oxygen from entering the pixel area DA through the first and second organic insulating layers 121 and 122 and the pixel defining layer 123 .

[0086] Figure 4 is shown with Figure 1 An enlarged view of part A corresponding to the second peripheral part in FIG. Figure 5 It is shown along Figure 4 A cross-sectional view of the display device taken along line II' in FIG. Figure 6 It is shown Figure 1 A plan view of a first organic insulating layer and a second organic insulating layer in portion A of FIG.

[0087] refer to Figure 1 , Figure 4 and Figure 5 , the dam portion DMA may be disposed in the first peripheral portion PA1 adjacent to the display portion DA.

[0088] A first power voltage line VL1 and a second power voltage line VL2 may be disposed in the first peripheral portion PA1.

[0089] The first and second power voltage lines VL1 and VL2 may include a first and second source metal patterns SM1 and SM2 . The second source metal pattern SM2 may be connected to the first source metal pattern SM1 through a contact hole formed in the first organic insulating layer 121 .

[0090] The dam portion DMA may be formed on the first and second power voltage lines VL1 and VL2 , and may overlap the first and second power voltage lines VL1 and VL2 .

[0091] The dam portion DMA may be disposed in the first peripheral portion PA1 adjacent to the display portion DA in the first direction D1 and may extend in a second direction D2 crossing the first direction D1. The dam portion DMA may be disposed between the display portion DA and the pad portion PDA.

[0092] In an exemplary embodiment, reference Figure 1 , the dam portion DMA may be disposed between the display portion DA and the bending portion BDA.

[0093] The dam portion DMA may include a first dam area DMA1 adjacent to the display portion DA in the first direction D1 , a second dam area DMA2 adjacent to the first dam area DMA1 in the first direction D1 , and a third dam area DMA3 adjacent to the second dam area DMA2 in the first direction D1 .

[0094] In example embodiments, the dam portion DMA may include a blocking portion BP in which the first and second organic insulating layers 121 and 122 are removed between the first and second dam areas DMA1 and DMA2 .

[0095] At least one first dam DM1 may be disposed in the first dam area DMA1 and may extend in the second direction D2 .

[0096] At least one second dam DM2 may be disposed in the second dam area DMA2, may be adjacent to the at least one first dam DM1 in the first direction D1, and may extend in the second direction D2.

[0097] At least one third dam DM3 may be disposed in the third dam area DMA3, may be adjacent to the at least one second dam DM2 in the first direction D1, and may extend in the second direction D2.

[0098] Each of the first dam DM1 , the second dam DM2 , and the third dam DM3 may have a structure in which at least two layers of the first organic insulating layer 121 , the second organic insulating layer 122 , and the pixel defining layer 123 are stacked.

[0099] The first dam DM1 , the second dam DM2 , and the third dam DM3 of the dam portion DMA may block the organic layer 132 of the encapsulation layer 130 for sealing the display portion DA from flowing toward the edge portion of the display device.

[0100] In example embodiments, the first dam area DMA1 may include a first dam DM1 and a stepped portion STP. The stepped portion STP may have a second height h2 lower than a first height h1 of the first dam DM1.

[0101] The first dam DM1 and the stepped portion STP may be on the first interlayer insulating layer 116. A lower structure of the first interlayer insulating layer 116 may include a buffer layer 111, a gate insulating layer 113, and a gate metal pattern GM, which are sequentially stacked on the substrate 110.

[0102] The first height h1 of the first dam DM1 may be determined as a stack thickness of the first source metal pattern SM1 , the first organic insulation layer 121 , the second source metal pattern SM2 , the second organic insulation layer 122 , and the pixel defining layer 123 .

[0103] In the region where the first power voltage line VL1 and the second power voltage line VL2 are formed, the second height h2 of the step portion STP may be determined as the stack thickness of one of the first source metal pattern SM1 and the second source metal pattern SM2, the first organic insulating layer 121, and the pixel defining layer 123. In the region where the first power voltage line VL1 and the second power voltage line VL2 are not formed, the second height h2 of the step portion STP (at Figure 5 (not shown) may be determined as a stack thickness of the first organic insulating layer 121 and the pixel defining layer 123.

[0104] The second dam DM2 may be disposed in the second dam area DMA2.

[0105] The second dam DM2 may be on the first interlayer insulating layer 116. A lower structure of the first interlayer insulating layer 116 may include a buffer layer 111, a gate insulating layer 113, and a gate metal pattern GM sequentially stacked on the substrate 110.

[0106] The first height of the second dam DM2 may be determined as a stack thickness of the first source metal pattern SM1 , the first organic insulation layer 121 , the second source metal pattern SM2 , the second organic insulation layer 122 , and the pixel defining layer 123 .

[0107] The third dam DM3 may be disposed in the third dam area DMA3.

[0108] The third dam DM3 may be on the first interlayer insulating layer 116. A lower structure of the first interlayer insulating layer 116 may include a buffer layer 111, a gate insulating layer 113, and a gate metal pattern GM sequentially stacked on the substrate 110.

[0109] A first height of the third dam DM3 may be determined as a stack thickness of the first source metal pattern SM1 , the first organic insulation layer 121 , the second source metal pattern SM2 , the second organic insulation layer 122 , and the pixel defining layer 123 .

[0110] The organic layer 132 of the encapsulation layer 130 may be prevented from flowing to the edge portion of the display device by the stepped portion STP and the first dam DM1 of the first dam area DMA1. In addition, the organic layer 132 of the encapsulation layer 130 may be prevented from flowing to the edge portion of the display device by the second dam DM2 of the second dam area DMA2. In addition, the organic layer 132 of the encapsulation layer 130 may be prevented from flowing to the edge portion of the display device by the third dam DM3 of the third dam area DMA3.

[0111] In an exemplary embodiment, reference Figure 4 and Figure 6The blocking portion BP from which the first and second organic insulating layers 121 and 122 are removed may be formed in a region between the first and second dam regions DMA1 and DMA2. The blocking portion BP may be formed in a region between the first and second dam regions DMA1 and DMA2 in which the first and second power voltage lines VL1 and VL2 are not formed.

[0112] As described above, external air such as moisture and oxygen may be blocked from entering the display portion DA in the region between the first dam area DMA1 and the second dam area DMA2. For example, in the region where the first power voltage line VL1 and the second power voltage line VL2 are formed, external air may be blocked from entering the display portion DA by the first source metal pattern SM1 and the second source metal pattern SM2 of the first power voltage line VL1 and the second power voltage line VL2. In addition, in the region where the first power voltage line VL1 and the second power voltage line VL2 are not formed, external air may be blocked from entering the display portion DA by removing the blocking portion BP from the first organic insulating layer 121 and the second organic insulating layer 122.

[0113] Figure 7 is a diagram showing a method according to an example embodiment Figure 1 A plan view of a first organic insulating layer and a second organic insulating layer in portion A of FIG.

[0114] refer to Figure 7 In example embodiments, a blocking portion BP from which the first and second organic insulating layers 121 and 122 are removed may be formed in a region between the second and third dam regions DMA2 and DMA3. The blocking portion BP may be formed in a region between the second and third dam regions DMA2 and DMA3 in which the first and second power voltage lines VL1 and VL2 are not formed.

[0115] It is possible to block external air such as moisture and oxygen from entering the display portion DA in the region between the first dam area DMA1 and the second dam area DMA2. For example, in the region where the first power voltage line VL1 and the second power voltage line VL2 are formed, it is possible to block external air from entering the display portion DA by the first source metal pattern SM1 and the second source metal pattern SM2 of the first power voltage line VL1 and the second power voltage line VL2. In addition, in the region where the first power voltage line VL1 and the second power voltage line VL2 are not formed, it is possible to block external air from entering the display portion DA by removing the blocking portion BP from the first organic insulating layer 121 and the second organic insulating layer 122.

[0116] Hereinafter, the same reference numerals are used to refer to the same or like components as those described in the previous example embodiment, and the same detailed description will not be repeated unless necessary for clarity.

[0117] Figure 8 is a cross-sectional view illustrating a display device according to example embodiments.

[0118] refer to Figure 4 and Figure 8 , the dam portion DMA may be disposed in the first peripheral portion PA1 adjacent to the display portion DA.

[0119] The first and second power voltage lines VL1 and VL2 may be disposed in the first peripheral portion PA1. The first and second power voltage lines VL1 and VL2 may include first and second source metal patterns SM1 and SM2. The second source metal pattern SM2 is connected to the first source metal pattern SM1 through a contact hole formed in the first organic insulating layer 121.

[0120] The dam portion DMA may be disposed in the first peripheral portion PA1 adjacent to the display portion DA in the first direction D1 and may extend in a second direction D2 crossing the first direction D1.

[0121] In example embodiments, the dam portion DMA may be disposed between the display portion DA and the pad portion PDA.

[0122] The dam portion DMA may include a first dam area DMA1 adjacent to the display portion DA in the first direction D1 , a second dam area DMA2 adjacent to the first dam area DMA1 in the first direction D1 , and a third dam area DMA3 adjacent to the second dam area DMA2 in the first direction D1 .

[0123] In example embodiments, the dam portion DMA may include a blocking portion BP between the first dam area DMA1 and the second dam area DMA2 in which the first organic insulating layer 121 and the second organic insulating layer 122 are removed.

[0124] In example embodiments, the dam portion DMA may include a blocking portion BP between the second dam area DMA2 and the third dam area DMA3 in which the first organic insulating layer 121 and the second organic insulating layer 122 are removed.

[0125] At least one first dam DM1 may be disposed in the first dam area DMA1 and may extend in the second direction D2 .

[0126] At least one second dam DM2 may be disposed in the second dam area DMA2, may be adjacent to the at least one first dam DM1 in the first direction D1, and may extend in the second direction D2.

[0127] At least one third dam DM3 may be disposed in the third dam area DMA3, may be adjacent to the at least one second dam DM2 in the first direction D1, and may extend in the second direction D2.

[0128] In an example embodiment, if Figure 8 As shown, the first dam area DMA1 may include a plurality of first dams DM1 and a plurality of stepped portions STP1.

[0129] The plurality of first dams DM1 and the plurality of stepped portions STP1 may be on the first interlayer insulating layer 116. A lower structure of the first interlayer insulating layer 116 may include a buffer layer 111, a gate insulating layer 113, and a gate metal pattern GM sequentially stacked on the substrate 110.

[0130] The first height h1 of the first dam DM1 may be determined as a stack thickness of the first source metal pattern SM1 , the first organic insulation layer 121 , the second source metal pattern SM2 , the second organic insulation layer 122 , and the pixel defining layer 123 .

[0131] The second height h2 of the stepped portion STP1 may be determined as a stack thickness of the first and second source metal patterns SM1 and SM2 and the first organic insulation layer 121 interposed therebetween.

[0132] The second dam DM2 may be disposed in the second dam area DMA2.

[0133] The second dam DM2 may be on the first interlayer insulating layer 116. A lower structure of the first interlayer insulating layer 116 may include a buffer layer 111, a gate insulating layer 113, and a gate metal pattern GM sequentially stacked on the substrate 110.

[0134] The first height of the second dam DM2 may be determined as a stack thickness of the first source metal pattern SM1 , the first organic insulation layer 121 , the second source metal pattern SM2 , the second organic insulation layer 122 , and the pixel defining layer 123 .

[0135] The third dam DM3 may be disposed in the third dam area DMA3.

[0136] The third dam DM3 may be on the first interlayer insulating layer 116. A lower structure of the first interlayer insulating layer 116 may include a buffer layer 111, a gate insulating layer 113, and a gate metal pattern GM sequentially stacked on the substrate 110.

[0137] A first height of the third dam DM3 may be determined as a stack thickness of the first source metal pattern SM1 , the first organic insulation layer 121 , the second source metal pattern SM2 , the second organic insulation layer 122 , and the pixel defining layer 123 .

[0138] The organic layer 132 of the encapsulation layer 130 may be prevented from flowing to the edge portion of the display device by the stepped portion STP1 and the first dam DM1 of the first dam area DMA1. In addition, the organic layer 132 of the encapsulation layer 130 may be prevented from flowing to the edge portion of the display device by the second dam DM2 of the second dam area DMA2. In addition, the organic layer 132 of the encapsulation layer 130 may be prevented from flowing to the edge portion of the display device by the third dam DM3 of the third dam area DMA3.

[0139] According to example embodiments, the display device includes a blocking portion in which the organic layer is removed from a region between the first dam region and the second dam region or between the second dam region and the third dam region. Therefore, external air such as moisture and oxygen can be prevented from entering the display portion through the organic layer and the inorganic layer formed on the edge portion of the display device.

[0140] Fig. 9 is a cross-sectional view illustrating a display device according to example embodiments.

[0141] refer to Figure 4 and Fig. 9 , the dam portion DMA may be disposed in the first peripheral portion PA1 adjacent to the display portion DA.

[0142] The first and second power voltage lines VL1 and VL2 may be disposed in the first peripheral portion PA1. The first and second power voltage lines VL1 and VL2 may include first and second source metal patterns SM1 and SM2. The second source metal pattern SM2 may be connected to the first source metal pattern SM1 through a contact hole formed in the first organic insulating layer 121.

[0143] The dam portion DMA may be disposed in the first peripheral portion PA1 adjacent to the display portion DA in the first direction D1 and may extend in a second direction D2 crossing the first direction D1. The dam portion DMA may be disposed between the display portion DA and the pad portion PDA.

[0144] The dam portion DMA may include a first dam area DMA1 adjacent to the display portion DA in the first direction D1 , a second dam area DMA2 adjacent to the first dam area DMA1 in the first direction D1 , and a third dam area DMA3 adjacent to the second dam area DMA2 in the first direction D1 .

[0145] In example embodiments, the dam portion DMA may include a blocking portion BP between the first dam area DMA1 and the second dam area DMA2 in which the first organic insulating layer 121 and the second organic insulating layer 122 are removed.

[0146] In example embodiments, the dam portion DMA may include a blocking portion BP between the second dam area DMA2 and the third dam area DMA3 in which the first organic insulating layer 121 and the second organic insulating layer 122 are removed.

[0147] At least one first dam DM1 may be disposed in the first dam area DMA1 and may extend in the second direction D2 .

[0148] At least one second dam DM2 may be disposed in the second dam area DMA2, may be adjacent to the at least one first dam DM1 in the first direction D1, and may extend in the second direction D2.

[0149] At least one third dam DM3 may be disposed in the third dam area DMA3, may be adjacent to the at least one second dam DM2 in the first direction D1, and may extend in the second direction D2.

[0150] In an example embodiment, Fig. 9 As shown, the first dam area DMA1 may include a plurality of first dams DM1 and a plurality of stepped portions STP2.

[0151] The plurality of first dams DM1 and the plurality of stepped portions STP2 may be on the first interlayer insulating layer 116. A lower structure of the first interlayer insulating layer 116 may include a buffer layer 111, a gate insulating layer 113, and a gate metal pattern GM sequentially stacked on the substrate 110.

[0152] The first height h1 of the first dam DM1 may be determined as a stack thickness of the first source metal pattern SM1 , the first organic insulation layer 121 , the second source metal pattern SM2 , the second organic insulation layer 122 , and the pixel defining layer 123 .

[0153] A second height h2 of the stepped portion STP2 may be determined as a stack thickness of one of the first and second source metal patterns SM1 and SM2 , the first organic insulating layer 121 , and the pixel defining layer 123 .

[0154] The second dam DM2 may be disposed in the second dam area DMA2.

[0155] The second dam DM2 may be on the first interlayer insulating layer 116. A lower structure of the first interlayer insulating layer 116 may include a buffer layer 111, a gate insulating layer 113, and a gate metal pattern GM sequentially stacked on the substrate 110.

[0156] The first height of the second dam DM2 may be determined as a stack thickness of the first source metal pattern SM1 , the first organic insulation layer 121 , the second source metal pattern SM2 , the second organic insulation layer 122 , and the pixel defining layer 123 .

[0157] The third dam DM3 may be disposed in the third dam area DMA3.

[0158] The third dam DM3 may be on the first interlayer insulating layer 116. A lower structure of the first interlayer insulating layer 116 may include a buffer layer 111, a gate insulating layer 113, and a gate metal pattern GM sequentially stacked on the substrate 110.

[0159] A first height of the third dam DM3 may be determined as a stack thickness of the first source metal pattern SM1 , the first organic insulation layer 121 , the second source metal pattern SM2 , the second organic insulation layer 122 , and the pixel defining layer 123 .

[0160] The organic layer 132 of the encapsulation layer 130 may be prevented from flowing to the edge portion of the display device by the stepped portion STP2 and the first dam DM1 of the first dam area DMA1. In addition, the organic layer 132 of the encapsulation layer 130 may be prevented from flowing to the edge portion of the display device by the second dam DM2 of the second dam area DMA2. In addition, the organic layer 132 of the encapsulation layer 130 may be prevented from flowing to the edge portion of the display device by the third dam DM3 of the third dam area DMA3.

[0161] According to example embodiments, the display device includes a blocking portion in which the organic layer is removed from a region between the first dam region and the second dam region or between the second dam region and the third dam region. Therefore, external air such as moisture and oxygen can be prevented from entering the display portion through the organic layer and the inorganic layer formed on the edge portion of the display device.

[0162] Example embodiments may be applied to display devices and electronic devices having the same, for example, computer monitors, laptop computers, digital cameras, cellular phones, smart phones, smart tablets, televisions, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, navigation systems, game consoles, video phones, and the like.

[0163] By way of summary and review, when impurities such as moisture and / or oxygen enter the display device from the outside, the life of the electronic device included in the display device may be shortened. In the case of an organic light-emitting display device, the efficiency of light emission of the organic light-emitting layer may be reduced. In this case, degradation of the emission color of the organic light-emitting layer may occur.

[0164] Therefore, when manufacturing a display device, a sealing process may be performed to isolate internal electronic components from the outside, thereby preventing impurities from penetrating. The sealing process includes a method of stacking a layer made of an organic polymer on a lower substrate on which a thin film transistor and an organic light-emitting layer are formed, a method of forming a lid or cover with an encapsulation substrate and sealing the edges of the lower substrate and the encapsulation substrate, and a method of forming an encapsulation member including a plurality of encapsulation layers to replace the encapsulation substrate.

[0165] As described above, the embodiments relate to a display device having a dam formed in a peripheral region adjacent to a display region. Example embodiments may provide a display device for blocking external air.

[0166] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for the purpose of limitation. In some cases, as will be apparent to one of ordinary skill in the art from the time of filing this application, unless otherwise specifically indicated, the features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the invention as set forth in this disclosure.

Claims

1. A display device, wherein: The display device comprises: A display portion including a plurality of pixels arranged on a substrate; a plurality of dams in a first peripheral portion adjacent to the display portion, the plurality of dams extending in a longitudinal direction of the first peripheral portion and arranged in a direction crossing the longitudinal direction, the plurality of dams comprising a stack of a first organic insulating layer and a second organic insulating layer; and a blocking portion disposed between the plurality of dams and corresponding to removed portions of the first organic insulating layer and the second organic insulating layer, wherein at least one power supply voltage line that transmits a power supply voltage applied to the plurality of pixels is provided in the first peripheral portion, The at least one power supply voltage line includes a first source metal pattern and a second source metal pattern connected to the first source metal pattern through a contact hole formed in the first organic insulating layer, and The second organic insulating layer is on the second source metal pattern.

2. The display device according to claim 1, wherein: The plurality of dams include: at least one first dam, the at least one first dam being in a dam region adjacent to the display portion; a second dam, the second dam being adjacent to the first dam; and A third dam, wherein the third dam is adjacent to the second dam.

3. The display device according to claim 2, wherein: The first dam, the second dam, and the third dam are on the at least one power supply voltage line and partially overlap the at least one power supply voltage line.

4. The display device according to claim 2, wherein: The blocking portion is in a region between the first dam and the second dam in which the at least one power supply voltage line is not formed.

5. The display device according to claim 2, wherein: The blocking portion is in a region between the second dam and the third dam in which the at least one power supply voltage line is not formed.

6. The display device according to claim 2, wherein: Each of the plurality of pixels comprises a pixel circuit, the pixel circuit comprising: A transistor, the transistor comprising an active pattern, a gate electrode, a source electrode and a drain electrode; an organic light emitting diode connected to the transistor, the organic light emitting diode comprising a pixel electrode, a light emitting layer and a common electrode; and a pixel defining layer, the pixel defining layer comprising an opening in which the light emitting layer is disposed, The first organic insulating layer and the second organic insulating layer are between the source electrode and the pixel electrode.

7. The display device according to claim 6, wherein: Each of the first dam, the second dam, and the third dam has a first height, and The first height corresponds to a stacking thickness of the first source metal pattern, the first organic insulating layer, the second source metal pattern, the second organic insulating layer, and the pixel defining layer.

8. The display device according to claim 6, wherein: The first dam having a first height and a step portion having a second height lower than the first height are provided in the dam area, The step portion is adjacent to the display portion, and The first dam is adjacent to the second dam.

9. The display device according to claim 8, wherein: The second height of the stepped portion corresponds to a stack thickness of the first source metal pattern or the second source metal pattern, the first organic insulation layer, and the pixel defining layer.

10. The display device according to claim 6, wherein: A plurality of first dams having a first height and a step portion having a second height lower than the first height and disposed between the plurality of first dams are disposed in the dam region.

11. The display device according to claim 10, wherein: The second height of the stepped portion corresponds to a stack thickness of the first source metal pattern, the first organic insulating layer, and the second source metal pattern.

12. The display device according to claim 10, wherein: The second height of the stepped portion corresponds to a stack thickness of the first source metal pattern or the second source metal pattern, the first organic insulation layer, and the pixel defining layer.

13. The display device according to claim 6, wherein: The display device further includes an encapsulation layer on the common electrode of the display portion.

14. The display device according to claim 13, wherein: The encapsulation layer includes an inorganic layer, an organic layer and an inorganic layer stacked sequentially.

15. The display device according to claim 13, wherein: The display device further includes: a first touch electrode of a touch sensor on the encapsulation layer of the display portion; a second touch electrode of the touch sensor on the first touch electrode of the display portion; and An interlayer insulating layer is between the first touch electrode and the second touch electrode.

16. The display device according to claim 1, wherein: The substrate includes a plurality of plastic layers.

17. The display device according to claim 16, wherein: The display device further includes: a pad portion located at the first peripheral portion and including a plurality of pads connected to an external circuit film; and A bent portion is located at the first peripheral portion between the display portion and the pad portion.

18. The display device according to claim 17, wherein: The plurality of dams are disposed between the display portion and the bending portion.

19. The display device according to claim 17, wherein: The display device further includes a valley portion provided in a second peripheral portion surrounding the display portion except for the first peripheral portion and corresponding to removed portions of the first organic insulating layer and the second organic insulating layer in the second peripheral portion.

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