A three-dimensional stacked integrated package structure with low RDSON and a preparation method thereof

Abstract

The present invention discloses a three-dimensional stacked integrated package structure with low RDSON and a preparation method thereof. The preparation method includes the following steps: providing a carrier board, sequentially mounting a conductive material and a first solder mask layer on one side of the carrier board, opening holes in the first solder mask layer, and applying solder paste at the openings; mounting a first chip with double-sided I / O ports and a conductive block at the solder paste positions, performing encapsulation and then fabricating a first redistribution layer; de-bonding, flipping and fixing, etching the conductive material to form a second redistribution layer; fabricating a second solder mask layer on one side of the second redistribution layer, and opening holes at positions corresponding to the conductive blocks in the second solder mask layer; mounting a second chip on one side of the second solder mask layer, connecting the I / O ports of the second chip and the second redistribution layer by leads, and performing encapsulation on the second chip. The present invention effectively reduces RDSON, reduces the package size, improves the system integration degree, avoids the void phenomenon generated by the TMV structure, reduces the difficulty of the electroplating process, and reduces the production cost.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and particularly relates to a low-RDSON three-dimensional stacked integrated packaging structure and a preparation method thereof. Background Art

[0002] A metal-oxide-semiconductor field-effect transistor, abbreviated as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), is a field-effect transistor that can be widely used in analog circuits and digital circuits.

[0003] For high-end MOS chips, a small RDSON value is beneficial to reducing the loss generated by the device during conduction. Therefore, when selecting a device, under the condition that the cost permits, a device with a relatively small RDSON can be appropriately selected. RDSON is also a positive temperature coefficient, and this characteristic helps in the parallel use of MOSFETs. However, as the temperature increases, the conduction loss of the MOSFET increases. Summary of the Invention

[0004] The purpose of the present invention is to provide a preparation method of a low-RDSON three-dimensional stacked integrated packaging structure and a low-RDSON three-dimensional stacked integrated packaging structure prepared by the preparation method. By using this preparation method to perform three-dimensional stacking on a chip with double-sided I / O ports and a chip with single-sided I / O ports, the RDSON value and the packaging size can be effectively reduced, and at the same time, the system integration degree can be improved.

[0005] To achieve this purpose, the present invention adopts the following technical solutions:

[0006] On the one hand, a preparation method of a low-RDSON three-dimensional stacked integrated packaging structure is provided, including the following steps:

[0007] S10. Provide a carrier board, sequentially attach a conductive material and a first solder mask layer on one side of the carrier board along its thickness direction, perform an opening process on the first solder mask layer to form a first hole position and a second hole position where part of the conductive material is exposed, and apply solder paste at the first hole position and the second hole position respectively;

[0008] S20. Attach a first chip with double-sided I / O ports at the solder paste corresponding to the first hole position and attach a conductive block at the solder paste corresponding to the second hole position. After encapsulation, fabricate a first redistribution layer connected to the I / O ports of the first chip and the conductive block;

[0009] S30. Debond, combine, flip, and fix, and perform an etching process on the conductive material to form a second redistribution layer;

[0010] S40. Fabricate a second solder mask layer on the side of the second rewiring layer away from the first chip, and perform an opening process on the position of the second solder mask layer corresponding to the conductive block to form a third hole position.

[0011] S50. Mount a second chip on the side of the second solder mask layer away from the first chip, with the I / O ports of the second chip facing away from the first chip. Connect the I / O ports of the second chip and the second rewiring layer using leads passing through the third hole position, and encapsulate the second chip to form a second encapsulation layer.

[0012] As a preferred embodiment of the preparation method of the low - RDSON three - dimensional stacked integrated packaging structure, step S20 specifically includes the following steps:

[0013] S20a. Mount a first chip with double - sided I / O ports on the solder paste corresponding to the first hole position and mount a conductive block on the solder paste corresponding to the second hole position.

[0014] S20b. Encapsulate the first chip and the conductive block to form a first encapsulation layer.

[0015] S20c. Perform an opening process on the position of the first encapsulation layer corresponding to the I / O ports of the conductive block and the side of the first chip away from the second chip to form a fourth hole position.

[0016] S20d. Fabricate a first rewiring layer on the surface of the first encapsulation layer and connect the first rewiring layer to the conductive pillars made in the fourth hole position.

[0017] As a preferred embodiment of the preparation method of the low - RDSON three - dimensional stacked integrated packaging structure, after step S50, the following steps are further included:

[0018] S60. Debond, merge, flip and fix. Fabricate a third encapsulation layer on the surface of the first rewiring layer and the first encapsulation layer exposed on the surface of the first rewiring layer, and perform an opening process on the third encapsulation layer to expose the pad area of the first rewiring layer.

[0019] S70. Provide metal bumps and implant the metal bumps by soldering into the pad area of the first rewiring layer.

[0020] As a preferred embodiment of the preparation method of the low - RDSON three - dimensional stacked integrated packaging structure, the material of the conductive block is Cu, Ag or Au.

[0021] On the other hand, provide a low - RDSON three - dimensional stacked integrated packaging structure prepared by the above - mentioned preparation method, including:

[0022] The first solder mask layer is provided with a first hole position and a second hole position that penetrate through it in the thickness direction at intervals;

[0023] A first plastic encapsulation layer on one side of the first solder mask layer, a conductive block encapsulated in the first plastic encapsulation layer and located at the first hole position, and a first chip with double-sided I / O ports located at the second hole position. The first plastic encapsulation layer is provided with a fourth hole position for exposing the I / O ports on one side of the first chip and the conductive block;

[0024] A first redistribution layer located on the first plastic encapsulation layer and connected to the conductive block through conductive pillars in the fourth hole position;

[0025] Metal bumps connected to the pad area of the first redistribution layer;

[0026] A second redistribution layer and a second solder mask layer located in sequence on the side of the first solder mask layer away from the first chip, and a second chip mounted on the second solder mask layer facing away from the first chip. The second solder mask layer is provided with a third hole position corresponding to the position of the conductive block, and the I / O ports of the second chip are connected to the second redistribution layer through chips passing through the third hole position.

[0027] As a preferred embodiment of the low RDSON three-dimensional stacked integrated packaging structure, it further includes solder paste. The solder paste is located in the first hole position and the second hole position. One side of the solder paste is connected to the first chip and the conductive block, and the other side is connected to the second redistribution layer.

[0028] As a preferred embodiment of the low RDSON three-dimensional stacked integrated packaging structure, it further includes a second plastic encapsulation layer located on the second solder mask layer and covering the second chip and the leads.

[0029] As a preferred embodiment of the low RDSON three-dimensional stacked integrated packaging structure, it further includes a third plastic encapsulation layer located on the first plastic encapsulation layer and covering the first redistribution layer. The third plastic encapsulation layer is provided with a hole for exposing the pad area of the first redistribution layer, and the metal bumps are located in this hole.

[0030] As a preferred embodiment of the low RDSON three-dimensional stacked integrated packaging structure, it further includes a seed layer located on the surface of the first plastic encapsulation layer and the fourth hole position. The first redistribution layer is located on the seed layer and is connected to the conductive pillars filling the fourth hole position.

[0031] As a preferred embodiment of the low RDSON three-dimensional stacked integrated packaging structure, the number of the first chips is one or more.

[0032] Advantages of the present invention: The present invention combines SMT process, PCB process, re - wiring process and wire bonding process, effectively reducing RDSON. The mos chip and the controller chip are three - dimensionally stacked, reducing the package size and improving the system integration. By mounting the conductive block before electroplating, the holes on the first encapsulation layer with a large aspect ratio are converted into two blind holes with a smaller aspect ratio during the electroplating process, thus effectively avoiding the phenomenon of voids in the TMV structure, greatly reducing the process difficulty of electroplating, shortening the electroplating time, improving the reliability of the product, and reducing the production cost. Brief Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention will be briefly introduced below. Obviously, the following - described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1 It is a flowchart of a method for preparing a low - RDSON three - dimensional stacked integrated package structure according to an embodiment of the present invention.

[0035] Figure 2 It is a specific flowchart of step S20 in the method for preparing a low - RDSON three - dimensional stacked integrated package structure according to an embodiment of the present invention.

[0036] Figure 3 It is a cross - sectional schematic view of a conductive material and a first solder mask layer sequentially attached to a first carrier board according to an embodiment of the present invention.

[0037] Figure 4 It is a cross - sectional schematic view after the first solder mask layer is opened with holes according to an embodiment of the present invention.

[0038] Figure 5 It is a cross - sectional schematic view after applying solder paste, mounting a conductive block and a first chip according to an embodiment of the present invention.

[0039] Figure 6 It is a cross - sectional schematic view after encapsulating the first chip to form a first encapsulation layer according to an embodiment of the present invention.

[0040] Figure 7 It is a cross - sectional schematic view after manufacturing the first re - wiring layer according to an embodiment of the present invention.

[0041] Figure 8 It is a cross - sectional schematic view after debonding, flipping and fixing on a second carrier board according to an embodiment of the present invention.

[0042] Figure 9It is a cross-sectional schematic view after opening holes in the conductive material to form the second rewiring layer according to an embodiment of the present invention.

[0043] Figure 10 It is a cross-sectional schematic view after manufacturing the second solder mask and mounting the second chip by opening holes according to an embodiment of the present invention.

[0044] Figure 11 It is a cross-sectional schematic view after connecting the second chip and the second rewiring layer by using leads according to an embodiment of the present invention.

[0045] Figure 12 It is a cross-sectional schematic view after encapsulating the second chip to form the second encapsulation layer according to an embodiment of the present invention.

[0046] Figure 13 It is a cross-sectional schematic view after de-bonding, flipping and fixing on the third carrier board and then manufacturing the third encapsulation according to an embodiment of the present invention.

[0047] Figure 14 It is a cross-sectional schematic view after implanting metal bumps into the pad area of the first rewiring layer according to an embodiment of the present invention.

[0048] In the figure:

[0049] 11. First carrier board; 12. Second carrier board;

[0050] 21. First rewiring layer; 22. Conductive material; 23. Second rewiring layer;

[0051] 31. First solder mask; 32. Second solder mask;

[0052] 4. Solder paste;

[0053] 51. First chip; 52. Second chip;

[0054] 6. Conductive block;

[0055] 7. Lead;

[0056] 81. First encapsulation layer; 82. Second encapsulation layer; 83. Third encapsulation layer;

[0057] 9. Metal bump. Detailed implementation manners

[0058] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and through specific implementation manners.

[0059] Among them, the attached drawings are only for illustrative purposes, showing only schematic diagrams rather than actual physical diagrams, and should not be construed as a limitation on this patent; to better illustrate the embodiments of the present invention, some components in the attached drawings will be omitted, enlarged or reduced, which do not represent the dimensions of actual products; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the attached drawings may be omitted.

[0060] In the attached drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the attached drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms used to describe the positional relationship in the attached drawings are only for illustrative purposes and should not be construed as a limitation on this patent. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0061] In the description of the present invention, unless otherwise clearly specified and limited, if terms such as "connection" are used to indicate the connection relationship between components, this term should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0062] The first chip 51 in this embodiment is a chip with double-sided I / O ports. For example, the first chip 51 is a mos chip but not limited to a mos chip; the second chip 52 is a chip with single-sided I / O ports. For example, the second chip 52 is a controller chip but not limited to a controller chip; next, taking the mos chip and the controller chip as examples, the technical solution of the present invention will be described in detail.

[0063] As Figure 1 shown, the preparation method of the low RDSON three-dimensional stacked integrated packaging structure in this embodiment includes the following steps:

[0064] S10. Refer to Figure 3 , provide a first carrier 11, sequentially mount a conductive material 22 and a first solder mask layer 31 on one side of the first carrier 11 along its thickness direction, perform an opening process on the first solder mask layer 31 ( Figure 4 ), form a first hole position and a second hole position where part of the conductive material 22 is exposed, and apply solder paste 4 at the first hole position and the second hole position respectively ( Figure 5); wherein, the material of the first carrier plate 11 can be one of BT (Bismaleimide Triazine Resin), FR4, FR5, PP, EMC, ABF or PI materials, but is not limited thereto; the opening positions and quantities of the first holes correspond one-to-one to the positions and quantities of the first chips 51 to be installed, and the opening positions and quantities of the second holes correspond one-to-one to the positions and quantities of the conductive blocks 6 to be installed;

[0065] S20. Mount the first chip 51 with double-sided I / O ports at the solder paste 4 corresponding to the first holes and mount the conductive block 6 at the solder paste 4 corresponding to the second holes ( Figure 5 ), and electrically lead out the I / O ports of the first chip 51, that is, electrically lead out all the I / O ports on both sides of the first chip 51;

[0066] S30. After debonding, combining and flipping, etch the conductive material 22 to form the second rewiring layer 23; the second rewiring layer 23 is obtained by subtractive process from the conductive material 22. After the conductive material 22 is etched, a patterned hole that exposes part of the first solder mask layer 31 is formed, thereby obtaining the second rewiring layer 23; specifically, after debonding, combining and flipping, the first encapsulation layer 81 is mounted on the second carrier plate 12 through a first temporary bonding adhesive ( Figure 8 ), and then the conductive material 22 is etched to obtain the second rewiring layer 23 ( Figure 9 ); the material of the second carrier plate 12 is the same as that of the first carrier plate 11, which will not be elaborated here;

[0067] S40. Make a second solder mask layer 32 on the side of the second rewiring layer 23 away from the first chip 51, and perform an opening process on the position of the second solder mask layer 32 corresponding to the conductive block 6 to form a third hole, so that part of the conductive block 6 is exposed outside the second solder mask layer 32 ( Figure 10 );

[0068] S50. Mount the second chip 52 on the side of the second solder mask layer 32 away from the first chip 51, and make the I / O ports of the second chip 52 face away from the first chip 51. Use the lead 7 passing through the third hole to connect the I / O ports of the second chip 52 and the second rewiring layer 23, and encapsulate the second chip 52 to form a second encapsulation layer 82 ( Figure 11 ).

[0069] Wherein, both the first solder mask layer 31 and the second solder mask layer 32 are green oil for solder masking.

[0070] In this embodiment, the first chip 51 and the conductive block 6 are respectively mounted at the solder paste 4 at the corresponding positions. The solder paste 4 can play an automatic correction role in the installation positions of the conductive block 6 and the first chip 51 during the preheating process of encapsulation.

[0071] This embodiment combines the SMT (Surface Mount Technology), PCB (Printed Circuit Board) process, re-wiring process and wire bonding process, effectively reducing RDSON. At the same time, the wire bonding process is used for the second chip 52 to reduce the production cost. Then, the mos chip and the controller chip are three-dimensionally stacked, reducing the package size and improving the system integration. By mounting the conductive block 6 before electroplating, the holes in the first encapsulation layer 81 with a large aspect ratio are converted into two blind holes with a smaller aspect ratio during the electroplating process, effectively avoiding the phenomenon of voids in the TMV structure composed of the conductive block 6 and the conductive pillar, reducing the process difficulty of electroplating, shortening the electroplating time, and improving the reliability of the product.

[0072] Further, as Figure 2 shown, step S20 specifically includes the following steps:

[0073] S20a. Mount the first chip 51 with double-sided I / O ports at the solder paste 4 corresponding to the first hole position and mount the conductive block 6 at the solder paste 4 corresponding to the second hole position respectively ( Figure 5 );

[0074] S20b. Encapsulate the first chip 51 and the conductive block 6 to form the first encapsulation layer 81 ( Figure 6 );

[0075] S20c. Open holes at the positions of the I / O ports on the side of the first encapsulation layer 81 corresponding to the conductive block 6 and the first chip 51 away from the second chip 52 to form the fourth hole position;

[0076] S20d. Fabricate the first re-wiring layer 21 on the surface of the first encapsulation layer 81 and connect the first re-wiring layer 21 to the conductive pillars fabricated in the fourth hole position ( Figure 7 ).

[0077] In this embodiment, the first chip 51 is electrically led out and connected to the metal bump 9 through the fan-out re-wiring method.

[0078] Among them, the first re-wiring layer 21 is a structure with at least one layer, that is, it can be designed as one layer, two layers, three layers or even more than three layers according to actual needs.

[0079] Further, as Figure 1 shown, after step S50, the following steps are further included:

[0080] S60. Debond, merge, flip and fix, and fabricate the third encapsulation layer 83 on the surface of the first re-wiring layer 21 and the first encapsulation layer 81 exposed on the surface of the first re-wiring layer 21 ( Figure 12), and perform an opening process on the third encapsulation layer 83 to expose the pad area of the first rewiring layer 21. Figure 13 ); Specifically, after debonding, merging, and flipping, the second encapsulation layer 82 is mounted on the third carrier board through the second temporary bonding adhesive, and then the third encapsulation layer 83 is fabricated; among them, the function of the third encapsulation layer 83 is similar to that of the solder mask layer, so the solder mask layer can also be used instead. For example, first apply photosensitive ink on the surfaces of the first encapsulation layer 81 and the first rewiring layer 21, and after the photosensitive ink is cured, perform an opening process through exposure and development to form a solder mask layer that exposes the pad area of the first rewiring layer 21, which will not be elaborated here; among them, the second temporary bonding adhesive and the third carrier board are not shown in the figure.

[0081] S70. Provide metal bumps 9, and weld and implant the metal bumps 9 into the pad area of the first rewiring layer 21. Figure 14 ), and complete the preparation of the low RDSON three-dimensional stacked integrated packaging structure.

[0082] Finally, perform debonding and dicing to obtain the three-dimensional stacked integrated packaging structure with a lower RDSON in this embodiment.

[0083] In this embodiment, optionally, the first encapsulation layer 81, the second encapsulation layer 82, and the third encapsulation layer 83 are made of the same material, which may include polyimide, silica gel, and EMC (Epoxy Molding Compound), and EMC is preferably used in this embodiment.

[0084] Optionally, the metal bumps 9 are solder, silver solder, or gold-tin alloy solder, and the specific shape of the metal bumps 9 is not limited, and solder balls are preferably used.

[0085] Optionally, the material of the conductive block 6 in this embodiment is Cu, Ag, or Au.

[0086] As Figure 14 shown, this embodiment also provides a low RDSON three-dimensional stacked integrated packaging structure prepared by using the preparation method in the above embodiment, including:

[0087] A first solder mask layer 31, which is provided with a first hole position and a second hole position penetrating through it along its thickness direction at intervals;

[0088] A first encapsulation layer 81 located on one side of the first solder mask layer 31, a conductive block 6 encapsulated in the first encapsulation layer 81 and located at the first hole position, and a first chip 51 with double-sided I / O ports located at the second hole position. The first encapsulation layer 81 is provided with a fourth hole position for exposing the I / O ports on one side of the first chip 51 and the conductive block 6;

[0089] A first rewiring layer 21, which is located on the first encapsulation layer 81 and is connected to the conductive block 6 through conductive posts in the fourth hole position;

[0090] Metal bump 9, connected to the pad area of the first redistribution layer 21;

[0091] The second redistribution layer 23 and the second solder mask layer 32 located on the side of the first solder mask layer 31 away from the first chip 51 in sequence, and the second chip 52 mounted on the second solder mask layer 32 facing away from the first chip 51. A third hole is provided at the position of the second solder mask layer 32 corresponding to the conductive block 6. The I / O port of the second chip 52 is connected to the second redistribution layer 23 through a lead 7 passing through the third hole.

[0092] In this embodiment, the mos chip and the controller chip are three-dimensionally stacked, which can effectively reduce RDSON, reduce the package size, improve the system integration, effectively avoid the phenomenon of voids generated in the TMV structure, greatly reduce the process difficulty of electroplating, shorten the electroplating time, improve the reliability of the product, and reduce the production cost.

[0093] Furthermore, in order to achieve stable electrical connection between the conductive block 6 and the second redistribution layer 23 and between the first chip 51 and the second redistribution layer 23, the low-RDSON three-dimensional stacked integrated package structure of this embodiment further includes solder paste 4. The solder paste 4 is located in the first hole and the second hole. One side of the solder paste 4 is connected to the first chip 51 and the conductive block 6, and the other side is connected to the second redistribution layer 23.

[0094] Among them, the low-RDSON three-dimensional stacked integrated package structure further includes a second encapsulation layer 82 located on the second solder mask layer 32 and covering the second chip 52 and the lead 7 to protect the second chip 52 and the lead 7.

[0095] In this embodiment, the low-RDSON three-dimensional stacked integrated package structure further includes a third encapsulation layer 83 located on the first encapsulation layer 81 and covering the first redistribution layer 21. The third encapsulation layer 83 is provided with a hole for the pad area of the first redistribution layer 21 to be exposed, and the metal bump 9 is located in this hole.

[0096] Furthermore, the low-RDSON three-dimensional stacked integrated package structure further includes a seed layer located on the first encapsulation layer 81 and the surface of the fourth hole. The first redistribution layer 21 is located on the seed layer and is connected to the conductive pillars filling the fourth hole. The seed layer in this embodiment is not shown in the figure.

[0097] Among them, the seed layer includes a titanium metal layer located on the first encapsulation layer 81 and the surface of the fourth hole and a copper metal layer located on the titanium metal layer. Among them, the titanium metal layer has high adhesion, excellent conductivity and uniform thickness. Through the titanium metal layer, the copper metal layer can be stably attached to the first encapsulation layer 81.

[0098] Of course, the seed layer in this embodiment is not limited to a two-layer structure (titanium metal layer, copper metal layer), and can also be a single layer or a structure with more than two layers. The material of the seed layer is not limited to the laminated combination of two single metal materials, and can also be a single metal material or an alloy material, as long as the electrical connection stability between the first wiring layer 21 and the conductive block 6 and the I / O ports of the first chip 51 can be achieved, and details are not elaborated here.

[0099] Optionally, the number of the first chips 51 is one or more, and the specific number and specifications are determined according to the product design and are not specifically limited.

[0100] It should be noted that the above specific implementation manners are only the preferred embodiments of the present invention and the applied technical principles. Those skilled in the art should understand that various modifications, equivalent replacements, changes, etc. can be made to the present invention. However, as long as these transformations do not deviate from the spirit of the present invention, they should be within the protection scope of the present invention. In addition, some terms used in the specification and claims of this application are not restrictive, but are only for the convenience of description.

Claims

1. A preparation method of a three-dimensional stacked integrated package structure with low RDSON, characterized in that, It includes the following steps: S10. Provide a carrier board, sequentially mount a conductive material and a first solder mask layer on one side of the carrier board along its thickness direction, perform an opening process on the first solder mask layer to form a first hole position and a second hole position where part of the conductive material is exposed, and apply solder paste at the first hole position and the second hole position respectively; S20a. Mount a first chip with double-sided I / O ports at the solder paste corresponding to the first hole position and mount a conductive block at the solder paste corresponding to the second hole position; S20b. Encapsulate the first chip and the conductive block to form a first encapsulation layer; S20c. Perform an opening process at the position of the I / O ports on the side of the first encapsulation layer corresponding to the conductive block and the side of the first chip away from the second chip to form a fourth hole position; S20d. Fabricate a first redistribution layer on the surface of the first encapsulation layer and connect the first redistribution layer to the conductive pillars fabricated in the fourth hole position; S30. Debond, merge, flip and fix, and etch the conductive material to form a second redistribution layer; S40. Fabricate a second solder mask layer on the side of the second redistribution layer away from the first chip, and perform an opening process at the position of the second solder mask layer corresponding to the conductive block to form a third hole position; S50. Mount a second chip on the side of the second solder mask layer away from the first chip, make the I / O ports of the second chip face away from the first chip, connect the I / O ports of the second chip and the second redistribution layer by leads passing through the third hole position, and encapsulate the second chip to form a second encapsulation layer.

2. The preparation method of the low RDSON three-dimensional stacked integrated package structure according to claim 1, after step S50, it further includes the following steps: S60. Debond, merge, flip and fix, fabricate a third encapsulation layer on the surface of the first redistribution layer and the surface of the first encapsulation layer exposed outside the first redistribution layer, and perform an opening process on the third encapsulation layer to expose the pad area of the first redistribution layer; S70. Provide metal bumps and weld and implant the metal bumps into the pad area of the first redistribution layer.

3. The manufacturing method of the low RDSON three-dimensional stacked integrated package structure according to claim 1, characterized in that, The material of the conductive block is Cu, Ag or Au.

4. A low RDSON three-dimensional stacked integrated packaging structure prepared by the preparation method according to any one of claims 1 to 3, characterized in that, It includes: A first solder mask layer, which is provided with a first hole position and a second hole position that penetrate through it along its thickness direction at intervals; A first encapsulation layer on one side of the first solder mask layer, a conductive block encapsulated in the first encapsulation layer and located at the first hole position, and a first chip with double-sided I / O ports located at the second hole position. The first encapsulation layer is provided with a fourth hole position for the I / O ports on one side of the first chip and the conductive block to be exposed; A first redistribution layer, which is located on the first encapsulation layer and is connected to the conductive block through the conductive pillars in the fourth hole position; Metal bumps, which are connected to the pad area of the first redistribution layer; A second redistribution layer and a second solder mask layer, which are successively located on the side of the first solder mask layer away from the first chip, and a second chip mounted on the second solder mask layer opposite to the first chip. A third hole is formed in the second solder mask layer at a position corresponding to the conductive block. The I / O ports of the second chip are connected to the second redistribution layer through leads passing through the third hole.

5. The low RDSON three-dimensional stacked integrated package structure according to claim 4, wherein, It further includes solder paste, which is located in the first hole and the second hole. One side of the solder paste is connected to the first chip and the conductive block, and the other side is connected to the second redistribution layer.

6. The low RDSON three-dimensional stacked integrated package structure according to claim 4, wherein, It further includes a second encapsulation layer located on the second solder mask layer and covering the second chip and the leads.

7. The three-dimensional stacked integrated package structure with low RDSON according to claim 4, characterized in that, It further includes a third encapsulation layer located on the first encapsulation layer and covering the first redistribution layer. The third encapsulation layer is provided with a hole for exposing the pad area of the first redistribution layer, and the metal bump is located in this hole.

8. The low RDSON three-dimensional stacked integrated package structure according to claim 4, characterized in that, It further includes a seed layer located on the surface of the first encapsulation layer and the fourth hole. The first redistribution layer is located on the seed layer and is connected to the conductive pillars filling the fourth hole.

9. The low RDSON three-dimensional stacked integrated package structure according to claim 4, wherein The number of the first chips is one or more.

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