Communication control circuits and electronic equipment

Abstract

The present invention discloses a communication control circuit and electronic equipment, the communication control circuit comprises: a signal modulation circuit, the signal modulation circuit comprises a first signal input terminal, a strobe signal input terminal and an output terminal, the signal modulation circuit is used to modulate a first communication signal connected to the first signal input terminal and a strobe signal connected to the strobe signal input terminal and then output a modulated signal; an integrated chip, the integrated chip comprises a first input / output terminal and a second input / output terminal, the first input / output terminal is connected to the output terminal of the signal modulation circuit, and the second input / output terminal of the integrated chip is used to connect a second communication signal. The present invention is conducive to simplifying the packaging of the integrated chip and reducing the manufacturing cost of the integrated chip.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a communication control circuit and electronic equipment. Background Art

[0002] In existing integrated chip communications, three signal lines are usually required to achieve communication, so three I / O ports need to be set up on the integrated chip to access three signals. The more pins an integrated chip has, the more complex the process is, and it brings great design pressure to circuit wiring, etc. In addition, the more pins an integrated chip has, the smaller the scope of use of the package, so the packaging cost and price will be higher. Summary of the invention

[0003] The main purpose of the present invention is to provide a communication control circuit and an electronic device, aiming to simplify the packaging of an integrated chip.

[0004] To achieve the above object, the present invention provides a communication control circuit, the communication control circuit comprising:

[0005] A signal modulation circuit, the signal modulation circuit comprising a first signal input terminal, a strobe signal input terminal and an output terminal, the signal modulation circuit being used to modulate a first communication signal connected to the first signal input terminal and a strobe signal connected to the strobe signal input terminal and then output a modulated signal;

[0006] An integrated chip, the integrated chip includes a first input / output terminal and a second input / output terminal, the first input / output terminal is connected to the output terminal of the signal modulation circuit, and the second input / output terminal of the integrated chip is used to access the second communication signal.

[0007] Optionally, a signal demodulation circuit is integrated in the integrated chip, and an input end of the signal demodulation circuit is connected to the first input / output end;

[0008] The signal demodulation circuit is used to demodulate the connected modulated signal into a chip selection signal and an internal communication signal.

[0009] Optionally, the signal demodulation circuit includes a first signal processing circuit and a second signal processing circuit, an input end of the first signal processing circuit and the second signal processing circuit are respectively connected to the first input / output end, and the output end of the first signal processing circuit is connected to another input end of the second signal processing circuit.

[0010] Optionally, the signal modulation circuit includes a first resistor and a first diode, the anode of the first diode is the selection signal input terminal of the signal modulation circuit, the first end of the first resistor is the first signal input terminal of the signal modulation circuit; the common end of the second end of the first resistor and the cathode of the first diode is the output terminal of the signal modulation circuit.

[0011] Optionally, the signal modulation circuit further includes a first pull-up resistor, a first end of the first pull-up resistor is connected to the anode of the first diode, and a second end of the first pull-up resistor is connected to a first DC power supply.

[0012] Optionally, a second resistor is integrated in the integrated chip, a first end of the second resistor is connected to the first input / output end, and a second end of the second resistor is grounded.

[0013] Optionally, the signal modulation circuit includes a third resistor and a second diode, the cathode of the second diode is the selection signal input terminal of the signal modulation circuit, the first end of the third resistor is the first signal input terminal of the signal modulation circuit; the common end of the second end of the third resistor and the anode of the second diode is the output terminal of the signal modulation circuit.

[0014] Optionally, the signal modulation circuit further includes a first pull-down resistor, a first end of the first pull-down resistor is connected to the cathode of the second diode, and a second end of the first pull-down resistor is grounded.

[0015] Optionally, a fourth resistor is integrated in the integrated chip, a first end of the fourth resistor is connected to the first input / output end, and the fourth resistor is connected to a power supply end of the integrated chip.

[0016] The present invention further provides an electronic device, comprising the communication control circuit as described above.

[0017] The communication control circuit of the present invention is provided with a signal modulation circuit, and modulates the first communication signal connected to the first signal input terminal and the selection signal connected to the selection signal input terminal, and then outputs the modulated signal to the integrated chip, the first input / output terminal of the integrated chip is connected to the output terminal of the signal modulation circuit, and the second input / output terminal of the integrated chip is connected to the second communication signal. The integrated chip of the present invention uses one pin to realize the multiplexing input of two-way signals, and only two chip pins are needed to realize the input of three-way signals, which can save the pins of the integrated chip. The present invention is conducive to simplifying the packaging of the integrated chip and reducing the production cost of the integrated chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of functional modules of an embodiment of a communication control circuit of the present invention;

[0020] Figure 2 A schematic diagram of functional modules of another embodiment of the communication control circuit of the present invention;

[0021] Figure 3 A schematic diagram of the circuit structure of an embodiment of a communication control circuit of the present invention;

[0022] Figure 4 FIG. 2 is a schematic diagram of the circuit structure of another embodiment of the communication control circuit of the present invention.

[0023] Description of Figure Numbers:

[0024]

[0025] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0028] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0029] The present invention proposes a communication control circuit, which is suitable for an electronic device provided with an integrated chip. For example, an electronic device provided with an MCU and a plurality of memories and processors, the MCU is connected to these integrated chips respectively, and when working, the corresponding integrated chip is triggered to work by a strobe signal. Usually, when communicating between chips, three signal lines need to be set, namely, a strobe signal (chip select signal), a clock signal line and a data signal line. Therefore, at least three chip pins need to be provided on the MCU and each integrated chip to realize communication between chips. However, when designing a chip, if one more IC pin is added, a chip package with more than one pin position should be used, which greatly increases the packaging cost of the IC. For example, the IC design has exactly 25 pins: 3 communication control pins and 22 other function pins; at this time, usually only a general package with 28 pins can be selected, and if only 2 control signals are used, a general package with 24 pins can be used. Because the 24-pin package is more widely used than the 28-pin package, the packaging cost and cost will be much lower. And the chip process can be reduced.

[0030] Reference Figures 1 to 4 In one embodiment of the present invention, a new communication control circuit is provided, which is intended to use two pins to realize signal transmission on three signal lines. The communication control circuit includes:

[0031] A signal modulation circuit 10, wherein the signal modulation circuit 10 comprises a first signal input terminal, a strobe signal input terminal and an output terminal, and the signal modulation circuit 10 is used to modulate a first communication signal connected to the first signal input terminal and a strobe signal connected to the strobe signal input terminal and then output a modulated signal;

[0032] The integrated chip 20 includes a first input / output terminal I / O1 and a second input / output terminal, wherein the first input / output terminal I / O1 is connected to the output terminal of the signal modulation circuit 10, and the second input / output terminal I / O2 of the integrated chip 20 is used to access the second communication signal.

[0033] In this embodiment, the first signal input terminal of the signal modulation circuit 10 and the second input / output terminal I / O2 of the integrated chip 20 are used to input a clock signal and a data signal, respectively, wherein the first signal input terminal of the signal modulation circuit 10 can be connected to a clock signal, and the second input / output terminal I / O2 inputs a data signal. Alternatively, the first signal input terminal of the signal modulation circuit 10 can be connected to a data signal, and the second input / output terminal I / O2 inputs a clock signal. In this embodiment, the first communication signal is recorded as "signal A", and the second communication signal connected to the second input / output terminal I / O2 is recorded as "signal B". After the signal modulation circuit 10 modulates the selection signal and the "signal A", it outputs a modulated signal to the first input / output terminal I / O1 of the integrated chip 20. It is modulated into a signal through level modulation and sent to the inside of the integrated chip 20 through an IC pin.

[0034] It can be understood that the selection signal can be a high-level trigger integrated chip 20, or a low-level trigger integrated chip 20. Specifically, when the integrated chip 20 is triggered at a high level, in the non-selected state, the signal connected to the selection signal input terminal of the signal modulation circuit 10 is a low level. At this time, regardless of whether there is a signal input to the first signal input terminal, the signal modulation circuit 10 does not perform modulation. In the selected state, the signal connected to the selection signal input terminal of the signal modulation circuit 10 is a high level, and the signal modulation circuit 10 modulates the high-level or low-level communication signal input to the first signal input terminal with the high-level selection signal and outputs the integrated chip 20. When the integrated chip 20 is triggered at a low level, in the non-selected state, the signal connected to the selection signal input terminal of the signal modulation circuit 10 is a high level. At this time, regardless of whether there is a signal input to the first signal input terminal, the signal modulation circuit 10 does not perform modulation. In the selection state, the signal input terminal of the signal modulation circuit 10 receives a low-level signal. The signal modulation circuit 10 modulates the high-level or low-level communication signal input from the first signal input terminal with the high-level selection signal and outputs the integrated chip 20.

[0035] In the integrated chip 20, the integrated chip 20 can demodulate the modulated signal, and decompose and identify the "signal A" and the selection signal. When the selection signal is not connected, the integrated chip 20 is in a dormant state. When the selection signal is connected, the integrated chip 20 realizes data transmission according to the decomposed A signal and the B signal connected to the second input / output terminal I / O2, thereby realizing the function of the integrated chip 20.

[0036] The communication control circuit of the present invention is provided with a signal modulation circuit 10, and modulates the first communication signal connected to the first signal input terminal and the selection signal connected to the selection signal input terminal, and then outputs the modulated signal to the integrated chip 20. The first input / output terminal I / O1 of the integrated chip 20 is connected to the output terminal of the signal modulation circuit 10, and the second input / output terminal I / O2 of the integrated chip 20 is connected to the second communication signal. The integrated chip 20 of the present invention uses one pin to realize the multiplexing input of two-way signals, and only two chip pins are needed to realize the input of three-way signals, which can save the pins of the integrated chip 20. The present invention is conducive to simplifying the packaging of the integrated chip 20 and reducing the manufacturing cost of the integrated chip 20.

[0037] Reference Figures 1 to 4 In one embodiment, the integrated chip 20 integrates a signal demodulation circuit 21, and the input end of the signal demodulation circuit 21 is connected to the first input / output end I / O1;

[0038] The signal demodulation circuit 21 is used to demodulate the received modulated signal into a chip selection signal and an internal communication signal.

[0039] In this embodiment, the signal demodulation circuit 21 is integrated inside the IC, and the signal sent is decomposed into a "selection signal" and a "signal A" by level comparison, and the three communication control line signals of the IC are converted into signals that can be input through two IC pins, while maintaining the timing compatibility with the original three communication control lines. In this way, the chip packaging cost can be greatly reduced by adding peripheral devices with limited cost, and the original communication control timing can be maintained.

[0040] Furthermore, in the above embodiment, the signal demodulation circuit 21 includes a first signal processing circuit 211 and a second signal processing circuit 212, an input end of the first signal processing circuit 211 and the second signal processing circuit 212 are respectively connected to the first input / output end I / O1, and an output end of the first signal processing circuit 211 is connected to another input end of the second signal processing circuit 212.

[0041] In this embodiment, the integrated chip 20 can be a microprocessor such as a single chip microcomputer, DSP and FPGA, or a functional chip such as a memory. Those skilled in the art can integrate some hardware circuits and software programs or algorithms in the integrated chip 20, use various interfaces and lines to connect various parts of the entire electronic device, and execute or execute the software programs and / or modules in the integrated chip 20, and call the data in the integrated chip 20 to execute various functions of the electronic device and process data, thereby monitoring the electronic device as a whole, or realizing various functions of the electronic device. The first signal processing circuit 211 and the second signal processing circuit 212 are integrated in the integrated chip 20. In a specific embodiment, hardware circuits such as comparators can be used to implement them. When the levels of the selection signal and the signal A are input or not input, they will be reflected differently in the modulation signal output by the signal modulation circuit 10. The "demodulation threshold 1" and "demodulation threshold 2" are reasonably configured inside the chip, wherein the first signal processing circuit 211 is used to trigger the second signal processing circuit 212 to work according to whether the modulation signal meets the demodulation threshold 1 condition. If so, the second signal processing circuit 212 is triggered, otherwise the second signal processing circuit 212 does not work. After being triggered, the second signal processing circuit 212 compares the modulated signal with the demodulation threshold 2 to identify whether the input signal A is at a high level or a low level.

[0042] This embodiment recovers the "internal selection signal" and "internal signal A" by comparing the level of the first input / output terminal I / O1. In the embodiment of low-level selection of the integrated chip 20, it is recognized that: "the level of the first input / output terminal I / O1">="demodulation threshold 1", at this time, the integrated chip 20 internally processes: "internal selection signal": high level (VDD), not selected. "Internal signal A": At this time, the chip interface does not work, and there is no need to care about what "signal A" is. When it is recognized that: "the level of the first input / output terminal I / O1"<"demodulation threshold 1", the internal processing at this time: "internal selection signal": low level (GND), select "internal signal A": when "the level of the first input / output terminal I / O1">"demodulation threshold 2", "internal signal A" is high level; when "the level of the first input / output terminal I / O1"<="demodulation threshold 2", "internal signal A" is low level.

[0043] In the embodiment of the high-level gating of the integrated chip 20, it is recognized that: "the level of the first input / output terminal I / O1" <= "demodulation threshold 1", at this time, the internal processing of the integrated chip 20: "internal gating signal": low level (GND), not gating. "Internal signal A": At this time, the chip interface does not work, and there is no need to care about what "signal A" is. When it is recognized that: "the level of the first input / output terminal I / O1" > "demodulation threshold 1", at this time, the internal processing: "internal gating signal": high level (VDD), gating "internal signal A": when "the level of the first input / output terminal I / O1" > "demodulation threshold 2", "internal signal A" is high level; when "the level of the first input / output terminal I / O1" <= "demodulation threshold 2", "internal signal A" is low level.

[0044] Reference Figures 1 to 4 In one embodiment, the signal modulation circuit 10 includes a first resistor R1 and a first diode D1, the anode of the first diode D1 is the selection signal input terminal of the signal modulation circuit 10, and the first end of the first resistor R1 is the first signal input terminal of the signal modulation circuit 10; the common end of the second end of the first resistor R1 and the cathode of the first diode D1 is the output terminal of the signal modulation circuit 10.

[0045] In this embodiment, the integrated chip 20 is low-level gated, that is, when not working, the gate signal is high, and when the integrated chip 20 is triggered to work, the gate signal is low. The anode of the first diode D1 is also connected to the first DC power supply VDD through the resistor R11. The resistance value of the first resistor R1 is set to be relatively large, and the driving capacity is much smaller than the first diode D1. Therefore, in the non-gated state, the gate signal is high (VDD), the anode of the first diode D1 is high and turned on, and the voltage of the first input / output terminal I / O1 is VDD-Von; wherein Von is the conduction voltage drop of the first diode D1. The chip I / O interface does not work when gated, and there is no need to care whether "signal A" is connected. In the gated state, the gate signal is low, and a low-level signal is connected externally, and the first diode D1 is cut off. At this time, the voltage of the first input / output terminal I / O1 is determined by signal A.

[0046] Reference Figures 1 to 4 In one embodiment, the integrated chip 20 further integrates a second resistor R2, a first end of the second resistor R2 is connected to the first input / output terminal I / O1, and a second end of the second resistor R2 is grounded.

[0047] In this example, when the integrated chip 20 is enabled, the voltage at the first input / output terminal I / O1 is determined by the "signal A". The voltage of the "signal A" is divided by the first resistor R1 and the second resistor R2. When the "signal A" is at a high level, the voltage at the first input / output terminal I / O1 is VDD * R2 / (R1+R2). When the "signal A" is at a low level, the voltage at the first input / output terminal I / O1 is at a low level GND. The voltage at the first input / output terminal I / O1 satisfies the following relationship: "VDD - Von" > "VDD * R2 / (R1+R2)".

[0048] In one embodiment, the signal modulation circuit 10 further includes a first pull-up resistor R11, wherein a first end of the first pull-up resistor R11 is connected to an anode of the first diode D1, and a second end of the first pull-up resistor R11 is connected to a first DC power supply VDD. The first pull-up resistor R11 is a resistor with relatively small resistance, and provides a pull-up function when the "select signal" does not have a strong pull-up. Of course, when the "select signal" itself has a strong pull-up driving capability, the R11 resistor is not required.

[0049] Reference Figures 1 to 4 In one embodiment, the signal modulation circuit 10 includes a third resistor R3 and a second diode D2, the cathode of the second diode D2 is the selection signal input terminal of the signal modulation circuit 10, and the first end of the third resistor R3 is the first signal input terminal of the signal modulation circuit 10; the common end of the second end of the third resistor R3 and the anode of the second diode D2 is the output terminal of the signal modulation circuit 10.

[0050] In this embodiment, the integrated chip 20 is high-level gated, that is, when not working, the gate signal is low-level, and when the integrated chip 20 is triggered to work, the gate signal is high-level. The cathode of the second diode D2 is also connected to the ground line through the resistor R12. The resistance value of the third resistor R3 is set to be relatively large, and the driving capacity is much smaller than the second diode D2. Therefore, in the non-gated state, the gate signal is low-level (GND), and the cathode of the second diode D2 is grounded and turned on. At this time, the voltage of the first input / output terminal I / O1 is GND + Von; wherein Von is the conduction voltage drop of the first diode D1. The chip I / O interface does not work when gated, and there is no need to care whether "signal A" is connected. In the gated state, the gate signal is high-level, a high-level signal is connected externally, and the first diode D1 is cut off. At this time, the voltage of the first input / output terminal I / O1 is determined by signal A.

[0051] Reference Figures 1 to 4In one embodiment, the integrated chip 20 further integrates a fourth resistor R4, a first end of the fourth resistor R4 is connected to the first input / output terminal I / O1, and the fourth resistor R4 is connected to the power supply terminal of the integrated chip 20.

[0052] In this example, when the integrated chip 20 is enabled, the voltage at the first input / output terminal I / O1 is determined by the "signal A". The "signal A" voltage is divided by the third resistor R3 and the fourth resistor R4. When the "signal A" is at a high level, the voltage at the first input / output terminal I / O1 is at a low level GND. When the "signal A" is at a low level, the voltage at the first input / output terminal I / O1 is VDD * R3 / (R3+R4).

[0053] Reference Figures 1 to 4 In one embodiment, the signal modulation circuit 10 further includes a first pull-down resistor R12, wherein a first end of the first pull-down resistor is connected to a cathode of the second diode D2, and a second end of the first pull-down resistor R12 is grounded. In this embodiment, the first pull-down resistor R12 is a resistor with a relatively small resistance, and provides a pull-down function when the "select signal" does not have a strong pull-down. Of course, when the "select signal" itself has a strong pull-down driving capability, the R12 resistor is not required.

[0054] The present invention further provides an electronic device, the electronic device comprising the communication control circuit as described above. The detailed structure of the communication control circuit can refer to the above embodiment, which will not be described in detail here; it can be understood that since the above communication control circuit is used in the electronic device of the present invention, the embodiment of the electronic device of the present invention includes all technical solutions of all embodiments of the above communication control circuit, and the technical effects achieved are also exactly the same, which will not be described in detail here.

[0055] The above descriptions are only optional embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A communication control circuit, characterized in that: The communication control circuit comprises: A signal modulation circuit, the signal modulation circuit comprising a first signal input terminal, a strobe signal input terminal and an output terminal, the signal modulation circuit being used to modulate a first communication signal connected to the first signal input terminal and a strobe signal connected to the strobe signal input terminal and then output a modulated signal; An integrated chip, the integrated chip comprising a first input / output terminal and a second input / output terminal, the first input / output terminal is connected to the output terminal of the signal modulation circuit, and the second input / output terminal of the integrated chip is used to access a second communication signal; The integrated chip is integrated with a signal demodulation circuit, and the input end of the signal demodulation circuit is connected to the first input / output end; The signal demodulation circuit is used to demodulate the received modulated signal into a chip selection signal and an internal communication signal; The signal demodulation circuit comprises a first signal processing circuit and a second signal processing circuit, wherein an input terminal of the first signal processing circuit and an input terminal of the second signal processing circuit are respectively connected to the first input / output terminal, and an output terminal of the first signal processing circuit is connected to another input terminal of the second signal processing circuit; The integrated chip is provided with a demodulation threshold, and the first signal processing circuit is used to trigger the second signal processing circuit to work or not work according to whether the modulated signal meets the demodulation threshold condition.

2. The communication control circuit according to claim 1, characterized in that: The signal modulation circuit includes a first resistor and a first diode, the anode of the first diode is the selection signal input terminal of the signal modulation circuit, the first end of the first resistor is the first signal input terminal of the signal modulation circuit; the common end of the second end of the first resistor and the cathode of the first diode is the output terminal of the signal modulation circuit.

3. The communication control circuit according to claim 2, characterized in that: The signal modulation circuit further includes a first pull-up resistor, a first end of the first pull-up resistor is connected to the anode of the first diode, and a second end of the first pull-up resistor is connected to a first DC power supply.

4. The communication control circuit according to claim 2, characterized in that: A second resistor is also integrated in the integrated chip, a first end of the second resistor is connected to the first input / output end, and a second end of the second resistor is grounded.

5. The communication control circuit according to claim 1, characterized in that: The signal modulation circuit includes a third resistor and a second diode, the cathode of the second diode is the selection signal input terminal of the signal modulation circuit, the first end of the third resistor is the first signal input terminal of the signal modulation circuit; the common end of the second end of the third resistor and the anode of the second diode is the output terminal of the signal modulation circuit.

6. The communication control circuit according to claim 5, characterized in that: The signal modulation circuit further includes a first pull-down resistor, a first end of the first pull-down resistor is connected to the cathode of the second diode, and a second end of the first pull-down resistor is grounded.

7. The communication control circuit according to claim 5, characterized in that: A fourth resistor is also integrated in the integrated chip, a first end of the fourth resistor is connected to the first input / output end, and the fourth resistor is connected to the power supply end of the integrated chip.

8. An electronic device, characterized in that: The electronic device comprises the communication control circuit as claimed in any one of claims 1 to 7.

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