Group delay optimization circuit and related device

Abstract

A group delay optimization circuit and a related device are provided. The group delay optimization circuit receives a first signal (e.g., a voltage signal) and a second signal (e.g., a current signal). It is noteworthy that the first signal and the second signal may experience different group delays, which may cause the first signal and the second signal to be misaligned at an amplifier circuit configured to amplify a radio frequency (RF) signal. The group delay optimization circuit is configured to determine a statistical indicator indicating a group delay offset between the first signal and the second signal. Therefore, the group delay optimization circuit can minimize the group delay offset by reducing the statistical indicator to below a defined threshold in one or more group delay optimization cycles. As a result, it is possible to pre-compensate for the group delay offset in the RF signal, thereby helping to improve the efficiency and linearity of the amplifier circuit.

Description

Technical Field

[0001] The disclosed technology generally relates to envelope tracking (ET) power management in wireless communication devices. Background Art

[0002] Mobile communication devices have become increasingly common in today's society. The popularity of these mobile communication devices is driven in part by the many functions now implemented on such devices. Increased processing power in such devices means that mobile communication devices have evolved from being mere communication tools to sophisticated mobile multimedia centers that can enhance the user experience.

[0003] The redefined user experience requires higher data rates provided by wireless communication technologies, such as Long Term Evolution (LTE). To achieve higher data rates in mobile communication devices, complex power amplifiers (PAs) may be employed to increase the output power of radio frequency (RF) signals transmitted by the mobile communication devices (e.g., to maintain sufficient energy per bit). However, the increased output power of RF signals may result in increased power consumption and heat dissipation of the mobile communication devices, thereby compromising overall performance and user experience.

[0004] Envelope tracking is a power management technique designed to increase the efficiency level of PAs, thereby helping to reduce power consumption and heat dissipation in mobile communication devices. As the name implies, envelope tracking employs a system that tracks the amplitude envelope of the RF signal transmitted by the mobile communication device. The envelope tracking system continuously adjusts the supply voltage applied to the PA to ensure that the PA can operate at a higher efficiency for a given instantaneous output power requirement of the RF signal.

[0005] However, envelope tracking systems can only maintain good linearity and high efficiency up to an inherent bandwidth limit. With the advent of fifth generation new radio (5G-NR) technology, RF signals may be modulated with higher bandwidths (e.g., >100 MHz) than the inherent bandwidth limit of envelope tracking systems, thereby reducing the linearity and efficiency of envelope tracking systems. Therefore, it is desirable to improve the linearity and efficiency of envelope tracking systems to support 5G-NR technology. Summary of the invention

[0006] Aspects disclosed in the detailed description include a group delay optimization circuit and related devices. In the examples discussed herein, the group delay optimization circuit receives a first signal (e.g., a voltage signal) and a second signal (e.g., a current signal). It is noteworthy that the first signal and the second signal may experience different group delays, which may cause the first signal and the second signal to be misaligned at an amplifier circuit configured to amplify a radio frequency (RF) signal. In this regard, the group delay optimization circuit is configured to determine a statistical indicator indicating a group delay offset between the first signal and the second signal. Therefore, the group delay optimization circuit can minimize the group delay offset by reducing the statistical indicator to below a defined threshold in one or more group delay optimization cycles. As a result, it is possible to pre-compensate for the group delay offset in the RF signal, thereby helping to improve the efficiency and linearity of the amplifier circuit.

[0007] In one aspect, a group delay optimization circuit is provided. The group delay optimization circuit includes a first input node configured to receive a first signal. The group delay optimization circuit also includes a second input node configured to receive a second signal. The group delay optimization circuit also includes a control circuit. The control circuit is configured to sample a first selected signal of the first signal and the second signal within a delay estimation window corresponding to a second selected signal of the first signal and the second signal to generate a plurality of amplitude samples of the first selected signal. The control circuit is also configured to determine a statistical indicator indicating a group delay offset between the first signal and the second signal based on the amplitude samples. The control circuit is also configured to reduce the statistical indicator to below a defined threshold in one or more group delay optimization cycles to minimize the group delay offset between the first signal and the second signal.

[0008] On the other hand, an ET device is provided. The ET device includes an amplifier circuit configured to receive a signal corresponding to a time-varying signal envelope from a coupled transceiver circuit and amplify the signal based on an ET voltage signal. The ET device includes an ET integrated circuit (ETIC). The ETIC is configured to generate an ET voltage signal based on an ET target voltage signal. The ETIC is also configured to generate a sense current signal corresponding to a time-varying current envelope, which is proportionally related to the time-varying signal envelope. The ET device also includes a group delay optimization circuit. The group delay optimization circuit includes a first input node configured to receive a selected voltage signal from the ET target voltage signal and the ET voltage signal. The group delay optimization circuit also includes a second input node configured to receive the sense current signal. The group delay optimization circuit also includes a control circuit. The control circuit is configured to sample a first selected signal from the sense current signal and the selected voltage signal in a delay estimation window corresponding to a second selected signal from the sense current signal and the selected voltage signal to generate a plurality of amplitude samples of the first selected signal. The control circuit is also configured to determine a statistical indicator indicating a group delay offset between the selected voltage signal and the sense current signal based on the amplitude samples. The control circuit is further configured to reduce the statistical indicator below a defined threshold during one or more group delay optimization cycles to minimize a group delay offset between the selected voltage signal and the sensed current signal.

[0009] Those skilled in the art may understand the scope of the present disclosure and recognize other aspects of the present disclosure after reading the following detailed description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0011] Figure 1A is a schematic diagram of an exemplary prior art envelope tracking (ET) amplifier arrangement that may experience overall linearity performance degradation due to inherent processing and / or propagation delays of prior art ET arrangements;

[0012] Figure 1B is provided in Figure 1A A diagram showing an exemplary illustration of a time misalignment between a time-varying voltage envelope and a time-varying signal envelope that may occur in a prior art ET device;

[0013] Figure 1C How does the time delay affect Figure 1A A graph showing an exemplary illustration of an adjacent channel leakage ratio (ACLR) of an amplifier circuit in a conventional ET device;

[0014] Figure 2 is provided due to Figure 1A A symbol diagram of an exemplary diagram of amplitude changes of ET voltage and load current caused by group delay changes between a time-varying ET voltage envelope and a time-varying signal envelope in a conventional ET device;

[0015] Figure 3 is a schematic diagram of an exemplary group delay optimization circuit configured in accordance with an embodiment of the present disclosure, which optimizes a group delay offset between a voltage signal and a current signal by minimizing a statistical indicator indicative of a statistical distribution of the voltage signal and / or the current signal;

[0016] Figure 4 is a schematic diagram of an exemplary group delay optimization circuit configured in accordance with an alternative embodiment of the present disclosure;

[0017] Figure 5 is a schematic diagram of an exemplary group delay optimization circuit configured in accordance with another alternative embodiment of the present disclosure;

[0018] Fig. 6A According to an embodiment of the present disclosure, the Figures 3 to 5 A schematic diagram of an exemplary ET device of a group delay optimization circuit; and

[0019] Figure 6B According to another embodiment of the present disclosure, Figures 3 to 5 Schematic diagram of an exemplary ET device of a group delay optimization circuit. DETAILED DESCRIPTION

[0020] The embodiments set forth below represent necessary information to enable those skilled in the art to practice the embodiments, and show the best mode of practicing the embodiments. When reading the following description according to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure, and will recognize the application of these concepts not particularly proposed herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0021] It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] It should be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending to another element "on", it can be directly on or directly extended to another element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly on" or "directly extending to another element", there is no intermediate element. Similarly, it should be understood that when an element such as a layer, region or substrate is referred to as being "above" or extending to another element "above", it can be directly above or directly extended to another element, or there can also be an intermediate element. On the contrary, when an element is referred to as being "directly above" or "directly extending to another element", there is no intermediate element. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intermediate element. On the contrary, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0023] Relative terms, such as "below" or "above" or "up" or "lower" or "horizontally" or "vertically", may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It should be understood that these terms, as well as those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0024] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should be further understood that, unless explicitly defined herein, the terms used herein should be interpreted as having a meaning consistent with that in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0026] Aspects disclosed in the detailed description include a group delay optimization circuit and related devices. In the examples discussed herein, the group delay optimization circuit receives a first signal (e.g., a voltage signal) and a second signal (e.g., a current signal). It is noteworthy that the first signal and the second signal may experience different group delays, which may cause the first signal and the second signal to be misaligned at an amplifier circuit configured to amplify a radio frequency (RF) signal. In this regard, the group delay optimization circuit is configured to determine a statistical indicator indicating a group delay offset between the first signal and the second signal. Therefore, the group delay optimization circuit can minimize the group delay offset by reducing the statistical indicator to below a defined threshold in one or more group delay optimization cycles. As a result, it is possible to pre-compensate for the group delay offset in the RF signal, thereby helping to improve the efficiency and linearity of the amplifier circuit.

[0027] Before discussing the group delay optimization circuit of the present disclosure, first refer to Figures 1A to 1C , briefly summarizes existing ET devices that may experience overall linearity performance degradation due to the inherent time delays associated with existing ET devices. Figure 2 This paper discusses how group delay changes affect the amplitude changes of voltage and current signals to help establish the basis for using statistical methods to determine the optimal delay offset between current and voltage signals. Figure 3 A discussion begins with specific exemplary aspects of the group delay optimization circuit of the present disclosure.

[0028] Figure 1A is a schematic diagram of an exemplary prior art ET device 10 that may experience overall linearity performance degradation due to inherent processing and / or propagation delays of the prior art ET device 10. The prior art ET device 10 includes a signal processing circuit 12, an ET integrated circuit (ETIC) 14, and an amplifier circuit 16. The signal processing circuit 12 receives a digital signal 18 that includes a plurality of time-varying digital signal amplitudes 20 representing a time-varying digital signal envelope 22. Hereinafter, the phrase "time-varying" is used to refer to a parameter (e.g., amplitude, voltage, power, etc.) that varies (e.g., increases or decreases) over time.

[0029] Signal processing circuit 12 is configured to convert digital signal 18 into RF signal 24 having time varying signal envelope 26 formed based on time varying digital signal envelope 22. In this regard, time varying digital signal envelope 22 defined by time varying digital signal amplitude 20 may be considered a digital representation of time varying signal envelope 26.

[0030] The digital signal 18 may be modulated to include a digital in-phase signal 28I having a plurality of time-varying in-phase amplitudes I and a digital quadrature signal 28Q having a plurality of time-varying quadrature amplitudes Q. In this regard, each of the time-varying digital signal amplitudes 20 of the digital signal 18 may be represented as

[0031] The prior ET device 10 includes a mixer 30 that combines the time-varying digital signal amplitude 20 with a digital voltage reference signal 32 to generate a digital target voltage reference signal 34. In this regard, the digital target voltage reference signal 34 is associated with the time-varying digital signal envelope 22, and thus the time-varying digital signal amplitude 20.

[0032] The existing ET device 10 includes a look-up table (LUT) circuit system 36 (in Figure 1A 4. In one embodiment, the LUT circuit system 36 is a digital signal processing unit (hereinafter referred to as “LUT”) that can store a plurality of predetermined target voltage amplitude values ​​corresponding to the time-varying digital signal amplitude 20. In this regard, the LUT circuit system 36 converts the time-varying digital signal amplitude 20 into a plurality of time-varying digital target voltage amplitudes 38 and associates the time-varying digital target voltage amplitudes 38 with the digital target voltage signal 40. As a result of this digital conversion, the time-varying digital target voltage amplitudes 38 may be distorted. For example, the LUT circuit system 36 may be non-strictly monotonic. As a result, the digital target voltage amplitudes in the time-varying digital target voltage amplitudes 38 may become higher or lower than the corresponding digital signal amplitudes in the time-varying digital signal amplitudes 20.

[0033] The existing ET device 10 includes a voltage digital-to-analog converter (DAC) 42 configured to convert a digital target voltage signal 40 into a target voltage signal 44 having a time-varying target voltage envelope 46 formed based on the time-varying digital target voltage amplitude 38. The voltage DAC 42 is configured to provide the target voltage signal 44 to the ETIC 14.

[0034] The ETIC 14 receives a target voltage signal 44 having a time-varying target voltage envelope 46. The time-varying target voltage envelope 46 may represent the ET target voltage V 目标 The ETIC 14 is configured to generate an ET voltage V having a time-varying ET voltage envelope 48. CC , the time-varying ET voltage envelope tracks the time-varying target voltage envelope 46. ET voltage V CC is based on the ET target voltage V 目标 Therefore, the ET voltage V CC Tracking ET target voltage V 目标 .

[0035] The amplifier circuit 16 is coupled to the signal processing circuit 12 to receive the RF signal 24 having the time-varying signal envelope 26. The amplifier circuit 16 is also coupled to the ETIC 14 to receive the ET voltage V corresponding to the time-varying ET voltage envelope 48. CC The amplifier circuit 16 is configured to generate a voltage based on the ET voltage V CCto amplify the RF signal 24. The amplifier circuit 16 may be presented to the ETIC 14 as a current source and may be responsive to receiving the ET voltage V CC The induced load current I 负载 If the time-varying signal envelope 26 corresponds to a high peak-to-average ratio (PAR), the ETIC 14 may have to provide at least a portion of the load current I 负载 , to continuously track the time-varying signal envelope 26. In this regard, in order to avoid amplitude limiting in the RF signal 24, the load current I 负载 It is necessary to rise and fall from time to time according to the time-varying signal envelope 26 of the RF signal 24. In addition, in order to maintain linearity and efficiency in the amplifier circuit 16, the ET voltage V CC The time-varying ET voltage envelope 48 of φt also needs to be closely aligned with the time-varying signal envelope 26 at the amplifier circuit 16 .

[0036] However, signal processing circuit 12, LUT circuit system 36, voltage DAC 42, and ETIC 14 may each incur processing and / or propagation delays. In addition, amplifier circuit 16 may be a multi-stage amplifier including driver stage 50 and output stage 52, which also incur corresponding processing and / or propagation delays. As a result, time-varying ET voltage envelope 48 may no longer be aligned with time-varying signal envelope 26 at amplifier circuit 16. Hereinafter, the phrase "group delay" generally refers to the delay associated with generating ET voltage V CC Or the sum of all delays (processing and propagation) associated with providing the RF signal 24 to the amplifier circuit 16.

[0037] In this regard, Figure 1B Yes Figure 1A FIG. 4 is a graph of an exemplary illustration of a time misalignment between a time-varying ET voltage envelope 48 and a time-varying signal envelope 26 . Figure 1A Combination of components Figure 1B are referenced and will not be described again here.

[0038] If the time-varying signal envelope 26 and the time-varying ET voltage envelope 48 are perfectly aligned, then the voltage V S The instantaneous amplitude of the RF signal 24 (not shown) will be substantially equal to the time t x ET voltage V CC However, if Figure 1B As shown, the time-varying signal envelope 26 lags the time-varying ET voltage envelope 48 by a time delay Δt. Thus, at time tx, the amplifier circuit 16 (not shown) receives a lower ET voltage V′. CC , instead of ET voltage V CCIn this regard, the time-varying ET voltage envelope 48 deviates from the time-varying signal envelope 26 by a voltage difference Δv at time tx. As a result, the amplifier circuit 16 may suffer from degraded linearity performance.

[0039] In a non-limiting example, the linearity performance of the amplifier circuit 16 can be measured by the adjacent channel leakage ratio (ACLR). ACLR represents the ratio between the in-band power and the out-of-band leakage power. In this regard, a higher ACLR indicates better linearity performance of the amplifier circuit 16. Figure 1C Yes Figure 1B How does the time delay Δt affect Figure 1A FIG. 1 is a graph of an exemplary illustration of the ACLR of the amplifier circuit 16 . Figure 1A and Figure 1B Combination of components Figure 1C are referenced and will not be described again here.

[0040] Figure 1C A first ACLR curve 54 and a second ACLR curve 56 are included. In a non-limiting example, the first ACLR curve 54 corresponds to an RF signal (e.g., RF signal 24) modulated with a 100 MHz bandwidth, and the second ACLR curve 56 corresponds to an RF signal (e.g., RF signal 24) modulated with a 60 MHz bandwidth. Figure 1C As shown, the first ACLR curve 54 has a steeper slope than the second ACLR curve 56. In this regard, to achieve an ACLR of -32 dB, for example, when the RF signal 24 is modulated with a 100 MHz bandwidth, the existing ET device 10 is limited to a delay budget of approximately 1.0 nanoseconds (ns). In contrast, when the RF signal 24 is modulated with a 60 MHz bandwidth, for the same ACLR of -32 dB, the existing ET device 10 will experience a more relaxed delay budget of approximately 1.3 ns.

[0041] It is worth noting that the RF signal 24 may be a long term evolution (LTE) signal, which is typically modulated with a modulation bandwidth of up to 60 MHz, or a fifth generation new radio (5G-NR) signal, which is often modulated with a bandwidth greater than 100 MHz. In this regard, the existing ET device 10 must adhere to a tighter delay budget to achieve a desired ACLR at the amplifier circuit 16 for transmitting the RF signal 24 in a 5G-NR system.

[0042] Reference again Figure 1B, in order to mitigate linearity degradation and achieve the desired ACLR at the amplifier circuit 16, it is necessary to reduce the time delay Δt between the time-varying ET voltage envelope 48 and the time-varying signal envelope 26. However, it may be difficult to adequately do this in existing ET devices 10 to meet the tighter delay budget required to transmit 5G-NR signals modulated with higher modulation bandwidths (e.g., >100 MHz). As such, it may be desirable to improve the delay tolerance of existing ET devices 10 to reduce linearity degradation caused by time misalignment between the time-varying ET voltage envelope 48 and the time-varying signal envelope 26.

[0043] It is worth noting that the time delay Δt between the time-varying ET voltage envelope 48 and the time-varying signal envelope 26 may cause the ET voltage V CC and load current I 负载 In this regard, Figure 2 is provided due to Figure 1A The ET voltage V caused by the group delay variation between the time-varying ET voltage envelope 48 and the time-varying signal envelope 26 in the prior art ET device 10 CC and load current I 负载 Graph 58 is an exemplary diagram of the amplitude variation of . Figure 1A Combining components in Figure 2 are referenced and will not be re-described here.

[0044] In graph 58, frequency band region 60 represents the ET voltage V when the time-varying ET voltage envelope 48 is aligned with the time-varying signal envelope 26. CC and load current I 负载 The graph 58 includes a plurality of first points 62 and a plurality of second points 64. The first point 62 represents the ET voltage V when the time-varying ET voltage envelope 48 is ahead of the time-varying signal envelope 26. CC and load current I 负载 The second point 64 represents the ET voltage V when the time-varying ET voltage envelope 48 is behind the time-varying signal envelope 26. CC and load current I 负载 distribution.

[0045] An important observation can be made from graph 58. When the time-varying ET voltage envelope 48 is aligned with the time-varying signal envelope 26, the ET voltage V CC and load current I 负载 The distribution of V may be close to the statistical mean (eg, in the frequency band region 60). In contrast, when the time-varying ET voltage envelope 48 is not aligned with the time-varying signal envelope 26, the ET voltage V CC and load current I 负载 The distribution of may deviate from the statistical mean, such as the first point 62 or the second point 64.

[0046] In this regard, it may be indicated that the ET voltage V CC and / or load current I 负载 A defined statistical metric (e.g., standard deviation) of the distribution of is associated with the group delay offset between the time-varying ET voltage envelope 48 and the time-varying signal envelope 26. As discussed below in exemplary aspects of the present disclosure, by minimizing the defined statistical metric, it is possible to optimize the group delay offset between the time-varying ET voltage envelope 48 and the time-varying signal envelope 26.

[0047] In one non-limiting example, the load current I 负载 The current-dependent delay estimation window 66 is defined by the low current threshold 68 and the high current threshold 70. The current-dependent delay estimation window 66 can be determined (e.g., by simulation) to correspond to a higher voltage sensitivity. Therefore, the ET voltage V may be set within the current-dependent delay estimation window 66. CC Sampling is performed to determine the indicated ET voltage V CC The voltage-related statistical index σv of the distribution. Since the ET voltage V CC is based on the ET target voltage V 目标 generated, it is also possible to estimate the ET target voltage V in the current-dependent delay estimation window 66 目标 Sampling is performed to determine the indicated ET voltage V CC Therefore, by minimizing the voltage V CC The associated voltage-related statistical indicator σv makes it possible to optimize the group delay offset between the time-varying ET voltage envelope 48 and the time-varying signal envelope 26 .

[0048] In another non-limiting example, the ET voltage V CC (or ET target voltage V 目标 ) to define the voltage-dependent delay estimation window 72. The voltage-dependent delay estimation window 72 may be determined (e.g., by simulation) to correspond to a higher current sensitivity. Therefore, the load current I may be estimated in the voltage-dependent delay estimation window 72. 负载 Sampling is performed to determine the indicated load current I 负载 Therefore, by minimizing the load current I 负载 The associated current-related statistical indicator σi may optimize the group delay offset between the time-varying ET voltage envelope 48 and the time-varying signal envelope 26 .

[0049] In this regard, Figure 3is a schematic diagram of an exemplary group delay optimization circuit 78 configured according to an embodiment of the present disclosure, which minimizes the group delay offset between the voltage signal 80 (also referred to as the “first signal”) and the current signal 82 (also referred to as the “second signal”) by minimizing a statistical indicator σ indicating the statistical distribution of the voltage signal 80 and / or the current signal 82. Figure 2 and Figure 3 The common elements between the embodiments are shown with common element numbers and will not be described repeatedly here.

[0050] The group delay optimization circuit 78 may include a first input node 83A and a second input node 83B configured to receive a voltage signal 80 and a current signal 82, respectively. In a non-limiting example, the voltage signal 80 may be Figure 1A The ET voltage V CC Or ET target voltage V 目标 , and the current signal 82 may be the load current I 负载 Or with the load current I 负载 It is worth noting that the voltage signal 80 may correspond to a voltage group delay τ v , and the current signal 82 may correspond to the current group delay τ i Therefore, the group delay offset between the voltage signal 80 and the current signal 82 corresponds to the voltage group delay τ v and current group delay τ i The difference between (e.g., τ v -τ i or τ i -τ v ). Therefore, it is possible to adjust (increase or decrease) the voltage group delay τ v and / or current group delay τ i to adjust (increase or decrease) the group delay offset.

[0051] In one embodiment, the group delay optimization circuit 78 can be configured to sample the voltage signal 80 (also referred to as “the first selected signal of the voltage signal 80 and the current signal 82”) in the current-related delay estimation window 66 corresponding to the current signal 82 (also referred to as “the second selected signal of the voltage signal 80 and the current signal 82”) to generate a plurality of voltage amplitude samples of the voltage signal 80. Therefore, the group delay optimization circuit 78 can determine the voltage-related statistical indicator σv based on the voltage amplitude samples. The voltage-related statistical indicator σv can be determined based on any one of the following equations (Eq.1.1-1.3).

[0052]

[0053]

[0054]

[0055] In the above equations (Eq.1.1-1.3), “N” represents the count of voltage amplitude samples, and “x i " represents any one of the voltage amplitude samples, and "μ" represents the average value of the voltage amplitude samples. The group delay optimization circuit 78 can be configured to perform one or more group delay optimization cycles to minimize the group delay offset σ. In a non-limiting example, in each group delay optimization cycle, the group delay optimization circuit 78 can adjust the group delay offset between the voltage signal 80 and the current signal 82. Therefore, the group delay optimization circuit 78 can resample the voltage signal 80 to generate voltage amplitude samples and re-determine the voltage-related statistical indicator σv based on the voltage amplitude samples. The group delay optimization circuit 78 can be configured to stop the group delay optimization cycle once the voltage-related statistical indicator σv is lower than a defined threshold. Hereinafter, the group delay offset that causes the voltage-related statistical indicator σv to be lower than the defined threshold is referred to as an optimized group delay offset. Therefore, the group delay optimization circuit 78 can output a group delay correction signal 84 indicating the optimized group delay offset.

[0056] In another embodiment, the group delay optimization circuit 78 can be configured to sample the current signal 82 (also referred to as the "first selected signal of the voltage signal 80 and the current signal 82") in the voltage-dependent delay estimation window 72 corresponding to the voltage signal 80 (also referred to as the "second selected signal of the voltage signal 80 and the current signal 82") to generate a plurality of current amplitude samples of the current signal 82. Therefore, the group delay optimization circuit 78 can determine the current-related statistical indicator σi based on the voltage amplitude samples. The current-related statistical indicator σi can be determined based on any one of the following equations (Eq.2.1-2.3).

[0057]

[0058]

[0059]

[0060] Thus, the group delay optimization circuit 78 may perform a group delay optimization cycle to minimize the group delay offset to below a defined threshold and then output a group delay correction signal 84 indicative of the optimized group delay offset.

[0061] The group delay optimization circuit 78 includes a comparator circuit 86 configured to receive the voltage signal 80 and the current signal 82. The group delay optimization circuit 78 also includes a control circuit 88. In a non-limiting example, the comparator circuit 86 is coupled to the control circuit 88 via a switch circuit 90. Thus, the comparator circuit 86 can be configured to activate or deactivate the control circuit 88 via the switch circuit 90.

[0062] In one embodiment, the comparator circuit 86 can be configured to compare the current signal 82 with the low current threshold 68 and the high current threshold 70 to determine whether the current signal 82 falls within the current-related delay estimation window 66. If the comparator circuit 86 determines that the current signal 82 falls within the current-related delay estimation window 66, the comparator circuit 86 can control the switch circuit 90 to activate the control circuit 88 to determine an optimized group delay offset between the voltage signal 80 and the current signal 82 by sampling the voltage signal 80, determining the voltage-related statistical indicator σv, and minimizing the voltage-related statistical indicator σv to below a defined threshold.

[0063] In another embodiment, the comparator circuit 86 can be configured to compare the voltage signal 80 with the lower voltage threshold 74 and the upper voltage threshold 76 to determine whether the voltage signal 80 falls within the voltage-dependent delay estimation window 72. If the comparator circuit 86 determines that the voltage signal 80 falls within the voltage-dependent delay estimation window 72, the comparator circuit 86 can control the switch circuit 90 to activate the control circuit 88 to determine an optimized group delay offset between the voltage signal 80 and the current signal 82 by sampling the current signal 82, determining the current-related statistical indicator σi, and minimizing the current-related statistical indicator σi to below a defined threshold.

[0064] In a non-limiting example, the control circuit 88 includes a statistics calculator circuit 92 and a delay optimizer circuit 94. The statistics calculator circuit 92 can be configured to sample the voltage signal 80 and / or the current signal 82 in the current-dependent delay estimation window 66 and / or the voltage-dependent delay estimation window 72. Thus, the statistics calculator circuit 92 can be configured to determine the voltage-related statistical indicator σ based on the voltage amplitude samples of the voltage signal 80. v and / or determining a current-related statistical indicator σ based on the current amplitude samples of the current signal 82 i The delay optimizer circuit 94 may be configured to optimize the voltage-dependent statistical indicator σ by executing a group delay optimization cycle. v and / or current related statistical indicators σ i The optimized group delay offset between the voltage signal 80 and the current signal 82 is determined by decreasing the voltage group delay τ to below a defined threshold. It is worth noting that the delay optimizer circuit 94 can be configured to adjust the voltage group delay τ by vand / or current group delay τ i to adjust (increase or decrease) the group delay offset in each group delay optimization cycle.

[0065] The group delay optimization circuit 78 may further include a current subtraction circuit 96 . In a non-limiting example, the current subtraction circuit 96 may be configured to remove unwanted current signals from the current signal 82 before providing the current signal 82 to the comparator circuit 86 .

[0066] Figure 4 is a schematic diagram of an exemplary group delay optimization circuit 78A configured in accordance with an alternative embodiment of the present disclosure. Figure 3 and Figure 4 The common elements between the embodiments are shown with common element numbers and will not be described repeatedly here.

[0067] The group delay optimization circuit 78A includes a second comparator circuit 86A. The group delay optimization circuit 78A also includes a control circuit 88A, which further includes a second statistics calculator circuit 92A coupled to the second comparator circuit 86A via a second switch circuit 90A. In a non-limiting example, the comparator circuit 86 is configured to determine whether the current signal 82 falls within the current-dependent delay estimation window 66, and the second comparator circuit 86A is configured to determine whether the voltage signal 80 falls within the voltage-dependent delay estimation window 72.

[0068] When the comparator circuit 86 determines that the current signal 82 falls within the current-related delay estimation window 66, the comparator circuit 86 activates the statistical calculator circuit 92 to sample the voltage signal 80 and determine the voltage-related statistical indicator σ v Similarly, when the second comparator circuit 86A determines that the voltage signal 80 falls within the voltage-related delay estimation window 72, the second comparator circuit 86A activates the second statistical calculator circuit 92A to sample the current signal 82 and determine the current-related statistical indicator σ i The control circuit 88A includes a delay optimizer circuit 94A configured to determine the delay of the signal based on the voltage-related statistical indicator σ v And current related statistical indicators σ i A delay optimization cycle is performed to determine an optimized group delay offset between the voltage signal 80 and the current signal 82 .

[0069] Figure 5 is a schematic diagram of an exemplary group delay optimization circuit 78B configured in accordance with another alternative embodiment of the present disclosure. Figure 3 and Figure 5 The common elements between the embodiments are shown with common element numbers and will not be described repeatedly here.

[0070] The group delay optimization circuit 78B includes at least one second comparator circuit 86B. The group delay optimization circuit 78B also includes a control circuit 88B, which further includes at least one second statistics calculator circuit 92B coupled to the second comparator circuit 86B via at least one second switch circuit 90B. The control circuit 88B also includes a delay optimizer circuit 94B.

[0071] In one embodiment, both the comparator circuit 86 and the second comparator circuit 86B are configured to determine whether the current signal 82 decreases with the current-related delay estimation window 66. If the current signal 82 decreases with the current-related delay estimation window 66, the comparator circuit 86 and the second comparator circuit 86B are configured to activate the statistical calculator circuit 92 and the second statistical calculator circuit 92B, respectively. The statistical calculator circuit 92 and the second statistical calculator circuit 92B can simultaneously sample the voltage signal 80 to generate voltage amplitude samples and determine the voltage-related statistical indicator σv. The delay optimizer circuit 94B can perform a delay optimization cycle to determine an optimized delay offset between the voltage signal 80 and the current signal 82. In a non-limiting example, the delay optimizer circuit 94 can adjust at least one second delay offset between the voltage signal 80 and the current signal 82 in each delay optimization cycle. In this regard, the group delay optimization circuit 78B can simultaneously evaluate the voltage-related statistical indicator σv based on multiple group delay offsets. Therefore, the number of delay optimization cycles may be reduced.

[0072] In another embodiment, both the comparator circuit 86 and the second comparator circuit 86B are configured to determine whether the voltage signal 80 decreases with the voltage-dependent delay estimation window 72. If the voltage signal 80 decreases with the voltage-dependent delay estimation window 72, the comparator circuit 86 and the second comparator circuit 86B are configured to activate the statistical calculator circuit 92 and the second statistical calculator circuit 92B, respectively. The statistical calculator circuit 92 and the second statistical calculator circuit 92B can simultaneously sample the current signal 82 to generate current amplitude samples and determine the current-related statistical indicator σi. The delay optimizer circuit 94B can perform a delay optimization cycle to determine the optimized delay offset between the voltage signal 80 and the current signal 82. In a non-limiting example, the delay optimizer circuit 94 can adjust at least one second delay offset between the voltage signal 80 and the current signal 82 in each delay optimization cycle. In this regard, the group delay optimization circuit 78B can simultaneously evaluate the voltage-related statistical indicator σv based on multiple group delay offsets. Therefore, the number of delay optimization cycles may be reduced.

[0073] Can be provided in ET device Figure 3 Group delay optimization circuit 78, Figure 4 The group delay optimization circuit 78A and Figure 5The group delay optimization circuit 78B can help improve the efficiency and / or linearity performance of the amplifier circuit. In this regard, Fig. 6A According to an embodiment of the present disclosure, the Figure 3 Group delay optimization circuit 78, Figure 4 The group delay optimization circuit 78A or Figure 5 Schematic diagram of an exemplary ET device 98A of a group delay optimization circuit 78B. Figure 3 , Figure 4 , Figure 5 and Fig. 6A The common elements between the embodiments are shown with common element numbers and will not be described repeatedly here.

[0074] ET device 98A includes a circuit configured to generate a voltage signal V CC The amplifier circuit 100 amplifies the signal 102. The signal 102 that may be provided to the amplifier circuit 100 from the coupled transceiver circuit 104 corresponds to a signal similar to Figure 1A The time-varying signal envelope 106 of the time-varying signal envelope 26 in FIG.

[0075] The ET device 98A includes a circuit configured to generate a voltage signal based on the ET target voltage signal V 目标 Generate ET voltage signal V CC In a non-limiting example, the ETIC 108A includes a voltage amplifier 110 configured to generate a voltage signal based on the ET target voltage signal V 目标 Generate initial ET voltage signal V' CC The voltage amplifier 110 may be coupled to a compensation capacitor 112 configured to convert the initial ET voltage signal V′ CC Converted into ET voltage signal V CC ETIC 108A may include a feedback loop 114 configured to convert the ET voltage signal V CC A copy of ET is provided back to the voltage amplifier 110. 目标 may correspond to a time-varying target voltage envelope 116, which is similar to Figure 1A Therefore, the ETIC 108A is configured to generate an ET voltage signal V having a time-varying ET voltage envelope 118. CC , the time-varying ET voltage envelope tracks the time-varying target voltage envelope 116 .

[0076] and Figure 1A Similar to the existing ET device 10, Figures 1A to 1CFor reasons similar to those described in , ET device 98A may cause the time-varying ET voltage envelope 118 to be misaligned with the time-varying signal envelope 106 at amplifier circuit 100. Therefore, it may be desirable to combine Figure 3 Group delay optimization circuit 78, Figure 4 The group delay optimization circuit 78A and Figure 5 The group delay optimization circuit 78B of the ET device 98A is used to minimize the group delay offset between the time-varying ET voltage envelope 118 and the time-varying signal envelope 106. It is worth noting that the group delay optimization circuit 78, the group delay optimization circuit 78A and the group delay optimization circuit 78B can be integrated into the ETIC 108A or coupled to the ETIC 108A from the outside.

[0077] Similar to Figure 1A The amplifier circuit 16 in the embodiment of the present invention can be presented to the ETIC 108A as a current source and respond to receiving the ET voltage signal V CC The induced load current I 负载 If the time-varying signal envelope 106 corresponds to a higher PAR, the voltage amplifier 110 in the ETIC 108A may be forced to provide a current IAC such that the load current I 负载 The time-varying signal envelope 106 can be continuously tracked. In this regard, the current I AC Can be compared with the load current I 负载 Considering the load current I 负载 The current I AC The time-varying signal envelope 106 can likewise be closely tracked.

[0078] The voltage amplifier 110 is configured to generate a sense current signal I 感测 , which indicates the current I provided by the voltage amplifier 110 AC In a non-limiting example, the sensing current signal I 感测 With current I AC is proportionally related and therefore to the load current I 负载 In this regard, the sensed current signal I 感测 The time-varying signal envelope 106 can also be closely tracked. In this way, the sensed current signal I 感测 can be provided to the group delay optimization circuit 78 as the current signal 82. In addition, the ET target voltage signal V 目标 (Also called "ET target voltage signal V 目标 and ET voltage signal V CC The selected voltage signal in (“) can be provided to the group delay optimization circuit 78 as the voltage signal 80.

[0079] Amplifier circuit 100 may be coupled to load capacitor 120, which may sense capacitor current I CL In this regard, the load current I 负载 Can contain current I AC and capacitor current I CL Both (I 负载 =I AC +I CL ). In this regard, the capacitor current I CL may become an unwanted signal. Therefore, according to Figure 3 , the current subtraction circuit 96 may be configured to extract the current from the sensed current signal I before providing it to the comparator circuit 86. 感测 Subtract the capacitor current I CL .

[0080] Figure 6B According to another embodiment of the present disclosure, Figure 3 Group delay optimization circuit 78, Figure 4 The group delay optimization circuit 78A or Figure 5 Schematic diagram of an exemplary ET device 98B of the group delay optimization circuit 78B. Fig. 6A and Figure 6B The common elements between the embodiments are shown with common element numbers and will not be described repeatedly here.

[0081] ET device 98B includes ETIC 108B. ET device 98B and Fig. 6A The difference of the ET device 98A is that the group delay optimization circuit 78 is configured to receive the ET voltage signal V CC (Also called "ET target voltage signal V 目标 and ET voltage signal V CC The selected voltage signal in “”) is used as the voltage signal 80.

[0082] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A group delay optimization circuit, comprising: a first input node configured to receive a first signal; a second input node configured to receive a second signal; as well as A control circuit configured to: sampling a first selected one of the first signal and the second signal within a delay estimation window defined by a second selected one of the first signal and the second signal to generate a plurality of amplitude samples of the first selected signal; determining a statistical indicator indicative of a distribution of the first selected signal within the delay estimation window based on the plurality of amplitude samples; determining a group delay offset between the first signal and the second signal based on the determined statistical indicator; as well as The statistical indicator is reduced below a defined threshold in one or more group delay optimization cycles to minimize the group delay offset between the first signal and the second signal.

2. The group delay optimization circuit of claim 1 , wherein in each of the one or more group delay optimization cycles, the control circuit is further configured to: adjusting the group delay offset between the first signal and the second signal; resampling the first selected signal to generate a plurality of amplitude samples of the first selected signal; re-determining the statistical indicator based on the plurality of amplitude samples; as well as The statistical indicator is compared with the defined threshold to determine whether the statistical indicator is below the defined threshold.

3. The group delay optimization circuit according to claim 1, wherein the statistical indicator is determined based on a statistical equation selected from the group consisting of: The first statistical equation of The second statistical equation of The third statistical equation is: N represents a count of the plurality of amplitude samples; x i represents any one of the plurality of amplitude samples; and μ represents the average value of the plurality of amplitude samples. 4 . The group delay optimization circuit according to claim 1 , wherein the first signal and the second signal correspond to a voltage signal and a current signal, respectively.

5. The group delay optimization circuit according to claim 4, further comprising a comparator circuit, wherein the comparator circuit is configured to: determining whether the second selected signal falls within the delay estimation window; and The control circuit is activated in response to the second selected signal falling within the delay estimation window.

6. The group delay optimization circuit of claim 5, further comprising a current subtraction circuit coupled to the comparator circuit and configured to subtract an unwanted current signal from the current signal before providing the current signal to the comparator circuit.

7. The group delay optimization circuit according to claim 5, wherein: The comparator circuit is further configured to: determining whether the current signal falls within a current-dependent delay estimation window; and activating the control circuit in response to the current signal falling within the current-dependent delay estimation window; and The control circuit is further configured to: sampling the voltage signal within the current-dependent delay estimation window to generate a plurality of voltage amplitude samples; determining a voltage-related statistical indicator indicative of the group delay offset based on the plurality of voltage amplitude samples; as well as The voltage-related statistical indicator is reduced below the defined threshold during the one or more group delay optimization cycles to minimize the group delay offset.

8. The group delay optimization circuit according to claim 5, wherein: The comparator circuit is further configured to: determining whether the voltage signal falls within a voltage-dependent delay estimation window; and activating the control circuit in response to determining that the voltage signal falls within the voltage-dependent delay estimation window; and The control circuit is further configured to: sampling the current signal within the voltage-dependent delay estimation window to generate a plurality of current amplitude samples; determining a current-related statistical indicator indicative of the group delay offset based on the plurality of current amplitude samples; as well as The current-related statistical indicator is reduced below the defined threshold during the one or more group delay optimization cycles to minimize the group delay offset.

9. The group delay optimization circuit of claim 5, further comprising a second comparator circuit, wherein: The comparator circuit is further configured to determine whether the current signal falls within a current-dependent delay estimation window; The second comparator circuit is configured to determine whether the voltage signal falls within a voltage-dependent delay estimation window; and The control circuit is further configured to: sampling the voltage signal within the current-dependent delay estimation window to generate a plurality of voltage amplitude samples; sampling the current signal within the voltage-dependent delay estimation window to generate a plurality of current amplitude samples; determining the statistical indicator indicative of the group delay shift based on the plurality of voltage amplitude samples and the plurality of current amplitude samples; as well as The statistical indicator is reduced below the defined threshold during the one or more group delay optimization cycles to minimize the group delay offset.

10. The group delay optimization circuit of claim 5, further comprising at least one second comparator circuit, the second comparator circuit being configured to determine whether the current signal falls within the delay estimation window, wherein: In each of the one or more group delay optimization cycles, the control circuit is further configured to: adjusting at least one second group delay offset between the current signal and the voltage signal; resampling the first selected signal to generate a plurality of second amplitude samples; re-determining the statistical indicator based on the plurality of amplitude samples and the plurality of second amplitude samples; as well as The statistical indicator is compared with the defined threshold to determine whether the statistical indicator is below the defined threshold.

11. An envelope tracking (ET) device, comprising: an amplifier circuit configured to receive a signal corresponding to the time-varying signal envelope from a coupled transceiver circuit and amplify the signal based on the ET voltage signal; ET integrated circuit ETIC, which is configured to: generating the ET voltage signal based on the ET target voltage signal; as well as generating a sense current signal corresponding to a time-varying current envelope, the time-varying current envelope being proportionally related to the time-varying signal envelope; as well as A group delay optimization circuit comprising: a first input node configured to receive a selected voltage signal from among the ET target voltage signal and the ET voltage signal; a second input node configured to receive the sense current signal; and A control circuit, the control circuit being configured to: sampling a first selected one of the sensed current signal and the selected voltage signal within a delay estimation window defined by a second selected one of the sensed current signal and the selected voltage signal to generate a plurality of amplitude samples of the first selected signal; determining a statistical indicator indicative of a distribution of the first selected signal within the delay estimation window based on the plurality of amplitude samples; determining a group delay offset between the selected voltage signal and the sensed current signal based on the determined statistical indicator; and The statistical indicator is reduced below a defined threshold in one or more group delay optimization cycles to minimize the group delay offset between the selected voltage signal and the sensed current signal. 12 . The ET device of claim 11 , wherein the second input node is further configured to receive the ET target voltage signal as the selected voltage signal. 13 . The ET device of claim 11 , wherein the second input node is further configured to receive the ET voltage signal as the selected voltage signal.

14. The ET device of claim 11, wherein in each of the one or more group delay optimization cycles, the control circuit is further configured to: adjusting the group delay offset between the sensed current signal and the selected voltage signal; resampling the first selected signal to generate a plurality of amplitude samples of the first selected signal; re-determining the statistical indicator based on the plurality of amplitude samples; as well as The statistical indicator is compared with the defined threshold to determine whether the statistical indicator is below the defined threshold.

15. The ET device of claim 14, wherein the control circuit is further configured to provide the group delay offset to the coupled transceiver circuit that causes the statistical indicator to be below the defined threshold.

16. The ET device of claim 11, wherein the statistical indicator is determined based on a statistical equation selected from the group consisting of: The statistical equation of The statistical equation of The statistical equation of , where: N represents a count of the plurality of amplitude samples; x i represents any one of the plurality of amplitude samples; and μ represents the average value of the plurality of amplitude samples.

17. The ET device of claim 11, wherein the group delay optimization circuit further comprises a comparator circuit configured to: determining whether the second selected signal falls within the delay estimation window; and The control circuit is activated in response to determining that the second selected signal falls within the delay estimation window.

18. The ET device of claim 17, wherein the group delay optimization circuit further comprises a current subtraction circuit coupled to the comparator circuit and configured to subtract an unwanted current signal from the sense current signal before providing the sense current signal to the comparator circuit.

19. The ET device of claim 17, wherein: The comparator circuit is further configured to: determining whether the sensed current signal falls within a current-dependent delay estimation window; and activating the control circuit in response to determining that the sensed current signal falls within the current-dependent delay estimation window; and The control circuit is further configured to: sampling the selected voltage signal within the current-dependent delay estimation window to generate a plurality of voltage amplitude samples; determining a voltage-related statistical indicator indicative of the group delay offset based on the plurality of voltage amplitude samples; as well as The voltage-related statistical indicator is reduced below the defined threshold during the one or more group delay optimization cycles to minimize the group delay offset.

20. The ET device of claim 17, wherein: The comparator circuit is further configured to: determining whether the selected voltage signal falls within a voltage dependent delay estimation window; and activating the control circuit in response to determining that the selected voltage signal falls within the voltage-dependent delay estimation window; and The control circuit is further configured to: sampling the sensed current signal within the voltage-dependent delay estimation window to generate a plurality of current amplitude samples; determining a current-related statistical indicator indicative of the group delay offset based on the plurality of current amplitude samples; as well as The current-related statistical indicator is reduced below the defined threshold during the one or more group delay optimization cycles to minimize the group delay offset.

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