High Voltage Extended Drain MOS Transistor

Abstract

A semiconductor device (100) includes a MOS transistor (101) located in a semiconductor substrate (105) of a first conductivity type. The transistor (101) includes a body well (135) located between a drain well (130) and a substrate contact well (160). A buried voltage blocking region (155) of a second conductivity type is located in the substrate (105) and connected to the body well (135). The buried voltage blocking region (155) extends toward the substrate contact well (160), wherein an unmodified portion (195) of the substrate (105) remains between the voltage blocking region (155) and the substrate contact well (160).

Description

Technical Field

[0001] This invention relates generally to semiconductor devices, and more particularly to drain-extended MOS transistors with improved high voltage operation. Background Art

[0002] Drain-extended (DE)-MOS transistors are used in various high voltage applications, such as power RF and driving piezoelectric ultrasonic transducers. Such transistors are generally characterized by a relatively high breakdown voltage between the drain and the substrate. However, some existing DEMOS transistors (more specifically DE-PMOS transistors) are limited to a breakdown voltage of less than about 50 V. This limitation makes DE-PMOS transistors unsuitable in some applications. Summary of the invention

[0003] The described examples include various methods and apparatus that are beneficially applicable to transistors in integrated circuits (ICs). It is expected that these embodiments can improve the performance and / or yield of such transistors and ICs, but the embodiments do not require specific results unless explicitly stated.

[0004] This description describes a device, such as a junction-terminated drain-extended MOS transistor. The device includes a MOS transistor formed in a semiconductor substrate, the semiconductor substrate being of a first conductivity type and having a body well located between a drain well and a substrate contact well. A buried voltage blocking region of a second conductivity type is connected to the body well and is located between the body well and the substrate contact well. An unmodified portion of the substrate is located between the buried voltage blocking region and the substrate contact well.

[0005] Another embodiment provides a method, for example, for forming an electrical device. The method includes forming a body well and a drain well of a DE-MOS transistor in a semiconductor substrate. A junction termination diode is also formed in the substrate, and the junction termination diode has a first terminal and a second terminal. The first terminal is connected to the substrate at a substrate contact well, and the second terminal is connected to the body well.

[0006] In yet another embodiment, an electronic device (e.g., a DE-MOS transistor) includes a p-type substrate and a first p+ well and a second p+ well within the substrate. An n-well is located within the substrate between the first p+ well and the second p+ well, and a gate is located above the n-well. A buried n-type region partially overlaps the n-well and extends from the n-well toward the first p+ well. An unmodified portion of the p-type substrate is located between the first p+ well and the buried n-type region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A plan view of an LD-MOS device formed according to various embodiments is presented.

[0008] Figure 2In the exemplary embodiment Figure 1 Cross-sectional view of an LD-MOS device.

[0009] Figure 3 Illustrated instructions include Figure 1 and 2 An exemplary push-pull driver circuit of an LD-MOS device.

[0010] Figure 4 Graphical explanation of the formation Figure 1 and 2 Embodiments of the method for an LD-MOS device.

[0011] Figures 5A to 5I A cross-sectional view is provided to illustrate a method for forming a Figure 1 and 2 Devices to implement Figure 4 The process steps of the method.

[0012] Figure 6 and 7 In the exemplary embodiment presented Figure 2 Detailed diagram of a portion of an LD-MOS device. DETAILED DESCRIPTION

[0013] The drawings are not drawn to scale. The present invention is not limited by the illustrated ordering of actions or events, because some actions or events may occur in different orders and / or simultaneously with other actions or events. In addition, some illustrated actions or events are optional to implement the method according to this description.

[0014] Figure 1 A plan view of an electronic device 100 is presented according to various embodiments, the electronic device 100 comprising, for example, a drain-extended MOS transistor 101 and a junction-termination diode 102 . Figure 2 The display device 100 is Figure 1 . Both figures are referenced in the following discussion. Some aspects of transistor 101 are described in the context of a PMOS transistor in this discussion, but are not limited thereto. Those skilled in the relevant art will appreciate that the principles of the described embodiments can be adapted for use with NMOS transistors by suitable modifications without undue experimentation.

[0015] Device 100 is formed over substrate 105, with junction termination diode 102 surrounding transistor 101 in the illustrated embodiment. As discussed further below, diode 102 provides breakdown protection, enabling transistor 101 to operate at a higher source voltage than would otherwise be possible in some applications. Substrate 105 includes a lightly doped epitaxial ("epi") layer 106 of a first polarity type (e.g., p-type). Epitaxial layer 106 may be doped, for example, with boron to achieve a resistivity in a range from about 1 ohm-cm to about 20 ohm-cm, corresponding to a resistivity from about 7e14 atoms / cm 3 to about 1.4e16 atoms / cm 3 1 to 5. The epitaxial layer 106 may have a dopant concentration within a range of 100 to 200 ohm-cm. The substrate 105 below the epitaxial layer 106 may have a higher resistivity, for example within a range from about 50 ohm-cm to about 200 ohm-cm. A field oxide layer 108 overlies the epitaxial layer 106. The transistor 101 includes a source electrode 110, a gate electrode 115, and a drain electrode 120. The diode 102 is connected to the substrate electrode 125 and the source electrode 110. Although in the illustrated embodiment the transistor 101 and the diode 102 share the source electrode 110, other embodiments may provide separate contacts for the source of the transistor 101 and the source of the diode 102.

[0016] The transistor 101 further includes a drain well 130 having a first polarity type (eg, p-type) and a body well 135 having a second polarity type (eg, n-type). The drain well 130 may be heavily doped, denoted as “p + ”, meaning that this region may be doped more heavily than the epitaxial layer 106, for example, at least about 10 16 dopant atoms / cm 3 , or the conductivity is about 0.5 ohm-cm or less. The drain well 130 is connected to the drain electrode 120 through a via 180 , and the body well 135 is connected to the source electrode 110 through another via 180 .

[0017] A surface drift region 140 of a first conductivity type (e.g., p-type) is located between the drain well 130 and the body well 135 in the surface layer and provides a current path from the drain well 130 to the body well 135. The drift region 140 can serve as an extended drain of the transistor 101. In these embodiments, the I DL The (drain current under load) may be greater than in embodiments where the unmodified epitaxial layer 106 is used as a drift region.

[0018] In some embodiments, transistor 101 includes an HV well 145 located between body well 135 and drain well 130. HV well 145 is doped with a dopant species of a second conductivity type, such as an n-type dopant when epitaxial layer 106 is p-type and transistor 101 is a PMOS transistor. In these embodiments, HV well 145 can help to spatially define drift region 140 and can also provide charge balance for blocking high voltages in the transistor off state.

[0019] For example, a gate 150 including polysilicon is located above the body well 135, and a gate dielectric 640 (see Figure 6 ) is located between the gate 150 and the body well 135. The gate 150 is connected to the gate electrode 115 through another through hole 180. A polysilicon field plate 151 located above the HV well 145 can be formed at the same time as the gate 150 and is connected to the drain electrode 120 through another through hole 180. The field plate 151 can help reduce the electric field between the drain well 130 and the HV well 145 where the electric field can be concentrated.

[0020] Figure 6 A detailed view of a portion of the body well 135, gate 150, and associated via 180 is shown. Two additional doped regions provide an interface between the body well 135 and the via 180. + Doped body contact 610 can provide an ohmic connection between via 180 and body well 135. + The doped source region 620 can operate as the source of the PMOS transistor. In the illustrated embodiment, the body contact 610 and the source region 620 are maintained at a common potential because they are commonly connected to the via 180. In other embodiments, the body contact 610 and the source region 620 may not be at a common potential, depending on the specific device application. The gate dielectric 630 (e.g., thermal oxide) is located between the gate 150 and the body well 135. In this example, the n-type body channel region 640 is located between the source region 620 and the drift region 140 ( Figure 2 ). The bulk channel region 640 includes a portion of the bulk well 135 that is located below the gate 150 and extends in the bulk well 135 to a depth of approximately the source region 620. The bulk channel region 640 can be depleted by a negative voltage on the gate 150, thereby allowing conduction between the source region 620 and the drain well 130.

[0021] return Figure 2, a buried voltage blocking region 155 of a second conductivity type (e.g., n-type) is connected to the body well 135. "Buried" means that a portion of the epitaxial layer 106 is located between the voltage blocking region 155 and the field oxide layer 108. In this context, "connected" means that the body well 135 and the voltage blocking region 155 partially overlap so that both the dopant from the body well 135 and the dopant from the voltage blocking region 155 are located in the overlapping portion. A first portion 155a of the voltage blocking region 155 extends laterally from the body well 135 to the drain well 130 and partially overlaps these regions. A second portion 155b extends toward the substrate contact well 160.

[0022] When the epitaxial layer 106 is p-type, the voltage blocking region 155 is a lightly doped region of a second conductivity type (e.g., n-type). In the context of the voltage blocking region 155, "lightly doped" means that the voltage blocking region 155 has a resistivity in a range between about 50 ohm-cm and about 200 ohm-cm. When the n-type dopant is phosphorus, this corresponds to a resistivity of about 2e13 atoms / cm -3 to about 9e13 atoms / cm -3 The voltage blocking region 155 may be formed by implanting a second conductivity type dopant into the epitaxial layer 106 with sufficient energy to generate a buried region whose conductivity type is converted from the first conductivity type to the second conductivity type, while leaving a portion of the epitaxial layer 106 between the voltage blocking region 155 and the field oxide layer 108 unchanged.

[0023] In transistor 101, voltage blocking region 155 can achieve high voltage blocking by forming a spatially diffused depletion region below drift region 140 and HV well 145. In some embodiments, as illustrated, voltage blocking region 155 overlaps a portion of HV well 145. Optionally, the dopant concentration in voltage blocking region 155 can be graded in region 165 of first portion 155a of voltage blocking region 155 such that the dopant concentration in voltage blocking region 155 decreases in the direction of drain well 130. This aspect is further described below.

[0024] The diode 102 includes a body well 135 and a substrate contact well 160 , such as a p-well. Figure 7 A detailed view showing a portion of a substrate contact well 160 and associated via 180. In some embodiments, the substrate contact well 160 is more heavily doped than the drain well 130. A portion 170 of the implant creating drift region 140 may be present in the substrate contact well 160. + Doped contact region 710 helps provide an ohmic connection between substrate contact well 160 and associated via 180. + A doped contact region may be used to achieve the same purpose in the drain well 130 .

[0025] The substrate contact well 160 provides a first terminal of the diode 102, and the body well 135 can provide a second terminal. The substrate contact well 160 provides a connection to the epitaxial layer 106 via the substrate electrode 125. In this case, the body well 135 of the diode 102 coincides with the second terminal. In other embodiments not shown, the second terminal of the diode 102 can be separate and distinct from the body well 135.

[0026] The diode 102 further includes a portion of the epitaxial layer 106 located between the body well 135 and the substrate contact well 160. The second portion 155b of the voltage blocking region 155 extends laterally from the body well 135 toward the substrate contact well 160 by a distance D 1 , where the width D of the epitaxial layer 106 is 2 The unmodified portion 195 of the epitaxial layer 106 is located between the second portion 155b and the substrate contact well 160, so that the voltage blocking region 155 is laterally spaced apart from the substrate contact well 160. In this context, "unmodified" means that the dopant concentration of the portion of the epitaxial layer 106 has not been changed from its original state. Thus, for example, if the epitaxial layer 106 is p-type and has a resistivity p, then the portion between the substrate contact well 160 and the voltage blocking region 155 is still p-type and has a resistivity p.

[0027] As previously described, diode 102 provides breakdown protection for transistor 101. Generally, the high voltage protection provided by diode 102 depends at least in part on the 1 and D 2 , where D 1 The protection provided is expected to play a major role. 1 The larger the value of , the higher the breakdown voltage of the body well 135. In various embodiments, the voltage blocking region 155 extends laterally from the body well 135 toward the substrate contact well 160 to at least about D 1 +D 2 In other words, in these embodiments, D 1 It can be D 2 In other embodiments, the voltage blocking region 155 extends laterally from the body well 135 toward the substrate contact well 160 by at least about 20 μm, D 1 ≥ 20 μm. When substrate 105 is silicon, this distance is expected to provide at least about 100V breakdown protection for body well 135. In other embodiments, D 1 It can be 200 μm or greater. At a distance of 200 μm, the diode 102 is expected to provide about 2000 V breakdown protection for the body well 135. 1The larger the value, the greater the breakdown voltage protection, but this protection can be balanced with the required area. Therefore, D can be determined based on the expected breakdown risk and the required device area. 1 In some embodiments, the width D 2 can be in the range of about 20 μm to about 200 μm. However, due to the breakdown voltage protection provided by diode 102, D 1 Play a major role, so D 2 Larger values ​​of provide little actual additional benefit.

[0028] Finally, dielectric layer 175 and metal layer 185 are located over substrate 105 to provide connections from electrodes 110, 115, 120 and 125 to body well 135, gate 150 and wells 130, 160, respectively. Various unmentioned metal features illustrated in metal layer 185 may include, for example, dummy metal features, interconnect lines, etc.

[0029] It will be understood by those skilled in the art that a balanced depletion region is formed between the epitaxial layer 106 and the voltage blocking region 155 due to the semiconductor junction between the epitaxial layer 106 and the voltage blocking region 155. During operation, a potential may be set across the substrate electrode 125 and the source electrode 110 so that the unbalanced depletion region 190 is larger than the balanced depletion region. Since the voltage blocking region 155 and the epitaxial layer 106 are lightly doped, the unbalanced depletion region may include a large portion of the voltage blocking region 155 (up to substantially all of the voltage blocking region 155 between the body well 135 and the substrate contact well 160) and the portion of the epitaxial layer 106 between the voltage blocking region 155 and the field oxide layer 108. This condition is referred to as "fully depleted". Therefore, the magnitude of the electric field between the body well 135 and the substrate contact well 160 may be limited to a value below the breakdown voltage of the epitaxial layer 106, and these depletion regions form a depletion isolation region that insulates the body well 135 from the substrate contact well 160. Because body well 135 can serve as both the source of transistor 101 and the second terminal of diode 102, depletion region 190 serves as a junction termination around transistor 101, insulating transistor 101 from substrate contact well 160. Thus, transistor 101 can operate at a higher source voltage than would otherwise be possible if diode 102 were not present.

[0030] In just one example, device 100 may be used in applications where transistor 101 is a PMOS transistor used as a high-side transistor in, for example, a piezoelectric transducer driver circuit. Figure 3This representative circuit is illustrated in a non-limiting manner. In this figure, transistor 101 (shown as a PMOS transistor in this embodiment) and NMOS transistor 310 are operated to provide a symmetrical push-pull waveform for transducer 320. Node 330 can be maintained at ground potential under this condition, setting a supply potential across body well 135 and the body of transistor 101. In the absence of diode 102, this potential can exceed the breakdown strength of the substrate 105 material (e.g., silicon). However, the isolation provided by diode 102 is increased by a distance D 1 Distributing the voltage drop adds a degree of high voltage protection to the source-to-bulk path.

[0031] Steering Figure 4 , presents an embodiment of a method 400 for forming a junction-terminated MOS transistor (e.g., device 100). In a first step 410, a substrate of a first conductivity type (e.g., p-type) is provided. An implant region is formed with a dopant of a second, opposite conductivity type (e.g., n-type). The lateral boundaries of the implant region at the substrate surface correspond to the desired lateral extent of the buried voltage blocking region 155. Sufficient second conductivity type dopant is implanted as a dopant source to form the voltage blocking region 155 in a subsequent diffusion step. In step 420, an epitaxial layer of the first conductivity type (e.g., epitaxial layer 106) is formed over the implant region.

[0032] In step 430, a well of the second conductivity type (e.g., HV well 145) is formed in the substrate and connected to the doped region. In step 440, a first well and a second well of the first conductivity type are formed in the epitaxial layer. For example, the first well can be a substrate contact well 160, and the second well can be a drain well 130. The drain well 130 is formed at one end of the HV well 145. In step 450, a third well of the second conductivity type (e.g., an n-type source well 135) is formed in the substrate between the wells of the first conductivity type. The source well 135 is formed at one end of the HV well 145 opposite to the drain well 130.

[0033] In step 460, a surface drift region (e.g., surface drift region 140) is formed in the substrate by dopants of the first conductivity type, and the surface drift region is connected to the second well and the third well. In step 470, a source region (e.g., source region 620) is formed in the third well by dopants of the first conductivity type. In step 480, a gate structure (e.g., gate 150) is formed over the third well to form a DE-MOS transistor in which the second well is a drain well.

[0034] An activation / diffusion anneal may be performed after one or more of steps 420 to 470. The anneal generally causes the dopants in the various implanted regions to diffuse vertically and horizontally into the substrate 105 from their original implantation locations. Vertical diffusion will cause the dopants implanted into the substrate 105 in step 410 to diffuse deeper into the substrate and also toward the surface. Similarly, the dopants in regions 130, 135, 145, and 160 will diffuse laterally and deeper into the substrate 105. The dopant profile after diffusion forms Figure 2 . For example, voltage blocking region 145 is connected to the second well and the third well, partially overlaps HV well 145, and extends from the third well toward the first well. An unmodified portion of the substrate is located between the first well and the voltage blocking region. Voltage blocking region 145 may be approximately centered on plane 199, which represents the initial surface of substrate 105 before forming epitaxial layer 106, but there may be no detectable interface.

[0035] Figures 5A to 5I An embodiment of a method 500 of forming device 100 is presented in cross-sectional views at various fabrication stages. Method 500 is described with respect to an embodiment in which transistor 101 is a PMOS transistor. One skilled in the relevant art will be able to adapt the described method to produce a similar NMOS device without undue experimentation.

[0036] exist Figure 5A , the device 100 is shown in an early manufacturing stage. The substrate 105 comprises a crystalline semiconductor material suitable for forming electronic devices in a wafer production facility. For example, the substrate 105 can be a polished silicon wafer of a first conductivity type (e.g., p-type). The photoresist pattern 505 defines an exposed implantation area of ​​the substrate 105. The implantation area can correspond to the lateral span of the buried voltage blocking region 155 in the plane of the substrate 105. The implantation process 510 provides a dopant of a second conductivity type (e.g., n-type). The implanted dopant forms a layer 155′ that is shallower and more concentrated than the voltage blocking region 155. As further described below, the layer 155′ is used as a dopant source in a subsequent diffusion step to form the voltage blocking region 155.

[0037] In an exemplary embodiment, the energy may be about 100 keV and from about 1e12 atoms / cm 2 to about 1e13 atoms / cm 2 The comb pattern 515 has been positioned to produce phosphorus in region 165 (see also Figure 2) in an implant pattern that forms an optional lateral dopant gradient or graded dopant profile. In the illustrated embodiment, where portions of the comb pattern 515 are narrower, a greater amount of dopant will reach the substrate 105, and where portions of the comb pattern 515 are wider, a lesser amount of dopant will reach the substrate 105. Thus, in the direction in which the width of the resist line in the comb pattern 515 increases, the dopant concentration will decrease. This dopant gradient is referred to herein as a graded dopant profile. Preferably, the doping gradient in region 165 is approximately linear.

[0038] exist Figure 5B , epitaxial growth process 520 forms epitaxial layer 106 over layer 155'. Process 520 may be a chemical vapor deposition (CVD) process and may include dopants to make epitaxial layer 106 have the same conductivity type as substrate 105 and have a resistivity in a range from about 1 ohm-cm to about 20 ohm-cm.

[0039] Figure 5C The diagram illustrates an optional step of forming a doped region 145′ in the epitaxial layer 106. Pattern 525 includes openings that define the span of the doped region 145′, which corresponds to the desired span of the HV well 145. An implantation process 530 delivers a dopant of the second conductivity type to the epitaxial layer 106 to form the doped region 145′. For example, an implantation process 530 may be performed at an energy of about 500 keV and at a density of about 1e12 atoms / cm 2 to about 1e14 atoms / cm 2 Phosphorus is implanted at a dose in the range of 100 Å to 100 Å. Doped region 145 ′ provides dopants that will diffuse vertically into epitaxial layer 106 to form HV well 145 in a subsequent thermal process step.

[0040] exist Figure 5D , the device 100 is shown during the formation of doped regions 130′, 160′, which will diffuse in subsequent process steps to form the drain well 130 and the substrate contact well 160. The openings in the resist pattern 535 correspond to the desired locations of the wells 130, 160. An implantation process 540 delivers a dopant species (e.g., boron) of the same conductivity type as the epitaxial layer 106 to the epitaxial layer 106. The implantation depth of the dopant species is such that at a subsequent thermal process, the dopant will diffuse vertically into the epitaxial layer 106 to produce a desired dopant profile in the wells 130, 160. In an exemplary embodiment of the implantation process 540, the dopant may be implanted at an energy of about 50 keV and at a density ranging from about 1e13 atoms / cm 2 to about 1e15 atoms / cm 2In some embodiments, the openings that access the region 130' may be formed in a comb-shaped pattern so that the dopant concentration in the region 130' is less than the dopant concentration in the region 160', thereby making the dopant concentration in the drain well 130 less than the dopant concentration in the substrate contact well 160.

[0041] exist Figure 5E , device 100 is shown during the formation of doped region 135′, which will later form body well 135. Resist layer 545 has been patterned to create openings through which implantation process 550 delivers a dopant species of the second conductivity type, such as phosphorus, to epitaxial layer 106. The opening corresponds to the location of body well 135 and may partially overlap region 145′. In an exemplary embodiment of implantation process 550, the implant may be performed at an energy of about 200 keV and at a density ranging from about 1e13 atoms / cm 2 to about 1e15 atoms / cm 2 Phosphorus is implanted within a range of doses.

[0042] Fig. 5F The substrate 105 is illustrated exposed to a thermal diffusion process 555. Process 555 represents one or more diffusion steps that may follow any of the aforementioned implantation steps. For example, any of the previously implanted regions may be partially diffused prior to diffusion process 555. In one embodiment, no diffusion process is performed prior to diffusion process 555. In an exemplary embodiment, thermal diffusion process 555 is performed in a tube furnace in a nitrogen environment at 100° C. for 400 minutes.

[0043] The diffusion process 555 causes the dopants in each of the implanted regions to diffuse laterally and vertically in the substrate 105 to form the desired configuration of doped regions of the device 100. For example, the HV well 145 partially overlaps the body well 135 and the voltage blocking region 155, and the buried voltage blocking region 155 is connected to both the drain well 130 and the body well 135. In addition, a portion of the unmodified epitaxial layer 106 is located between the substrate contact well 160 and the voltage blocking region 155.

[0044] Figure 5G The diagram illustrates the formation of a surface drift region 140 in the surface layer between the drain well 130 and the body well 135. The resist layer 560 includes an opening above the HV well 145 and overlaps the edge of each of the wells 130, 135. The implantation process 565 provides a dopant of the first conductivity type so that the surface portion of the HV well 145 is converted from n-type to p-type, for example. For example, the implantation process 565 may be performed at an energy of about 70 keV and at a concentration of about 5e12 atoms / cm 2 to about 1e13 atoms / cm 2Boron is implanted at a dose in the range of 100 to 1000. Dopants are also implanted into wells 130, 135 so that the surface drift region 140 is connected to both wells. A thermal diffusion step (not shown) may be used to activate the dopants without extensive diffusion of the dopants. For example, a rapid thermal anneal (RTA) may be performed, or a subsequent thermal process (e.g., as described below) may be performed. Figure 5H The field oxidation process described in the context of ) can provide activation energy.

[0045] Figure 5H The diagram illustrates the device 100 after a gate 150 has been formed over the body well 135. A field oxide layer 108 has also been formed, such as conventionally using a LOCOS process. An opening is formed in the field oxide layer 108 over a portion of the body well 135 and a portion of the drift region 140. A gate dielectric 630 has been conventionally formed over the exposed body well 135 and drift region 140 (see FIG. Figure 6 ), and a polysilicon layer has been formed over the gate dielectric 630. The polysilicon layer has been patterned to produce the gate 150 and the field plate 151.

[0046] at last, Fig.5I The device 100 is illustrated after the dielectric layer 175 and the via 180 are formed within the dielectric level 185. The dielectric layer 175 has been patterned to create via openings above the wells 130, 135, 160. After patterning, conventional implant processes have formed the contact regions 710 within the substrate contact well 160 (see Figure 7 ). Similarly, body contact 610 and source region 620 have been formed within well 135. After the contact implant, via 180 has been formed as is conventional.

[0047] Return to reference Figure 2 , shows device 100 after forming additional dielectric layers 175 and metal layers 185. Additional examples of vias 180 have been formed within dielectric layer 175 to connect electrodes 110, 120, and 125 to wells 135, 130, and 160, respectively, and to connect gate electrode 115 to gate 150. Additional dielectric layers and metal connections may be formed as needed to interconnect device 100 with other devices in an integrated circuit.

[0048] Modifications may be made in the described embodiments and other embodiments may exist within the scope of the claims.

Claims

1. A semiconductor device comprising: A MOS transistor formed in a semiconductor substrate of a first conductivity type and having a surface drift layer of the first conductivity type, the surface drift layer being located between a body well and a drain well, and the surface drift layer being directly connected to the body well and the drain well; a buried voltage blocking region of a second conductivity type connected to the body well and extending from the body well toward a substrate contact well; and An unmodified portion of the substrate is located between the buried voltage blocking region and the substrate contact well.

2. The semiconductor device of claim 1 , wherein the buried voltage blocking region forms a PN junction with the substrate, and the body well and the substrate contact well are configured to apply a reverse bias to the PN junction, thereby producing an unbalanced depletion isolation region, the unbalanced depletion isolation region being adjacent to the unmodified substrate portion and including at least some of the unmodified substrate portion. 3 . The semiconductor device of claim 2 , wherein the unbalanced depletion isolation region has a breakdown voltage of at least 700V. 4 . The semiconductor device of claim 1 , wherein the buried voltage blocking region extends from the body well toward the substrate contact well by at least 80% of a distance between the body well and the substrate contact well. 5 . The semiconductor device of claim 1 , wherein the buried voltage blocking region extends at least 20 μm from the body well toward the substrate contact well. 6 . The semiconductor device of claim 1 , wherein the buried voltage blocking region extends from the body well toward the drain well. 7 . The semiconductor device of claim 1 , wherein the semiconductor substrate includes an HV well of the second conductivity type between the body well and the drain well, and the buried voltage blocking region partially overlaps the HV well.

8. A method of forming an electronic device, the method comprising: Forming a body well and a drain well of a drain-extended DE-MOS transistor having a second different conductivity type in a semiconductor substrate having a first conductivity type, the drain well having the first conductivity type, the DE-MOS transistor comprising a surface drift layer having the first conductivity type, the surface drift layer being located between the body well and the drain well, and the surface drift layer being directly connected to the body well and the drain well; and A junction-terminated diode having a first terminal and a second terminal is formed in the semiconductor substrate, wherein the first terminal is connected to the substrate at a substrate contact well having the first conductivity type, and the second terminal is connected to the body well, wherein the semiconductor substrate includes an epitaxial layer of a first conductivity type, and the substrate contact well has the first conductivity type, and the method further includes forming a buried region of a second conductivity type in the epitaxial layer extending from the body well toward the substrate contact well, wherein a portion of the epitaxial layer is located between the buried region and the substrate contact well, and the portion of the epitaxial layer has a lower dopant concentration than the substrate contact well. 9 . The method of claim 8 , wherein the buried region extends 20 μm to 200 μm from the body well toward the substrate contact well.

10. The method of claim 8, wherein the second terminal coincides with the body well.

11. The method of claim 8, wherein the junction termination diode has a breakdown voltage of at least 700V. 12 . The method of claim 8 , further comprising forming an HV well of the second conductivity type between the body well and the drain well of the DE-MOS transistor, the HV well partially overlapping the buried region.

13. The method of claim 8, wherein the buried region extends from the body well toward the drain well with a graded dopant profile.

14. The method of claim 8, wherein the first conductivity type is p-type and the second conductivity type is n-type.

15. A high voltage MOS transistor, comprising: p-type substrate; A first p-well and a second p-well, which are located in the substrate; an n-well located between the first p-well and the second p-well in the substrate; A p-type surface drift region is located between the n-well and the second p-well and is directly connected to the n-well and the second p-well; a gate located above the n-well; and a buried n-type region partially overlapping the n-well and extending from the n-well toward the first p-well, wherein The first p-well is laterally spaced apart from the buried n-type region.

16. The MOS transistor of claim 15, wherein the n-well is a first n-well, and the MOS transistor further comprises a second n-well located between and partially overlapping the first n-well, the second p-well, and the buried n-type region. 17 . The MOS transistor of claim 15 , wherein the buried n-type region extends from the n-well toward the second p-well with a graded dopant profile.

18. The MOS transistor of claim 15, wherein the n-well and the first p-well are configured to receive a potential capable of completely depleting a region of the p-type substrate between the buried n-type region and a surface of the substrate.

19. The MOS transistor of claim 15, wherein the buried n-type region extends at least 20 μm from the n-well toward the p-well.

20. The MOS transistor of claim 15, wherein the buried n-type region has a graded dopant profile that decreases in a direction from the n-well toward the second p-well.

21. A method of forming an integrated circuit, the method comprising: forming a first doping region and a second doping region of the first conductivity type in a semiconductor substrate of the first conductivity type; forming a third doping region of the second conductivity type, wherein the third doping region is located between the first doping region and the second doping region in the substrate; forming a fourth doping region of the first conductivity type on the surface of the substrate, wherein the fourth doping region is located between the first doping region and the third doping region and is directly connected to the first doping region and the third doping region; forming a gate electrode above the third doped region; and A buried layer having the second conductivity type is formed in the substrate, the third doped region is located between the buried layer and the gate electrode, and the buried layer partially extends from the third doped region toward the first doped region, wherein The second doped region is laterally spaced apart from the buried layer.

22. The method of claim 21, wherein the first conductivity type is p-type and the second conductivity type is n-type. 23 . The method according to claim 21 , further comprising forming a fifth doping region having the second conductivity type, the fifth doping region being located between the first doping region and the third doping region and between the buried layer and the fourth doping region. 24 . The method of claim 21 , wherein the buried layer extends from the third doping region toward the first doping region with a graded dopant profile.

25. The method of claim 21, wherein the second doped region and the third doped region are configured to receive a potential capable of completely depleting a region of the substrate between the buried layer and a surface of the substrate. 26 . The method of claim 21 , wherein the buried layer extends at least 20 μm from the third doping region toward the second doping region. 27 . The method of claim 21 , wherein the buried layer has a graded dopant profile that decreases in a direction from the third doping region toward the first doping region.

28. A method of forming an integrated circuit, the method comprising: forming a source region and a drain region having a first conductivity type in a semiconductor substrate having the first conductivity type; forming a buried layer having a second conductivity type, the buried layer extending under the source region and the drain region; forming a first well region having the first conductivity type, the first well region extending from the source region to the buried layer; forming a second well region of the first conductivity type in the semiconductor substrate, the second well region being spaced apart from the first well region; and forming a surface well region having the first conductivity type, the surface well region extending from the first well region to a third well region having the second conductivity type, the third well region being located between the first well region and the second well region in the semiconductor substrate, the surface well region being directly connected to the first well region and the second well region, A semiconductor substrate portion is located between the second well region and the buried layer, and the substrate portion has a lower dopant concentration than the second well region. 29 . The method of claim 28 , wherein the buried layer has a graded dopant profile such that a concentration of the second conductivity type dopant decreases from the first well region toward the third well region.

30. The method of claim 28, further comprising forming a buried well region having the second conductivity type between the surface well region and the buried layer, the buried well region extending from the first well to the third well.

31. The method of claim 28, wherein the substrate portion extends between the first well and the second well at a substrate surface.

32. The method of claim 28, wherein the first conductivity type is p-type and the second conductivity type is n-type.

33. A method of forming an integrated circuit, comprising: An n-type body well and a p-type drain well of a drain-extended DE-MOS transistor are formed in a p-type semiconductor substrate, wherein the DE-MOS transistor has a p-type surface drift layer, wherein the surface drift layer is located between the n-type body well and the p-type drain well, and the p-type surface drift layer is directly connected to the n-type body well and the p-type drain well; as well as A junction-terminated diode having a first terminal and a second terminal is formed in the semiconductor substrate, wherein the first terminal is connected to the substrate at a p-type substrate contact well and the second terminal is connected to the body well, wherein the semiconductor substrate includes a p-type epitaxial layer, and the substrate contact well is p-type, and the method further includes forming an n-type buried region in the epitaxial layer extending from the body well toward the substrate contact well, wherein a portion of the epitaxial layer is located between the buried region and the substrate contact well, and the portion of the epitaxial layer has a lower dopant concentration than the substrate contact well.

34. The method of claim 33, wherein the junction termination diode has a breakdown voltage of at least 700V.

35. The method of claim 33, wherein the buried region extends at least 20 μm from the body well toward the substrate contact well.

36. The method of claim 33, wherein the second terminal coincides with the body well.

37. The method of claim 33, further comprising forming an n-type high voltage (HV) well between the body well and the drain well of the DE-MOS transistor.

38. The method of claim 37, wherein the HV well overlaps the buried region.

39. The method of claim 33, wherein the buried region extends from the body well toward the drain well with a graded dopant profile.

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