Voltage generator and method of operating the same

Abstract

A voltage generator and a method for operating the same are provided. The method includes providing a reference voltage, sensing a magnitude of a charging current for increasing voltages of a plurality of word lines based on the reference voltage, determining whether the magnitude of the sensed charging current is greater than a peak current value, increasing the reference voltage according to a first slope when the magnitude of the sensed charging current is less than or equal to the peak current value, and increasing the reference voltage according to a second slope less than the first slope when the magnitude of the sensed charging current is greater than the peak current value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0157473 filed on December 7, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a voltage generator. Background Art

[0004] The semiconductor memory device is implemented by using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). The semiconductor memory device can be classified into a volatile memory device and a nonvolatile memory device.

[0005] When using a vertical NAND flash memory having a stacked structure, as the number of stacked word lines increases, parasitic capacitance increases and peak current may be generated between word lines. When the magnitude of the word line charging current is maintained in order to maintain the performance of the memory, erroneous operation of the memory device may be caused by the peak current. When the magnitude of the word line charging current is reduced to prevent the generation of the peak current, the word line setup time may increase and the performance of the memory device may deteriorate. Summary of the invention

[0006] The inventive concept provides a voltage generator for variably controlling a slope of a word line charging voltage by sensing a charging current input to the word line, and a method of operating the same.

[0007] The inventive concept also provides a voltage generator for recognizing charging of a word line and quickly performing a standby process by using a sensed value of a charging current although a standby time previously determined for charging the word line has not passed, and a method of operating the same.

[0008] According to one aspect of the inventive concept, a voltage generator is provided, which includes at least one driving circuit, a current sensing circuit, a peak detection circuit, and a slope control circuit. At least one driving circuit is connected to a plurality of word lines of a memory device. At least one driving circuit is configured to provide a current for increasing the voltage of the plurality of word lines based on a reference voltage. The current sensing circuit is configured to sense the magnitude of a charging current input to the at least one driving circuit. The peak detection circuit is configured to compare the magnitude of the sensed charging current with a peak current value. The slope control circuit is configured to: provide a reference voltage to the at least one driving circuit; when the magnitude of the sensed charging current is less than or equal to the peak current value, increase the reference voltage according to a first slope; and when the magnitude of the sensed charging current is greater than the peak current value, increase the reference voltage according to a second slope less than the first slope.

[0009] According to one aspect of the inventive concept, a method for operating a voltage generator is provided. The method includes: providing a reference voltage; sensing a magnitude of a charging current for increasing voltages of a plurality of word lines based on the reference voltage; determining whether the magnitude of the sensed charging current is greater than a peak current value, increasing the reference voltage according to a first slope when the magnitude of the sensed charging current is less than or equal to the peak current value, and increasing the reference voltage according to a second slope less than the first slope when the magnitude of the sensed charging current is greater than the peak current value. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a storage device according to an example embodiment of the inventive concept;

[0012] Figure 2 is a block diagram illustrating a nonvolatile memory device according to an example embodiment of the inventive concept;

[0013] Figure 3 is a circuit diagram illustrating a memory block included in a memory cell array according to an example embodiment of the inventive concept;

[0014] Figure 4 is a circuit diagram illustrating another example of a memory block included in a memory cell array according to an example embodiment of the inventive concept;

[0015] Figure 5 is a perspective view illustrating a memory block according to an example embodiment of the inventive concept;

[0016] Figure 6 is a circuit diagram illustrating a voltage generator according to an example embodiment of the inventive concept;

[0017] Figure 7 is a flowchart illustrating a method of operating a voltage generator according to an example embodiment of the inventive concept;

[0018] Figure 8 is a diagram illustrating a charging current and a word line voltage according to an example embodiment of the inventive concept;

[0019] Fig.9A is a circuit diagram illustrating an example of a slope control unit according to an example embodiment of the inventive concept;

[0020] Fig. 9B is a diagram illustrating a charging current and a word line voltage according to an example embodiment of the inventive concept;

[0021] Fig. 10A is a circuit diagram illustrating another example of a slope control unit according to an example embodiment of the inventive concept;

[0022] Fig. 10B is a diagram illustrating a charging current and a word line voltage according to an example embodiment of the inventive concept;

[0023] Fig.11A is a circuit diagram illustrating a voltage generator including an event detector according to an example embodiment of the inventive concept;

[0024] Fig. 11B is a diagram illustrating a time point of generating an event according to an exemplary embodiment of the inventive concept; and

[0025] Fig.12 is a block diagram illustrating an example in which each of the memory devices according to example embodiments of the inventive concept is applied to a solid state drive (SSD) system. DETAILED DESCRIPTION

[0026] Figure 1 is a block diagram illustrating a storage device 1 according to an example embodiment of the inventive concept.

[0027] refer to Figure 1, the memory device 1 may include a non-volatile memory device 10, a memory controller 20, and a power management integrated circuit (PMIC) 30. In an example, each of the host HOST, the memory controller 20, and the non-volatile memory device 10 may be provided as a chip, a package, or a module. Alternatively, the memory controller 20 and the nonvolatile memory device 10 may be provided by using a package such as a package on package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual in-line package (PDIP), a die in waffle pack, a die in wafer form, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat pack (MQFP), a thin quad flat pack (TQFP), a small outline integrated circuit (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system in package (SIP), a multichip package (MCP), or a multichip package (MCP). package (MCP), wafer-level fabricated package (WFP), and wafer-level processed stack package (WSP).

[0028] The memory controller 20 may control the nonvolatile memory device 10 in response to a write request or a read request received from the host HOST. For example, the memory controller 20 may send a command CMD and an address ADDR to the nonvolatile memory device 10 in response to a write request or a read request received from the host HOST. The address ADDR sent by the memory controller 20 to the nonvolatile memory device 10 may be a physical address of the nonvolatile memory device 10. The memory controller 20 may send data DATA to the nonvolatile memory device 10 and receive data DATA from the nonvolatile memory device 10. In one example, when the command CMD is a write command CMD_w, the nonvolatile memory device 10 may write the data DATA received from the memory controller 20 into the memory cell array 110, and when the command CMD is a read command CMD_r, the nonvolatile memory device 10 may output the data DATA stored in the address ADDR received from the memory controller 20 to the memory controller 20. The memory controller 20 may be implemented in the memory device 1 as hardware or software, or in the form of a combination of hardware and software. For example, more specifically, the memory controller 20 may include but is not limited to a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0029] The PMIC 30 may provide power to the nonvolatile memory device 10 and the memory controller 20. According to various example embodiments, the PMIC 30 receives main power from an external power source and may convert the received main power into power requested by each of the nonvolatile memory device 10 and the memory controller 20. For example, when the nonvolatile memory device 10 executes a data write command, the PMIC 30 may provide a high voltage (e.g., 40 V) to the nonvolatile memory device 10. In another example, when the nonvolatile memory device 10 executes a data read command, the PMIC 30 may provide a low voltage (e.g., 12 V) to the nonvolatile memory device 10.

[0030] According to various example embodiments, the nonvolatile memory device 10 may include a memory cell array 110, a row decoder 120, and a voltage generator 130. The memory cell array 110 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. Hereinafter, the example embodiments will be described in detail taking the case where the plurality of memory cells are NAND flash memory cells as an example. However, the spirit of the inventive concept is not limited thereto. In another example embodiment, the plurality of memory cells may be resistive memory cells, such as resistive random access memory (RRAM), phase change RAM (PRAM), and magnetic RAM (MRAM).

[0031] According to example embodiments, the memory cell array 110 may be a three-dimensional (3D) memory cell array. The 3D memory cell array is monolithically formed in an active region arranged on a silicon substrate, and at least one physical level of the memory cell array has a circuit formed on or in a silicon substrate as a circuit associated with the operation of the memory cell. The term "monolithic" means that the layers of each level of the configuration 3D memory cell array are stacked on each lower level layer in the memory cell array. The 3D memory cell array includes NAND strings arranged in a vertical direction so that at least one memory cell is located on another memory cell. At least one memory cell may include a charge trap layer. However, the inventive concept is not limited thereto. In another example embodiment, the memory cell array 110 may be a 2D memory cell array. In U.S. Patent Publication Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235 and U.S. Patent Publication No. 2011 / 0233648, suitable configurations of 3D memory cell arrays formed by multiple levels in which word lines and / or bit lines are shared between levels are described in detail. U.S. Patent Publication Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235 and U.S. Patent Publication No. 2011 / 0233648 are incorporated herein by reference. In addition, U.S. Patent Publication Nos. 2014-0334232 and 8,488,381 are incorporated herein by reference.

[0032] According to an example embodiment, the row decoder 120 may select part of the word lines WL in response to the address ADDR information. The row decoder 120 sends the word line voltage VWL to the word line WL. During a programming operation, the row decoder 120 may apply a programming voltage and a verification voltage to the selected word line, and may apply a program inhibit voltage to an unselected word line. During a read operation, the row decoder 120 may apply a read voltage to the selected word line, and may apply a read inhibit voltage to an unselected word line. During a recovery operation, the row decoder 120 may apply a recovery voltage to the selected word line. In addition, the row decoder 120 may select part of the string selection lines or part of the ground selection lines in response to the address ADDR information.

[0033] According to example embodiments, the voltage generator 130 may generate various voltages for performing write, read, and erase operations on the memory cell array 110 based on the voltage control signal Ctrl_vol. In detail, the voltage generator 130 may generate a word line voltage VWL (e.g., a program voltage (or write voltage)), a read voltage, a pass voltage (or a word line unselected voltage), a verification voltage, or a recovery voltage.

[0034] On the other hand, the storage device 1 can be implemented by one of various storage devices such as: a solid state drive (SSD), an embedded multimedia card (eMMC), an MMC, a universal flash storage (UFS), an embedded UFS, a reduced size MMC (RS-MMC), an MMC in the form of a micro MMC, a compact flash (CF) card, a secure digital (SD) card, a micro secure digital (SD) card, a mini SD card, an extreme digital (xD) card, a smart media card, and a memory stick.

[0035] The storage device 1 can be embedded in an electronic device, or can be attached to and removed from the electronic device. The electronic device can be implemented by, for example, a personal computer (PC), a data server, an ultra-mobile PC (UMPC), a workstation, a netbook, a network-attached storage (NAS), a smart TV, an Internet of things (IoT) device, or a portable electronic device. The portable electronic device can be a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an e-book, or a wearable device.

[0036] Figure 2 1 is a block diagram illustrating a nonvolatile memory device 10 according to an example embodiment of the inventive concept. Figure 1 The description is the same as the description of .

[0037] refer to Figure 2 , the nonvolatile memory device 10 may include a control logic 100 , a memory cell array 110 , a row decoder 120 , a voltage generator 130 , a page buffer 140 , and an input / output circuit 150 .

[0038] According to various example embodiments, the control logic 100 may output various control signals for controlling the memory controller ( Figure 1The control logic 100 may write data in the memory cell array 110 or read data from the memory cell array 110 according to the command CMD_w / CMD_r and the address ADDR received by the control logic 100 in 20). According to an example embodiment, the control logic 100 may send a plurality of control signals to the voltage generator 130. For example, the control logic 100 may send a resistor digital-to-analog converter (R-DAC) control signal R-DCA_Ctrl or a current source bias control signal I_bias_Ctrl to the voltage generator 130. The control logic 100 may be implemented in the nonvolatile memory device 10 as hardware or software, or in the form of a combination of hardware and software. For example, more specifically, the control logic 100 may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0039] According to an example embodiment, the voltage generator 130 may further include a current sensing unit (or current sensing circuit) 131, a peak detection unit (or peak detection circuit) 132, and a slope control unit (or slope control circuit) 133. The current sensing unit 131 may sense the magnitude of the current. For example, the current sensing unit 131 may sense the magnitude of the charging current input to charge the plurality of word lines.

[0040] The peak detection unit 132 may detect whether the magnitude of the charging current is greater than the peak current value. The peak detection unit 132 may determine whether the magnitude of the charging current is greater than the peak current value by using a comparator. For example, the peak detection unit 132 receives a value obtained by sensing the charging current from the current sensing unit 131, and may compare the sensed value with the peak current value.

[0041] The slope control unit 133 may control the reference voltage input to at least one driving circuit based on whether the magnitude of the charging current is greater than the peak current value. For example, when the magnitude of the charging current is greater than the peak current value, the slope control unit 133 may reduce the slope of the reference voltage. When the slope of the reference voltage decreases, the magnitude of the charging current may decrease. In another example, when the magnitude of the charging current is less than the peak current value, the slope control unit 133 may increase the slope of the reference voltage. When the slope of the reference voltage increases, the magnitude of the charging current may increase. Figure 6 The current sensing unit 131, the peak detection unit 132, and the slope control unit 133 included in the voltage generator 130 will be described in detail.

[0042] According to an example embodiment, the page buffer 140 may include a write driver and a sense amplifier. During a write operation, the page buffer 140 may send a bit line voltage corresponding to data to be written in a bit line of the memory cell array 110. During a read operation or a verify operation, the page buffer 140 may sense data stored in a selected memory cell via a bit line. The page buffer 140 may include a plurality of latch groups (not shown) connected to one or two bit lines.

[0043] According to example embodiments, the input and output circuit 150 receives data from the outside (eg, the memory controller 20) and stores the input data in the memory cell array 110. In addition, the input and output circuit 150 reads data from the memory cell array 110 and may output the read data to the outside.

[0044] Figure 3 is a circuit diagram illustrating a memory block included in the memory cell array 110 according to an example embodiment of the inventive concepts.

[0045] refer to Figure 3 , memory cell array (e.g., Figure 2 110) may be a memory cell array of a horizontal NAND flash memory and may include a plurality of memory blocks. Each memory block BLKa may include m cell strings STR, in which n memory cells MC are connected in series in the direction of the bit lines BL0 to BLm-1. Figure 3 In a NAND flash memory device having a structure of , erasure is performed in units of blocks, and programming is performed in units of pages corresponding to word lines WL0 to WL7. Figure 3 An example is shown in which n pages for n word lines WL1 to WLn are provided in one block. Figure 1 and Figure 2 The nonvolatile memory device 10 may include a plurality of memory cell arrays that perform the same operation as that of the above-described memory cell array 110 and have the same structure as that of the above-described memory cell array 110 .

[0046] Figure 4 is a circuit diagram illustrating another example of a memory block included in a memory cell array according to example embodiments of the inventive concepts.

[0047] refer to Figure 4 , memory cell array (e.g., Figure 2110) may be a memory cell array of a vertical NAND flash memory and may include a plurality of memory blocks. Each memory block BLK0 may include a plurality of NAND cell strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of bit lines BL1 to BL3, a plurality of ground selection lines GSL1 to GSL3, a plurality of cell string selection lines SSL1 to SSL3, and a common source line CSL. Here, according to example embodiments, the number of NAND cell strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of cell string selection lines may vary.

[0048] NAND cell strings NS11, NS21, and NS31 are provided between a first bit line BL1 and a common source line CSL. NAND cell strings NS12, NS22, and NS32 are provided between a second bit line BL2 and a common source line CSL. NAND cell strings NS13, NS23, and NS33 are provided between a third bit line BL3 and a common source line CSL. Each NAND cell string (e.g., NS11) may include a cell string selection transistor SST, a plurality of memory cells MC1 to MC8 connected in series, and a ground selection transistor GST.

[0049] The cell string selection transistor SST is connected to the corresponding cell string selection lines SSL1 to SSL3. A plurality of memory cells MC1 to MC8 are respectively connected to the corresponding word lines WL1 to WL8. The ground selection transistor GST is connected to the corresponding ground selection lines GSL1 to GSL3. The cell string selection transistor SST is connected to the corresponding bit lines BL1 to BL3, and the ground selection transistor GST is connected to the common source line CSL.

[0050] The word lines (e.g., WL1) of the same height are connected in common, the cell string selection lines SSL1 to SSL3 are separated from each other, and the ground selection lines GSL1 to GSL3 are separated from each other. For example, when the memory cells connected to the first word line WL1 and belonging to the cell strings NS11, NS12, and NS13 are programmed, the first word line WL1 and the first cell string selection line SSL1 are selected. The ground selection lines GSL1 to GSL3 may be connected in common to each other.

[0051] Figure 5 is a perspective view illustrating a memory block BLK0 according to an example embodiment of the inventive concepts.

[0052] refer to Figure 5 , including in a memory cell array (e.g., Figure 2 Each memory block in 110) is formed in a vertical direction relative to the substrate SUB. Figure 5, it is shown that the memory block includes two selection lines GSL and SSL, 8 word lines WL1 to WL8, and 3 bit lines BL1 to BL3. However, the memory block may include more or less selection lines, word lines, and bit lines.

[0053] The substrate SUB has a first conductivity type (e.g., p-type). A common source line CSL extending in a first direction (e.g., Y direction) and doped with impurities of a second conductivity type (e.g., n-type) is provided on the substrate SUB. On a region of the substrate SUB between two adjacent common source lines CSL, a plurality of insulating layers IL extending in the first direction are sequentially provided in a third direction (e.g., Z direction), and the plurality of insulating layers IL are spaced a certain distance from each other in the third direction. For example, the plurality of insulating layers IL may include an insulating material such as silicon oxide.

[0054] On the region of the substrate SUB between two adjacent common source lines CSL, a plurality of pillars P are provided which are sequentially arranged along the first direction and pass through the plurality of insulating layers IL along the third direction. For example, the plurality of pillars P pass through the plurality of insulating layers IL and contact the substrate SUB. In detail, the surface layer S of each pillar P may include a silicon material having a first type and may be used as a channel region. On the other hand, the inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

[0055] In the region between two adjacent common source lines CSL, a charge storage layer CS is provided along the exposed surfaces of the insulating layer IL, the pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (or referred to as a "tunnel insulating layer"), a charge trap layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, in the region between two adjacent common source lines CSL, on the exposed surface of the charge storage layer CS, gate electrodes GE such as select lines GSL and SSL and word lines WL1 to WL8 are provided.

[0056] Drains or drain contacts DR are provided on the plurality of pillars P, respectively. For example, the drains or drain contacts DR may include a silicon material doped with impurities of the second conductivity type. On the drains DR, bit lines BL1 to BL3 extending in the second direction (eg, X direction) and spaced apart from each other in the first direction are provided.

[0057] Figure 6 is a circuit diagram illustrating a voltage generator according to an example embodiment of the inventive concept.

[0058] refer to Figure 6The voltage generator 130 may include a switch circuit 134 , a current sensing unit 131 , a peak detection unit 132 , a slope control unit 133 , at least one driving circuit 136 , and a word line 139 .

[0059] According to example embodiments, the switch circuit 134 may select a current source of a charging current input to the word line WL. For example, the switch circuit 134 may be connected to a PMIC 30 located outside the nonvolatile memory device 10. In another example, the switch circuit 134 may be connected to a charge pump 135 in the voltage generator 130. According to various example embodiments, the switch circuit 134 may select a connection to the PMIC 30 or the charge pump 135 according to application requirements of the nonvolatile memory device 10. The application requirements may refer to the magnitude of a voltage and the magnitude of a current required to execute a plurality of commands including performance (e.g., a maximum allowable current, a maximum supply power, a rectified current, or a rectified voltage) that may be provided by the PMIC 30, a data read command, a data write command, and an erase command.

[0060] According to example embodiments, the current sensing unit 131 may be connected to the switch circuit 134. The current sensing unit 131 may replicate the charging current input to the plurality of word lines via the switch circuit 134. According to various example embodiments, the current sensing unit 131 may include a current mirror circuit or a coupler for replicating the charging current. The current mirror circuit or the coupler may replicate the charging current input via the switch circuit 134 to a size of 1 / M. M may have a positive integer value. For example, M may be 1000. Since the size of the current replicated by the current mirror circuit or the coupler is only 1 / 1000 of the charging current, a current that does not affect the charging of the word line and determines whether the size of the charging current is greater than the size of the peak current may be obtained.

[0061] According to an example embodiment, the current sensing unit 131 may further include a resistor 141. The resistor 141 may be one terminal (e.g., a positive input terminal) of the comparator and may be connected to a ground terminal. Since one terminal of the comparator is equivalent to an open circuit, the charging current replicated by the current mirror circuit or the coupler may flow to the ground terminal via the resistor 141. Therefore, the voltage value V_detect formed by the replicated charging current flowing to the resistor 141 may be input to the one terminal of the comparator. The current sensing unit 131 may sense the magnitude of the charging current passing through the switch circuit 134 based on the voltage value V_detect.

[0062] The peak detection unit 132 may include a comparator. A voltage value V_detect is input to one terminal of the comparator, and a peak voltage may be applied to the other terminal of the comparator. The peak voltage may have a voltage level corresponding to a peak current value. For example, a peak voltage having a voltage value V_peak for detecting a peak current may have a voltage level obtained by multiplying the value of the resistor 141 by the peak current value. The output terminal of the comparator may be connected to a slope control unit 133. When the output signal of the comparator is a logic low or "0", the slope control unit 133 may determine that the voltage value V_detect is inconsistent with the voltage value V_peak. When the output signal of the comparator is a logic high or "1", the slope control unit 133 may determine that the voltage value V_detect is consistent with the voltage value V_peak. In various example embodiments, the output signal of the comparator may be referred to as a peak detection signal Peak_Detect.

[0063] In the above exemplary embodiment, it is described that M is 1000. However, the inventive concept is not limited thereto. M may be variable as long as it does not affect the magnitude of the charging current. For example, M may be 100 to 10000.

[0064] In the above-described example embodiments, the peak current value is described as being previously determined. However, the inventive concept is not limited thereto. In various example embodiments, the peak current value may be changed based on application requirements. For example, when the switch circuit 134 is connected to the PMIC 30 having a large maximum allowable current value, the peak current value may be increased.

[0065] The slope control unit 133 may transmit a slope control signal to the at least one driving circuit 136. Specifically, the slope control unit 133 may transmit the slope control signal to the reference voltage generator 137 included in the at least one driving circuit 136. According to various example embodiments, the slope control signal may correspond to a signal for controlling the size of the reference voltage increased per unit time.

[0066] At least one driving circuit 136 may charge the word line 139. In various example embodiments, the word line 139 may be modeled to include a capacitor and a current source. The current source may correspond to a leakage current of a non-ideal capacitor. In various example embodiments, at least one driving circuit 136 may include a reference voltage generator 137 and an operational amplifier 138. The reference voltage V_ formed by the reference voltage generator 137 is REF may be provided to the negative input terminal of the operational amplifier 138 .

[0067] According to an example embodiment, the reference voltage generator 137 receives a control signal from the slope control unit 133 and can change the magnitude of the reference voltage. For example, when the magnitude of the charging current is greater than the peak current value, the magnitude of the slope of the reference voltage increase can be reduced. In another example, when the magnitude of the charging current is less than the peak current value, the magnitude of the slope of the reference voltage increase can be increased. In the above example embodiments, the reference voltage generator 137 is described as being included in at least one driving circuit 136. However, the inventive concept is not limited thereto.

[0068] In various example embodiments, the reference voltage generator 137 may be disposed outside the at least one driving circuit 136. In this case, the reference voltage may be applied to a negative input terminal of an operational amplifier 138 included in the at least one driving circuit 136.

[0069] Figure 7 is a flowchart illustrating a method of operating a voltage generator according to an example embodiment of the inventive concept.

[0070] refer to Figure 7 In operation S110, the voltage generator 130 may start to ramp the word line voltage VWL. For example, the control logic 100 may send a voltage control signal Ctrl_vol to the voltage generator 130. The voltage generator 130 may perform a voltage ramp to charge the word line WL in response to the voltage control signal Ctrl_vol.

[0071] In operation S120, the voltage generator 130 may sense the charging current. The voltage generator 130 may activate the current sensing unit 131 in response to the voltage control signal Ctrl_vol of operation S110. For example, the current sensing unit 131 may copy the charging current flowing through the switch circuit 134 to a size of 1 / 1000. In the above example embodiment, it is described that the current is copied to a size of 1 / 1000 of the charging current. However, the inventive concept is not limited thereto. In addition, in the above example embodiment, it is described that the current sensing unit 131 is activated in response to the voltage control signal Ctrl_vol. However, the inventive concept is not limited thereto. In various example embodiments, the current sensing unit 131 may sense the charging current in response to an additional enable signal.

[0072] In operation S130, the voltage generator 130 may determine whether the sensed current is greater than the peak current. The voltage generator 130 may compare the magnitude of the sensed current with the peak current value by using the peak detection unit 132. Figure 6 or Figure 7, the comparator of the peak detection unit 132 may compare the voltage value V_detect generated by the sensed current flowing through the resistor 141 with the voltage value V_peak for detecting the peak current. When the voltage value V_detect is equal to the voltage value V_peak, the comparator of the peak detection unit 132 may output a high signal indicating that the charging current is greater than the peak current. When the voltage value V_detect is different from the voltage value V_peak, the comparator of the peak detection unit 132 may output a low signal. Therefore, when the slope control unit 133 receives a high signal from the peak detection unit 132, it may be determined that the sensed current has reached the peak current value.

[0073] In operation S140, the voltage generator 130 may ramp up the reference voltage according to the first slope. When the magnitude of the sensed current is not greater than the peak current value, the slope control unit 133 may ramp up the reference voltage according to the first slope. When the reference voltage is ramped up according to the first slope, the magnitude of the charging current, which is the sum of the currents input to the at least one driving circuit 136, may increase.

[0074] In operation S150, the voltage generator 130 may ramp up the voltage according to the second slope. When the magnitude of the sensed current is greater than the peak current value, the slope control unit 133 may ramp up the voltage according to the second slope. The second slope may correspond to a value less than the first slope. When the reference voltage is ramped up according to the reduced second slope, the magnitude of the charging current, which is the sum of the currents input to the at least one driving circuit 136, may be reduced.

[0075] In operation S160, the voltage generator 130 may determine whether the reference voltage is the same as the target voltage. For example, when it is determined that the word line voltage VWL is the same as the target voltage, since the word line WL is fully charged and the magnitude of the charging current is reduced, the slope control unit 133 may stop the slope control for detecting the peak current. In another example, when the word line voltage VWL is lower than the target voltage, the slope control unit 133 may perform operation S130 to determine again whether the magnitude of the sensed current is greater than the peak current value.

[0076] Figure 8 is a diagram illustrating a charging current and a word line voltage according to an example embodiment of the inventive concept.

[0077] refer to Figure 8, in the period t0 to t1, the voltage generator 130 may ramp up the word line voltage VWL. For example, the voltage generator 130 receives the voltage control signal Ctrl_vol from the control logic 100, and may determine to precharge the word line WL. In the period t0 to t1, since the magnitude of the charging current flowing through the switch circuit 134 is less than the peak current value, the comparator of the peak detection unit 132 may output a low signal. When a low signal is input from the peak detection unit 132, the slope control unit 133 may perform control to ramp up the reference voltage according to a first slope. When the plurality of word line voltages are ramped up according to the first slope, the charging current, which is the sum of the currents input to the at least one drive circuit 136 via the switch circuit 134, may increase sharply.

[0078] In the period t1 to t2, the slope control unit 133 may perform control to ramp up the voltage according to the second slope. The voltage value formed in the current sensed at time t1 may be equal to the voltage value for detecting the peak current. Therefore, since the voltage values ​​of the two terminals of the comparator of the peak detection unit 132 are equal, a high signal may be output. When a high signal is output from the peak detection unit 132, the slope control unit 133 determines that the magnitude of the charging current flowing via the switch circuit 134 reaches the peak current value and can reduce the slope of the voltage ramping. The magnitude of the second slope may be smaller than the magnitude of the first slope. The slope control unit 133 may maintain the ramping of the reference voltage according to the second slope until the time point when the low signal is received from the peak detection unit 132. Since the magnitude of the second slope is smaller than the magnitude of the first slope, when the multiple word line voltages are ramped up according to the second slope, the magnitude of the current requested by the at least one drive circuit 136 may be smaller than when the reference voltage is ramped up according to the first slope. Therefore, the magnitude of the charging current, which is the sum of the currents input to the at least one drive circuit 136 via the switch circuit 134, may be reduced.

[0079] In the period t2 to t3, the slope control unit 133 determines that the magnitude of the charging current is not greater than the peak current value, and the reference voltage can be ramped up according to the first slope. Specifically, at time t2, the slope control unit 133 can determine that the magnitude of the charging current flowing via the switch circuit 134 is reduced to not greater than the peak current value in response to the low signal received from the peak detection unit 132. Therefore, the slope control unit 133 can perform control to ramp up the reference voltage according to the first slope. Similar to the period t0 to t1, when the reference voltage is ramped up according to the first slope, the magnitude of the charging current flowing via the switch circuit 134 can increase.

[0080] According to various example embodiments, when the magnitude of the charging current is greater than the peak current value, the slope control unit 133 may perform control by ramping up the reference voltage according to the second slope so that the magnitude of the charging current is less than the peak current value. When the magnitude of the charging current is less than the peak current value, the slope control unit 133 may quickly ramp up the word line voltage VWL by ramping up the reference voltage according to the first slope until a time point when the magnitude of the charging current is greater than the peak current value.

[0081] According to various example embodiments, when the slope control unit 133 variably controls the slope for ramping up the reference voltage, the time taken to reach the target voltage may correspond to t5. On the other hand, in a conventional method of generating a charging current whose magnitude is not greater than the peak current value and ramping up the reference voltage according to a fixed slope, the time taken to reach the target voltage may be t6. That is, by variably controlling the slope for ramping up the reference voltage, in the case where the magnitude of the charging current is not greater than the peak current value, the standby time for driving the word line WL may be reduced from t6 to t5.

[0082] In the above exemplary embodiment, it is described that the slope control unit 133 increases the reference voltage according to the first slope or the second slope. However, the inventive concept is not limited thereto. According to various exemplary embodiments, the slope control unit 133 may change the slope value in the clock mode or the sensing level mode.

[0083] According to various example embodiments, in the clock mode, the slope is changed based on the reference clock signal. For example, the slope control unit 133 may operate based on the timing of the rising and falling edges of the clock signal. For example, the slope control unit 133 may count the reference clock from the time point when the peak detection unit 132 receives the high signal. The slope control unit 133 may control the reference voltage increased according to the first slope to increase according to the second slope in response to the received high signal. The slope control unit 133 may count the number of previously determined reference clocks from the time point when the high signal is received. For example, the previously determined number of times may correspond to 10. When the reference clock passes 10 times from the time point when the high signal is received, the slope control unit 133 may additionally change the slope value of the reference voltage. For example, the slope control unit 133 may increase the reference voltage according to a third slope. The third slope may correspond to a value less than the second slope.

[0084] According to various example embodiments, in the sensing level mode, the slope is changed based on multiple peak current values. The voltage generator 130 may include multiple comparators. The multiple comparators may detect multiple peak current values, respectively. Although not shown, the first peak detection unit detects the first current level, the second peak detection unit detects the second current level, and the third peak detection unit detects the third current level. The second current level may have a greater value than the first current level, and the third current level may have a greater value than the second current level. The slope control unit 133 may control the reference voltage increased according to the first slope to increase according to the second slope in response to a high signal received from the first peak detection unit. The second slope may correspond to a smaller value than the first slope. Then, when the charging current increases continuously and the magnitude of the charging current is greater than the second peak current value, the slope control unit 133 may receive a high signal from the second peak detection unit. In this case, the slope control unit 133 may control the reference voltage increased according to the second slope to increase according to the third slope. The third slope may have a smaller value than the second slope. Similar to the second peak detection unit, when a high signal is received from the third peak detection unit, the slope control unit 133 may control the reference voltage increased according to the third slope to increase according to the fourth slope.

[0085] Fig.9A is a circuit diagram illustrating an example of a slope control unit according to an example embodiment of the inventive concept.

[0086] refer to Fig.9A , the slope control unit 133 may include a current source 201, a capacitor 202, and a comparator 203. The current source 201 may output a current independently. According to an example embodiment, the current source 201 may change the magnitude of the output current based on a signal received from the peak detection unit 132. The output current may be referred to as a bias current. For example, when a signal indicating that the magnitude of the charging current is greater than the peak current value is received from the peak detection unit 132, the current source 201 may reduce the magnitude of the output current. In another example, when a signal indicating that the magnitude of the charging current is less than the peak current value is received from the peak detection unit 132, the current source 201 may increase the magnitude of the output current.

[0087] The capacitor 202 can form a reference voltage by using a bias current. Since the input terminal of the comparator 203 is equivalent to an open circuit, the bias current output from the current source 201 can pass through the capacitor 202. Since the bias current passes through the capacitor 202, a charge can be charged in the capacitor 202 and a voltage can be formed. The formed voltage can be input to at least one driving circuit 136 as a reference voltage.

[0088] According to an example embodiment, the comparator 203 may form a feedback loop. The feedback loop may include an electrical path from the output terminal of the comparator 203 to the current source 201, an electrical path from the current source 201 to the capacitor 202, and an electrical path from the capacitor 202 to the input terminal of the comparator 203. According to an example embodiment, the comparator 203 determines whether the reference voltage is the same as the target voltage, and may output a slope control signal. For example, when the reference voltage is the same as the target voltage, the output terminal may output a low signal. According to the feedback loop, the low signal may be fed back to the current source 201. The current source 201 receiving the low signal may maintain the output of the current. In another example, when the reference voltage reaches the target voltage, the comparator 203 may output a high signal. According to the feedback loop, the high signal may be fed back to the current source 201. When the high signal is received, the current source 201 may stop outputting the bias current.

[0089] Fig. 9B is a diagram illustrating a charging current and a word line voltage according to an example embodiment of the inventive concept.

[0090] refer to Fig. 9B At time t0, the slope control signal may be enabled. The current source 201 may output a bias current in response to the slope control signal. The bias current may have a first magnitude. Fig.9A As shown in , the output bias current can pass only through the capacitor 202 without being applied to the comparator 203 equivalent to an open circuit. In the period t0 to t1, since the bias current having the first magnitude passes through the capacitor 202, the charge is charged in the capacitor 202, and a reference voltage increased according to the first slope can be formed. The first slope can have the same magnitude as the first magnitude of the bias current. The reference voltage increased according to the first slope can be applied to at least one drive circuit 136. As the increase ratio of the reference voltage increases, the magnitude of the current flowing to the word line connected to the at least one drive circuit 136 can also increase. Since the charging current through the switch circuit 134 is the sum of the currents input to the plurality of word lines, the charging current can increase rapidly.

[0091] At time t1, the peak detection signal Peak_Detect may be enabled. The magnitude of the charging current that increases rapidly in the period t0 to t1 may be greater than the peak current value. The peak detection unit 132 may send a peak detection signal Peak_Detect to the current source 201, which indicates that the magnitude of the charging current through the switch circuit 134 is greater than the peak current value. The current source 201 may reduce the output of the bias current at time t1. For example, the current source 201 may output a current of a second magnitude that is less than the first magnitude. In the period t1 to t2, since the bias current of the second magnitude passes through the capacitor 202, a charge is charged in the capacitor 202, and a reference voltage that increases according to a second slope may be formed. The second slope may have a magnitude equal to the first magnitude of the bias current. The reference voltage that increases according to the second slope may be applied to at least one drive circuit 136. Compared to the reference voltage that increases according to the first slope, since the increase ratio of the reference voltage that increases according to the second slope decreases, the magnitude of the current that flows to the word line connected to the at least one drive circuit 136 may be reduced. In this case, since the charging current passing through the switch circuit 134 is the sum of currents input to a plurality of word lines, the magnitude of the charging current can also be reduced.

[0092] At time t2, the peak detection signal Peak_Detect may be disabled. The charging current reduced in the period t1 to t2 may be reduced to a value not greater than the peak current value. The peak detection unit 132 may indicate that the magnitude of the charging current through the switch circuit 134 is reduced to a value not greater than the peak current value by disabling the peak detection signal Peak_Detect. The current source 201 may increase the output of the bias current at time t2. For example, the current source 201 may output a bias current of a first magnitude. The description of the period t2 to t3 may be the same as the description of the period t0 to t1. The description of the period t3 to t4 may be the same as the description of the period t1 to t2.

[0093] At time t5, the slope control signal may be disabled. Fig.9A , the comparator 203 may perform an operation of comparing the reference voltage with the target voltage. When the reference voltage is the same as the target voltage at time t5, the output terminal of the comparator 203 may output a high signal. When the current source 201 receives a high signal from the output terminal of the comparator 203 forming a feedback loop, the current source 201 may stop outputting the bias current. When the bias current is not output, additional charge may not be charged in the capacitor 202. Since the previously charged charge exists in the capacitor 202, the reference voltage reaching the target voltage may be uniformly maintained.

[0094] According to various example embodiments, the slope control unit 133 may inactivate the current sensing unit 131. For example, after time t5, the charging current may be quickly reduced. When it is determined that the reference voltage is consistent with the target voltage, the slope control unit 133 may determine whether a current of a previously determined value is detected. When a current of a previously determined value is detected, the slope control unit 133 may determine that the word line WL is fully charged, thus stabilizing the charging current. Therefore, the slope control unit 133 may inactivate the current sensing unit 131.

[0095] Fig. 10A is a circuit diagram illustrating another example of the slope control unit 133 according to an example embodiment of the inventive concept.

[0096] refer to Fig. 10A , the slope control unit 133 may include a resistor-digital analog converter (R-DAC).

[0097] In various example embodiments, the R-DAC may include a plurality of voltage nodes corresponding to a plurality of voltage levels, respectively. Based on voltage distribution performed by a plurality of resistors connected between ground nodes, the plurality of voltage nodes may correspond to a plurality of voltage levels, respectively. For example, referring to Fig. 10A , the R-DAC may include 12 resistors. A first voltage may be applied to the first node. In various example embodiments, the R-DAC may include a plurality of switches corresponding to the plurality of nodes, respectively.

[0098] In various example embodiments, the control logic ( Figure 2 100) can control a plurality of switches included in the R-DAC. The control logic 100 can select the R-DAC output voltage by sending an R-DAC control signal. The R-DAC output voltage can be input to at least one driving circuit 136 as a reference voltage. According to an example embodiment, when a signal indicating that the magnitude of the charging current is not greater than the peak current value is received from the peak detection unit 132, the control logic 100 can control a plurality of switches so as to apply a reference voltage increased according to a first slope. Since a plurality of nodes of the R-DAC correspond to discrete voltage values, respectively, the control logic 100 can increase the switch distance to correspond to the reference voltage increased according to the first slope. For example, the control logic 100 can sequentially switch the first node, the third node, the fifth node, the seventh node, and the ninth node.

[0099] The increased switching distance can correspond to that obtained by using Fig. 9BAccording to another example embodiment, when a signal indicating that the magnitude of the charging current is greater than the peak current value is received from the peak detection unit 132, the control logic 100 may control the plurality of switches so as to apply a reference voltage that increases according to a second slope. Since the plurality of nodes of the R-DAC correspond to discrete voltage values, respectively, the control logic 100 may reduce the switching distance to correspond to the reference voltage that increases according to the second slope. For example, the control logic 100 may sequentially switch the first node, the second node, the third node, the fourth node, and the fifth node. The reduced switching distance may correspond to the switching of the first node, the second node, the third node, the fourth node, and the fifth node by using Fig. 9B The bias current of the second magnitude increases according to the reference voltage at a second slope.

[0100] Fig. 10B is a diagram illustrating a charging current and a word line voltage according to an example embodiment of the inventive concept.

[0101] refer to Fig. 10B , at time t0, the slope control signal may be enabled. The control logic 100 may send the R-DAC control signal to the voltage generator 130 in response to the slope control signal. For example, the R-DAC may sequentially switch the first node, the third node, and the fifth node. According to the switch, the first voltage, the third voltage, and the fifth voltage corresponding to the first node, the third node, and the fifth node, respectively, may be input as reference voltages. Since the change ratio of the reference voltage is a positive value, the magnitude of the charging current through the switch circuit 134 may increase.

[0102] At time t1, the peak detection signal Peak_Detect may be enabled. The magnitude of the charging current that increases rapidly in the period t0 to t1 may be greater than the peak current value. The peak detection unit 132 may send a peak detection signal Peak_Detect to the control logic 100 indicating that the magnitude of the charging current through the switch circuit 134 is greater than the peak current value. The control logic 100 may send a control signal to the R-DAC for reducing the switching distance of the R-DAC. The R-DAC may reduce the voltage switching distance. For example, the R-DAC may switch the fifth node, the sixth node, and the seventh node sequentially. According to the switch, a fifth voltage, a sixth voltage, and a seventh voltage corresponding to the fifth node, the sixth node, and the seventh node, respectively, may be input as reference voltages. In response to a decrease in the change ratio of the reference voltage, the magnitude of the current flowing to the word line connected to the at least one drive circuit 136 may be reduced. In this case, since the charging current through the switch circuit 134 is the sum of the currents input to the plurality of word lines, the magnitude of the charging current may also be reduced.

[0103] At time t2, the peak detection signal Peak_Detect may be disabled. In the period t1 to t2, the magnitude of the charging current may be reduced to not more than the peak current value. The peak detection unit 132 may indicate that the magnitude of the charging current through the switch circuit 134 is reduced to not more than the peak current value by disabling the peak detection signal Peak_Detect. The control logic 100 may send a control signal for instructing the R-DAC to increase the switching distance. The R-DAC may increase the voltage switching distance. For example, the R-DAC may sequentially switch the seventh node, the ninth node, and the eleventh node.

[0104] According to the switch, the seventh voltage, the ninth voltage, and the eleventh voltage corresponding to the seventh node, the ninth node, and the eleventh node, respectively, can be input as reference voltages. In response to the increase in the change ratio of the reference voltage, the magnitude of the current flowing to the word line connected to at least one drive circuit 136 can be increased. In this case, since the magnitude of the charging current through the switch circuit 134 is the sum of the currents input to the plurality of word lines, the magnitude of the charging current can be increased again. The description of the period t2 to t3 is the same as the description of the period t0 to t1. The description of the period t3 to t4 is the same as the description of the period t1 to t2.

[0105] At time t5, the slope control signal may be disabled. Fig. 10B A detailed description can be like Fig. 9B The description of time t5 is the same.

[0106] Fig.11A is a circuit diagram illustrating a voltage generator 130 including an event creation unit 300 according to an example embodiment of the inventive concept.

[0107] refer to Fig.11A , the voltage generator 130 may include a PMIC 30, a switch circuit 134, a charge pump 135, a current sensing unit 131, a peak detection unit 132, and an event creation unit 300. Although not shown, the voltage generator 130 may include Figure 6 At least one driving circuit 136, a reference voltage generator 137, an operational amplifier 138, and a word line 139 are shown. The event creation unit 300 may receive a value obtained by sensing the charging current from the current sensing unit 131. The event creation unit 300 may generate a signal for instructing a word line charging event based on the received sensing value.

[0108] According to an example embodiment, the event creation unit 300 may compare the received sensing value with a previously determined current value. The previously determined current value may refer to a size of a charging current that is reduced enough to assume that the word line 139 reaches the target voltage. As the word line voltage value approaches the target voltage value, since the size of the charging current used to increase the word line voltage decreases, when the sensing value of the charging current received from the current sensing unit 131 is equal to the previously determined current value, the event creation unit 300 may determine that the word line 139 reaches the target voltage.

[0109] When receiving the sense value equal to the previously determined current value, the event creation unit 300 may transmit an event creation signal to the control logic 100. Since the word line 139 is fully charged, in response to the event creation signal received from the event creation unit 300, the control logic 100 may perform control to process the next process.

[0110] Fig. 11B is a diagram illustrating a time point of generating an event according to an example embodiment of the inventive concept.

[0111] refer to Fig. 11B , the event creation unit 300 may determine whether to generate an event based on the sensed value received from the current sensing unit 131. The event may indicate that the word line 139 is fully charged.

[0112] At time t0, the event creation unit 300 may determine that the magnitude of the charging current received from the current sensing unit 131 is equal to the previously determined current value. In response to determining that the magnitude of the charging current is equal to the previously determined current value, the event creation unit 300 may send an event creation signal to the control logic 100. In response to the event creation signal, the control logic 100 may perform control to execute various commands including a data read command and a data write command by using the fully charged word line 139.

[0113] Time t1 may refer to the minimum time that the control logic 100 stands by in order to charge the word line 139 in the conventional art. When the charging current is not measured in real time, the control logic 100 may perform control to execute various commands after waiting for the time t1, where it may be assumed at time t1 that the word line 139 is fully charged. Therefore, the event creation unit 300 according to the above-described example embodiment may send an event creation signal to the control logic 100 at t0, which is a time point when the word line 139 is actually charged, by determining the magnitude of the charging current received from the current sensing unit 131, without waiting for the word line 139 to be charged until t1. Therefore, the control logic 100 may reduce the standby time for driving the word line 139 and improve performance by performing an operation (e.g., a data read operation or a data write operation) according to an input command without waiting until time t1.

[0114] Fig.12 1 is a block diagram illustrating an example in which a memory device according to an example embodiment of the inventive concept is applied to a solid state drive (SSD) system 1000 .

[0115] refer to Fig.12 , the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 sends signals to and receives signals from the host 1100 via a signal connector, and receives power via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and a plurality of memory devices 1230, 1240, and 1250. At this time, at least one of the plurality of memory devices 1230, 1240, and 1250 may be connected to the SSD 1200 by using Figures 1 to 11B The SSD controller 1210 may be implemented in the SSD 1200 as hardware or software, or in the form of a combination of hardware and software. For example, more specifically, the SSD controller 1210 may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0116] Specifically, Figure 2 The nonvolatile memory device 10 may be applied to at least one of the plurality of memory devices 1230, 1240, and 1250. Therefore, when the magnitude of the charging current for charging the word line 139 is greater than the peak current value, at least one of the plurality of memory devices 1230, 1240, and 1250 may increase the reference voltage according to the second slope. When the magnitude of the charging current for charging the word line 139 is not greater than the peak current value, at least one of the plurality of memory devices 1230, 1240, and 1250 may increase the reference voltage according to the first slope.

[0117] Therefore, shutdown or malfunction of the SSD 1200 can be prevented by controlling the magnitude of the charging current to be not greater than the peak current value and charging the word line 139. In addition, by quickly increasing the reference voltage according to the first slope during a period in which the magnitude of the charging current is not greater than the peak current value, the time taken to increase the word line voltage to the target voltage can be reduced compared to a case in which the reference voltage is increased according to a fixed slope.

[0118] The memory device according to the example embodiments of the inventive concept may be installed in or applied to a memory card system, a computing system, or a UFS as well as the SSD 1200. In addition, the method of operating the memory device according to the example embodiments of the inventive concept may be applied to each of various electronic systems in which a nonvolatile memory device is installed.

[0119] While the inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A voltage generator, comprising: at least one driver circuit connected to a plurality of word lines of a memory device, the at least one driver circuit being configured to provide a current for increasing a voltage of the plurality of word lines based on a reference voltage; a current sensing circuit configured to sense a magnitude of a charging current input to the at least one driving circuit; a peak detection circuit configured to compare the magnitude of the sensed charging current with a peak current value; as well as a slope control circuit configured to provide a reference voltage to the at least one driving circuit, When the magnitude of the sensed charging current is less than or equal to the peak current value, increasing the reference voltage according to a first slope, and When the magnitude of the sensed charging current is greater than the peak current value, the reference voltage is increased according to a second slope that is less than the first slope.

2. The voltage generator according to claim 1, further comprising: switch, configured to select a power management integrated circuit PMIC or a charge pump, The charging current is input from the PMIC or the charge pump to the at least one driving circuit via a switch.

3. The voltage generator according to claim 2, in, The current sensing circuit includes a feedback loop including a mirror circuit configured to replicate a current having a magnitude of 1 / M of a magnitude of a charging current input to the at least one driving circuit via the current sensing circuit or the operational amplifier, and Wherein, M is a positive integer.

4. The voltage generator according to claim 1, in, The slope control circuit includes a current source and a capacitor. wherein when the magnitude of the sensed charging current is less than or equal to the peak current value, the slope control circuit reduces the magnitude of the current output from the current source to charge the capacitor, and when the magnitude of the sensed charging current is greater than the peak current value, the slope control circuit increases the magnitude of the current output from the current source to charge the capacitor, and The capacitor is charged based on the current output from the current source to form a reference voltage.

5. The voltage generator according to claim 1, in, The slope control circuit includes a plurality of switches connected to a plurality of nodes, respectively, and a resistor-digital-analog converter R-DAC for outputting a voltage of one of the plurality of nodes as a reference voltage in response to a switch signal, the plurality of nodes respectively corresponding to the plurality of voltages, and The slope control circuit is configured to increase the switching distance when the magnitude of the sensed charging current is less than or equal to the peak current value, and output a voltage among the plurality of voltages corresponding to one of the plurality of nodes through the switching distance, and When the magnitude of the sensed charging current is greater than the peak current value, the switching distance is reduced, and another voltage among the plurality of voltages corresponding to another node among the plurality of nodes is output through the switching distance.

6. The voltage generator according to claim 1, wherein: The slope control circuit is configured as measuring an output voltage of the at least one driver circuit, and When the measured output voltage agrees with the target voltage, the current sensing circuit is deactivated.

7. The voltage generator according to claim 1, wherein: The slope control circuit is configured as Operate based on the timing of the rising and falling edges of the clock signal, or The operation is performed based on a sense level obtained by a current sensing circuit.

8. The voltage generator according to claim 1, wherein: The peak current value varies based on the requirements of the application.

9. The voltage generator according to claim 1, wherein: When the magnitude of the charging current obtained by the current sensing circuit is not greater than a previously determined magnitude, the slope control circuit is configured to deactivate the current sensing circuit.

10. The voltage generator according to claim 1, in, The current sensing circuit is configured to determine whether the magnitude of the sensed charging current is consistent with a previously determined magnitude, and When the magnitude of the sensed charging current is consistent with the previously determined magnitude, an event creation signal is sent to the control logic, and Among them, the event creation signal indicates the start of the next process to be processed.

11. A method of operating a voltage generator, the method comprising: providing a reference voltage to at least one driver circuit; sensing a magnitude of a charging current, the charging current being used to increase a voltage of a plurality of word lines based on a reference voltage; determining whether the magnitude of the sensed charging current is greater than the peak current value; When the magnitude of the sensed charging current is less than or equal to the peak current value, increasing the reference voltage according to a first slope; as well as When the magnitude of the sensed charging current is greater than the peak current value, the reference voltage is increased according to a second slope that is less than the first slope.

12. The method of claim 11, further comprising: By using a switching circuit to select a power management integrated circuit PMIC or a charge pump as a current source, Wherein, sensing the magnitude of the charging current further comprises using a mirror circuit to replicate a current having a magnitude of 1 / M of the magnitude of the charging current, Wherein, M is a positive integer.

13. The method according to claim 11, in, The voltage generator includes a current source for outputting a current, and a capacitor charged by using the current output from the current source to form a reference voltage, Wherein, increasing the reference voltage according to the first slope includes increasing the magnitude of the current output from the current source, and Wherein, increasing the reference voltage according to the second slope includes reducing the magnitude of the current output from the current source.

14. The method according to claim 11, in, The voltage generator includes a plurality of switches connected to a plurality of nodes, respectively, and a resistor-digital-analog converter R-DAC for outputting a voltage of one of the plurality of nodes as a reference voltage in response to a switch signal, the plurality of nodes respectively corresponding to the plurality of voltages, wherein increasing the reference voltage according to the first slope comprises increasing a switching distance, outputting a voltage among the plurality of voltages corresponding to one of the plurality of nodes through the switching distance, and Increasing the reference voltage according to the second slope includes reducing a switching distance, through which another voltage among the plurality of voltages corresponding to another node among the plurality of nodes is output.

15. The method of claim 11, further comprising: Determine whether the reference voltage is consistent with the target voltage; as well as When the reference voltage is consistent with the target voltage, the operation of sensing the magnitude of the charging current is bypassed.

16. The method of claim 11, wherein: The steps of applying the reference voltage increasing according to the first slope and applying the reference voltage increasing according to the second slope operate based on the timing of rising and falling edges of the clock signal, or operate based on a sensed level obtained by a current sensing circuit.

17. The method of claim 11, wherein: The peak current value varies based on the requirements of the application.

18. The method of claim 11, further comprising: When the magnitude of the charging current is not greater than the previously determined magnitude, the current sensing circuit is deactivated.

19. The method of claim 11, further comprising: determining whether the magnitude of the sensed charging current is consistent with a previously determined magnitude; as well as When the magnitude of the sensed charging current is consistent with the previously determined magnitude, an event creation signal is sent to the control logic, The event creation signal indicates that the voltage of the word line reaches the target voltage.

20. A non-volatile memory device comprising: a memory cell array; a row decoder connected to the memory cell array via a plurality of word lines; as well as Voltage generator, configured as: sensing a magnitude of a charging current input to at least one driving circuit connected to the plurality of word lines, The magnitude of the sensed charging current is compared with the peak current value. providing a reference voltage to the at least one driving circuit, When the magnitude of the sensed charging current is less than or equal to the peak current value, increasing the reference voltage according to a first slope, and When the magnitude of the sensed charging current is greater than the peak current value, the reference voltage is increased according to a second slope that is less than the first slope.

Images