Mixed modulus converter circuit

Abstract

The present invention discloses a hybrid analog-to-digital converter circuit that can stably load the voltages at both ends and reduce the output voltage ripple, comprising a power supply, a digital converter, an analog converter, and a load component; the analog converter includes a plurality of power supply capacitors arranged in parallel, and when the load component is operating, it is connected to each power supply capacitor in turn, and the power supply capacitors not in a connected state with the load component are connected to the digital converter in turn. The present invention also discloses a hybrid analog-to-digital converter circuit, comprising a power supply, a digital converter, an analog converter, and a load component; the digital converter includes an element multiplexer connected to the input end and the output end of the power supply through wires, the element multiplexer includes a plurality of power supply capacitors arranged in series, the analog converter includes the element multiplexer, and both ends of each power supply capacitor in the element multiplexer are respectively connected to the input end and the output end of the load component through discharge wires, and when the load component is operating, it is connected to each power supply capacitor in turn.

Description

Technical Field

[0001] The present invention relates to a hybrid analog-to-digital converter circuit. Background Art

[0002] A DC / DC converter is a voltage converter that effectively outputs a specified voltage after converting an input voltage. DC / DC converters are divided into three categories: boost DC / DC converters, buck DC / DC converters, and buck-boost DC / DC converters. DC / DC converters have both linear and switching modes. Traditional linear voltages have low efficiency, generate a large amount of heat, and are large in size. The mainstream of high-power conversion is switched-mode power supplies. Traditional switched-mode power supplies are based on digital converters and use semiconductor devices as switches. The switching action generates square voltage / current waveforms and will suffer severe instantaneous power shocks during frequent switching, so a large low-pass filter is required to filter the ripples.

[0003] Currently, there are mainly three existing methods to solve the problem of the overly large size of the low-pass filter:

[0004] One is to reduce the ripple size from the power supply. Usually, a multilevel converter is used to reduce the ripple size of the power supply. However, a multilevel converter requires a large number of semiconductors, and an additional sensing circuit and a complex control method are required to maintain the power balance between sub-modules.

[0005] The second is to increase the gain of the low-pass filter during transmission. By increasing the switching frequency, the filtering effect of a specific low-pass filter can be increased. However, increasing the switching frequency will increase the power loss in semiconductors and magnetic units. In addition, parasitic elements such as capacitors, resistors, and inductors will reduce the filtering effect of the filter at high frequencies.

[0006] The third is to adopt an advanced control method, such as the active capacitance method. This method can transfer the ripple power to the energy storage device, thereby reducing the ripple power size transmitted to the load. However, according to the Shannon sampling theorem, the control bandwidth in existing DC / DC converters is limited by the switching frequency. However, the frequency of the main component of the switching ripple is equal to or greater than the switching frequency. Therefore, the existing active control methods cannot reduce the switching harmonics. Summary of the Invention

[0007] The technical problem to be solved by the present invention is: to provide a hybrid analog-to-digital converter circuit that can stabilize the voltage across the load, reduce the output voltage ripple, and increase the power density of the transformer.

[0008] To solve the above technical problem, the technical solution adopted by the present invention is: a hybrid analog-to-digital converter circuit, including a power supply and a digital converter connected to the power supply. An analog converter is connected between the input end and the output end of the digital converter, and the analog converter is connected to a load component;

[0009] The analog-to-digital converter includes a number of power supply capacitors. Both ends of each power supply capacitor are respectively connected to the input end and the output end of the digital converter through charging wires, and at least one of the charging wires is provided with a charging switch; both ends of each power supply capacitor are respectively connected to the input end and the output end of the load component through discharging wires, and at least one of the discharging wires is provided with a discharging switch; when the load component works, it is connected to each power supply capacitor in turn by closing the corresponding discharging switch, and the power supply capacitor not in a connected state with the load component is connected to the digital converter in turn by closing the corresponding charging switch.

[0010] Among them, the load component is equivalent to a load capacitor C L and a load resistor R L connected in parallel, and a load inductor L connected in series with the two after parallel connection;

[0011] When a part of the equivalent capacitance C L of the load component is given, the minimum capacitance value C 1 , C 2 ,... C N of the power supply capacitor is equal to the DC bus capacitance value C bus and is calculated by the following formula: where I o is the output current on the partial equivalent resistor R L of the load component; V o is the output voltage on the partial equivalent resistor R L of the load component; ΔV o is the output voltage ripple on the partial equivalent resistor R L of the load component; f sw is the circuit switching frequency;

[0012] When a part of the equivalent capacitance C L of the load component is not limited, the minimum capacitance value C 1 , C 2 ,... C N of the power supply capacitor is equal to the DC bus capacitance value C bus . It is calculated by the following formula: Let NC bus = C L , and the required minimum C L is obtained: where N is the number of power supply capacitors, I o is the output current on the partial equivalent resistor R L of the load component; V o is the output voltage on the partial equivalent resistor R L of the load component; ΔV o is the output voltage ripple on the partial equivalent resistor R L of the load component; fsw is the circuit switching frequency.

[0013] As a preferred solution, the digital converter is a DC / DC converter.

[0014] As a preferred solution, the digital converter is a buck converter or a boost converter or a resonant converter.

[0015] As a preferred solution, the charging time and the discharging time of each power supply capacitor are both the circuit switching period T sw / the number of power supply capacitors N.

[0016] Another technical problem to be solved by the present invention is: to provide another hybrid analog-digital converter circuit that can stabilize the voltage across the load, reduce the output voltage ripple, and improve the power density of the transformer.

[0017] To solve the above technical problems, the technical solution adopted by the present invention is:

[0018] A hybrid analog-digital converter circuit includes a power supply and a digital converter connected to the power supply. An analog converter is connected between the input end and the output end of the digital converter, and the analog converter is connected to a load component;

[0019] The digital converter includes an element multiplexer connected to the input end and the output end of the power supply through wires. The element multiplexer includes a plurality of power supply capacitors arranged in series. The analog converter includes the element multiplexer, and both ends of each power supply capacitor in the element multiplexer are respectively connected to the input end and the output end of the load component through discharge wires, and at least one discharge wire is provided with a discharge switch; when the load component works, it is connected to each power supply capacitor in turn by closing the corresponding discharge switch.

[0020] As a preferred solution, among them, the load component is equivalently a parallel-connected load capacitor C L and a load resistor R L and a load inductor L connected in series with the parallel combination of the two;

[0021] When a part of the equivalent capacitance C of the load component L is given, the minimum capacitance value C of the power supply capacitor 1 , C 2 , … C N is equal to the DC bus capacitance value C bus , and is calculated by the following formula: where N is the number of power supply capacitors, I o is the output current on the partial equivalent resistance R of the load component L ; V o is the output voltage on the partial equivalent resistance R of the load component L ; ΔVo is the equivalent resistance R of the load component part L output voltage ripple on; f sw is the switching frequency;

[0022] When the equivalent capacitance C of the load component part L is not defined, the minimum capacitance value C of the power supply capacitor 1 , C 2 , … C N is equal to the DC bus capacitance value C bus , and is calculated by the following formula: Let NC bus = C L , and we get: where N is the number of power supply capacitors, I o is the output current on the equivalent resistance R of the load component part L ; V o is the output voltage on the equivalent resistance R of the load component part L ; ΔV o output voltage ripple on the equivalent resistance R of the load component part L ; f sw switching frequency.

[0023] As a preferred solution, the charging time and discharging time of each of the power supply capacitors are both the circuit switching period T sw / the number of power supply capacitors N.

[0024] The beneficial effects of the present invention are as follows:

[0025] In the circuit disclosed by the present invention, the load draws energy from the power supply capacitors one by one. Therefore, the voltage across the load always remains between the voltages of the selected capacitors, can remain stable, and will not suddenly have the severe voltage fluctuations (from 0 to E) in traditional digital converters;

[0026] In addition, the charging circuit and the discharging circuit are independent circuits. Therefore, even without advanced control technology or high-bandwidth control, the ripple power will be forced to transfer to the capacitors on the DC bus instead of directly supplying the load;

[0027] By selecting a specific digital converter and the connection method of the DC bus capacitor, different types of hybrid analog-digital converter circuits can be obtained in this circuit, and the most suitable solution can be selected for specific problems.

[0028] This hybrid analog-digital converter circuit can effectively reduce the ripple voltage on the load, and the larger the switching frequency, the more obvious this phenomenon is. Furthermore, it can reduce the low-pass filter and improve the power density.

[0029] Since the power supply voltage, current of the hybrid analog-to-digital converter circuit including the component multiplexer and the voltage and current of the load do not have square waves, the ripple is very small, only a very small low-pass filter is required, which can effectively improve the power density. Moreover, the power supply current is not in a square wave or square-wave-like mode, the electromagnetic interference is small, and the maximum required current will decrease.

[0030] The circuit described in this patent discloses the L and C that minimize the overall volume of the circuit. L ,C bus The minimum limit values of, if the actual use value is greater than the minimum limit value, the output ripple is smaller and the quality is higher.

[0031] And when C L is unknown, with the aim of minimizing the overall volume of the capacitors. The overall volume of the total capacitors is determined by the total capacitance value (i.e., NC bus +C L ). Because for the product of two parameters (i.e., NC bus and C L ) being constant, then the sum of the parameters (i.e., NC bus +C L ) has a minimum value, which is obtained when and only when these two parameters are equal to each other. Since the overall volume of the capacitors is proportional to the total capacitance value of the capacitors (i.e., NC bus +C L ), so when NC bus =C L , the overall volume is the smallest. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is the circuit diagram of the hybrid analog-to-digital converter circuit according to Embodiment 1 of the present invention;

[0033] Figure 2 is the circuit diagram of the buck converter and the parallel DC capacitor according to Embodiment 2 of the present invention;

[0034] Figure 3 is the waveform diagram of the buck converter and the parallel DC capacitor according to Embodiment 2 of the present invention;

[0035] Figure 4 is the graph obtained from the simulation experiment of the comparison of the output ripple sizes between the hybrid analog-to-digital converter and the discontinuous conduction buck converter circuit according to Embodiment 2 of the present invention;

[0036] Figure 5 is the circuit diagram of the N:1 voltage divider and the series capacitor according to Embodiment 4 of the present invention;

[0037] Figure 6 is the equivalent circuit diagram of the N:1 voltage divider and the series capacitor according to Embodiment 4 of the present invention;

[0038] Figure 7 It is the waveform diagram of the N:1 voltage divider and the series capacitor for Embodiment 4 of the present invention. Detailed implementation manners

[0039] The following will describe in detail the specific implementation manners of the present invention with reference to the accompanying drawings.

[0040] Embodiment 1 is as Figure 1 shown. A hybrid analog-to-digital converter circuit includes a power supply and a digital converter connected to the power supply. An analog converter is connected between the input end and the output end of the digital converter, and the analog converter is connected to a load component;

[0041] The analog converter includes a plurality of power supply capacitors. Both ends of each power supply capacitor are respectively connected to the input end and the output end of the digital converter through charging wires, and charging switches are provided on two of the charging wires; both ends of each power supply capacitor are respectively connected to the input end and the output end of the load component through discharging wires, and discharging switches are provided on two of the discharging wires; when the load component is working, it is connected to each power supply capacitor in turn by closing the corresponding discharging switch, and the power supply capacitor not in a connected state with the load component is connected to the digital converter in turn by closing the corresponding charging switch. The charging time and the discharging time of each power supply capacitor are both the circuit switching period T sw / the number of power supply capacitors N.

[0042] Among them, the load component is equivalent to a load capacitor C L and a load resistor R L connected in parallel, and a load inductor L connected in series with the two in parallel;

[0043] When a part of the equivalent capacitance C L of the load component is given, the minimum capacitance value C 1 , C 2 ,... C N of the power supply capacitor is equal to the DC bus capacitance value C bus , and is calculated by the following formula: where I o is the output current on the partial equivalent resistor R L of the load component; V o is the output voltage on the partial equivalent resistor R L of the load component; ΔV o is the upper limit value given for the output voltage ripple on the partial equivalent resistor R L of the load component; f sw is the circuit switching frequency; L is the partial equivalent inductor of the load component;

[0044] When the partial equivalent capacitance C L of the load component is not limited, the minimum capacitance value C of the power supply capacitor1 , C 2 , …C N is equal to the DC bus capacitance value C bus . It is calculated by the following formula: Let NC bus = C L , and the required minimum C L is obtained as follows: where N is the number of supply capacitors, and I o is the output current on the equivalent resistance R L of the load component part; V o is the output voltage on the equivalent resistance R L of the load component part; ΔV o is the upper limit value given for the output voltage ripple on the equivalent resistance R L of the load component part; f sw is the circuit switching frequency; L is the equivalent inductance of the load component part.

[0045] Embodiment 2. As shown in the appendix Figure 2 : A hybrid analog-to-digital converter circuit includes a power supply and a digital converter connected to the power supply. The digital converter uses a buck converter. An analog converter is connected between the input terminal and the output terminal of the digital converter, and the analog converter is connected to a load component;

[0046] The analog converter includes a plurality of supply capacitors arranged in parallel. Both ends of each supply capacitor are respectively connected to the input terminal and the output terminal of the digital converter through charging wires, and a charging switch is provided on one of the charging wires; both ends of each supply capacitor are respectively connected to the input terminal and the output terminal of the load component through discharging wires, and a discharging switch is provided on one of the discharging wires; when the load component is working, it is connected to each supply capacitor in turn by closing the corresponding discharging switch, and the supply capacitors not in a connected state with the load component are connected to the digital converter in turn by closing the corresponding charging switches. The charging time and discharging time of each supply capacitor are both the circuit switching period T sw / the number of supply capacitors N.

[0047] Among them, the load component is equivalent to a load capacitor C L and a load resistor R L connected in parallel, and a load inductor L connected in series with the two in parallel;

[0048] The equivalent capacitance C L of the load component part is given, and the minimum capacitance value C 1 , C 2 , …C N is equal to the DC bus capacitance value C bus , and it is calculated by the following formula: where I ois the equivalent resistance R of the load component part L of the output current; V o is the equivalent resistance R of the load component part L of the output voltage; ΔV o is the equivalent resistance R of the load component part L of the upper limit value of the output voltage ripple given; f sw is the circuit switching frequency; L is the equivalent inductance of the load component part;

[0049] After the circuit layout form is determined, the specific working principle and the solution of the minimum capacitance value required for the power supply capacitor are as follows:

[0050] (1) In the figure, S uc1 and S uc2 are the charging switches, and S ud1 and S ud2 are the discharging switches. When C 1 is charging, C 2 is discharging;

[0051] (2) S 1 / S 2 complies with the working principle of the buck converter. When the buck converter operates in the discontinuous current mode, the modulation ratio M is equal to:

[0052]

[0053] where, V bus is the voltage of the DC bus capacitor, D is the duty cycle, R L is the equivalent resistance of the load component; E is the power supply voltage; f sw is the switching frequency; L 1 is the inductor of the buck converter;

[0054] According to the above formula (1), the duty cycle D is solved. According to the circuit switching period, the conduction states of each switch as shown in Figure 3 are obtained, where t 0 is the starting moment of the conduction of S 1 in the first circuit switching period; t 1 is the starting moment of the turn-off of S 1 in the first circuit switching period; t 2 is the starting moment of the conduction of S 1 in the second circuit switching period, corresponding to t 0 of the previous period; t 3 is the starting moment of the turn-off of S 1 in the second circuit switching period, corresponding to t 0 of the previous period;

[0055] (3) At [t0 , t 2 time period, C 1 Charging, C 2 Discharging, the equivalent circuit is as Figure 2 b.

[0056] (4) During [t 2 , t 4 time period, C 2 Charging, C 1 Discharging, the equivalent circuit is as Figure 2 c.

[0057] Because the charge-discharge loop is independent, the output voltage ripple depends on the discharge loop. This discharge loop has three energy storage devices (C bus , L, C L ). According to the state-space method of network theory, three state equations (2)-(4) can be obtained to find the general solution, and three equations (5)-(7) are used to identify the initial state.

[0058]

[0059] Among them, L 2 is the equivalent inductance of the load component part; C L is the equivalent capacitance of the load component part; C bus is the equivalent capacitance on the DC bus; I o is the output current on the equivalent resistance R L of the load component part; V o is the output voltage on the equivalent resistance R L of the load component part; ΔV o is the output voltage ripple on the equivalent resistance R L of the load component part; f sw is the switching frequency; L is the equivalent inductance of the load component part;

[0060]

[0061] Among them, I o is the output current on the equivalent resistance R L of the load component part; V o is the output voltage on the equivalent resistance R L of the load component part; T sw is the circuit switching period; L is the equivalent inductance of the load component part; The solutions of formulas (2)-(7) are as follows:

[0062]

[0063] According to the above formulas, it can be obtained that in Appendix Figure 3 v C1 and vC2 and i L 、v o waveform diagrams. As can be seen from the figures, v Cbus (the value is equal to v C1 and v C2 ) is proportional to (-t), i L and (-t 2 ) are proportional, v o (the value is equal to v CL (t)) and (-t 3 ) are proportional. These conclusions are also verified by formulas (8)-(10).

[0064] In formula (10), let the maximum and minimum values be denoted as v CL_max and V CL_min respectively, and the result is as shown in formula (11).

[0065]

[0066] Through formula (11), the ripple voltage of the load of this circuit can be obtained, denoted as ΔV o_MAD , and the result is as shown in formula (12), and this result can be verified by subsequent simulation analysis.

[0067]

[0068] When the upper limit value of the ripple voltage of the given load is ΔV o , the minimum capacitance value C 1 of the power supply capacitor can be calculated from the above formula (12), C 2 ,…C N that is, the DC bus capacitance value C bus .

[0069] Denote the ripple voltage of the discontinuous conduction buck converter circuit (DCM Buck circuit) as ΔV o_BUCK , and the result is as shown in formula (13).

[0070]

[0071] By comparing formulas (12) and (13), it can be found that the ΔV o of the hybrid analog-to-digital converter circuit described in this patent is lower, because ΔV o_MAD is proportional to , while the ripple voltage ΔV o_BUCK of the discontinuous conduction buck converter circuit (DCM Buck circuit) is proportional to 1 / f sw . In addition, the coefficient of formula (12) is smaller than that of formula (13).

[0072] The discontinuous conduction buck converter circuit (DCM Buck circuit) and the hybrid analog-to-digital converter in this embodiment have the output ripple ΔV o The comparison of the magnitudes is as shown in the graph obtained from the simulation experiment Figure 4 as follows. Among them, the parameters are as follows: P = 1000W, E = 400V, V o = 200V. In the hybrid analog-to-digital converter, L 1 = L 2 = 1μH, C 1 = C 2 = C L = 20μF; in the discontinuous conduction buck converter circuit, L total = 2μH, and C total = 60μF.

[0073] Embodiment 3 is basically the same as Embodiment 2, and the difference lies in that: the equivalent capacitance C of the load component part is not limited, and the minimum capacitance value C L of the power supply capacitor, C 1 , C 2 ,... C N is equal to the DC bus capacitance value C bus . It is calculated by the following formula: Let NC bus = C L , at this time the total volume of the capacitor is the smallest, and the required minimum C L is obtained: where N is the number of power supply capacitors, I o is the output current on the equivalent resistance R L of the load component part; V o is the output voltage on the equivalent resistance R L of the load component part; ΔV o is the upper limit value given for the output voltage ripple on the equivalent resistance R L of the load component part; f sw is the circuit switching frequency; L is the equivalent inductance of the load component part.

[0074] Embodiment 4. A hybrid analog-to-digital converter circuit, including a power supply and a digital converter connected to the power supply. An analog converter is connected between the input end and the output end of the digital converter, and the analog converter is connected to a load component;

[0075] The digital converter includes an element multiplexer connected to the input and output terminals of a power supply through wires. The element multiplexer includes N power supply capacitors arranged in series. The analog converter includes this element multiplexer, and both ends of each power supply capacitor in the element multiplexer are respectively connected to the input and output terminals of a load component through discharge wires, and at least one discharge wire is provided with a discharge switch; when the load component operates, it is connected to each power supply capacitor in turn by closing the corresponding discharge switch. The charging time and discharge time of each power supply capacitor are both the circuit switching period T sw / Number of power supply capacitors N.

[0076] Among them, the load component is equivalent to a load capacitor C connected in parallel L and a load resistor R L and a load inductor L connected in series with the two in parallel;

[0077] Part of the equivalent capacitance C of the load component L is given, and the minimum capacitance value C of the power supply capacitor 1 , C 2 , … C N is equal to the DC bus capacitance value C bus , and is calculated by the following formula: where I o is the output current on the partial equivalent resistance R of the load component L ; V o is the output voltage on the partial equivalent resistance R of the load component L ; ΔV o is the output voltage ripple on the partial equivalent resistance R of the load component L ; f sw is the circuit switching frequency; L is the partial equivalent inductance of the load component;

[0078] The circuit diagram of this hybrid analog-to-digital converter circuit is as shown in the appendix Figure 5 : Capacitors C 1 -C N are connected in series to form a voltage divider of N:1 and also serve as the capacitance of the DC bus. The equivalent circuits in different operating stages are as shown in the appendix Figure 6 and the waveforms are as shown in Figure 7 .

[0079] Similar to the hybrid analog-to-digital converter circuit based on a buck converter in Embodiment 2 above, the modulation index M and ΔV o respectively depend on the charging and discharging circuits. For a voltage divider, M = 1 / N; Figure 3 and Figure 7 The main difference is that Figure 7 the ripple frequency in is Nf sw and the discharge current of the DC bus capacitance Cbus is (I o -IS )。Therefore, ΔV in the circuit diagram of the hybrid analog-to-digital converter circuit of this embodiment o can be derived from formula (14):

[0080]

[0081] The accuracy of formula (14) can be verified through simulation analysis. Moreover, the voltage / current from the power supply and the voltage and current from the load (e.g., E, i s (t), v L (t), i L (t)) do not have square waves, as shown in Figure 7 . Therefore, the ripple power is very small, and only a very small low-pass filter is required.

[0082] Embodiment 5 is basically the same as Embodiment 4, with the difference being that: the equivalent capacitance C of the load component part L is not limited, and the minimum capacitance value C of the power supply capacitance 1 , C 2 ,... C N is equal to the DC bus capacitance value C bus。 which is calculated by the following formula: Let NC bus = C L , the total capacitance volume is the smallest, and the required minimum C L is obtained as:

[0083] where N is the number of power supply capacitances, I o is the output current on the equivalent resistance R L of the load component part; V o is the output voltage on the equivalent resistance R L of the load component part; ΔV o is the output voltage ripple on the equivalent resistance R L of the load component part; f sw is the circuit switching frequency.

[0084] The above embodiments only illustratively explain the principles and effects of the present invention and some applied embodiments, rather than limiting the present invention; it should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention.

Claims

1. A hybrid analog-to-digital converter circuit, characterized in that: it includes a power supply and a digital converter connected to the power supply. An analog converter is connected between the input end and the output end of the digital converter, and the analog converter is connected to a load component; the analog converter includes a plurality of power supply capacitors. Both ends of each power supply capacitor are respectively connected to the input end and the output end of the digital converter through charging wires, and at least one charging wire is provided with a charging switch; both ends of each power supply capacitor are respectively connected to the input end and the output end of the load component through discharging wires, and at least one discharging wire is provided with a discharging switch; when the load component works, it is connected to each power supply capacitor in turn by closing the corresponding discharging switch, and the power supply capacitors not in connection with the load component are connected to the digital converter in turn by closing the corresponding charging switches; Among them, the load component is equivalent to a load capacitor C connected in parallel L and a load resistor R L and a load inductor L connected in series with the two after parallel connection; When the equivalent capacitance C of the load component part L is given, the minimum capacitance value C of the power supply capacitor 1 , C 2 , … C N is equal to the DC bus capacitance value C bus , and is calculated by the following formula: where I o is the output current on the equivalent resistance R of the load component part L ; V o is the output voltage on the equivalent resistance R of the load component part L ; ΔV o is the upper limit value given by the output voltage ripple on the equivalent resistance R of the load component part L ; f sw is the circuit switching frequency; When the equivalent capacitance C of the load component part L is not defined, the minimum capacitance value C of the power supply capacitor 1 , C 2 , … C N is equal to the DC bus capacitance value Cbus; it is calculated by the following formula: Let NC bus = C L , and the required minimum C L is obtained as follows: where N is the number of power supply capacitors, I o is the output current on the equivalent resistance R L of the load component part; V o is the output voltage on the equivalent resistance R L of the load component part; ΔV o is the upper limit value given for the output voltage ripple on the equivalent resistance R L of the load component part; f sw is the circuit switching frequency.

2. The hybrid analog-to-digital converter circuit according to claim 1, characterized in that: the digital converter is a DC / DC converter.

3. The hybrid analog-to-digital converter circuit according to claim 2, characterized in that: the digital converter is a buck converter or a boost converter or a resonant converter.

4. The hybrid analog-to-digital converter circuit according to any one of claims 1-3, characterized in that: the charging time and the discharging time of each power supply capacitor are both the circuit switching period Tsw divided by the number of power supply capacitors N.

5. A hybrid analog-to-digital converter circuit, characterized in that: it includes a power supply and a digital converter connected to the power supply. An analog converter is connected between the input end and the output end of the digital converter, and the analog converter is connected to a load component; the digital converter includes an element multiplexer connected to the input end and the output end of the power supply through wires. The element multiplexer includes a plurality of power supply capacitors arranged in series. The analog converter includes the element multiplexer, and both ends of each power supply capacitor in the element multiplexer are respectively connected to the input end and the output end of the load component through discharging wires, and at least one discharging wire is provided with a discharging switch; when the load component works, it is connected to each power supply capacitor in turn by closing the corresponding discharging switch.

6. The hybrid analog-to-digital converter circuit according to claim 5, characterized in that: wherein, The load component is equivalent to a load capacitor C connected in parallel L and a load resistor R L and a load inductor L connected in series with the two after parallel connection; When the equivalent capacitance C of the load component part L is given, the minimum capacitance value C of the power supply capacitor 1 , C 2 , … C N is equal to the DC bus capacitance value C bus , and is calculated by the following formula: where N is the number of power supply capacitors, I o is the output current on the equivalent resistance R of the load component part L ; V o is the output voltage on the equivalent resistance R of the load component part L ; ΔV o is the upper limit value given by the output voltage ripple on the equivalent resistance R of the load component part L ; f sw is the switching frequency; When the equivalent capacitance C of the load component part L is not defined, the minimum capacitance value C of the power supply capacitor 1 , C 2 , … C N is equal to the DC bus capacitance value C bus , and is calculated by the following formula: Let NC bus = C L , and we get: where N is the number of power supply capacitors, I o is the output current on the equivalent resistance R L of the load component part; V o is the output voltage on the equivalent resistance R L of the load component part; ΔV o is the upper limit value given by the output voltage ripple on the equivalent resistance R L of the load component part; f sw is the switching frequency.

7. The hybrid analog-to-digital converter circuit according to claim 6, characterized in that: The charging time and discharging time of each power supply capacitor are both the circuit switching period T sw / The number of power supply capacitors N.

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