A circuit for controlling voltage ripple

Abstract

The present invention provides a circuit for controlling voltage ripple, the circuit comprising: a clock-triggered charge pump module, a first NMOS tube, a second NMOS tube, a comparison voltage module, a stable gate voltage module, a control switch signal module and a load module, the output end of the clock-triggered charge pump module is respectively connected to the gate of the first NMOS tube, the drain of the first NMOS tube, the drain of the second NMOS tube, the input end of the stable gate voltage module and the load module, the source of the first NMOS tube is connected to the comparison voltage module, the comparison voltage module is connected to the input end of the clock-triggered charge pump module, the gate of the second NMOS tube is connected to the output end of the stable gate voltage module, and the control switch signal module is respectively connected to the clock-triggered charge pump module and the stable gate voltage module. In the circuit provided by the present invention, the gate capacitor provides a stable gate voltage for the gate of the second NMOS tube, thereby obtaining a stable working voltage with suppressed voltage ripple.

Description

Technical Field

[0001] The invention relates to the field of non-volatile memory, in particular to a circuit for controlling voltage ripple. Background Art

[0002] Currently, non-volatile memories are basically provided with a working voltage that meets the operating requirements by a charge pump. The charge pump is a switched capacitor voltage converter, which is a DC converter that uses so-called "fast" or "pumping" capacitors instead of inductors or transformers to store energy. It can increase or decrease the input power supply voltage and can also be used to generate negative voltages. The internal MOS switch array controls the charging and discharging of fast capacitors in a certain way, so that the input voltage is multiplied or reduced by a certain factor (1 / 2, 2 or 3) to obtain the required output voltage. However, using a charge pump to provide voltage for non-volatile memories is prone to generate a large amount of voltage ripple.

[0003] The charge pump circuit of the existing non-volatile memory is shown in the accompanying drawings of the specification. Figure 1The working principle is as follows: the voltage at the "+" end of the two input ends of the voltage comparator (12) is a preset reference voltage VREF, and the voltage at the "-" end is a comparison voltage generated after the output voltage of the charge pump 10 is divided by the resistor R1 (13). The resistor R2 (14) and the resistor R1 (13) are connected in series to provide a comparison voltage for the "-" end of the voltage comparator. When the charge pump circuit starts to work, the comparison voltage value is less than the VREF voltage value. According to the function of the voltage comparator (12), its output end outputs a high-level signal, which is given to the clock circuit (11), triggering the clock circuit (11) to output a square wave signal to the charge pump (10). The charge pump (10) starts to work and generates an output voltage VOUT, which gradually increases. VOUT is provided to the load (15) for use through the filtering and stabilizing capacitor C1 (16). According to the characteristics of the charge pump (10), the voltage generated by it may be higher than the voltage required for the load (15) to work. When VOUT When the voltage rises to the voltage required for the load (15) to work, or is higher than the voltage required for work, at this time, the comparison voltage generated by the voltage division of the resistor R1 (13) is higher than the VREF voltage value, then the output end of the voltage comparator (12) outputs a low-level signal, and the low-level signal is given to the clock circuit (11), the clock circuit (11) stops the circuit, outputs a low level to the charge pump (10), the charge pump (10) stops working, and the VOUT voltage starts to drop. When the VOUT voltage drops so that the comparison voltage generated by the voltage division of the resistor R1 (13) is lower than the VREF voltage value, the output end of the voltage comparator (12) outputs a high-level signal again, and the high-level signal is given to the clock circuit (11) as a trigger signal of the clock circuit (11), triggering the clock circuit (11) to output a square wave signal to the charge pump (10), and the charge pump (10) starts working again, thus repeating periodically. This is the working principle of the existing non-volatile memory charge pump circuit, as shown in FIG. Figure 2 The waveform of VOUT when the conventional charge pump is working is shown, wherein the ideal required VOUT should be in the form of a black solid line shown by vtarget, while the actual VOUT is in the state shown by a dotted line, having a relatively large ripple.

[0004] Even the best reference voltage source device has ripples in its output voltage. Voltage ripple reduces the efficiency of the power supply. Strong ripples will cause surge voltage or current, resulting in burning of electrical equipment. They will also interfere with the logical relationship of digital circuits and affect the normal operation of digital circuits. The existing methods for suppressing voltage ripples are generally to increase the capacitance of the filter circuit as much as possible, or to use a voltage stabilizing circuit with good effect. In places where ripple suppression is required, analog voltage stabilizing power supplies are used instead of switching power supplies. However, when the above methods are applied to non-volatile memory, they will result in relatively high costs. In addition, the above methods require relatively more electrical components and occupy a relatively large volume, which does not conform to the trend of miniaturization of non-volatile memory. Summary of the invention

[0005] In view of the above problems, the present invention provides a circuit for controlling voltage ripple, which suppresses the voltage ripple generated by the charge pump of the non-volatile memory in the prior art and provides a more stable operating voltage for the non-volatile memory compared with the prior art.

[0006] An embodiment of the present invention provides a circuit for controlling voltage ripple, the circuit comprising:

[0007] A clock-triggered charge pump module, a first NMOS tube, a second NMOS tube, a comparison voltage module, a gate voltage stabilization module, a control switch signal module, and a load module;

[0008] The output end of the clock-triggered charge pump module is respectively connected to the gate of the first NMOS tube, the drain of the first NMOS tube, the drain of the second NMOS tube, the input end of the gate voltage stabilization module and the load module, so as to provide a working voltage for the load;

[0009] The source of the first NMOS tube is connected to the comparison voltage module;

[0010] The comparison voltage module is connected to the input end of the clock-triggered charge pump module and is used to generate a comparison voltage;

[0011] The gate of the second NMOS tube is connected to the output end of the stable gate voltage module, and the stable gate voltage module is used to generate a stable gate voltage for the gate of the second NMOS tube;

[0012] The source of the second NMOS tube is connected to the load module, and the source voltage of the second NMOS tube is a stable load operating voltage;

[0013] The control switch signal module is connected to the clock-triggered charge pump module and the stable gate voltage module respectively, and is used to generate a level signal for controlling the PMOS tube in the stable gate voltage module.

[0014] Optionally, the clock-triggered charge pump module includes: a voltage comparator, a clock circuit and a charge pump;

[0015] The voltage comparator comprises a reference voltage connection terminal, a comparison voltage connection terminal and an output terminal;

[0016] The reference voltage connection terminal is connected to the reference voltage, the comparison voltage connection terminal is connected to the comparison voltage module, and the voltage comparator output terminal is respectively connected to the clock circuit input terminal and the control switch signal module input terminal, for providing a trigger signal for the clock circuit and the control switch signal module;

[0017] The output end of the clock circuit is connected to the input end of the charge pump, so as to provide a clock signal for the charge pump;

[0018] The charge pump output end is the clock-triggered charge pump module output end.

[0019] Optionally, the comparison voltage module includes a plurality of series resistors;

[0020] One end of the first resistor among the multiple series resistors is connected to the source of the first NMOS tube, and the other end is respectively connected to the comparison voltage connection end of the voltage comparator and the second resistor. The other end of the second resistor is connected to one end of any resistor among the multiple series resistors except the first and second resistors.

[0021] Optionally, the gate voltage stabilization module comprises: a PMOS tube and a gate capacitor;

[0022] The source of the PMOS tube is connected to the output end of the clock-triggered charge pump module;

[0023] The PMOS tube gate is connected to the output end of the control switch signal module;

[0024] The drain of the PMOS tube is respectively connected to one end of the gate capacitor and the gate of the second NMOS tube, so as to connect the circuit and charge the gate capacitor when the PMOS tube is turned on;

[0025] The other end of the gate capacitor is grounded, and is used to provide a stable gate voltage for the gate of the second NMOS tube when the PMOS tube is turned off.

[0026] Optionally, the circuit for controlling voltage ripple is applied to a memory, and the memory further comprises a control module;

[0027] The control module is connected to the control switch signal module, and the control module is used to send an enable signal to the control switch signal module, and the enable signal is used to control the control switch signal module to generate a level signal for controlling the PMOS tube in the stable gate voltage module.

[0028] Optionally, the control switch signal module includes: a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, a first inverter and a second inverter;

[0029] The two input signals of the first NAND gate are the enable signal and the voltage comparator output signal respectively, and the voltage comparator output signal is also the input signal of the second inverter;

[0030] The output terminal of the first NAND gate is connected to an input terminal of the second NAND gate;

[0031] The output terminal of the second NAND gate is connected to an input terminal of the third NAND gate;

[0032] The output end of the third NAND gate is respectively connected to the input end of the first inverter and the other input end of the second NAND gate;

[0033] The output end of the first inverter is respectively connected to an input end of the seventh NAND gate and an input end of the fourth NAND gate;

[0034] The output terminal of the second inverter is connected to another input terminal of the fourth NAND gate;

[0035] The output terminal of the fourth NAND gate is connected to an input terminal of the fifth NAND gate;

[0036] The output terminal of the fifth NAND gate is connected to an input terminal of the sixth NAND gate;

[0037] The output end of the sixth NAND gate is respectively connected to another input end of the seventh NAND gate and another input end of the fifth NAND gate;

[0038] Another input terminal signal of the third NAND gate is the enable signal;

[0039] Another input terminal signal of the sixth NAND gate is the enable signal;

[0040] The output end of the seventh NAND gate is connected to the gate of the PMOS tube, and the output end of the seventh NAND gate is the output end of the control switch signal module.

[0041] Optionally, the load module includes: a load and a filter capacitor;

[0042] The load is connected to the source of the second NMOS tube, and the source voltage of the second NMOS tube provides an operating voltage for the load;

[0043] The filter capacitor is connected to the drain of the second NMOS tube and is used to filter the operating voltage to stabilize the operating voltage.

[0044] Optionally, during the high-level period of the enable signal, when the output terminal of the voltage comparator outputs a first high-level signal, the output terminal of the seventh NAND gate outputs a low-level signal, and the holding time of the low-level signal is equal to the duration period of the first high-level signal;

[0045] When the output terminal of the voltage comparator outputs a first low level signal, the output terminal of the seventh NAND gate outputs a high level signal.

[0046] Optionally, when the output end of the seventh NAND gate outputs a low level signal, the PMOS tube is turned on, and when the output end of the seventh NAND gate outputs a high level signal, the PMOS tube is turned off.

[0047] Compared with the prior art, the present invention provides a circuit for controlling voltage ripple. When the charge pump of the non-volatile memory starts to be established, the PMOS tube is turned on to charge the gate capacitor. After the voltage value reaches the working voltage required by the load, the PMOS tube is turned off, and the gate capacitor provides a stable gate voltage for the gate of the second NMOS tube, thereby obtaining a stable working voltage with suppressed voltage ripple. This circuit has a simple structure, uses relatively few electrical components, and does not increase the volume of the non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0049] Figure 1 is the circuit diagram of the existing charge pump;

[0050] Figure 2 is a waveform diagram of the output voltage of the existing charge pump;

[0051] Figure 3 It is a module schematic diagram of a voltage ripple control circuit of the present invention;

[0052] Figure 4 It is a control voltage ripple circuit diagram of the present invention;

[0053] Figure 5 is a timing diagram of one of the modules of the present invention;

[0054] Figure 6 The present invention discloses an output voltage waveform diagram of a voltage ripple control circuit. DETAILED DESCRIPTION

[0055] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, are only part of the embodiments of the present invention, not all of the embodiments, and are not used to limit the present invention.

[0056] Reference Figure 3, shows a module schematic diagram of a control voltage ripple circuit, which may specifically include:

[0057] The clock-triggered charge pump module 20 , the first NMOS transistor 30 , the second NMOS transistor 40 , the voltage comparison module 50 , the gate voltage stabilization module 60 , the switch signal control module 70 and the load module 80 .

[0058] The output end of the clock-triggered charge pump module 20 is respectively connected to the gate of the first NMOS tube 30, the drain of the first NMOS tube 30, the drain of the second NMOS tube 40, the input end of the stable gate voltage module 60 and the load module 80, so as to provide a working voltage for the load. The source of the first NMOS tube 30 is connected to the comparison voltage module 50, and the comparison voltage module 50 is connected to the input end of the clock-triggered charge pump module 20, so as to generate a comparison voltage. The gate of the second NMOS tube 40 is connected to the output end of the stable gate voltage module 60, and the stable gate voltage module 60 is used to generate a stable gate voltage for the gate of the second NMOS tube 40. The source of the second NMOS tube 40 is connected to the load module 80, and the source voltage of the second NMOS tube 40 is a stable load working voltage. The control switch signal module 70 is respectively connected to the clock-triggered charge pump module 20 and the stable gate voltage module 60, so as to generate a level signal for controlling the PMOS tube in the stable gate voltage module 60.

[0059] Optionally, refer to Figure 4 The clock-triggered charge pump module 20 in the circuit of the present invention includes: a voltage comparator 201 , a clock circuit 202 and a charge pump 203 .

[0060] The voltage comparator 201 includes a reference voltage connection terminal, a comparison voltage connection terminal and an output terminal. The reference voltage connection terminal is connected to the reference voltage VREF, and the comparison voltage connection terminal is connected to the comparison voltage module 50. The output terminal of the voltage comparator 201 is respectively connected to the input terminal of the clock circuit 202 and the input terminal of the control switch signal module 70, and is used to provide a trigger signal for the clock circuit 202 and the control switch signal module 70. When the reference voltage VREF is greater than the comparison voltage, the voltage comparator 201 outputs a high-level signal. When the reference voltage VREF is less than the comparison voltage, the voltage comparator 201 outputs a low-level signal.

[0061] The output end of the clock circuit 202 is connected to the input end of the charge pump 203 for providing a clock signal to the charge pump 203 .

[0062] The charge pump 203 can output a voltage according to the clock signal of the clock circuit 202 , and the output end of the charge pump 203 is the output end of the clock-triggered charge pump module 20 .

[0063] Optionally, refer to Figure 4The comparison voltage module 50 in the circuit of the present invention includes multiple series resistors, one end of the first resistor among the multiple series resistors is connected to the source of the first NMOS tube 30, and the other end is respectively connected to the comparison voltage connection end of the voltage comparator 201 and the second resistor, the other end of the second resistor is connected to the multiple series resistors, and the comparison voltage module 50 is used to provide a comparison voltage to the voltage comparator 201.

[0064] Optionally, refer to Figure 4 The gate voltage stabilizing module 60 in the circuit of the present invention includes: a PMOS tube 601 and a gate capacitor 602 .

[0065] The source of the PMOS tube 601 is connected to the output end of the clock-triggered charge pump module 20, the gate of the PMOS tube 601 is connected to the output end of the control switch signal module 70, and the drain of the PMOS tube 601 is respectively connected to one end of the gate capacitor 602 and the gate of the second NMOS tube 40, so as to connect the circuit and charge the gate capacitor 602 when the PMOS tube is turned on.

[0066] The other end of the gate capacitor 602 is grounded, and is used to provide a stable gate voltage for the gate of the second NMOS transistor 40 when the PMOS transistor 601 is turned off.

[0067] Optionally, refer to Figure 4 The circuit of the present invention is applied to a non-volatile memory. The memory has a control module, which is connected to a control switch signal module 70. The control module is used to send an enable signal to the control switch signal module 70. The enable signal is used to enable the control switch signal module 70 to generate a level signal for controlling the PMOS tube 601 to be turned on or off.

[0068] Optionally, refer to Figure 4 The control switch signal module 70 in the circuit of the present invention includes: a first NAND gate nand1, a second NAND gate nand2, a third NAND gate nand3, a fourth NAND gate nand4, a fifth NAND gate nand5, a sixth NAND gate nand6, a seventh NAND gate nand7, a first inverter inv1 and a second inverter inv2.

[0069] The two input signals of the first NAND gate nand1 are respectively the enable signal sent by the control module and the output signal of the voltage comparator 201. The output signal of the voltage comparator 201 is also sent to the second inverter inv2. The output end of the first NAND gate nand1 is an input end of the second NAND gate nand2; the output end of the second NAND gate nand2 is an input end of the third NAND gate nand3; the output ends of the third NAND gate nand3 are respectively the input end of the first inverter inv1 and the other input end of the second NAND gate nand2; the output ends of the first inverter inv1 are respectively an input end of the seventh NAND gate nand7 and an input end of the fourth NAND gate nand4; the output end of the second inverter inv2 is the other input end of the fourth NAND gate nand4; the output end of the fourth NAND gate nand4 is an input end of the fifth NAND gate nand5; the output end of the fifth NAND gate nand5 is respectively the input end of the sixth NAND gate nand7 and the input end of the fourth NAND gate nand4. An input end of the NOT gate nand6; the output ends of the sixth NAND gate nand6 are respectively the other input ends of the seventh NAND gate nand7 and the other input end of the fifth NAND gate nand5; the other input end signal of the third NAND gate nand3 is the enable signal sent by the control module; the other input end signal of the sixth NAND gate nand6 is the enable signal sent by the control module; the output end of the seventh NAND gate nand7 is connected to the gate of the PMOS tube 601, when the output end of the seventh NAND gate nand7 outputs a low level signal, the PMOS tube 601 is turned on, and when the output end of the seventh NAND gate nand7 outputs a high level signal, the PMOS tube 601 is turned off. This part of the circuit enables the PMOS tube 601 to be turned on with the first high level signal of the voltage comparator 201 during the operation of the charge pump, and to be turned off when the first high level signal becomes a low level signal. The circuit structure is simple and practical, and the number of electrical components used is small, and the reliability is high. It should be noted that the circuit also includes an inverter inv3 as a backup, which can generate another signal. The control switch signal module in the above embodiment can also be composed of a circuit composed of other electrical components. The embodiment of the present invention does not limit it. Any circuit that can achieve the above functions falls within the protection scope of the present invention.

[0070] In summary, compared Figure 4Compared with the circuit of the prior art, the working principle of the circuit of the present invention is: when the charge pump 203 needs to work, the control module of the non-volatile memory sends an enable signal, and the enable signal is high level, that is, EN=1. The voltage of the "+" terminal of the two input terminals of the voltage comparator 201 is the preset reference voltage VREF, and the voltage of the "-" terminal is the comparison voltage generated after the output voltage of the charge pump 203 is divided by a resistor. At this time, the comparison voltage value is less than the VREF voltage value. According to the function of the voltage comparator 201, its output terminal outputs a high level signal, that is, DISPMP=1. The high level signal is simultaneously sent to the clock circuit 202, the first NAND gate nand1 and the second inverter inv2. The high level signal is used as a trigger signal of the clock circuit 202, triggering the clock circuit 202 to output a square wave signal to the charge pump 203, and the charge pump 203 starts to work, generating an output At the same time, the high-level signal generates a low-level signal through the control switch signal module 70, that is, S1W=0. At this time, the PMOS tube 601 is turned on, and the output voltage VP charges the gate capacitor 602 through the PMOS tube 601, and provides a gate voltage for the second NMOS tube 40. According to the characteristics of the MOS tube, the output voltage VP is the source voltage VP1 of the first NMOS tube 30 plus the threshold of the first NMOS tube 30, and the working voltage VOUT is the output voltage VP minus the threshold of the second NMOS tube 40. Because the threshold of the first NMOS tube 30 is equal to the threshold of the second NMOS tube 40, the working voltage VOUT is equal to the source voltage VP1 of the first NMOS tube 30, that is, the value of the working voltage VOUT is provided to the "-" end of the voltage comparator 201 through the source voltage VP1 of the first NMOS tube 30.According to the characteristics of the charge pump 203, the voltage generated by the charge pump 203 may be higher than the voltage required for the load 801 to work. When the VOUT voltage rises to the voltage required for the load 801 to work, or is higher than the voltage required for work, the comparison voltage generated by the resistor voltage divider is higher than the VREF voltage value, and the output end of the voltage comparator 201 outputs a low-level signal, that is, DISPMP=0. The low-level signal is simultaneously sent to the clock circuit 202, the first NAND gate nand1 and the second inverter inv2. The low-level signal is given to the clock circuit 202, and the clock circuit 202 outputs a low-level signal to the charge pump 203. The charge pump 203 stops working, and the output voltage VP starts to decrease. At the same time, the low-level signal generates a high-level signal through the control switch signal module 70, that is, S1W=1. At this time, the PMOS tube 601 is turned off. Since the gate capacitor 602 has no discharge path, the voltage VPG generated by it is a stable voltage value, and because the capacitor The voltage loss generated by the second NMOS tube 40 is basically negligible. According to the characteristics of the MOS tube, the gate voltage of the second NMOS tube 40 is stable, and the source voltage thereof is stable, so the VOUT voltage is stable, and the current required by the load is provided by VP. When the load continues to work, the VOUT voltage begins to decrease. When the VOUT voltage decreases so that the comparison voltage generated by the resistor voltage division is lower than the VREF voltage value, the output end of the voltage comparator 201 outputs a high-level signal again, that is, DISPMP=1. The high-level signal is given to the clock circuit 202, triggering the clock circuit 202 to output a square wave signal to the charge pump 203, and the charge pump 203 starts to work again to generate an output voltage VP. Because the gate voltage of the second NMOS tube 40 is always provided by VPG generated by the gate capacitor 602, the VOUT voltage is relatively stable, and the voltage ripple is suppressed to the greatest extent. The above process is repeated periodically to obtain a load working voltage VOUT with a well-suppressed voltage ripple.

[0071] Optionally, refer to Figure 5, shows a timing diagram of the circuit control switch signal module 70 of the present invention when it is working. It can be seen from the timing diagram that when the charge pump 203 is working, the control module of the non-volatile memory sends an enable signal, which is a high level, that is, EN=1. When the charge pump starts to work, the comparison voltage value is less than the VREF voltage value. According to the function of the voltage comparator 201, its output terminal outputs a high level signal, that is, DISPMP=1. The high level signal generates a low level signal through the control switch signal module 70, that is, S1W=0. At this time, the PMOS tube 601 is turned on. When the VOUT voltage rises to the voltage required for the load 801 to work, or is higher than the voltage required for the work, the comparison voltage generated by the resistor voltage division is higher than the VREF voltage value, and the output terminal of the voltage comparator 201 outputs a low level signal, that is, DISPMP=0. The low level signal generates a high level signal through the control switch signal module 70, that is, S1W=1. At this time, the PMOS tube 601 is turned off.

[0072] Optionally, refer to Figure 6 , shows the waveform of the circuit of the present invention, wherein VP1 is the voltage with ripples output by the charge pump 203, and VPG is the stable voltage generated by the gate capacitor 602. It can be seen that the obtained VOUT value is a stable voltage with basically no voltage ripples.

[0073] The gate voltage stabilization module 60 and the switch signal control module 70 used in the embodiment of the present invention have a simple overall circuit structure and use fewer electrical components, which makes the circuit more reliable. At the same time, the load operating voltage is controlled to be stable with less ripple, which effectively suppresses voltage ripple.

[0074] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0075] The above is a detailed introduction to a circuit for controlling voltage ripple provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A circuit for controlling voltage ripple, characterized in that: The circuit comprises: A clock-triggered charge pump module, a first NMOS tube, a second NMOS tube, a comparison voltage module, a gate voltage stabilization module, a control switch signal module, and a load module; The output end of the clock-triggered charge pump module is respectively connected to the gate of the first NMOS tube, the drain of the first NMOS tube, the drain of the second NMOS tube, the input end of the stable gate voltage module and the load module, so as to provide a working voltage for the load; The source of the first NMOS tube is connected to the comparison voltage module; The comparison voltage module is connected to the input end of the clock-triggered charge pump module and is used to generate a comparison voltage; The gate of the second NMOS tube is connected to the output end of the stable gate voltage module, and the stable gate voltage module is used to generate a stable gate voltage for the gate of the second NMOS tube; The source of the second NMOS tube is connected to the load module, and the source voltage of the second NMOS tube is a stable load operating voltage; The control switch signal module is connected to the clock-triggered charge pump module and the stable gate voltage module respectively, and is used to generate a level signal for controlling the PMOS tube in the stable gate voltage module; The clock-triggered charge pump module includes: a voltage comparator, a clock circuit and a charge pump; The voltage comparator comprises a reference voltage connection terminal, a comparison voltage connection terminal and an output terminal; The reference voltage connection terminal is connected to the reference voltage, the comparison voltage connection terminal is connected to the comparison voltage module, and the voltage comparator output terminal is respectively connected to the clock circuit input terminal and the control switch signal module input terminal, for providing a trigger signal for the clock circuit and the control switch signal module; The output end of the clock circuit is connected to the input end of the charge pump, so as to provide a clock signal for the charge pump; The charge pump output end is the clock-triggered charge pump module output end; The circuit for controlling voltage ripple is applied to a memory, and the memory further comprises a control module; The control module is connected to the control switch signal module, and the control module is used to send an enable signal to the control switch signal module, and the enable signal is used to control the control switch signal module to generate a level signal for controlling the PMOS tube in the stable gate voltage module.

2. The circuit according to claim 1, characterized in that The comparison voltage module includes a plurality of series resistors; One end of the first resistor among the multiple series resistors is connected to the source of the first NMOS tube, and the other end is respectively connected to the comparison voltage connection end of the voltage comparator and the second resistor. The other end of the second resistor is connected to one end of any resistor among the multiple series resistors except the first and second resistors.

3. The circuit according to claim 1, characterized in that The gate voltage stabilization module comprises: a PMOS tube and a gate capacitor; The source of the PMOS tube is connected to the output end of the clock-triggered charge pump module; The PMOS tube gate is connected to the output end of the control switch signal module; The drain of the PMOS tube is respectively connected to one end of the gate capacitor and the gate of the second NMOS tube, so as to connect the circuit and charge the gate capacitor when the PMOS tube is turned on; The other end of the gate capacitor is grounded, and is used to provide a stable gate voltage for the gate of the second NMOS tube when the PMOS tube is turned off.

4. The circuit according to claim 1, characterized in that The control switch signal module includes: a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, a first inverter and a second inverter; The two input signals of the first NAND gate are the enable signal and the voltage comparator output signal respectively, and the voltage comparator output signal is also the input signal of the second inverter; The output terminal of the first NAND gate is connected to an input terminal of the second NAND gate; The output terminal of the second NAND gate is connected to an input terminal of the third NAND gate; The output end of the third NAND gate is respectively connected to the input end of the first inverter and the other input end of the second NAND gate; The output end of the first inverter is respectively connected to an input end of the seventh NAND gate and an input end of the fourth NAND gate; The output terminal of the second inverter is connected to another input terminal of the fourth NAND gate; The output terminal of the fourth NAND gate is connected to an input terminal of the fifth NAND gate; The output terminal of the fifth NAND gate is connected to an input terminal of the sixth NAND gate; The output end of the sixth NAND gate is respectively connected to another input end of the seventh NAND gate and another input end of the fifth NAND gate; Another input terminal signal of the third NAND gate is the enable signal; Another input terminal signal of the sixth NAND gate is the enable signal; The output end of the seventh NAND gate is connected to the gate of the PMOS tube, and the output end of the seventh NAND gate is the output end of the control switch signal module.

5. The circuit according to claim 1, characterized in that The load module includes: a load and a filter capacitor; The load is connected to the source of the second NMOS tube, and the source voltage of the second NMOS tube provides an operating voltage for the load; The filter capacitor is connected to the drain of the second NMOS tube and is used to filter the operating voltage to stabilize the operating voltage.

6. The circuit according to claim 4, characterized in that During the high-level period of the enable signal, when the output terminal of the voltage comparator outputs a first high-level signal, the output terminal of the seventh NAND gate outputs a low-level signal, and the holding time of the low-level signal is equal to the duration period of the first high-level signal; When the output terminal of the voltage comparator outputs a first low level signal, the output terminal of the seventh NAND gate outputs a high level signal.

7. The circuit according to claim 4, characterized in that When the output end of the seventh NAND gate outputs a low level signal, the PMOS tube is turned on, and when the output end of the seventh NAND gate outputs a high level signal, the PMOS tube is turned off.

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