Semiconductor package and method of manufacturing semiconductor package

Abstract

In a method for manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices spaced apart from the first semiconductor device are stacked on the package substrate, with the electrostatic discharge structure interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0162037 filed on December 14, 2018 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Apparatuses and methods according to one or more exemplary embodiments relate to a semiconductor package and a method of manufacturing the semiconductor package, and more particularly, to a semiconductor package including a plurality of semiconductor chips stacked in one package and a method of manufacturing the semiconductor package. Background Art

[0004] During the manufacture of semiconductor packages, a die attach process may be performed to adhere multiple semiconductor chips to a printed circuit board. During the die attach process, when the adhesive film is peeled off from the underlying base film, a high static charge may be generated. In the related art, an ion generator may be used to remove the generated static charge. However, it may be difficult to manage the ion generator and the ability to remove the static charge may be insufficient, resulting in damage to the logic chip. Summary of the invention

[0005] Aspects of one or more exemplary embodiments provide a method of manufacturing a semiconductor package capable of improving a yield rate and maximizing productivity, and a semiconductor package manufactured by the method.

[0006] According to one aspect of an exemplary embodiment, a method for manufacturing a semiconductor package is provided, the method comprising: arranging a first semiconductor device on a packaging substrate; forming an electrostatic discharge structure on a ground substrate pad exposed from an upper surface of the packaging substrate; stacking a plurality of second semiconductor devices spaced apart from the first semiconductor device on the packaging substrate, with the electrostatic discharge structure interposed between the first semiconductor device and the plurality of second semiconductor devices; and forming a molding member on the packaging substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

[0007] According to an aspect of another exemplary embodiment, a method for manufacturing a semiconductor package is provided, the method comprising: providing a packaging substrate having a ground substrate pad on an upper surface thereof; arranging a first semiconductor device on the packaging substrate; performing a wire bonding process to electrically connect the first semiconductor device to the packaging substrate; forming an electrostatic discharge structure on the ground substrate pad during the wire bonding process; stacking a plurality of second semiconductor devices spaced apart from the first semiconductor device on the packaging substrate, with the electrostatic discharge structure interposed between the first semiconductor device and the plurality of second semiconductor devices; and forming a molding member on the packaging substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

[0008] According to an aspect of another exemplary embodiment, a semiconductor package is provided, comprising: a packaging substrate; a first semiconductor device arranged on the packaging substrate; a plurality of second semiconductor devices on the packaging substrate spaced apart from the first semiconductor device; an electrostatic discharge structure disposed on a ground substrate pad exposed from an upper surface of the packaging substrate between the first semiconductor device and the plurality of second semiconductor devices; and a molding component on the packaging substrate covering the first semiconductor device and the plurality of second semiconductor devices.

[0009] According to one aspect of another exemplary embodiment, a semiconductor package is provided, comprising: a packaging substrate; a first semiconductor device arranged on the packaging substrate; a plurality of second semiconductor devices on the packaging substrate spaced apart from the first semiconductor device; and an electrostatic discharge structure, arranged on a ground substrate pad exposed from the upper surface of the packaging substrate between the first semiconductor device and the plurality of second semiconductor devices, or arranged on a ground chip pad exposed from the upper surface of the first semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] One or more exemplary embodiments will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment;

[0012] Figure 2 is a plan view showing a semiconductor package according to an exemplary embodiment;

[0013] Figure 3 yes Figure 1 An enlarged cross-sectional view of the portion "A" of FIG.

[0014] Figures 4 to 13 is a view showing a method of manufacturing a semiconductor package according to one or more exemplary embodiments;

[0015] Fig.14 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment;

[0016] Fig.15 It is shown Fig.14 An enlarged cross-sectional view of portion "B" of FIG.

[0017] Fig.16 and Fig.17 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more exemplary embodiments;

[0018] Fig.18 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment;

[0019] Fig.19 It is shown Fig.18 an enlarged cross-sectional view of portion "C" of FIG. 1 ; and

[0020] Figure 20 to Figure 22 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more exemplary embodiments. DETAILED DESCRIPTION

[0021] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0022] Figure 1 is a cross-sectional view illustrating a semiconductor package 100 according to an exemplary embodiment. Figure 2 is a plan view showing a semiconductor package according to an exemplary embodiment. Figure 3 It is shown Figure 1 An enlarged cross-sectional view of portion "A".

[0023] refer to Figures 1 to 3 The semiconductor package 100 may include a package substrate 110 , a first semiconductor device 200 , a plurality of second semiconductor devices 300 , at least one electrostatic discharge structure 400 , and a molding member 500 . In addition, the semiconductor package 100 may further include an external connection member 600 .

[0024] The package substrate 110 may be a substrate having an upper surface 112 and a lower surface 114 opposite to each other. For example, the package substrate 110 may include a printed circuit board (PCB). The printed circuit board may include a multilayer circuit board having vias and various circuit elements therein. The package substrate 110 may include a first circuit layer 110a and a second circuit layer 110b. The package substrate 110 may include a ground plate 116 therein.

[0025] The substrate pads 120 may be arranged on the upper surface 112 of the package substrate 110. The substrate pads 120 may be connected to a plurality of wirings, respectively. The wirings may extend on the upper surface 112 of the package substrate 110 or extend within the package substrate 110. For example, at least a portion of the wirings may be used as substrate pads, such as landing pads.

[0026] At least one ground substrate pad 122 may be disposed on the upper surface 112 of the package substrate 110. The ground substrate pad 122 may be electrically connected to the ground plate 116 through the ground wiring 118. As described below, the ground substrate pad 122, the ground wiring 118, and the ground plate 116 may serve as a ground path capable of safely discharging static charge on the upper surface 112 of the substrate 110.

[0027] exist Figures 1 to 3, the number and positions of the substrate pads 120 and the ground substrate pads 122 are exemplarily shown, and it should be understood that one or more other exemplary embodiments are not limited thereto.

[0028] The first insulating layer 140 may be formed on the upper surface 112 of the package substrate 110 to cover the wiring and expose the substrate pads 120 and the ground substrate pads 122. The first insulating layer 140 may cover the entire upper surface 112 of the package substrate 110 except for the substrate pads 120 and the ground substrate pads 122. For example, the first insulating layer 140 may include a solder resist.

[0029] The first semiconductor device 200 may be mounted on the package substrate 110. The first semiconductor device 200 may be adhered to the upper surface 112 of the package substrate 110 by an adhesive member 220. For example, the adhesive member may include an adhesive film such as a direct adhesive film (DAF). The first semiconductor device 200 may include an integrated circuit. For example, the first semiconductor device 200 may be a logic chip including a logic circuit. The logic chip may be a controller for controlling a memory chip.

[0030] The first semiconductor device 200 may include a chip pad 210 on an upper surface (ie, an active surface). The chip pad 210 may include an input / output terminal used as a power pin, an input / output terminal used as a ground pin, and / or an input / output terminal used as a data pin.

[0031] The first semiconductor device 200 may be electrically connected to the package substrate 110 through the first conductive connection member 230. Specifically, the first conductive connection member 230 may electrically connect the chip pad 210 of the first semiconductor device 200 to the substrate pad 120 of the package substrate 110. For example, the first conductive connection member 230 may include a bonding wire. Therefore, the first semiconductor device 200 may be stacked on the package substrate 110 through the adhesive member 220, and may be electrically connected to the package substrate 110 through a plurality of first conductive connection members 230.

[0032] Alternatively, the first conductive connection member 230 may include a solder bump, a penetration electrode, a solder ball, a conductive paste, etc. For example, the first semiconductor device 200 may be mounted on the package substrate 110 in a flip chip bonding manner. In this case, the first semiconductor device 200 may be arranged on the package substrate 110 so that the active surface of the first semiconductor device 200 on which the chip pad 210 is formed faces the package substrate 110. The chip pad 210 of the first semiconductor device 200 may be electrically connected to the substrate pad 120 of the package substrate 110 through a conductive bump (e.g., a solder bump). In addition, a plurality of first semiconductor devices 200 may be sequentially stacked on the package substrate 110.

[0033] A plurality of second semiconductor devices 300 may be mounted on the package substrate 110. The plurality of second semiconductor devices 300 may be arranged on the package substrate 110, spaced apart from the first semiconductor device 200. The plurality of second semiconductor devices 300 may be memory chips including memory circuits. For example, the plurality of second semiconductor devices 300 may include volatile memory devices such as dynamic random access memory (DRAM), NAND flash memory, etc.

[0034] A plurality of second semiconductor devices 300a, 300b, 300c, 300d, 300e, 300f, 300g, 300h, 300i, 300j (collectively referred to as 320) may be sequentially adhered to the upper surface 112 of the package substrate 110 using adhesive members 320a, 320b, 320c, 320d, 320e, 320f, 320g, 320h, 320i, 320j. For example, the adhesive member may include an adhesive film such as a direct adhesive film (DAF).

[0035] Specifically, the second to fifth dies or semiconductor devices 300b, 300c, 300d, 300e in the plurality of second semiconductor devices 300 may be stacked in a first cascade structure. The second to fifth dies 300b, 300c, 300d, 300e may be sequentially offset and aligned in a direction toward the first semiconductor device 200 on the package substrate 110.

[0036] The seventh to tenth dies or semiconductor devices 300g, 300h, 300i, 300j of the plurality of second semiconductor devices 300 may be stacked in a second cascade structure. The seventh to tenth dies 300g, 300h, 300i, 300j may be sequentially offset aligned in a direction away from the first semiconductor device 200 on the package substrate 110.

[0037] The plurality of second semiconductor devices 300 may include chip pads 310 on the upper surface (ie, active surface). The chip pads 310 may include input / output terminals used as power pins, input / output terminals used as ground pins, and / or input / output terminals used as data pins.

[0038] The plurality of second semiconductor devices 300 may be electrically connected to the package substrate 110 through the third conductive connection member 330. Specifically, the third conductive connection member 330 may electrically connect the chip pad 310 of each of the plurality of second semiconductor devices 300 to the substrate pad 120 of the package substrate 110. For example, the third conductive connection member 330 may include a bonding wire. Therefore, the plurality of second semiconductor devices 300 may be stacked on the package substrate 110 through the adhesive member 320, and may be electrically connected to the package substrate 110 through the plurality of third conductive connection members 330.

[0039] The number, size, position, etc. of the second semiconductor devices 300 are exemplarily shown, and it should be understood that one or more other exemplary embodiments are not limited thereto.

[0040] The electrostatic discharge structure 400 may be disposed on at least one ground substrate pad 122 exposed from the upper surface 112 of the package substrate 110. The electrostatic discharge structure 400 may be disposed on the ground substrate pad 122 between the first semiconductor device 200 and the plurality of second semiconductor devices 300. The plurality of ground substrate pads 122 may be arranged along one side of the first semiconductor device 200, and the plurality of electrostatic discharge structures 400 may be disposed on the ground substrate pads 122, respectively.

[0041] For example, the electrostatic discharge structure 400 may include a metal material such as gold (Au), copper (Cu), aluminum (Al), etc. The electrostatic discharge structure 400 may be formed using a wire drawn or pulled out from a wire bonding device. The height, thickness, material, etc. of the electrostatic discharge structure 400 may be determined in consideration of the voltage level of the electrostatic charge, the size of the first semiconductor device 200 and the second semiconductor device 300, etc.

[0042] like Figure 3 As shown in , the electrostatic discharge structure 400 may include a bonding portion 410 bonded to the ground substrate pad 122 and a tip portion 420 extending from the bonding portion 410 to a predetermined height. The tip portion 420 may include a sharp top. Therefore, static electricity generated when a plurality of second semiconductor devices 300 are stacked on the package substrate 110 using an adhesive film can be safely discharged through the electrostatic discharge structure 400 and the ground path in the package substrate 110.

[0043] The molding member 500 may be formed on the package substrate 110 to protect the first semiconductor device 200 and the plurality of second semiconductor devices 300 from the surrounding environment. The molding member 500 may include epoxy molding compound (EMC).

[0044] The external connection pads 130 for providing electrical signals may be formed on the lower surface 114 of the package substrate 110. The external connection pads 130 may be exposed from the second insulating layer 150. The second insulating layer 150 may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. An external connection member 600 for electrically connecting to an external device may be provided on the external connection pads 130. For example, the external connection member 600 may include a solder ball. The semiconductor package 100 may be mounted on a module substrate via the solder balls to form a memory module.

[0045] As described above, semiconductor package 100 may include at least one ESD structure 400 disposed on ground substrate pad 122 between first semiconductor device 200 and plurality of second semiconductor devices 300. ESD structure 400 may be grounded through ground plate 116 electrically connected to ground substrate pad 122.

[0046] Therefore, the electrostatic discharge structure 400 may be arranged adjacent to the first semiconductor device 200 to prevent the first semiconductor device 200 from being damaged due to static charges generated during the die attach process of the plurality of second semiconductor devices 300. Therefore, the yield of the semiconductor package 100 may be improved and productivity may be maximized.

[0047] In the following, the manufacturing Figure 1 A method of semiconductor packaging 100 is provided.

[0048] Figures 4 to 13 1 is a view illustrating a method of manufacturing the semiconductor package 100 according to one or more exemplary embodiments.

[0049] refer to Figure 4 , a package substrate 110 having at least one ground substrate pad 122 may be provided, and a first semiconductor device 200 may be stacked or provided (eg, arranged) on the package substrate 110 .

[0050] The package substrate 110 may be a substrate having an upper surface 112 and a lower surface 114 opposite to each other. For example, the package substrate 110 may include a printed circuit board (PCB). The printed circuit board may include a multilayer circuit board having vias and various circuit elements therein. The package substrate 110 may include a first circuit layer 110a and a second circuit layer 110b, as described above with reference to Figure 3 The package substrate 110 may include a ground plate 116 .

[0051] The substrate pads 120 may be arranged on the upper surface 112 of the package substrate 110. The substrate pads 120 may be connected to a plurality of wirings, respectively. The plurality of wirings may extend on the upper surface 112 of the package substrate 110 and / or extend within the package substrate 110. For example, at least a portion of the wirings may be used as substrate pads, such as connection pads.

[0052] At least one ground substrate pad 122 may be disposed on the upper surface 112 of the package substrate 110. The at least one ground substrate pad 122 may be electrically connected to the ground plate 116 through the ground wiring 118. The at least one ground substrate pad 122, the ground wiring 118, and the ground plate 116 may serve as a ground path capable of safely discharging static charge generated on the upper surface 112 of the substrate 110.

[0053] The first semiconductor device 200 may be stacked (e.g., arranged) on the upper surface 112 of the package substrate 110. The first semiconductor device 200 may be adhered to the upper surface 112 of the package substrate 110 by an adhesive member 220. For example, the adhesive member may include an adhesive film such as a direct adhesive film (DAF). The first semiconductor device 200 may include an integrated circuit. For example, the first semiconductor device 200 may be a logic chip including a logic circuit. The logic chip may be a controller for controlling a memory chip.

[0054] refer to Figure 5 , a first group 300a of the plurality of second semiconductor devices 300 may be arranged on the package substrate 110. For example, at least one second semiconductor device (i.e., a first die 300a) may be arranged on the package substrate 110. The first die 300a may be arranged on the package substrate 110, spaced apart from the first semiconductor device 200. The ground substrate pad 122 may be arranged between the first semiconductor device 200 and the first die 300a.

[0055] The first die 300a may be attached to the package substrate 110 using an adhesive member 320a. For example, the adhesive member 320a may include an adhesive film such as a direct adhesive film (DAF). In addition, as an example, the second semiconductor device 300 may include a volatile memory device such as a DRAM, a NAND flash memory, etc.

[0056] refer to Figures 6 to 8 , a wire bonding process may be performed to electrically connect the first semiconductor device 200 to the package substrate 110 , and an electrostatic discharge structure 400 may be formed on the ground substrate pad 122 during the wire bonding process.

[0057] First, a wire bonding process may be performed to connect the chip pad 210 of the first semiconductor device 200 to the substrate pad 120 on the upper surface 112 of the package substrate 110. The chip pad 210 of the first semiconductor device 200 may be connected to the substrate pad 120 through a first conductive connection member 230 (eg, a bonding wire).

[0058] Specifically, the capillary 20 of the wire bonding device 10 may be moved to the chip pad 210 to bond the wire 40 to the chip pad 210. A ball formed by the discharge torch may be pressed against the chip pad 210 so that the tip of the wire 40 may be bonded to the chip pad 210. When the wire 40 is pulled back from the capillary 20, the wire 40 may be moved from the chip pad 210 to the substrate pad 120 to be bonded to the substrate pad 120.

[0059] Then, an electrostatic discharge structure 400 may be formed on the ground substrate pad 122 .

[0060] like Figure 7 and Figure 8 As shown in FIG. 1 , the capillary 20 of the wire bonding device 10 may be moved to the ground substrate pad 122 to bond the wire 40 to the ground substrate pad 122. A ball formed by a discharge torch may be pressed against the ground substrate pad 122 so that the tip of the wire 40 may be bonded to the ground substrate pad 122. The capillary 20 may be moved upward to pull the wire 40 back to a predetermined height, and the jig 22 may cut the wire 40 to form a wire bump 400 having a tip portion at an upper end portion.

[0061] The lead bump-shaped electrostatic discharge structure 400 may include a bonding portion 410 bonded to the ground substrate pad 122 and a tip portion 420 extending from the bonding portion 410 to a predetermined height. The tip portion 420 may include a sharp top. Therefore, static electricity generated when the second semiconductor device 300 is stacked on the package substrate 110 through a subsequent die attach process can be safely discharged through the electrostatic discharge structure 400 and the ground path in the package substrate 110.

[0062] In this example, the first die 300a is arranged on the package substrate 110 before the wire bonding process. However, other exemplary embodiments are not limited thereto. For example, a wire bonding process may be performed to electrically connect the first semiconductor device 200 to the substrate pad 120 of the package substrate 110 and form the electrostatic discharge structure 400, and then the first die 300a may be arranged on the package substrate 110.

[0063] refer to Figures 9 to 12 , a second group 300 b , 300 c , 300 d , 300 e of the plurality of second semiconductor devices 300 may be stacked on the package substrate 110 , and a wire bonding process may be performed to electrically connect the second semiconductor devices 300 to the package substrate 110 .

[0064] First, if Fig. 9 and Fig.10 As shown in , a die attach process may be performed to arrange the second group 300b, 300c, 300d, 300e of the second semiconductor device 300 on the first group 300a of the second semiconductor device 300. The second to fifth dies 300b, 300c, 300d, 300e in the second semiconductor device 300 may be stacked on the first die 300a, and the first to fifth dies 300a, 300b, 300c, 300d, 300e may be electrically connected to the package substrate 110.

[0065] The second to fifth dies 300b, 300c, 300d, 300e may be stacked in a first cascade structure. The second to fifth dies 300b, 300c, 300d, 300e may be sequentially offset aligned on the package substrate 110 in a direction toward the first semiconductor device 200. The second to fifth dies 300b, 300c, 300d, 300e may be adhered to the package substrate 110 using an adhesive film 320b, 320c, 320d, 320e such as a direct adhesive film (DAF).

[0066] When performing the die attach process, when the adhesive films 320a, 320b, 320c, 320d, 320e are peeled off from the underlying base film, high static charge may be generated. Since the dies 300a, 300b, 300c, 300d, 300e are stacked on each other, the stacked dies may be closer to the first semiconductor device 200 due to the cascade structure. Therefore, the first semiconductor device 200 may be damaged by the generated static charge. In this case, the generated static charge can be safely discharged through the electrostatic discharge structure 400, thereby preventing the first semiconductor device 200 from being damaged by the static charge.

[0067] A wire bonding process may be performed to connect the chip pads 310 of the first to fifth dies 300a, 300b, 300c, 300d, 300e to the substrate pads 120 on the upper surface 112 of the package substrate 110. The chip pads 310 of the first to fifth dies 300a, 300b, 300c, 300d, 300e may be connected to the substrate pads 120 through second conductive connection members 330 (e.g., bonding wires 330).

[0068] like Fig.11 and Fig.12 As shown in , a die attach process may be performed to stack the sixth to tenth dies 300f, 300g, 300h, 300i, 300j in the second semiconductor device 300 on the fifth die 300e, and the sixth to tenth dies 300f, 300g, 300h, 300i, 300j may be electrically connected to the package substrate 110.

[0069] The sixth to tenth dies 300f, 300g, 300h, 300i, 300j may be stacked in a second cascade structure. The sixth to tenth dies 300f, 300g, 300h, 300i, 300j may be sequentially offset aligned on the package substrate 110 in a direction away from the first semiconductor device 200. The sixth to tenth dies 300f, 300g, 300h, 300i, 300j may be adhered to the package substrate 110 using an adhesive film 320f, 320g, 320h, 320i, 320j such as a direct adhesive film (DAF).

[0070] A wire bonding process may be performed to connect the chip pads 310 of the sixth to tenth dies 300f, 300g, 300h, 300i, 300j to the substrate pads 120 on the upper surface 112 of the package substrate 110. The chip pads 310 of the sixth to tenth dies 300f, 300g, 300h, 300i, 300j may be connected to the substrate pads 120 through second conductive connection members 330 (e.g., bonding wires).

[0071] refer to Fig.13 , a molding member 500 may be formed on the package substrate 110 to cover the first semiconductor device 200 and the second semiconductor device 300. The molding member 500 may include epoxy molding compound (EMC).

[0072] The external connection members 600 may be formed on the external connection pads 130 on the lower surface 114 of the package substrate 110 to complete the semiconductor package 100 .

[0073] As described above, in the method of manufacturing a semiconductor package, after the first semiconductor device 200 is attached to the package substrate 110, a wire bonding process may be performed to form an electrostatic discharge structure 400 on the ground substrate pad 122 of the package substrate 110. Then, a die attach process may be performed to attach a plurality of second semiconductor devices 300 to the package substrate 110.

[0074] When performing the die attach process, high static charge may be generated when peeling the adhesive film 320 from the underlying base film. The generated static charge can be safely discharged through the electrostatic discharge structure 400 arranged adjacent to the first semiconductor device 200, thereby preventing the first semiconductor device 200 from being damaged by the static charge.

[0075] Fig.14 is a cross-sectional view illustrating a semiconductor package 101 according to an exemplary embodiment. Fig.15 It is shown Fig.14 The semiconductor package 101 can be compared with the reference Figure 1 The semiconductor package 100 is substantially the same or similar except for the electrostatic discharge structures 400, 402. Therefore, the same reference numerals will be used to refer to the same or similar elements, and further repeated descriptions of the above elements may be omitted.

[0076] refer to Fig.14 and Fig.15 , the electrostatic discharge structure 402 of the semiconductor package 101 may include first and second bonding portions 412 bonded to the substrate pad 122 and an arched connection portion 422 connected to the first and second bonding portions 412. In this case, the electrostatic discharge structure 402 has a wire loop structure.

[0077] Therefore, static electricity generated when the second semiconductor device 300 is stacked on the package substrate 110 using the adhesive film 320 may be safely discharged through the electrostatic discharge structure 402 and a discharge path in the package substrate 110 .

[0078] In the following, the manufacturing Fig.14 A method of semiconductor packaging 101 is provided.

[0079] Fig.16 and Fig.17 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor package 101 according to one or more exemplary embodiments.

[0080] refer to Fig.16 and Fig.17 First, you can execute the same Figure 4 and Figure 5 A process similar to the process described above is used to arrange the first semiconductor device 200 and at least one second semiconductor device 300 on the packaging substrate 110, a wire bonding process can be performed to electrically connect the first semiconductor device 200 to the packaging substrate 110, and an electrostatic discharge structure 402 can be formed on the ground substrate pad 122 during the wire bonding process.

[0081] Specifically, the capillary 20 of the wire bonding apparatus 10 may be moved to the first side of the ground substrate pad 122 to bond the wire 40 to the first side of the ground substrate pad 122. A ball formed by the discharge torch may be pressed against the ground substrate pad 122 so that the tip of the wire 40 may be bonded to the ground substrate pad 122. While the capillary 20 is moved toward the second side of the ground substrate pad 122, the capillary 20 may be moved upward to pull the wire 40 back to a predetermined height, and then moved downward to the second side of the ground substrate pad 122 to bond the wire 40 to the second side of the ground substrate pad 122.

[0082] The arched electrostatic discharge structure 402 may include first and second bonding portions 412 bonded to the substrate pad 122 and an arched connecting portion 422 connected to the first and second bonding portions 412. The connecting portion 422 may include a sharp top.

[0083] Therefore, electrostatic charge generated when the second semiconductor device 300 is stacked on the package substrate 110 through a subsequent die attach process may be safely discharged through the electrostatic discharge structure 402 and a discharge path in the package substrate 110 .

[0084] Then, you can execute the same Figures 9 to 12A process similar to that described above may be used to stack a plurality of second semiconductor devices 300 on the package substrate 110 , and a wire bonding process may be performed to electrically connect the second semiconductor devices 300 to the package substrate 110 .

[0085] Then, you can execute the same Fig.13 The process is similar to the process described above to form a molding member 500 on the package substrate 110 to cover the first semiconductor device 200 and the second semiconductor device 300. The molding member 500 may include epoxy molding compound (EMC).

[0086] The external connection members 600 may be formed on the external connection pads 130 on the lower surface 114 of the package substrate 110 to complete the semiconductor package 101 .

[0087] Fig.18 is a cross-sectional view illustrating a semiconductor package 102 according to an exemplary embodiment. Fig.19 It is shown Fig.18 The semiconductor package 102 may be similar to the semiconductor package 102 of FIG. Figure 1 The semiconductor package 100 is substantially the same or similar except for the additional electrostatic discharge structure 450. Therefore, the same reference numerals will be used to refer to the same or similar elements, and further repeated descriptions of the above elements may be omitted.

[0088] refer to Fig.18 and Fig.19 The semiconductor package 102 may further include a second electrostatic discharge structure 450 .

[0089] The second electrostatic discharge structure 450 may be disposed on at least one ground die pad 212 exposed from the upper surface of the first semiconductor device 200. The ground die pad 212 may be an input / output terminal on the upper surface of the first semiconductor device 200 serving as a ground pin.

[0090] The ground chip pad 212 may be electrically connected to the package substrate 110. The ground chip pad 212 may be electrically connected to a substrate pad of the package substrate 110, for example, the ground substrate pad 122, through the first conductive connection member 230. The ground substrate pad 122 may be electrically connected to the ground plate 116 through the ground wiring 118. Therefore, the second electrostatic discharge structure 450 may be grounded through the first conductive connection member 230, the ground substrate pad 122, and the ground plate 116.

[0091] Alternatively, the semiconductor package 102 may include only the second electrostatic discharge structure 450 , and the first electrostatic discharge structure 400 may be omitted.

[0092] In the case where the first semiconductor device 200 is mounted on the package substrate 110 in a flip chip bonding manner, the ground die pad 212 may be electrically connected to the ground plate 116 of the package substrate 110 through a conductive bump (eg, a solder bump).

[0093] In the following, the manufacturing Fig.18 A method of semiconductor packaging 102 is provided.

[0094] Figure 20 to Figure 22 is a cross-sectional view illustrating a method of manufacturing a semiconductor package 102 according to one or more exemplary embodiments.

[0095] refer to Figure 20 to Figure 22 First, you can execute the same Figure 4 and Figure 5 A process similar to the process described above can be used to arrange the first semiconductor device 200 and at least one second semiconductor device 300 on the packaging substrate 110, a wire bonding process can be performed to electrically connect the first semiconductor device 200 to the packaging substrate 110, and during the wire bonding process, an electrostatic discharge structure 400 can be formed on the ground substrate pad 122 and a second electrostatic discharge structure 450 can be formed on the ground chip pad 212.

[0096] A chip pad 210 and at least one ground chip pad 212 may be disposed on an upper surface of the first semiconductor device 200. The ground chip pad 212 may be an input / output terminal used as a ground pin.

[0097] First, a wire bonding process may be performed to connect the chip pad 210 of the first semiconductor device 200 to the substrate pad 120 on the upper surface 112 of the package substrate 110. The chip pad 210 of the first semiconductor device 200 may be connected to the substrate pad 120 through a first conductive connection member 230 (eg, a bonding wire).

[0098] Then, an ESD structure 400 (first ESD structure 400) may be formed on the ground substrate pad 122, and a second ESD structure 450 may be formed on the ground chip pad 212. The method of forming the second ESD structure 450 may be substantially the same as the method of forming the ESD structure 400.

[0099] like Fig.21 and Fig. 22As shown in , the capillary 20 of the wire bonding device 10 can be moved to the ground chip pad 212 to bond the lead 40 to the ground chip pad 212. The ball formed by the discharge torch can be pressed on the ground chip pad 212 so that the tip of the lead 40 can be bonded to the ground chip pad 212. The capillary 20 can be moved upward to pull the lead 40 back to a predetermined height, and the fixture 22 can cut the lead 40 to form a lead bump 450 having a tip portion in the upper end portion. According to another exemplary embodiment, the second electrostatic discharge structure 450 can be formed to have an arched connection portion, as described above with reference to Fig.14 and Fig.15 described.

[0100] The second electrostatic discharge structure 450 in the lead bump shape may include a bonding portion bonded to the ground chip pad 212 and a tip portion extending from the bonding portion to a predetermined height. The tip portion may include a sharp top.

[0101] Therefore, static charge generated when the second semiconductor device 300 is stacked on the package substrate 110 through a subsequent die attach process may be safely discharged through the electrostatic discharge structure 400 , the second electrostatic discharge structure 450 , and the ground path in the package substrate 110 .

[0102] Then, you can execute the same Figures 9 to 12 A process similar to that described above may be used to stack a plurality of second semiconductor devices 300 on the package substrate 110 , and a wire bonding process may be performed to electrically connect the second semiconductor devices 300 to the package substrate 110 .

[0103] Then, you can execute the same Fig.13 The process is similar to the process described above to form a molding member 500 on the package substrate 110 to cover the first semiconductor device 200 and the second semiconductor device 300. The molding member 500 may include epoxy molding compound (EMC).

[0104] The external connection members 600 may be formed on the external connection pads 130 on the lower surface 114 of the package substrate 110 to complete the semiconductor package 102 .

[0105] An electronic device including semiconductor packages 100, 101, 102 according to an exemplary embodiment may include logic devices such as a central processing unit (CPU), a main processing unit (MPU), an application processor (AP), and volatile memory devices such as DRAM devices, high bandwidth memory (HBM) devices, or non-volatile memory devices such as flash memory devices, phase change random access memory (PRAM) devices, magnetoresistive random access memory (MRAM) devices, resistive random access memory (ReRAM) devices, etc. The electronic device may be specifically implemented by a personal computer (PC), a server device, a workstation, a processing device, or a portable electronic device such as a notebook, a cellular phone, a personal digital assistant (PDA), a camera, etc.

[0106] When performing a die attach process, when the adhesive film is peeled off from the underlying base film, high static charge may be generated. According to an exemplary embodiment, the generated static charge can be safely discharged through an electrostatic discharge structure arranged adjacent to the first semiconductor device, thereby preventing the first semiconductor device from being damaged by the static charge. Therefore, the yield rate of the semiconductor package can be improved and the productivity can be maximized.

[0107] The foregoing is an illustration of exemplary embodiments and should not be construed as limiting thereof. Although some exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made without substantially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments defined in the claims.

Claims

1. A method for manufacturing a semiconductor package, the method comprising: Arranging a first semiconductor device on a packaging substrate; forming an electrostatic discharge structure over an upper surface of the packaging substrate and on a ground substrate pad exposed from the upper surface of the packaging substrate; A plurality of second semiconductor devices spaced apart from the first semiconductor device are stacked on the packaging substrate, wherein the electrostatic discharge structure is interposed between the first semiconductor device and the plurality of second semiconductor devices; as well as A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices. 2 . The method according to claim 1 , wherein the electrostatic discharge structure is formed during a wire bonding process for electrically connecting the first semiconductor device and the package substrate. 3 . The method of claim 1 , wherein forming the electrostatic discharge structure comprises forming a lead bump having a tip portion at an upper portion thereof on the ground substrate pad.

4. The method of claim 3, wherein forming the electrostatic discharge structure comprises: Bonding a wire to the ground substrate pad by a wire bonding device; as well as The leads are cut to have a predetermined height. 5 . The method of claim 1 , wherein forming the electrostatic discharge structure comprises forming an arched wire loop on the ground substrate pad. 6 . The method of claim 1 , wherein the electrostatic discharge structure is formed after adhering at least one second semiconductor device of the plurality of second semiconductor devices to the package substrate. 7 . The method of claim 1 , wherein stacking the plurality of second semiconductor devices on the package substrate comprises adhering the plurality of second semiconductor devices using an adhesive film. 8 . The method of claim 7 , further comprising performing a wire bonding process to electrically connect the plurality of second semiconductor devices to the package substrate. 9 . The method of claim 1 , wherein the ground substrate pad is grounded through a ground plate in the package substrate. 10 . The method of claim 1 , further comprising forming a second electrostatic discharge structure on at least one grounded die pad exposed from an upper surface of the first semiconductor device.

11. A method for manufacturing a semiconductor package, the method comprising: providing a package substrate having a ground substrate pad on an upper surface thereof; Arranging a first semiconductor device on the packaging substrate; performing a wire bonding process to electrically connect the first semiconductor device to the packaging substrate; forming an electrostatic discharge structure over an upper surface of the packaging substrate and on the ground substrate pad during the wire bonding process; A plurality of second semiconductor devices spaced apart from the first semiconductor device are stacked on the packaging substrate, wherein the electrostatic discharge structure is interposed between the first semiconductor device and the plurality of second semiconductor devices; as well as A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices. 12 . The method of claim 11 , wherein forming the electrostatic discharge structure comprises forming a lead bump having a tip portion at an upper portion thereof on the ground substrate pad.

13. The method of claim 12, wherein forming the electrostatic discharge structure comprises: bonding a wire to the ground substrate pad by a wire bonding device; and The leads are cut to have a predetermined height.

14. The method of claim 11, wherein forming the electrostatic discharge structure comprises forming an arched wire loop on the ground substrate pad. 15 . The method of claim 11 , wherein the electrostatic discharge structure is formed after adhering at least one second semiconductor device of the plurality of second semiconductor devices to the package substrate. 16 . The method of claim 11 , wherein stacking the plurality of second semiconductor devices on the package substrate comprises adhering the plurality of second semiconductor devices using an adhesive film. 17 . The method of claim 16 , further comprising performing a wire bonding process to electrically connect the plurality of second semiconductor devices to the package substrate.

18. The method of claim 11, wherein the ground substrate pad is grounded through a ground plate in the package substrate. 19 . The method of claim 11 , further comprising forming a second electrostatic discharge structure on a grounded die pad of the first semiconductor device during the wire bonding process. 20 . The method of claim 11 , wherein the first semiconductor device comprises a logic chip, and the plurality of second semiconductor devices comprises memory chips.

21. A semiconductor package, comprising: Package substrate; a first semiconductor device disposed on the packaging substrate; a plurality of second semiconductor devices on the packaging substrate spaced apart from the first semiconductor device; an electrostatic discharge structure disposed on a ground substrate pad exposed from an upper surface of the packaging substrate between the first semiconductor device and the plurality of second semiconductor devices and above the upper surface of the packaging substrate; as well as The molding member on the packaging substrate covers the first semiconductor device and the plurality of second semiconductor devices.

22. The semiconductor package of claim 21, wherein the electrostatic discharge structure comprises a lead bump having a tip portion.

23. The semiconductor package of claim 21, wherein the electrostatic discharge structure comprises an arcuate lead ring. 24 . The semiconductor package according to claim 21 , wherein the plurality of second semiconductor devices are adhered to the package substrate using an adhesive film.

25. The semiconductor package according to claim 24, further comprising: Bonding wires electrically connect the chip pads of the plurality of second semiconductor devices and the substrate pads of the packaging substrate.

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