Nonvolatile memory device and neural network system including the same

Abstract

A nonvolatile memory device comprises: a memory cell array, wherein arithmetic internal data is written into the memory cell array; and an arithmetic circuit configured to receive arithmetic input data and arithmetic internal data, for performing an arithmetic operation of a neural network using the arithmetic internal data and the arithmetic input data in response to an arithmetic command, performing an arithmetic operation using the arithmetic internal data and the arithmetic input data to generate arithmetic result data, and outputting the arithmetic result data of the arithmetic operation of the neural network.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0164305 filed on December 18, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to arithmetic processing in neural network systems and / or models. Background Art

[0004] Semiconductor memory devices may be classified as volatile memory devices configured to lose stored data when power supply is interrupted, or non-volatile memory devices configured to retain stored data even if power supply is interrupted. Non-volatile memory devices may include read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory devices, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory devices may be broadly classified into NOR type and NAND type.

[0005] A neural network refers to a computing architecture modeled on a biological brain. Recently, with the development of neural network technology, a technology for analyzing input data and extracting effective information by applying a neural network device using at least one neural network model to various kinds of electronic systems has been intensively studied. Summary of the invention

[0006] Some example embodiments may include a nonvolatile memory device comprising: a memory cell array, wherein arithmetic internal data is written to the memory cell array; and an arithmetic circuit configured to receive arithmetic input data and arithmetic internal data, for performing an arithmetic operation of a neural network using the arithmetic internal data and the arithmetic input data in response to an arithmetic command, performing an arithmetic operation of the neural network using the arithmetic internal data and the arithmetic input data to generate arithmetic result data, and outputting the arithmetic result data of the arithmetic operation of the neural network.

[0007] Some example embodiments may include a nonvolatile memory device comprising: a memory cell array, wherein arithmetic internal data is written to the memory cell array; an arithmetic circuit configured to perform an arithmetic operation using a plurality of operands to generate arithmetic result data; and a control logic circuit configured to receive an arithmetic command for processing an arithmetic operation of a neural network, read the arithmetic internal data written to the memory cell array in response to the arithmetic command, generate an arithmetic control signal, wherein the arithmetic control signal causes the arithmetic circuit to perform an arithmetic operation for processing the neural network using a plurality of operands including the arithmetic internal data and arithmetic input data, and output the arithmetic result data of the arithmetic operation of the neural network.

[0008] Some example embodiments may include a neural network system configured to perform arithmetic operations of a neural network, wherein the neural network system includes a memory controller configured to generate an arithmetic command to perform the arithmetic operation, and to send the arithmetic command and arithmetic input data; and a memory device configured to receive the arithmetic command and the arithmetic input data, read arithmetic internal data written to a memory cell array in response to the arithmetic command, perform the arithmetic operation using the arithmetic input data and the arithmetic internal data, and output arithmetic result data of the arithmetic operation of the neural network. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Some example embodiments of some inventive concepts may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a memory system according to some example embodiments;

[0011] Figure 2 According to some example embodiments Figure 1 A detailed block diagram of a non-volatile memory device;

[0012] Figure 3 is a flowchart of a method of operating a nonvolatile memory device according to some example embodiments;

[0013] Figure 4 is a circuit diagram of a memory block included in a memory cell array according to some example embodiments;

[0014] Figure 5 is a circuit diagram of a memory block included in a memory cell array according to some example embodiments;

[0015] Figure 6 yes Figure 5 A perspective view of a storage block;

[0016] Figure 7is a diagram illustrating the operation of a memory system according to some example embodiments;

[0017] Fig. 8A and Figure 8B is a diagram illustrating a convolution operation of a neural network;

[0018] Fig. 9 is a diagram of a computing circuit included in a nonvolatile memory device according to some example embodiments;

[0019] Fig.10 According to some example embodiments Figure 1 A detailed block diagram of a non-volatile memory device;

[0020] Fig.11 It shows Figure 3 a flowchart of a method of operating a nonvolatile memory device according to some example embodiments of operation S130;

[0021] Fig. 12A and Fig. 12B is a timing diagram illustrating arithmetic operations of a neural network involving a nonvolatile memory device according to some example embodiments; and

[0022] Fig.13 is a block diagram of a solid-state drive (SSD) according to some example embodiments. DETAILED DESCRIPTION

[0023] Hereinafter, some example embodiments of some inventive concepts are described in detail with reference to the accompanying drawings.

[0024] Figure 1 is a block diagram of a memory system 10 according to an example embodiment.

[0025] refer to Figure 1, the memory system 10 may include a non-volatile memory device 100 and a memory controller 200. In some example embodiments, the memory system 10 may be implemented as an internal memory embedded in an electronic device and / or an external memory detachably attached to the electronic device. In some example embodiments, the memory system 10 may include, for example, a Universal Flash Storage (UFS) memory card, a Compact Flash (CF) memory card, a Secure Digital (SD) memory card, a micro SD memory card, a mini SD memory card, an extreme Digital (xD) memory card, or a memory stick. For example, the memory system 10 may be applied to a robot device (e.g., a drone and / or an Advanced Drivers Assistance System (ADAS)), a smart TV, a smart phone, a medical device, a mobile device, an image display device, a measuring device, and / or an Internet of Things (IoT) device. In addition, the memory system 10 may be installed on one of various types of electronic devices.

[0026] In some example embodiments, the memory system 10 may include a neural network model. The memory controller 200 may include a neural network processing circuit 1110. The memory system 10 including the neural network processing circuit 1110 may generate a neural network, train (or learn) a neural network, perform an arithmetic operation of the neural network based on received input data, generate an information signal based on a result of the arithmetic operation of the neural network, and / or retrain the neural network. The neural network may include various kinds of processing models, such as a Convolution Neural Network (CNN) (e.g., GoogleNet, AlexNet, and / or Visual Geometry Group (VGG) network), a Region with Convolution Neural Network (R-CNN), a Region Proposal Network (RPN), a Recurrent Neural Network (RNN), a Stacking-based Deep Neural Network (S-DNN), a State-Space Dynamic Neural Network (S-SDNN), a Deconvolution Network, a Deep Belief Network (DBN), a Restricted Boltzmann Machine (RBM), a Fully Convolutional Network, a Long Short-Term Memory (LSTM) network, and / or a Classification Network, but is not limited thereto. Neural networks may include, may be supplemented by and / or may operate in conjunction with various other processing models, such as Bayesian statistical classifiers, genetic evolutionary algorithms, fuzzy logic systems, and / or rule-based and / or heuristic classifiers (such as decision trees), including combinations thereof.

[0027] In some example embodiments, the memory controller 200 may control the nonvolatile memory device 100 to read data stored in the nonvolatile memory device 100 and / or write data to the nonvolatile memory device 100 in response to a read / write request from a host. The memory controller 200 may provide a command, address, and / or control signal to the nonvolatile memory device 100, and / or may control writing, reading, erasing, and / or arithmetic operations of a neural network involving the nonvolatile memory device 100. Data may be transmitted and / or received between the memory controller 200 and the nonvolatile memory device 100.

[0028] In some example embodiments, the memory controller 200 may provide the nonvolatile memory device 100 with an arithmetic command CMD_ar and / or arithmetic input data DATA_EX so that the nonvolatile memory device 100 may perform an arithmetic operation of a neural network. In this case, in order to read the arithmetic internal data DATA_IN written to the memory cell array 110, the memory controller 200 may further provide the nonvolatile memory device 100 with an arithmetic information signal IN_p. In some example embodiments, the memory controller 200 may provide the nonvolatile memory device 100 with an arithmetic command CMD_ar and / or arithmetic input data DATA_EX through a line through which a write command and / or a read command for a write operation and / or a read operation of the nonvolatile memory device 100 is transmitted.

[0029] In some example embodiments, the arithmetic information signal IN_p may include an address for indicating a storage location where the arithmetic internal data DATA_IN is written and / or accessible. In some example embodiments, the arithmetic information signal IN_p may include information about addresses of a plurality of pages storing the arithmetic internal data DATA_IN. In some example embodiments, the arithmetic information signal IN_p may include information about addresses of a plurality of pages storing the arithmetic internal data DATA_IN on which an initial read operation is to be performed. The arithmetic information signal IN_p may include information about the number of memory pages on which the arithmetic internal data DATA_IN is stored.

[0030] The nonvolatile memory device 100 may be implemented as a nonvolatile memory circuit. The nonvolatile memory device 100 may include a memory cell array 110 and an arithmetic circuit 140. The nonvolatile memory device 100 may perform an arithmetic operation of a neural network in response to an arithmetic command CMD_ar. The operation of the nonvolatile memory device 100 may broadly include one or more of an operation of reading arithmetic internal data DATA_IN, an operation of receiving arithmetic input data DATA_EX, an arithmetic operation of a neural network using arithmetic internal data DATA_IN and / or arithmetic input data DATA_EX, and / or an operation of outputting arithmetic result data DATA_R.

[0031] The memory cell array 110 may include a plurality of memory blocks, each of which may include a plurality of pages. In some example embodiments, each of the memory blocks may independently perform an erase operation, and / or each of the pages may independently perform a read operation. The memory cell array 110 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. Hereinafter, some example embodiments in which the plurality of memory cells may include NAND flash memory cells are described in detail. In other example embodiments, the plurality of memory cells may be resistive memory cells, such as resistive RAM (RRAM) cells, phase change RAM (PRAM) cells, or magnetic RAM (MRAM) cells.

[0032] In some example embodiments, the arithmetic circuit 140 may perform an arithmetic operation according to a model of a neural network. For example, the arithmetic circuit 140 may use a plurality of operands to perform an arithmetic operation of the neural network. In some example embodiments, the plurality of operands may include arithmetic input data DATA_EX provided by the memory controller 200 and / or arithmetic internal data DATA_IN written to the memory cell array 110. In some example embodiments, when the arithmetic command CMD_ar is received, the nonvolatile memory device 100 may read the arithmetic internal data DATA_IN from the memory cell array 110 and / or may use the arithmetic input data DATA_EX received externally and / or the read arithmetic internal data DATA_IN to perform an arithmetic operation of the neural network. The arithmetic circuit 140 may use a plurality of operands to perform an arithmetic operation of the neural network, may generate an arithmetic result data DATA_R, and / or may provide the arithmetic result data DATA_R to the memory controller 200.

[0033] In some example embodiments, the arithmetic circuit 140 may perform all or part of the convolution arithmetic operation of the neural network. To this end, the arithmetic circuit 140 may include a multiplication and accumulation circuit (MAC) configured to perform multiplication and addition operations, such as reference Fig. 9 In some example embodiments, the arithmetic circuit 140 may include a plurality of MACs connected in a ring form. In some example embodiments, the arithmetic circuit 140 may further include a nonlinear function processor and / or a quantizer.

[0034] The nonvolatile memory device 100 of the memory system 10 according to some example embodiments may perform an operation of reading the arithmetic internal data DATA_IN and / or an operation of receiving the arithmetic input data DATA_EX in parallel. In addition, during an arithmetic operation of the neural network using the arithmetic internal data DATA_IN and / or the arithmetic input data DATA_EX, an operation of reading the next arithmetic internal data DATA_IN for the next arithmetic operation of the neural network and / or an operation of receiving the next arithmetic input data DATA_EX for the next arithmetic operation of the neural network may be performed in parallel. Therefore, the time taken to perform the arithmetic operation of the neural network on the arithmetic internal data DATA_IN and / or the arithmetic input data DATA_EX may be reduced, so that the arithmetic operation speed may be increased, and thus the processing speed of the neural network may be increased. In the present disclosure, performing different operations in parallel may mean that there are portions in which different operations are performed simultaneously.

[0035] In contrast to the memory system in the prior art in which only the memory controller 200 performs arithmetic operations of the neural network, the nonvolatile memory device 100 according to some inventive concepts can perform arithmetic operations of the neural network in advance and then provide the arithmetic result DATA_R to the memory controller 200. Therefore, the efficiency of the arithmetic operations of the memory system 10 can be improved, thereby improving the performance of the memory system 10 and, therefore, improving the processing of the neural network.

[0036] Figure 2 According to some example embodiments Figure 1 Detailed block diagram of a non-volatile memory device 100.

[0037] refer to Figure 2 The nonvolatile memory device 100 may include a memory cell array 110, a page buffer 120, a row decoder circuit 130, an arithmetic circuit 140, a control logic circuit 150 and / or an input / output (I / O) circuit 160. The arithmetic circuit 140 may include a calculation circuit 141 and / or a buffer 143.

[0038] The memory cell array 110 may be connected to the page buffer 120 through the bit line BL, and connected to the row decoder circuit 130 through the word line WL. The memory cell array 110 may include a plurality of memory blocks and a plurality of pages PAGE1 to PAGEz. The nonvolatile memory device 100 may perform a read operation or a write operation in units of pages. In some example embodiments, the nonvolatile memory device 100 may perform arithmetic operations of a neural network in units of pages. Each of the memory cells included in the memory cell array 110 may store at least one bit. Each of the memory cells may include a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quadruple-level cell (QLC).

[0039] The page buffer 120 may select some bit lines from the bit lines BL in response to the column address Y-ADDR provided by the control logic circuit 150. For example, the page buffer 120 may operate as a write driver or a sense amplifier according to an operation mode (e.g., a write mode or a read mode). In some example embodiments, the page buffer 120 may operate as a sense amplifier configured to read the first arithmetic internal data DATA_IN1 to the kth arithmetic internal data DATA_INk from the memory cell array 110 to perform an arithmetic operation of the neural network. Each of the first arithmetic internal data DATA_IN1 to the kth arithmetic internal data DATA_INk may be Figure 1 Arithmetic internal data DATA_IN.

[0040] The row decoder circuit 130 may select at least one word line from the word lines WL in response to the row address X-ADDR provided by the control logic circuit 150. A group of memory cells connected to the selected word line may be interpreted as a selected page. In some example embodiments, the row decoder circuit 130 may sequentially select the first page PAGE1 to the kth page PAGEk to read the first arithmetic internal data DATA_IN1 to the kth arithmetic internal data DATA_INk used for arithmetic operations of the neural network, and / or may sequentially read the first arithmetic internal data DATA_IN1 written to the first page PAGE1 to the kth arithmetic internal data DATA_INk written to the kth page PAGEk. In some example embodiments, the first page PAGE1 to the kth page PAGEk may have consecutive addresses, but some example embodiments of some inventive concepts may not be limited thereto.

[0041] The calculation circuit 141 of the arithmetic circuit 140 may perform an arithmetic operation of a neural network using a plurality of operands in response to an arithmetic control signal CTRL_ar provided by the control logic circuit 150. At least one of the plurality of operands may be first to k-th arithmetic internal data DATA_IN1 to k-th arithmetic internal data DATA_INk provided by the page buffer 120. In addition, at least one of the plurality of operands may be first to k-th arithmetic input data DATA_EX1 to k-th arithmetic input data DATA_EXk that may be received by the nonvolatile memory device 100. Each of the first to k-th arithmetic input data DATA_EX1 to DATA_EXk may be Figure 1 Arithmetic input data DATA_EX.

[0042] In some example embodiments, the calculation circuit 141 may perform an arithmetic operation of the neural network using the first to k-th arithmetic internal data DATA_IN1 to k-th arithmetic internal data DATA_INk and / or the first to k-th arithmetic input data DATA_EX1 to perform an arithmetic operation of the neural network in response to the arithmetic control signal CTRL_ar. For example, the calculation circuit 141 may perform a first arithmetic operation of the neural network using the first arithmetic internal data DATA_IN1 and / or the first arithmetic input data DATA_EX1, and / or perform a k-th arithmetic operation of the neural network using the k-th arithmetic internal data DATA_INk and / or the k-th arithmetic input data DATA_EXk. The calculation circuit 141 may sequentially perform the first to k-th arithmetic operations of the neural network in response to the arithmetic control signal CTRL_ar, and / or sequentially and / or in parallel generate the first to k-th arithmetic result data DATA_R1 to k-th arithmetic result data DATA_Rk as corresponding results of the first to k-th arithmetic operations of the neural network. The calculation circuit 141 may sequentially output the first to k-th arithmetic result data DATA_R1 to DATA_Rk to the buffer 143. Each of the first to k-th arithmetic result data DATA_R1 to DATA_Rk may be Figure 1 The arithmetic result data DATA_R.

[0043] In some example embodiments, the arithmetic operation of the neural network performed by the computing circuit 141 may include all or part of the convolution operation. For example, the arithmetic internal data DATA_IN may be included in Fig. 8A The input feature data in the input feature map 401, and / or the arithmetic input data DATA_EX may be included in Fig. 8A The kernel data in the kernel 402. Fig. 8A An example describing the convolution operation.

[0044] The buffer 143 of the arithmetic circuit 140 may temporarily store the first to kth arithmetic result data DATA_R1 to DATA_Rk. In response to the arithmetic control signal CTRL_ar provided by the control logic circuit 150, the buffer 143 may be connected to the nonvolatile memory device 100 through the I / O circuit 160 (eg, Figure 1 The memory controller 200 of the memory controller 200 provides the stored first to kth arithmetic result data DATA_R1 to DATA_Rk. In some example embodiments, the buffer 143 may sequentially output the first to kth arithmetic result data DATA_R1 to DATA_Rk to the I / O circuit 160 in response to the arithmetic control signal CTRL_ar.

[0045] The control logic circuit 150 may control the overall operation of the nonvolatile memory device 100. In some example embodiments, the control logic circuit 150 may cause the arithmetic circuit 140 to perform an arithmetic operation of the neural network in response to an arithmetic command CMD_ar and / or an arithmetic information signal IN_p received from the memory controller 200 through the I / O circuit 160. For example, in response to the arithmetic command CMD_ar and / or the arithmetic information signal IN_p, the control logic circuit 150 may output various control signals such as a column address Y-ADDR, a row address X-ADDR, and / or an arithmetic control signal CTRL_ar to cause the arithmetic circuit 140 to perform one or more arithmetic operations of the neural network.

[0046] In some example embodiments, the arithmetic information signal IN_p may include addresses for indicating first pages PAGE1 to k-th pages PAGEk to which first to k-th arithmetic internal data DATA_IN1 to k-th arithmetic internal data DATA_INk are respectively written. Therefore, the control logic circuit 150 may provide the row address X-ADDR to the row decoder circuit 130 in response to the arithmetic information signal IN_p. In some example embodiments, the arithmetic information signal IN_p may include an address of the first page PAGE1 to which the first arithmetic internal data DATA_IN1 to which the first arithmetic operation of the neural network is to be performed is written and / or information about a value k as the number of pages to be read. The control logic circuit 150 may output the row address X-ADDR to the row decoder circuit 130 in response to the arithmetic information signal IN_p.

[0047] Figure 3 is a flowchart of a method of operating the nonvolatile memory device 100 according to some example embodiments. Figure 3, a first arithmetic operation of a neural network using the first arithmetic internal data DATA_IN1 and / or the first arithmetic input data DATA_EX1 is described as an example, but some example embodiments of some inventive concepts may not be limited thereto. For example, some example embodiments of some inventive concepts may be applied to a kth arithmetic operation of a neural network using the kth arithmetic internal data DATA_INk and / or the kth arithmetic input data DATA_EXk.

[0048] refer to Figure 2 and Figure 3 In operation S110, the nonvolatile memory device 100 may receive an arithmetic command CMD_ar. In operation S120, the nonvolatile memory device 100 may read arithmetic internal data written to a specific page in response to the arithmetic command CMD_ar. For example, the nonvolatile memory device 100 may read the first arithmetic internal data DATA_IN1 written to the first page PAGE1. Under the condition that the operation of reading the first arithmetic internal data DATA_IN1 is completed, the nonvolatile memory device 100 may read the second arithmetic internal data DATA_IN2 written to the second page PAGE2.

[0049] In operation S130, the nonvolatile memory device 100 may receive arithmetic input data. In operation S140, the nonvolatile memory device 100 may confirm whether the size of the received arithmetic input data corresponds to the size of the arithmetic internal data corresponding thereto. In some example embodiments, the nonvolatile memory device 100 may confirm whether the size of the received arithmetic input data corresponds to the size of a page of the memory cell array 110. For example, when operation S130 starts, the nonvolatile memory device 100 may start receiving the first arithmetic input data DATA_EX1. In operation S140, before performing the first arithmetic operation of the neural network, the nonvolatile memory device 100 may confirm whether all the first arithmetic input data DATA_EX1 have been received, that is, whether the size of the first arithmetic input data DATA_EX1 corresponds to the size of a page of the memory cell array 110, which may be the size of the first arithmetic internal data DATA_IN1.

[0050] In some example embodiments, the arithmetic operation of the neural network may involve arithmetic internal data and arithmetic input data as operands of the arithmetic operation, which have the same or similar size, type and / or format. Therefore, after receiving the arithmetic input data, the nonvolatile memory device 100 may confirm whether the arithmetic input data has been received in a size sufficient for performing the arithmetic operation of the neural network. If the size of the arithmetic input data satisfies the conditions for performing the arithmetic operation of the neural network, the control logic circuit 150 may send an arithmetic control signal CTRL_ar to the arithmetic circuit 140, and the operation S150 of the neural network may be performed.

[0051] In some example embodiments, the nonvolatile memory device 100 may perform operation S120 and operation S130 in parallel. Some example embodiments of some inventive concepts may not be limited thereto, and the nonvolatile memory device 100 may perform operation S120 and operation S130 in series, partially in series and partially in parallel, etc. That is, the operation of reading the first arithmetic internal data DATA_IN1 to the k-th arithmetic internal data DATA_INk and the operation of receiving the first arithmetic input data DATA_EX1 to the k-th arithmetic input data DATA_EXk may be performed in series, in parallel, partially in series and partially in parallel, etc. For example, the operation of reading the first arithmetic internal data DATA_IN1 and the operation of receiving the first arithmetic input data DATA_EX1 may be performed in series, in parallel, partially in series and partially in parallel, etc.

[0052] In operation S150, the nonvolatile memory device 100 may perform an arithmetic operation of the neural network using the arithmetic internal data and / or the arithmetic input data corresponding to each other. For example, the nonvolatile memory device 100 may perform a first arithmetic operation of the neural network using the first arithmetic internal data DATA_IN1 and / or the first arithmetic input data DATA_EX1.

[0053] In this case, during operation S150 of performing an arithmetic operation of a neural network using the arithmetic internal data and / or the arithmetic input data corresponding to the arithmetic internal data, the nonvolatile memory device 100 may perform operation S120 of reading other arithmetic internal data and / or operation S130 of receiving other arithmetic input data serially, in parallel, partially serially and partially in parallel, etc. In some example embodiments, during operation S150 of performing a first arithmetic operation of a neural network using the first arithmetic internal data DATA_IN1 and / or the first arithmetic input data DATA_EX1, the nonvolatile memory device 100 may perform operation S120 of reading second arithmetic internal data DATA_IN2 serially, in parallel, partially serially and partially in parallel, etc. Some example embodiments may perform operation S130 of receiving second arithmetic input data DATA_EX2 serially, in parallel, partially serially and partially in parallel, etc. Therefore, the time taken for the nonvolatile memory device 100 according to some example embodiments of some inventive concepts to sequentially and / or simultaneously perform multiple arithmetic operations of the neural network (e.g., first to kth arithmetic operations of the neural network) and output corresponding arithmetic result data (e.g., first to kth arithmetic result data DATA_R1 to kth arithmetic result data DATA_Rk) obtained by performing the multiple arithmetic operations of the neural network to a memory controller can be reduced.

[0054] In operation S160, the nonvolatile memory device 100 may output arithmetic result data generated as a result of the arithmetic operation of the neural network. The arithmetic result data may be provided to the memory controller. For example, when the nonvolatile memory device 100 performs the first arithmetic operation of the neural network, the nonvolatile memory device 100 may send the first arithmetic result data DATA_R1 to the memory controller.

[0055] Figure 4 is a circuit diagram of a memory block BLK included in a memory cell array according to some example embodiments.

[0056] refer to Figure 4 , memory cell array (e.g., Figure 2 110) may include a memory cell array and / or a plurality of memory blocks BLK of a horizontal NAND flash memory. Each of the memory blocks BLK may include m cell strings STR, wherein each of the cell strings STR includes a plurality of memory cells connected in series with corresponding bit lines BL1 to BLm (here, m is an integer equal to or greater than 2). As an example, Figure 4 A case is shown in which each of the cell strings STR includes n memory cells MC1 to MCn.

[0057] have Figure 4The NAND flash nonvolatile memory device of the structure shown may perform an erase operation in units of blocks and / or may perform a read operation and / or an arithmetic operation of a neural network in units of pages PAGE corresponding to each of the word lines WL1 to WLn. Figure 4 An example is shown in which one block includes n pages corresponding to n word lines WL1 to WLn, respectively. Figure 1 and / or Figure 2 100) may drive a selected word line connected to a memory cell on which a read operation is to be performed during an arithmetic operation of the neural network. In some example embodiments, when a read operation is performed on the third memory cell MC3, the third word line WL3 may be a selected word line. Figure 1 and / or Figure 2 The illustrated nonvolatile memory device 100 may include a plurality of memory cell arrays that may have the same or similar structure as the above-described memory cell array 110 and / or may perform the same or similar operation as the above-described memory cell array 110 .

[0058] Figure 5 is a circuit diagram of a memory block included in a memory cell array according to some example embodiments.

[0059] refer to Figure 5 , memory cell array (e.g., Figure 2 110) may be a memory cell array of a vertical NAND flash memory. The memory block BLK0 included in the memory cell array may include a plurality of NAND cell strings (e.g., NS11 to NS33), a plurality of word lines (e.g., WL1 to WL8), a plurality of bit lines (e.g., BL1 to BL3), a plurality of ground selection lines (e.g., GSL1 to GSL3), a plurality of cell string selection lines (e.g., SSL1 to SSL3), and a common source line CSL. In some example embodiments, the number of NAND cell strings, the number of word lines, the number of bit lines, the number of ground selection lines, and / or the number of cell string selection lines may vary.

[0060] NAND cell strings NS11, NS21 and / or NS31 may be provided between the first bit line BL1 and / or the common source line CSL. NAND cell strings NS12, NS22 and / or NS32 may be provided between the second bit line BL2 and / or the common source line CSL. NAND cell strings NS13, NS23 and / or NS33 may be provided between the third bit line BL3 and / or the common source line CSL. Each NAND cell string (e.g., NS11) may include a cell string selection transistor SST, a plurality of memory cells (e.g., MC1 to MC8) and / or a ground selection transistor GST that may be connected in series.

[0061] The NAND cell strings commonly connected to one bit line may constitute a column. For example, NAND cell strings NS11, NS21, and / or NS31 commonly connected to the first bit line BL1 may correspond to the first column, NAND cell strings NS12, NS22, and / or NS32 commonly connected to the second bit line BL2 may correspond to the second column, and / or NAND cell strings NS13, NS23, and / or NS33 commonly connected to the third bit line BL3 may correspond to the third column.

[0062] The NAND cell strings connected to one cell string selection line may constitute a row. For example, NAND cell strings NS11, NS12, and / or NS13 connected to a first cell string selection line SSL1 may correspond to a first row, NAND cell strings NS21, NS22, and / or NS23 connected to a second cell string selection line SSL2 may correspond to a second row, and / or NAND cell strings NS31, NS32, and / or NS33 connected to a third cell string selection line SSL3 may correspond to a third row.

[0063] The cell string selection transistor SST may be connected to the first cell string selection line SSL1 to the third cell string selection line SSL3 corresponding thereto. The first memory cell MC1 to the eighth memory cell MC8 may be connected to the first word line WL1 to the eighth word line WL8 corresponding thereto, respectively. The ground selection transistor GST may be connected to the first ground selection line GSL1 to the third ground selection line GSL3 corresponding thereto. The cell string selection transistor SST may be connected to the first bit line BL1 to the third bit line BL3 corresponding thereto, and / or the ground selection transistor GST may be connected to the common source line CSL.

[0064] Word lines (e.g., WL1) at the same level may be connected in common with each other, the first cell string selection lines SSL1 to the third cell string selection lines SSL3 may be separated from each other, and / or the first ground selection lines GSL1 to the third ground selection lines GSL3 may be separated from each other. For example, when memory cells connected to the first word line WL1 and / or belonging to cell strings NS11, NS12, and / or NS13 are programmed, the first word line WL1 and / or the first cell string selection line SSL1 may be selected. The first ground selection lines GSL1 to the third ground selection lines GSL3 may be connected in common with each other.

[0065] Figure 6 yes Figure 5 A perspective view of a storage block.

[0066] refer to Figure 6 , is included in a memory cell array (e.g., Figure 2Each memory block in 110) may be formed in a direction perpendicular to the substrate SUB. Figure 6 An example is shown in which a memory block includes two selection lines GSL and SSL, eight word lines WL1 to WL8 and / or three bit lines BL1 to BL3, but the memory block may include more or fewer selection lines, word lines and / or bit lines than the above in some example embodiments.

[0067] The substrate SUB may be of a first conductivity type (e.g., p-type). The common source line CSL may be provided on the substrate SUB and / or may extend in a first direction (e.g., Y direction). The common source line CSL may be doped with impurities of a second conductivity type (e.g., n-type). A plurality of insulating films IL may be provided on a region of the substrate SUB between two adjacent common source lines CSL and / or may extend in the first direction. A plurality of insulating films IL may be sequentially provided in a third direction and / or may be spaced apart from each other by a predetermined distance in a third direction (e.g., Z direction). For example, the plurality of insulating films IL may include an insulating material such as silicon oxide.

[0068] A plurality of pillars P may be provided on a region of the substrate SUB between two adjacent common source lines CSL and / or may be sequentially arranged in a first direction. The plurality of pillars P may pass through a plurality of insulating films IL in a third direction. For example, the plurality of pillars P may pass through a plurality of insulating films IL and / or may contact the substrate SUB. The surface layer S of each of the pillars P may include a first type silicon material and / or may be used as a channel region. The inner layer I of each of the pillars P may include an insulating material (e.g., silicon oxide) or an air gap.

[0069] The charge storage layer CS may be provided along the exposed surface of the substrate SUB between the insulating film IL, the pillar P and / or two adjacent common source lines CSL. The charge storage layer CS may include a gate insulating layer (or referred to as a "tunnel insulating layer"), a charge trapping layer and / or a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, gate electrodes GE such as selection lines GSL and SSL and word lines WL1 to WL8 may be provided on the exposed surface of the charge storage layer CS in the region between the two adjacent common source lines CSL.

[0070] The drain or drain contact DR may be provided on the plurality of pillars P, respectively. For example, the drain or drain contact DR may include a silicon material doped with impurities of the second conductivity type. The bit lines BL1 to BL3 may be provided on the drain DR. The bit lines BL1 to BL3 may extend in the second direction (e.g., the X direction) and / or may be spaced apart from each other by a predetermined distance in the first direction.

[0071] Figure 7 is a diagram illustrating the operation of a memory system according to some example embodiments. Figure 7 is a diagram of a structure of a convolutional neural network as an example of the structure of a neural network. A nonvolatile memory device of a memory system according to some example embodiments may constitute a part of a neural network.

[0072] refer to Figure 7 , the neural network NN may include a plurality of layers L1 to Li. Each of the layers L1 to Li may be a linear layer or a nonlinear layer. In some example embodiments, a combination of at least one linear layer and at least one nonlinear layer may be referred to as one layer. For example, the linear layer may include a convolutional layer and / or a fully connected layer, and the nonlinear layer may include a pooling layer and / or an activation layer.

[0073] For example, the first layer L1 may be a convolutional layer, the second layer L2 may be a pooling layer, and / or the i-th layer Li may be an output layer and / or a fully connected layer. In some example embodiments, the number of layers L1 to Li may vary, and / or the neural network NN may further include an activation layer and / or may further include a layer configured to perform another type of operation.

[0074] Each of the first layer L1 to the i-th layer Li can receive input data (e.g., input image frames) and / or a feature map generated at the previous layer as an input feature map. Each of the first layer L1 to the i-th layer Li can perform arithmetic operations of a neural network on the input feature map and / or can generate an output feature map or a recognition signal REC. A feature map may refer to data in which various features of the input data are represented. Feature maps FM1, FM2, and / or FMi may have, for example, a two-dimensional (2D) matrix form or a three-dimensional (3D) matrix (or tensor) form. Feature maps FM1, FM2, and / or FMi may have a width W (or column), a height H (or row), and / or a depth D, which may correspond to the x-axis, y-axis, and / or z-axis on the coordinates, respectively. Depth D may be referred to as the number of channels.

[0075] The first layer L1 may convolve the first feature map FM1 with the weight map WM and / or may generate a second feature map FM2. The weight map WM may filter the first feature map FM1 and may be referred to as a filter or a kernel. The depth (i.e., the number of channels) of the weight map WM may be equal to the depth (i.e., the number of channels) of the first feature map FM1, and / or the channels of the weight map WM may be convolved with the channels of the first feature map FM1 corresponding thereto, respectively. The weight map WM may be moved as a sliding window to traverse the first feature map FM1. The amount of movement may be referred to as a "stride length" or "stride". During each movement, each of the weight values ​​included in the weight map WM may be multiplied and / or added to all feature data in the area where each of the weight values ​​included in the weight map WM overlaps with the first feature map FM1. The data of the first feature map FM1 in the area where each of the weight values ​​included in the weight map WM overlaps with the first feature map FM1 may be referred to as extracted data. When the first feature map FM1 is convolved with the weight map WM, one channel of the second feature map FM2 may be generated. Despite Figure 7 In FIG. 1 , one weight map WM is indicated, but multiple weight maps may be substantially convolved with the first feature map FM1, and / or multiple channels of the second feature map FM2 may be generated. In other words, the number of channels of the second feature map FM2 may correspond to the number of weight maps. In some example embodiments, all or part of the convolution operation may be performed by Figure 1 The arithmetic circuit 140 of the nonvolatile memory device 100 shown is executed by Figure 2 The computing circuit 141 shown is used to perform; and / or as Figure 3 The operation S150 is performed.

[0076] The second layer L2 may change the spatial size of the second feature map FM2 due to the pooling operation and / or may generate a third feature map FM3. The pooling operation may be referred to as a sampling operation or a downsampling operation. The 2D pooling window PW may be moved on the second feature map FM2 in units of the size of the pooling window PW, and / or the maximum value (or average value) of the feature data of the area overlapping the pooling window PW may be selected. Therefore, a third feature map FM3 with a changed spatial size may be generated from the second feature map FM2. The number of channels of the third feature map FM3 may be equal to the number of channels of the second feature map FM2.

[0077] The i-th layer Li can combine the features of the i-th feature map FMi and / or can classify the category CL of the input data. In addition, the i-th layer Li can generate a recognition signal REC corresponding to the category CL. In some example embodiments, the input data may correspond to frame data included in a video stream, and / or the i-th layer Li can extract the category CL corresponding to the object included in the image indicated by the frame data based on the i-th feature map FMi provided by the previous layer, identify the object, and / or can generate a recognition signal REC corresponding to the identified object.

[0078] Fig. 8A and Figure 8B is a diagram illustrating an example of a convolution operation of a neural network. In some example embodiments, Fig. 8A and Figure 8B All or part of the convolution operation can be done by Figure 1 The arithmetic circuit 140 of the nonvolatile memory device 100 shown is executed by Figure 2 The computing circuit 141 shown is used to perform; and / or as Figure 3 The operation S150 is performed.

[0079] refer to Fig. 8A , the input feature map 401 may include D channels, and / or the input feature map of each channel may have a size of H rows and / or W columns (each of D, H, and W may be a natural number). Each of the kernels 402 may have a size of R rows and S columns, and the kernel 402 may include a number of channels equal to the number of channels (or depth) of the input feature map 401 (each of R and S may be a natural number). The output feature map 403 may be generated using a 3D convolution operation between the input feature map 401 and / or the kernel 402, and / or may include Y channels due to the 3D convolution operation.

[0080] You can refer to Figure 8B Describes the process of generating an output feature map using a convolution operation between an input feature map and a kernel. Figure 8B The depicted 2D convolution operation may be performed between an input feature map 401 of multiple channels and a kernel 402 of all such channels, thereby generating an output feature map 403 of all such channels.

[0081] exist Figure 8B , the input feature map 410 has a size of 6×6, the original kernel 420 has a size of 3×3, and the output feature map 430 has a size of 4×4. However, some example embodiments of some inventive concepts may not be limited thereto; for example, the neural network may be implemented with feature maps and / or kernels of various sizes. In addition, Figure 8BThe values ​​of the input feature map 410, the original kernel 420, and / or the output feature map 430 shown in may be merely examples, and some example embodiments of some inventive concepts may not be limited to the defined values.

[0082] The original kernel 420 may perform a convolution operation while sliding in units of a window of size 3×3 in the input feature map 410. The convolution operation may be an arithmetic operation of a neural network, for example, each feature data of the output feature map 430 is obtained by summing all values ​​obtained by multiplying each feature data of any window of the input feature map 410 by each of the weight values ​​of the corresponding position of the original kernel 420. The data included in the window of the input feature map 410 multiplied by the weight value may be referred to as extracted data, which is extracted from the input feature map 410. The original kernel 420 may first perform a convolution operation on the first extracted data 411 of the input feature map 410. That is, the feature data 1, 2, 3, 4, 5, 6, 7, 8, and 9 of the first extracted data 411 can be multiplied by the weight values ​​-1, -3, 4, 7, -2, -1, -5, 3, and 1 of the original kernel 420 corresponding thereto, respectively, and -1, -6, 12, 28, -10, -6, -35, 24, and 9 can be obtained as multiplication results. Next, all the obtained values ​​-1, -6, 12, 28, -10, -6, -35, 24, and 9 can be summed to obtain 15, and the feature data 431 in the first row and the first column of the output feature map 430 can be determined to be 15. Here, the feature data 431 in the first row and the first column of the output feature map 430 can correspond to the first extracted data 411. Similarly, a convolution operation can be performed between the second extracted data 412 of the input feature map 410 and the original kernel 420, so that the feature data 432 in the first row and the second column of the output feature map 430 can be determined to be 4. Finally, a convolution operation may be performed between the sixteenth extracted data 413 as the final extracted data of the input feature map 410 and the original kernel 420 , so that the feature data 433 in the fourth row and fourth column of the output feature map 430 may be determined to be 11.

[0083] In other words, the convolution operation between the input feature map 410 and the original kernel 420 may be performed by repeatedly multiplying the extracted data of the input feature map 410 and the weight value of the original kernel 420 corresponding thereto and summing the multiplication results, and / or the output feature map 430 may be generated as a result of the convolution operation.

[0084] In some example embodiments, Figure 1The arithmetic circuit 140 of the illustrated nonvolatile memory device 100 may perform a convolution operation. For example, the arithmetic input data DATA_EX may constitute the input feature map 410 , and / or the arithmetic internal data DATA_IN may constitute the original kernel 420 .

[0085] Fig. 9 is a diagram of a computing circuit included in a nonvolatile memory device according to some example embodiments. Fig. 9 The calculation circuit shown is merely an example, and the calculation circuit according to some example embodiments of some inventive concepts may not be limited thereto and may have various configurations. Fig. 9 , a first arithmetic operation of a neural network using the first arithmetic internal data DATA_IN1 and / or the first arithmetic input data DATA_EX1 is described as an example, but some example embodiments of some inventive concepts may not be limited thereto and may also be applied to a kth arithmetic operation of a neural network using the kth arithmetic internal data DATA_INk and / or the kth arithmetic input data DATA_EXk.

[0086] Figure 2 and Fig. 9 An example is shown in which the first arithmetic input data DATA_EX1 is received by the memory device 100 and / or the first arithmetic internal data DATA_IN1 is transmitted by the memory cell array 110. However, the same description may apply to the second to kth arithmetic internal data DATA_IN2 to DATA_INk and / or the second to kth arithmetic input data DATA_EX2 to DATA_EXk.

[0087] The computation circuit 141' may include a multiplication and accumulation circuit (MAC). Fig. 9 A case where the calculation circuit 141' includes one MAC is shown, but some example embodiments of some inventive concepts may not be limited thereto, and / or the calculation circuit 141' may include a plurality of MACs. For example, the first arithmetic input data DATA_EX1 may be j-bit data (here, j is a natural number), and the first arithmetic internal data DATA_IN1 may be j-bit data. For example, each of the first arithmetic input data DATA_EX1 and the first arithmetic internal data DATA_IN1 may be 8-bit data.

[0088] The calculation circuit 141' may perform a multiplication operation and / or an addition operation using the first arithmetic input data DATA_EX1 and / or the first arithmetic internal data DATA_IN1, and / or may generate and / or output the first arithmetic result data DATA_R1. For example, the first arithmetic result data DATA_R1 may be 2j-bit data or (2j+1)-bit data.

[0089] In some example embodiments, the calculation circuit 141' may include a multiplier 141_1, an adder 141_2, and / or a register 141_3. The calculation circuit 141' may perform a multiplication operation using the multiplier 141_1 and / or accumulate data using the adder 141_2 and / or the register 141_3.

[0090] The multiplier 141_1 may multiply the first arithmetic input data DATA_EX1 by the first arithmetic internal data DATA_IN1 , generate multiplication data DATA_mul, and / or provide the multiplication data DATA_mul to the adder 141_2 .

[0091] The register 141_3 may temporarily store arithmetic data and may provide the stored arithmetic data to the adder 141_2 as accumulation data DATA_acc.

[0092] The adder 141_2 may add the multiplication data DATA_mul and the accumulation data DATA_acc provided by the register 141_3, and / or generate updated data DATA_upd. That is, the adder 141_2 may add the multiplication data DATA_mul and the arithmetic data provided by the register 141_3, and may store the sum of the multiplication data and the arithmetic data. The register 141_3 may output the arithmetic data as the first arithmetic result data DATA_R1 at a point in time or during a point in time.

[0093] Fig.10 According to some example embodiments Figure 1 A detailed block diagram of a nonvolatile memory device 100 is shown. Fig.10 The nonvolatile memory device 100a and Figure 2 The same description is given in the nonvolatile memory device 100.

[0094] refer to Fig.10 , the nonvolatile memory device 100a may include a memory cell array 110, a page buffer 120, a row decoder circuit 130, an arithmetic circuit 140, a control logic circuit 150a, an I / O circuit 160, and / or a counting circuit 170a. Although the counting circuit 170a is shown as an additional circuit component, the counting circuit 170a may be included in the control logic circuit 150a and / or may perform a counting operation inside the control logic circuit 150a.

[0095] The counting circuit 170a may receive the clock signal CLK and / or may sequentially receive the first to k-th arithmetic input data DATA_EX1 to DATA_EXk. In some example embodiments, the counting circuit 170a may count the number of clock signals from a time point when the first arithmetic input data DATA_EX1 is received by the memory device 100a, and / or may provide the count value CNT to the control logic circuit 150a. In some example embodiments, the clock signal CLK may be a signal generated inside the nonvolatile memory device 100a.

[0096] The control logic circuit 150a may generate first to k-th data ready signals RS1 to RSk based on the count value CNT, and / or may output the first to k-th data ready signals RS1 to RSk to the arithmetic circuit 140. The arithmetic control signal CTRL_ar may include the first to k-th data ready signals RS1 to RSk. Fig.10 The first to kth data ready signals RS1 to RSk are illustrated as separate signals, but some example embodiments of some inventive concepts may not be limited thereto, and each of the first to kth data ready signals RS1 to RSk may be provided as the same data ready signal.

[0097] The arithmetic circuit 140 may perform a first arithmetic operation of a neural network on the first arithmetic input data DATA_EX1 and / or the first arithmetic internal data DATA_IN1 in response to the first data ready signal RS1, and / or may perform a kth arithmetic operation of a neural network on the kth arithmetic input data DATA_EXk and / or the kth arithmetic internal data DATA_INk in response to the kth data ready signal RSk.

[0098] The nonvolatile memory device 100a according to some example embodiments may (eg, from Figure 1 The memory controller 200 in the nonvolatile memory device 100a receives an arithmetic input data signal including first to k-th arithmetic input data DATA_EX1. In order to perform each of the first to k-th arithmetic operations of the neural network, the nonvolatile memory device 100a may divide each of the first to k-th arithmetic input data DATA_EX1 from the arithmetic input data signal using a counting circuit 170a.

[0099] The counting circuit 170a may be implemented in various types in the nonvolatile memory device 100a. In some example embodiments, the counting circuit 170a may be implemented in a hardware type or a software type. For example, when the counting circuit 170a is implemented in a software type, a program (or instruction) and / or a random I / O code stored in the nonvolatile memory device 100a may be executed by the control logic circuit 150a or at least one processor included in the nonvolatile memory device 100a to perform a counting operation.

[0100] Fig.11 It is shown Figure 3 1. A flowchart of a method of operating a nonvolatile memory device according to some example embodiments of the present invention is shown in FIG. 1. Operation S130 may include operation S131, operation S133, and / or operation S135. Although reference is made to Fig.11 , an operation of receiving the first arithmetic input data DATA_EX1 is described as an example, but some example embodiments of some inventive concepts may not be limited thereto. For example, the operation of receiving the arithmetic input data may include an operation of receiving the kth arithmetic input data DATA_EXk.

[0101] refer to Fig.10 and Fig.11 In operation S131, the nonvolatile memory device 100a may count the clock signal during reception of the arithmetic input data. For example, the clock signal may be counted starting from a time point when the first arithmetic input data DATA_EX1 is received.

[0102] In operation S133, the nonvolatile memory device 100a may compare the count value obtained by counting the clock signal with the reference value, and / or may determine whether the count value reaches the reference value. The reference value may be an expected value and / or a preset value. When the clock signal is counted until the count value reaches the reference value, it may be determined that the arithmetic input data has been received in terms of such a number of bits for performing an arithmetic operation of the neural network. For example, when the count value of the clock signal is 8, it may be determined that the nonvolatile memory device 100a has received all of the first arithmetic input data DATA_EX1.

[0103] In some example embodiments, after the count value reaches the reference value, the nonvolatile memory device 100a may reset the count value and may count the clock signal again (S131) ​​to determine whether the count value reaches the reference value (S133). Therefore, when the count value first reaches the reference value, the nonvolatile memory device 100a may determine that all of the first arithmetic input data DATA_EX1 has been received. When the count value reaches the reference value after the count value is reset, the nonvolatile memory device 100 may determine that all of the second arithmetic input data DATA_EX2 has been received.

[0104] In some other example embodiments, after the count value reaches the first reference value, the nonvolatile memory device 100a may count the clock signal (S131), and determine again whether the count value reaches a second reference value higher than the first reference value (S133). Therefore, when the count value reaches the first reference value, the nonvolatile memory device 100a may determine that all of the first arithmetic input data DATA_EX1 has been received. In addition, when the count value reaches the second reference value, the nonvolatile memory device 100a may determine that all of the second arithmetic input data DATA_EX2 has been received.

[0105] In operation S135, when the count value reaches the reference value, the nonvolatile memory device 100a may generate a data ready signal. For example, when the count value reaches the reference value and it is determined that all of the first arithmetic input data DATA_EX1 is received, the nonvolatile memory device 100a may generate a first data ready signal. The nonvolatile memory device 100a may perform a first arithmetic operation of a neural network on the first arithmetic input data DATA_EX1 and / or the first arithmetic internal data DATA_IN1 in response to the first data ready signal.

[0106] Fig. 12A and Fig. 12B is a timing diagram illustrating arithmetic operations of a neural network using a nonvolatile memory device according to some example embodiments. Fig.10 The nonvolatile memory device 100a describes Fig. 12A and 12B , but a similar description can be applied to Figure 2 The non-volatile memory device 100. Fig. 12A and Fig. 12B , the description of the operation on the first arithmetic internal data DATA_IN1 can be applied to the operation on the kth arithmetic internal data DATA_Ink. Similarly, the description of the operation on the first arithmetic input data DATA_EX1 can also be applied to the operation on the kth arithmetic input data DATA_EXk.

[0107] refer to Fig.10 and Fig. 12A , when the arithmetic command CMD_ar and / or the arithmetic information signal IN_p are received through the I / O circuit 160 (reference time point T_D), an operation of receiving the first arithmetic input data DATA_EX1 may start, and / or an operation of reading the first arithmetic internal data DATA_IN1 may start. That is, the operation of receiving the first arithmetic input data DATA_EX1 and / or the operation of reading the first arithmetic internal data DATA_IN1 may be performed serially, in parallel, partially serially and partially in parallel, etc.

[0108] When all the first arithmetic input data DATA_EX1 are received (reference time point T_l1), the first data ready signal RS1 may be generated and / or provided to the arithmetic circuit 140. For example, when all the first arithmetic input data DATA_EX1 are received, the first data ready signal RS1 may be changed from a low level to a high level. However, some example embodiments of some inventive concepts may not be limited thereto. For example, in some example embodiments, the first data ready signal RS1 may be changed from a high level to a low level. Similarly, although the first data ready signal RS1 to the kth data ready signal RSk are shown as separate signals, some example embodiments of some inventive concepts may not be limited thereto. For example, the first data ready signal RS1 to the kth data ready signal RSk may be provided as a single data ready signal.

[0109] In some example embodiments, after all the first arithmetic input data DATA_EX1 are received (reference time point T_l1), the operation of reading the first arithmetic internal data DATA_IN1 may be completed (reference time point T_R1). After the operation of receiving the first arithmetic input data DATA_EX1 and / or the operation of reading the first arithmetic internal data DATA_IN1 is completed (reference time point T_R1), the nonvolatile memory device 100a may perform the first arithmetic operation OP1 of the neural network on the first arithmetic input data DATA_EX1 and / or the first arithmetic internal data DATA_IN1. For example, the arithmetic circuit 140 may perform the first arithmetic operation OP1 of the neural network based on the time point T_l1 at which the first data ready signal RS1 is received and / or the time point T_R1 at which the operation of reading the first arithmetic internal data DATA_IN1 is completed.

[0110] After receiving all the first arithmetic input data DATA_EX1 used as operands of the first arithmetic operation of the neural network (reference time point T_l1), the nonvolatile memory device 100a may subsequently receive the second arithmetic input data DATA_EX2 used as operands of the second arithmetic operation of the neural network. In addition, with respect to the operation of reading the first arithmetic internal data DATA_IN1 (reference time point T_R1), the nonvolatile memory device 100a may simultaneously and / or subsequently perform an operation of reading the second arithmetic internal data DATA_IN2. Therefore, the operation of receiving the second arithmetic input data DATA_EX2 and / or the operation of reading the second arithmetic internal data DATA_IN2 may be performed serially, in parallel, partially serially and partially in parallel, etc. Similarly, the first arithmetic operation OP1 of the neural network may be performed serially, in parallel, partially serially and partially in parallel, etc.

[0111] When all the kth arithmetic input data DATA_EXk are received (reference time point T_lk), the first to kth arithmetic result data DATA_R1 to DATA_Rk stored in the buffer 143 may be sequentially output through the I / O circuit 160. In some example embodiments, while the first arithmetic result data DATA_R1 is being output, an operation of reading arithmetic internal data, such as kth arithmetic internal data DATA_Ink, may be performed.

[0112] After the operation of reading the kth arithmetic internal data DATA_INk is completed (reference time point T_Rk), the kth arithmetic operation OPk of the neural network may be performed. In some example embodiments, while the first arithmetic result data DATA_R1 is being output, the arithmetic operation of the neural network, for example, the kth arithmetic operation OPk of the neural network may be performed on the kth arithmetic input data DATA_EXk and / or the kth arithmetic internal data DATA_INk.

[0113] refer to Fig.10 and Fig. 12B, after the operation of reading the first arithmetic internal data DATA_IN1 is completed (reference time point T_R1'), all the first arithmetic input data DATA_EX1 may be received (reference time point T_l1'). After all the operations of receiving the first arithmetic input data DATA_EX1 (reference time point T_l1') and / or the operation of reading the first arithmetic internal data DATA_IN1 (reference time point T_R1') are completed, the nonvolatile memory device 100a may perform the first arithmetic operation OP1 of the neural network on the first arithmetic input data DATA_EX1 and / or the first arithmetic internal data DATA_IN1. That is, the first arithmetic operation OP1 of the neural network may be performed based on a later completion point (e.g., Fig. 12A T_R1 or Fig. 12B T_l1') is used to perform the first arithmetic operation OP1 of the neural network.

[0114] When all the k-th arithmetic input data DATA_EXk are received (reference time point T_lk'), the first to k-th arithmetic result data DATA_R1 stored in the buffer 143 may be sequentially output through the I / O circuit 160. In some example embodiments, while the first arithmetic result data DATA_R1 is being output, the nonvolatile memory device 100a may perform an arithmetic operation of a neural network, for example, a k-th arithmetic operation OPk of a neural network may be performed on the k-th arithmetic input data DATA_EXk and / or the k-th arithmetic internal data DATA_INk.

[0115] The nonvolatile memory device 100a according to some example embodiments of some inventive concepts may perform an operation of receiving arithmetic input data, an operation of reading arithmetic internal data from the memory cell array 110, and / or at least two instances of arithmetic operations of a neural network using the arithmetic input data and the arithmetic internal data in series, in parallel, partially in series and partially in parallel, etc. Therefore, the time taken for the nonvolatile memory device 100a to simultaneously and / or sequentially perform the first to k-th arithmetic operations OP1 to OPk of the neural network and output the first to k-th arithmetic result data DATA_R1 to DATA_Rk to the memory controller may be reduced, and thus the processing time of the neural network may be reduced.

[0116] Fig.13 is a block diagram of an SSD system 1 according to some example embodiments.

[0117] refer to Fig.13, the SSD system 1 may include a host 2000 and / or an SSD 1000. The SSD 1000 may send a signal to the host 2000 and / or receive a signal from the host 2000 through a signal connector.

[0118] The host 2000 may provide data DATA and / or a request REQ to the SSD controller 1100. For example, the host 2000 may provide a request REQ (e.g., a read request, a write request, or an arithmetic request) for the data DATA to the SSD controller 1100. In addition, the host 2000 may provide a command, an address, and / or priority information to the SSD controller 1100, but is not limited thereto. The host 2000 and the SSD controller 1100 may exchange data and signals with each other based on at least one of various interface protocols, such as a Universal Serial Bus (USB) protocol, a MultiMedia Card (MMC) protocol, a Serial Advanced Technology Attachment (SATA) protocol, a Parallel-ATA (PATA) protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, and an Integrated Drive Electronics (IDE) protocol. The host 2000 may be implemented as a system-on-chip (SoC) or an application processor including a central processing unit (CPU) and / or a graphics processing unit (GPU) together with the SSD controller 1100 .

[0119] The SSD 1000 may include an SSD controller 1100 and / or a plurality of nonvolatile memory devices (eg, 1200 and 1300 ). The SSD controller 1100 may include a neural network processing circuit 1110 .

[0120] The neural network processing circuit 1110 may generate a neural network, train (or learn) a neural network, perform arithmetic operations of the neural network based on received input data, generate information signals based on the results of the arithmetic operations of the neural network, and / or retrain the neural network. The neural network processing circuit 1110 may include at least one processor configured to perform arithmetic operations according to a model of the neural network. The neural network processing circuit 1110 may be otherwise referred to as a neural network processing device, a neural network integrated circuit (IC), or a neural network processing unit (NPU).

[0121] The neural network processing circuit 1110 may receive various kinds of input data and / or may generate information signals based on the input data. In some example embodiments, the input data received by the neural network processing circuit 1110 may be arithmetic result data received from the nonvolatile memory device 1300 including the arithmetic circuit 1310 .

[0122] The neural network processing circuit 1110 may cause the arithmetic circuit 140 to perform an arithmetic operation of the neural network on the input data. For example, the neural network processing circuit 1110 may generate an information signal that causes the arithmetic circuit 140 to perform an arithmetic operation of the neural network on the arithmetic input data and the arithmetic internal data. In some example embodiments, the arithmetic operation of the neural network may include a convolution operation. The information signal generated by the neural network processing circuit 1110 may include at least one of various kinds of recognition signals, such as a speech recognition signal, an object recognition signal, an image recognition signal, and / or a biometric information recognition signal. For example, the neural network processing circuit 1110 may receive frame data included in a video stream as input data, and / or may generate a recognition signal of an object included in an image represented by the frame data based on the frame data. However, some example embodiments of some inventive concepts may not be limited thereto. For example, the neural network processing circuit 1110 may receive various kinds of input data and / or may generate a recognition signal based on the input data.

[0123] Some nonvolatile memory devices (eg, 1300) among the plurality of nonvolatile memory devices (eg, 1200 and 1300) included in the SSD 1000 may be nonvolatile memory devices 1300 including an arithmetic circuit 1310, which may refer to a nonvolatile memory device including a processor. Figures 1 to 13 The examples shown are implemented in some example embodiments.

[0124] In some example embodiments, the term "circuit" and various components (including but not limited to memory devices such as non-volatile memory 100; row decoder circuit 130; arithmetic circuit 140, 1310; computing circuit 141; control logic circuit 150, 150a; I / O circuit 160; counting circuit 170a; memory controller 200; and / or neural network processing circuit) may include one or more forms of processing circuits, such as logic circuits; hardware / software combinations such as processors that execute software; or combinations thereof. In some example embodiments, the term "circuit" and such various components may include but are not limited to a central processing unit (CPU), an arithmetic logic unit (Arithmetic Logic Unit, ALU), a digital signal processor, a microcomputer, a field programmable gate array (Field Programmable Gate Array, FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC), etc. According to some example embodiments, the term "circuit" and such various components may be implemented as hardware and / or software. For example, when the computing circuit 141 is implemented as hardware, the computing circuit 141 may include a circuit configured to perform arithmetic operations of a neural network. As another example, when the computing circuit 141 is implemented as software, the program (or instruction) and / or I / O code stored in the non-volatile memory device 100 may be executed by the computing circuit 141 or at least one processor included in the non-volatile memory device 100 to perform arithmetic operations of a neural network. However, some example embodiments of some inventive concepts may not be limited to the above-described example embodiments. For example, the term "circuit" and such various components may be implemented as a combination of software and hardware, such as firmware in which instructions are written to a read-only memory, a write-once-read-many (WORM) memory, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. All such interpretations that are reasonable and logically possible and do not contradict other statements are intended to be included in the present disclosure, the scope of which should be understood to be limited only by the claims.

[0125] Some example embodiments of some inventive concepts are disclosed in the above description and accompanying drawings. Although specific terms are used, they are used in a general and descriptive sense only and not for limiting purposes. It will be understood by those of ordinary skill in the art that various changes in form and details may be made to the disclosed examples without departing from the spirit and scope of some example embodiments of some inventive concepts defined by the appended claims.

[0126] As used herein, terms such as "when..." and "at the same time" may, but are not necessarily intended to, imply a temporal relationship, such as the order of events. For example, an operation described as occurring "when" or "at" a condition being satisfied may be performed simultaneously with the satisfaction of the condition, or during the satisfaction of the condition, or after the satisfaction of the condition, or because the condition is satisfied or has been satisfied, etc. Similarly, phrases such as "under the condition of..." that associate an operation with a condition may indicate that the operation is performed simultaneously with the satisfaction of the condition, or during the satisfaction of the condition, or after the satisfaction of the condition, or because the condition is satisfied or has been satisfied, etc. As used herein, "simultaneously" and "in parallel" may refer to two or more operations, activities, and / or events occurring simultaneously, and / or (e.g., in an at least partially overlapping and / or interlaced manner) two or more operations, activities, and / or events occurring concurrently and / or simultaneously. All such interpretations that are reasonable and logically possible and not inconsistent with other statements are intended to be included in the present disclosure, the scope of which should be understood to be limited only by the claims.

[0127] Each of the flowcharts presented and discussed herein depicts a set of operations arranged in a particular order. However, it should be understood that the arrangement of the operations in each flowchart depicts only one example, and operations may be added, removed, reordered, and / or performed simultaneously in accordance with the subject matter of the present disclosure. For example, Figure 3 The operation S110 of receiving an arithmetic command is included, followed by the operation S120 of reading arithmetic data and the operation S130 of receiving an arithmetic input. However, in some example embodiments, the operation S110 may occur simultaneously with one or both of S120 and / or S130 and / or after one or both of S120 and / or S130. All such variations that are reasonable and logically possible and not inconsistent with other statements are intended to be included in the present disclosure, the scope of which should be understood to be limited only by the claims.

Claims

1. A non-volatile memory device, comprising: a memory cell array, wherein arithmetic internal data is written into the memory cell array; as well as The arithmetic circuit is configured as follows: receiving arithmetic input data and arithmetic internal data for an arithmetic operation of the neural network using the arithmetic internal data and the arithmetic input data in response to an arithmetic command, wherein the arithmetic internal data includes first arithmetic internal data written to a first page of the memory cell array and used as an operand for a first arithmetic operation of the neural network, and second arithmetic internal data written to a second page of the memory cell array and used as an operand for a second arithmetic operation of the neural network, performing an arithmetic operation of the neural network using the arithmetic internal data and the arithmetic input data to generate arithmetic result data, and Arithmetic result data of an arithmetic operation of a neural network is output, wherein the nonvolatile memory device is configured to (i) receive an arithmetic information signal including a first address indicating a first page, and (ii) sequentially read first arithmetic internal data and second arithmetic internal data in response to an arithmetic command and the arithmetic information signal.

2. The nonvolatile memory device according to claim 1, wherein: Arithmetic circuits include, a calculation circuit configured to perform an arithmetic operation and generate arithmetic result data; as well as A buffer is configured to store arithmetic result data.

3. The nonvolatile memory device according to claim 2, wherein: The buffer is configured to output arithmetic result data upon receiving second arithmetic input data for a second arithmetic operation of the neural network.

4. The nonvolatile memory device according to claim 1, wherein: The arithmetic information signal also includes a second address indicating a second page.

5. The nonvolatile memory device according to claim 1, wherein: The arithmetic information signal also includes the number of pages to be read for arithmetic operations of the neural network.

6. The nonvolatile memory device according to claim 1, wherein: The arithmetic circuit is further configured to perform the arithmetic operation in parallel with receiving second arithmetic input data for a second arithmetic operation of the neural network.

7. The nonvolatile memory device according to claim 1, wherein: The arithmetic circuit is further configured to perform the arithmetic operation in parallel with reading the second arithmetic internal data for the second arithmetic operation of the neural network.

8. The nonvolatile memory device according to claim 1, wherein: The arithmetic circuit includes a multiplication and accumulation circuit, wherein the multiplication and accumulation circuit is configured to perform a multiplication operation and an accumulation operation of the neural network using the arithmetic internal data and the arithmetic input data.

9. The nonvolatile memory device according to claim 8, wherein: The multiplication and accumulation circuit comprises, a multiplier configured to multiply the arithmetic internal data by the arithmetic input data and generate multiplication data; registers, configured to temporarily store arithmetic data; as well as An adder configured to store a sum of the multiplication data and the arithmetic data in a register.

10. A non-volatile memory device comprising: a memory cell array, wherein arithmetic internal data is written into the memory cell array; an arithmetic circuit configured to perform an arithmetic operation using a plurality of operands to generate arithmetic result data; The control logic circuit is configured to: receiving arithmetic commands for processing arithmetic operations of a neural network, In response to an arithmetic command, reading arithmetic internal data written to the memory cell array, generating an arithmetic control signal, wherein the arithmetic control signal causes the arithmetic circuit to perform an arithmetic operation for processing the neural network using a plurality of operands including arithmetic internal data and arithmetic input data, wherein the control logic circuit generates the arithmetic control signal under the condition that the size of the arithmetic internal data corresponds to the size of the arithmetic input data, and outputting arithmetic result data of the arithmetic operation of the neural network; and The counting circuit is configured to count the clock signal while the nonvolatile memory device receives arithmetic input data, wherein the control logic circuit generates the arithmetic control signal based on the counting result of the counting circuit.

11. The nonvolatile memory device according to claim 10, wherein: Arithmetic circuits include, a computing circuit configured to perform arithmetic operations of the neural network and generate arithmetic result data, and A buffer is configured to temporarily store the arithmetic result data and output the arithmetic result data in response to the arithmetic control signal.

12. The nonvolatile memory device according to claim 10, wherein: The arithmetic circuit is further configured to perform an arithmetic operation of the neural network in parallel with the non-volatile memory device receiving second arithmetic input data for a next arithmetic operation of the neural network.

13. The nonvolatile memory device according to claim 10, wherein: The arithmetic circuit is also configured to perform an arithmetic operation of the neural network in parallel with the memory cell array sending arithmetic internal data for a next arithmetic operation of the neural network to the arithmetic circuit.

14. A neural network system configured to perform arithmetic operations of a neural network, the neural network system comprising: a memory controller configured to generate an arithmetic command to perform an arithmetic operation, and to send the arithmetic command and arithmetic input data; as well as A memory device, configured to Receives arithmetic commands and arithmetic input data, In response to an arithmetic command, the arithmetic internal data written into the memory cell array is read, Generates an arithmetic control signal under the condition that the size of the arithmetic internal data corresponds to the size of the arithmetic input data In response to an arithmetic control signal, performing an arithmetic operation using the arithmetic input data and the arithmetic internal data, and Output the arithmetic result data of the arithmetic operation of the neural network, wherein the memory device comprises a counting circuit configured to count a clock signal while the memory device receives arithmetic input data, and Wherein, the memory device is configured to generate an arithmetic control signal based on a counting result of the counting circuit.

15. The neural network system according to claim 14, wherein: The memory device is a solid state drive SSD.

16. The neural network system according to claim 14, wherein: The memory device performs output by sending the arithmetic result data to the memory controller.

17. The neural network system according to claim 14, wherein: The memory device also includes: a computing circuit configured to perform arithmetic operations of the neural network and generate arithmetic result data; and A buffer is configured to store arithmetic result data.

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