Electronic chip memory

Abstract

The present disclosure relates to electronic chip memory. A device includes at least three memory cells. For each cell, there is a first doped semiconductor region and a switch coupling the cell to the first region. The first doped semiconductor region connects the first regions together. A memory may include a plurality of devices. For example, the cells may be arranged in a matrix, with each device defining a row of the matrix.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of French Patent Application No. 1873830 filed on December 21, 2018, which is hereby incorporated herein by reference.

[0003] This application is related to French Patent Application No. 1873848 and French Patent Application No. 1873833 filed on December 21, 2018, which are hereby incorporated by reference. U.S. Patent Application No. xx / xxx,xxx claims priority from French Patent Application No. 1873848, and U.S. Patent Application No. xx / xxx,xxx claims priority from French Patent Application No. 1873833. Technical Field

[0004] The present disclosure relates generally to electronic devices, such as memory. Background Art

[0005] The memory usually comprises memory cells which are arranged roughly in a matrix. In an irreversibly programmable memory, each cell can initially be programmed only once. After the only programming, the irreversibly programmable cell is no longer programmable and is accessible as a read-only memory, so the memory becomes a dead memory.

[0006] Typically, a generator having a physically unclonable function is used to encrypt data in a memory in order to protect the memory from being accessed by unauthorized persons.

[0007] It would be desirable to be able to improve protection against attacks aimed at obtaining data stored in memory, in particular dead memory. Summary of the invention

[0008] The present disclosure relates generally to electronic devices, and in particular to electronic chips for integrated circuits. Typically, the present disclosure relates to memories, such as irreversibly programmable memories, and to generators having physically unclonable functions.

[0009] One embodiment addresses some or all of the deficiencies of known memories, such as known irreversibly programmable memories.

[0010] One embodiment addresses some or all of the deficiencies of known generators with physically unclonable functions.

[0011] According to one aspect, an embodiment provides a device comprising at least three memory cells. For each cell, there is a first doped semiconductor region and a switch coupling the cell to the first region. The first doped semiconductor region connects the first regions together.

[0012] According to one embodiment, the first zone and the first region are located in the same semiconductor layer, preferably, the semiconductor layer covers the insulating layer.

[0013] According to an embodiment, the device further comprises conductive tracks connecting the first regions together.

[0014] According to one embodiment, each switch comprises a transistor having a gate which is discontinuous and has a co-linear elongated shape.

[0015] According to one embodiment, each cell comprises one or more irreversibly programmable memory points, each memory point comprising a second semiconductor region and a gate located on the second region.

[0016] According to one embodiment, a device includes a conductive region defining a gate of a memory point.

[0017] According to one embodiment, the conductive region and the gate of the transistor have the same direction of elongation.

[0018] Another embodiment provides a memory comprising a device as defined above.

[0019] According to one embodiment, the cells are arranged in a matrix, each device defining a row of the matrix.

[0020] According to one embodiment, two adjacent rows are arranged symmetrically about the axis.

[0021] According to one embodiment, the conductive areas of two adjacent rows constitute a common conductive area.

[0022] According to one embodiment, the second regions of two memory points respectively located in two adjacent rows and in the same column of the matrix alternately contact the second and third semiconductor regions arranged on both sides of the vertical alignment with the common conductive region.

[0023] According to one embodiment, the memory comprises conductive tracks connecting together the gates of the transistors of the columns of the matrix.

[0024] According to one embodiment, a memory includes a selection circuit for selecting one of cells and for programming the selected cell.

[0025] According to another aspect, an embodiment provides a device including a parallel connection of first and second irreversibly programmable memory points and a series connection of a first switch.

[0026] According to one embodiment, the device includes two nodes for temporarily applying a voltage for programming a memory point, the two nodes being coupled in series.

[0027] According to one embodiment, the connection node between the shunt connection and the first switch comprises a first doped semiconductor region connecting a storage point.

[0028] According to one embodiment, the first switch is connected to a central part of the first area.

[0029] According to one embodiment, the connection node further comprises a second doped semiconductor region connecting the first switch to the first storage point.

[0030] According to an embodiment, the device further includes a third doped semiconductor region connected to the second storage point, and a second switch connected to the third region.

[0031] According to one embodiment, the device comprises an additional switch connected to a central part of the first area.

[0032] According to one embodiment, each memory node includes a semiconductor region and a gate located on the semiconductor region.

[0033] According to one embodiment, the device includes a conductive region defining a gate of a memory point.

[0034] According to one embodiment, the first and second regions are located respectively on either side of a vertical alignment with the conductive region.

[0035] Another embodiment provides an electronic chip comprising one or more devices as defined above.

[0036] According to one embodiment, the chip further comprises components, each component comprising a memory cell and a switch, the components and devices being arranged in the same matrix, the space occupied by one of the devices being the same as the space occupied by two of the components located at adjacent spaces of the matrix.

[0037] According to one embodiment, the chip further includes a circuit configured to select one of the devices and provide a logic value based on a comparison between currents flowing in the first and second switches of the selected device.

[0038] According to one embodiment, in each of the devices, only one of the first and second memory points is in a programmed state.

[0039] Another embodiment provides a method for programming a device as defined above.

[0040] According to one embodiment, the method comprises temporarily applying a voltage for programming a memory point at a terminal of the series connection.

[0041] Another embodiment provides a method for reading a programmed value in a device as defined above.

[0042] According to one embodiment, the method comprises a comparison of the measured resistance value of the series connection with a threshold value.

[0043] According to another aspect, an embodiment provides a device comprising: irreversibly programmable memory points, each memory point comprising a first semiconductor region and a gate located on the first region; a conductive region defining the gate of the memory point; and a first semiconductor region and a second semiconductor region respectively located on both sides of a vertical alignment with the conductive region, the first region alternately contacting the first region and the second region.

[0044] According to an embodiment, the device comprises, for each of the first regions, a second doped semiconductor region in electrical contact only with the first region.

[0045] According to one embodiment, the isolation trench separates the first region.

[0046] According to one embodiment, the width of the isolation trench below the conductive region is less than 300 nm.

[0047] According to one embodiment, a device includes a first switch and a second switch connected to a first region and a second region, respectively.

[0048] According to one embodiment, the first switch and the second switch include first and second transistors, respectively, the first and second transistors having drain regions defined by the first region and the second region, respectively.

[0049] Another embodiment provides an electronic chip comprising one or more devices as defined above.

[0050] According to an embodiment, in which the devices are arranged in a matrix, the conductive regions of the rows of the matrix form a common conductive region.

[0051] According to an embodiment, the chip further includes: for each of the devices, a third doped semiconductor region connected to the first switch; and additional doped semiconductor regions coupling the third regions of the rows of the matrix together.

[0052] According to one embodiment, the chip comprises conductive tracks each coupling together control of switches of a matrix column.

[0053] According to one embodiment, the chip includes circuitry for programming memory points.

[0054] According to one embodiment, the programming circuit is configured to select one of the devices and select a region among the first and second regions of the selected device and temporarily apply a voltage for programming a memory point between the selected region and a conductive region of the selected device.

[0055] According to one embodiment, the programming circuit is configured such that the programming voltage is supplied by a source external to the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The above and other features and advantages will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0057] Figure 1 A memory of the type to which the embodiments described below relate is partially and schematically shown;

[0058] Figure 2 A partial and schematic cross-sectional view showing a memory of the type to which the embodiments described below relate;

[0059] Figure 3 A partial and schematic top view of one embodiment of a memory is shown;

[0060] Figure 4 A partial and schematic top view of one embodiment of a memory is shown;

[0061] Figure 5 A partial and schematic top view of one embodiment of a device including a memory cell is shown;

[0062] Figure 6 Show Figure 5 partial and schematic cross-sectional views of the illustrated embodiments;

[0063] Figure 7 Show Figure 5 further partial and schematic cross-sectional views of the illustrated embodiment;

[0064] Figure 8 A partial and schematic top view of one embodiment of a memory is shown;

[0065] Fig. 9 schematically illustrates one embodiment of a device including a memory cell;

[0066] Fig.10 Show Fig. 9 a partial and schematic cross-sectional view of one example of a device of the type shown;

[0067] Fig.11schematically shows a circuit for reading the contents of a memory cell;

[0068] Fig.12 Show Fig. 9 a partial and schematic top view of one example of a device of the type shown;

[0069] Fig.13 A partial and schematic top view showing one embodiment of a memory cell; and

[0070] Fig.14 A partial and schematic top view of one embodiment of a memory is shown. DETAILED DESCRIPTION

[0071] In the various drawings, the same reference numerals refer to the same features. In particular, common structural and / or functional features may have the same reference numerals and may have the same structure, dimensions, and material properties between the various embodiments.

[0072] For the sake of clarity, only operations and elements useful for understanding the embodiments described herein are shown and described in detail. In particular, circuits for programming and / or reading a memory and circuits for controlling a switch are not described in detail, and the described embodiments are compatible with conventional circuits for programming and / or reading a memory and conventional circuits for controlling a switch.

[0073] Unless otherwise specified, when referring to two elements being connected together, this means being directly connected without any intermediate elements other than conductors; and when referring to two elements being linked or coupled together, this means that the two elements may be connected, or linked or coupled by means of one or more other elements.

[0074] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as terms "above", "below", "higher", "lower", etc., or directional qualifiers, such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figures.

[0075] Unless otherwise indicated, the expressions "approximately", "approximately", "substantially" and "about" mean within 10%, preferably within 5%.

[0076] Figure 1 A memory of the type to which the embodiments described below relate is schematically shown. Typically, the memory is contained in an electronic chip for an integrated circuit.

[0077] The memory includes components 100 (only one of the components is shown), each of which includes a memory cell 110 and a switch 120, which are electrically coupled in series between nodes HV and BL. Preferably, the switch 120 of each component 100 has a control terminal coupled to the node WL. The components 100 are generally arranged in a matrix. For example, the node HV is shared by all components 100. The components 100 are connected to a circuit 130 for programming and reading the memory, for example, the circuit 130 is shared by all components 100. During operation, the circuit 130 selects one of the components and programs the cell 110 of the selected component or reads the content of the cell.

[0078] For programming and reading, circuit 130 applies a potential, such as a positive potential, to node HV, which is referenced to a reference potential such as ground. Circuit 130 closes switch 120, i.e., makes switch 120 passable. Circuit 130 applies a potential, such as a reference potential, lower than the potential of node HV to node BL. As a result, circuit 130 applies a voltage between nodes HV and BL.

[0079] During programming of the memory cell 110, the voltage applied by the circuit 130 is a programming voltage, i.e., a voltage that, when temporarily applied to the cell 110, can cause a permanent (preferably irreversible) modification of a physical property of the memory cell. The physical property is preferably resistance. Preferably, the memory cell includes a dielectric between two electrodes 112, 114. Electrode 112 is coupled (preferably connected) to a node HV, and electrode 114 is coupled (preferably connected) to a switch 120. Thus, the programming voltage is a voltage that exceeds the breakdown voltage of the dielectric. For example, such a breakdown corresponds to the creation of a conductive path in the dielectric. Thus, the temporary application of the programming voltage causes an irreversible decrease in resistance between the electrodes. Thereby the memory cell is irreversibly programmed.

[0080] Preferably, the programming voltage is more than 3 times the voltage applied between nodes HV and BL in order to read the cell content, for example, the programming voltage is greater than 5 V, for example greater than 10 V. For example, the programming voltage is supplied to the circuit 130 by a source external to the electronic chip comprising the memory and the circuit 130. Thus, during the only programming of the memory, the source can be coupled to the circuit 130, while during reading, the source can be disconnected from the circuit 130.

[0081] To read the contents of memory cell 110, circuit 130 compares the resistance between nodes HV and BL to a threshold. The stored logic value is a function of the result of this comparison. Therefore, the voltage applied by circuit 130 is less than the breakdown voltage.

[0082] Figure 21 is a partial and schematic cross-sectional view of an example of a memory of the type to which the described embodiments relate. More specifically, the memory includes the memory described above with reference to Figure 1 The type of assembly 100 is described. The assembly 100 is Figure 2 is shown in .

[0083] The memory is formed in and on the front (top) of a (preferably semiconducting) substrate 202, for example made of silicon. Preferably, an electrically insulating layer 204 covers the top of the substrate 202, for example, the electrically insulating layer 204 is made of silicon oxide. The layer 204 is covered with a semiconductor layer 206, for example, the semiconductor layer 206 is made of silicon. Thus, the substrate 202, the layer 204 and the semiconductor layer 206 define a SOI type structure (semiconductor on insulator). A trench 208 is filled with an electrical insulator, for example, with silicon oxide, which trenches 208 define portions of the layer 206 in each component 100. The trenches 208 isolate the portions from each other. For example, the trenches 208 extend from the front of the layer 206, through the layers 206 and 204 to a level located in the substrate 202.

[0084] The memory cell 110 comprises a gate 210 and a gate insulator 212 covered by the gate 210, the gate insulator 212 being located on a semiconductor region 214 of the layer 206 portion. Preferably, the gate 210, the gate insulator 212 and the region 214 of the memory cell are arranged in the same or similar manner as the gate, the gate insulator and the region for forming a channel of a field effect transistor type structure (e.g., of the MOS type), respectively. The gate 210 is coupled, preferably connected, to a node HV.

[0085] The switch 120 comprises a MOS field effect transistor 120T, which comprises a gate 220 and a gate insulator 222 covered by the gate 220, the gate insulator 222 being located on a semiconductor region 224 of the layer 206 portion. This region 224 corresponds to the region of the transistor for forming a channel. The gate 220 is coupled, preferably connected, to the node WL.

[0086] Preferably, regions 224 and 214 occupy layer 206 along the entire thickness of layer 206. Regions 224 and 214 define regions 230, 232, and 234 in a portion of layer 206. Regions 230 and 232 are located on both sides of the vertical alignment with gate 210. Regions 232 and 234 define the drain region and source region of transistor 120T, respectively. Source region 234 is coupled, preferably connected to node BL. Transistor 120T is preferably N-channel, while regions 232 and 234 are p-type doped. Thus, region 230 is preferably p-type doped.

[0087] During operation, when transistor 120T is passable and a voltage is applied between nodes HV and BL, region 214 of memory cell 110 (made conductive by field effect) defines an electrode of the memory cell. Gate 210 defines the other electrode. Gate insulator 212 defines a dielectric in the memory cell, the breakdown of which corresponds to irreversible programming of the memory cell.

[0088] Although the transistors and memory cells described herein are located in or on SOI type structures, the embodiments are compatible with the structures of conventional field effect transistors. In addition, region 214 can be doped with the same conductivity type as region 232, so that when there is no field effect, region 214 also defines a conductive electrode connected to doped semiconductor region 232.

[0089] Although the reference Figure 2 An assembly comprising a specific memory cell and a specific switch is described, but the embodiments described below are compatible with conventional types of memory cells and switches coupled in series, preferably connected in series.

[0090] Figure 3 A partial and schematic top view of one embodiment of a memory is shown. More specifically, Figure 3 3. Device 300 is shown, and device 300 includes a plurality of memory cells 110, preferably at least three memory cells 110. For example, cells 110 are in rows of a memory cell matrix. For example, device 300 corresponds to a row of the matrix. Preferably, as described above with reference to Figure 2 As described, each cell 110 is coupled in series (e.g., connected in series) to a transistor 120T. Thus, when viewed from above, each transistor includes a source region 232 and a drain region 234 on either side of a gate 220. The source region 232 and the drain region 234 are preferably part of the same semiconductor layer 206 portion defined by the trench 208.

[0091] In this embodiment, the source regions 234 of the transistors 120T of the device 300 are all connected to each other through the semiconductor region 302. The region 302 is doped with the same conductivity type as the source region 234, preferably n-type doping. Preferably, the region 302 is part of the layer 206. The doping level of the region 302 is preferably about the doping level of the source region 234, for example, the doping level of the region 302 and the region 234 are the same. Thus, the regions 302 and 234 of all transistors of the device 300 form a single doped semiconductor region.

[0092] Preferably, the source 234 of the transistor is coupled to a common node BL. The node BL is preferably defined by a semiconductor track (not shown here). The conductive path is parallel to the row direction. The conductive track is located in an insulating layer covering the front face.

[0093] For example, the gate 220 of the transistor is coupled to a separate node, preferably each node is defined by a separate semiconductor track WLa, WLb, WLc (not shown here). For example, each of the conductive tracks WLa, WLb and WLc is parallel to the column direction of the matrix. These conductive tracks are located in an insulating layer covering the front.

[0094] An attacker may attempt to read the contents of memory cell 110. To this end, the attacker can remove elements of the memory located above the transistor (in the front of the figure), such as conductive tracks, to obtain direct access to the transistor and the memory cell. These elements are usually removed by ion beam etching. The attacker then uses, for example, a conductive head, which he connects to the gate and the semiconductor region. However, even if the conductive track has been removed, the source region 234 of the transistor is still electrically connected through region 302. Therefore, it is more difficult for an attacker to distinguish between different contents of adjacent memory points in a memory including device 300 than in a memory without region 302. Therefore, a memory including device 300 ensures a higher level of protection for the data it contains than in the case of a memory without region 302.

[0095] The gate 220 of each transistor 120T preferably has an elongated shape, such as a rectangle when viewed from above. The elongation of this shape is in the width direction of the transistor, that is, in a direction orthogonal to the drain-source direction. The elongated shape of the gate 220 of the transistor 120T of the device 300 is preferably collinear, that is, arranged along the same axis parallel to the matrix row, and is elongated in the direction of the axis. When viewed from above, the long sides of the rectangular shape of the gate 220 of the transistor are collinear. Therefore, the width direction of the transistor corresponds to the row direction of the matrix. Therefore, when viewed from above, the source region 234 is all located on the same side of the gate 220 of the transistor. Therefore, a particularly simple shape, such as a rectangle, can be given to the region 302.

[0096] As a variant, the width direction of the transistors may be in any direction, for example the column direction of a matrix, and the region 302 may have any shape making it possible to connect together all source regions of the transistors of the device 300 .

[0097] As a variant, each transistor 120T is replaced by two transistors coupled in series (preferably connected in series), and each track WLa, WLb, WLc is replaced by two tracks, each of which is coupled (preferably connected) to one of the two transistors. During operation, in order to close the switch 120 formed by two transistors in the series connection in this way, a potential between the ground potential and the potential of the node HV is applied to the two tracks in question. These potentials are selected to limit the voltage experienced by the gate insulator of each of the two transistors. Therefore, compared with transistors that withstand programming voltages between their gates and their drain / source regions, the two transistors can be implemented in a simpler way. Therefore, the gates of the transistors preferably have an elongated shape in the same direction. Similarly, in another variant, each switch 120 includes more than two transistors. Then, each track WLa, WLb, WLc is replaced by as many tracks as the transistors there are in each switch.

[0098] Figure 4 Shown including Figure 3 300. More specifically, each device 300 forms a row of a matrix. Although three rows are shown, the matrix may also include two rows or more than three rows. In this embodiment, each memory cell includes a Figure 2 Thus, each memory node comprises a gate 210 covering a zone 214 in contact with the zone 232 in question.

[0099] The gates 210 of the memory points of each row constitute a common conductive region 402. Preferably, the common conductive region 402 has the shape of a strip when viewed from above. The strip is preferably rectilinear and has the direction of the row as its main direction. The conductive region 402 is coupled to the node HV. In each row, the source regions 234 of the transistors are coupled to conductive tracks Bla, BLb, BLc, which connect them between all the regions 234 of the row.

[0100] When viewed from above, the conductive region 402 and the gate 220 of the transistor have the shape of a strip and a rectangle respectively, which are elongated in the same direction. In the example shown, this direction is the direction of the row. Therefore, the gates 402 and 220 are easily realized by conventional manufacturing methods of transistor gates.

[0101] Preferably, adjacent rows of the matrix are arranged symmetrically about an axis D orthogonal to the previous one (axis D is orthogonal to the plane of the figure and is shown as a dot). For example, adjacent rows are arranged symmetrically about a plane (not shown) transverse to axis D and parallel to the row direction. Thus, transistors 110 of two adjacent rows are located in a strip 404, and memory cells 406 of two adjacent rows are located in a strip 406.

[0102] Figure 5 , Figure 6 and Figure 7 A partial and schematic view of an embodiment of a device 500 including a memory cell is shown, respectively, a view from above, a view cut along plane S6-S6, and a view cut along plane S7-S7. More specifically, the device 500 includes two memory cells 110_1 and 110_2. The memory cells 110_1 and 110_2 are preferably adjacent in a memory cell matrix. The memory cells are symmetrical relative to each other, for example, about an axis D orthogonal to the front.

[0103] Each memory cell includes a doped semiconductor region, 232_1, 232_2, respectively. Regions 232_1 and 232_2 are coupled (preferably connected) to respective nodes BL1 and BL2 via respective switches 120_1 and 120_2.

[0104] exist Figure 5 Schematically shown are switches 120_1 and 120_2. The control terminals of switches 120_1 and 120_2 are coupled to nodes WL1 and WL2, respectively. The switches preferably have a reference Figure 1 and Figure 2 The same type of switch 120 as above. In particular, as Figure 6 As schematically shown in FIG. 1 , switches 120_1 and 120_2 include Figure 2 The elements of the switch 120 shown are identical or similar, and are arranged in an identical or similar manner. Thus, each switch 120_1, 120_2 comprises a conductive gate 220_1, 220_2, respectively, which is arranged on a gate insulator 222_1, 222_2, respectively, and the gate insulator 222_1, 222_2 covers a semiconductor region 224_1, 224_2, respectively. Each region 224_1, 224_2 is located between a source region (respectively 234_1, 234_2) and a corresponding region (respectively 232_1, 232_2). The gate 220_1 is coupled, preferably connected to a node WL1, and the region 234_1 is coupled to a node BL1. The gate 220_2 is coupled, preferably connected to a node WL2, and the region 234_2 is coupled to a node BL2.

[0105] In the cell 110_1, the region 232_1 is in contact with one or more (two in the example shown) semiconductor regions 214_1. Each region 214_1 is located below the conductive gate 210_1 and is separated from the gate 210_1 by a gate insulator 212_1. Each gate insulator 212_1 is in contact with the gate 210_1 in question and the region 214_1. The stack of regions 214_1, gate insulators 212_1 and gates 210_1 thus obtained is configured in such a way that a temporary application of a programming voltage between the gate 210_1 and the region 232_1 triggers a breakdown of the gate insulator, in a manner similar to that for Figure 2 The illustrated cell 110 is described in a similar manner. Thus, the stack corresponds to the memory point 502_1.

[0106] In cell 110_2, region 232_2 is in contact with one or more (two in the example shown) semiconductor regions 214_2. The number of regions 214_2 can be equal to or different from the number of regions 214_1. As with regions 214_1, each region 214_2 is located below a semiconductor gate 210_2 and is separated from the gate by a gate insulator 212_2. The gate insulator 212_2 is in contact with the gate 210_2 and the region 214_2. The stack of regions 214_2, insulator 212_2, and gate 210_2 is configured in the same manner as in cell 110_1, so that the stack corresponds to a memory point 502_2.

[0107] The gates 210_1 and 210_2 are aligned and are alternating parts of the same conductive region 510. The regions 214_1 and 214_2 are aligned and alternate under the region 510. The conductive region 510 preferably has an elongated shape in the form of a strip in the alignment direction of the gates 210_1 and 210_2, and thus the alignment direction of the regions 214_1 and 214_2. Thus, the region 510 passes in sequence along one of the regions 214_1 and then one of the regions 214_2 (preferably repeatedly). Preferably, when viewed from above, each of the gates 210_1 and 210_2 and the regions 214_1 and 214_2 substantially occupies the width of the strip. When viewed from above, the conductive region 510 covers the space between the doped semiconductor regions 232_1 and 232_2.

[0108] Preferably, each region 214_1 is in contact with a semiconductor region 230_1, which is located on the side of the region 214_1 opposite to the region 232_1. Preferably, each region 214_2 is in contact with a semiconductor region 230_2, which is located on the side of the region 214_2 opposite to the region 232_2. Preferably, the regions 232_1, 232_2 and the regions 230_1, 230_2 have the same conductivity type, such as n-type, and have the same doping level.

[0109] The region 232_1 and the entirety of the area 214_1 and possibly 230_1 are isolated from the region 232_2, the area 214_2 and possibly the entirety of 230_2. This isolation is achieved in particular by means of an isolation trench 514. The trench 514 comprises at least one portion which is located below the region 510.

[0110] Preferably, the regions 232_1, 232_2, and the regions 214_1, 214_2, 230_1, and 230_2 are part of the same semiconductor layer 206. Figure 6 2, for example, having an SOI type structure. Preferably, the source regions 234_1, 234_2 of the transistor are also part of the layer 206. The isolation trench 208 surrounds the layer portion 206 in and on which the device 500 is located. Preferably, the trench 514 has the same depth as the trench 208. The gate insulators 212_1 and 212_2 have the same breakdown voltage. For this purpose, preferably, the gate insulators 212_1 and 212_2 are the same insulating layer 512 ( Figure 7 ) part.

[0111] To program the cell 110_1, the switch 120_1 is closed by applying the control potential of the switch to the node WL1. A programming voltage exceeding the insulator breakdown voltage is applied. The region 214_1 is conductive or becomes conductive due to the field effect caused by the voltage applied between the gate 210_1 and the region 232_1. This triggers the breakdown of at least one of the insulators 212_1. The programming of the cell 110_2 is similar to the programming of the cell 120_1.

[0112] To read the content of cell 110_1, switch 120_1 is closed and the resistance value of the series connection of switch 120_1 and cell 110_1 is compared with a threshold value. The reading of the content of cell 110_2 is similar to the reading of the content of cell 110_1.

[0113] An attacker may try to read the contents of the memory cells 110_1 and 110_2 of the device 500. To this end, the attacker can remove the elements of the memory located above the region 510 defining the gates 502_1, 502_2 of the memory points (in the front of the figure) by means of, for example, an ion beam. However, even if the attacker manages to connect the conductive points to the conductive area 510, he cannot apply different potentials to the gate 210_1 of the cell 110_1 and the gate 210_2 of the cell 110_2. Therefore, it is difficult for the attacker to distinguish the different contents of the cells 110_1 and 110_2. Therefore, the memory cells of the device 500 have a higher level of protection of their contents than memory cells that do not include memory points whose gates are defined by a common conductive area.

[0114] Furthermore, the groove 514 preferably has a moderate width in the elongation direction of the region 510 (the longitudinal direction of the strip shape of the region 510), i.e. less than about 500 nm, for example less than 500 nm, even more preferably less than about 300 nm, for example less than 300 nm. Preferably, the width is less than the diameter of an ion beam potentially used by an attacker. Even if an attacker attempts to remove the portion of the region 510 located on the groove 514 using an ion beam in order to separate the gates 210_1, 210_2 from each other, he will not succeed in separating the gates 210_1, 210_2 without the risk of also removing portions of the gates 210_1, 210_2 and making the contents of the memory points 502_1, 502_2 unreadable. This achieves a particularly high level of protection for the data contained in the cell.

[0115] Preferably, in the case where the memory cell 110_1 comprises a plurality of memory points, the programming voltage is applied in such a way that when one of the gate insulators 212_1 breaks down, this triggers a reduction in the voltage applied to the other gate insulators 212_1, which voltage reduction is sufficient to avoid the breakdown of the other gate insulators. For example, a resistor is provided in series with the switch 120_1 and the memory cell 110_1, which is capable of causing this voltage reduction upon breakdown. Thus, only one of the memory points of the cell is programmed. As a variant, any other method of only breaking down one of the gate insulators 212_1 can be used. Preferably, in the case where the memory cell 110_2 comprises a plurality of memory points, the memory cell is programmed in the same way as the cell 110_1 by ensuring that only one of the gate insulators 212_2 is broken down.

[0116] Since in each cell 110_1, 110_2 the memory point of the cell is connected in parallel between the node HV and the region 232_1, 232_2, programming only one of the gate insulators is sufficient to reduce the resistance of the memory cell. Therefore, the value programmed in the memory cell can be read by comparing this resistance with a threshold value.

[0117] If the attacker succeeds in determining that one of the memory points 502_1, 502_2 is not programmed, he cannot infer that the memory cell 110_1 or 110_2 in question is not programmed. The attacker must successfully read the content of all memory points of a cell to infer the content stored in the cell from the content of all memory points. Therefore, the greater the number of memory points per memory cell, the longer and more difficult the attacker's work is, and the higher the level of protection of the data.

[0118] Figure 8 A partial and schematic top view of one embodiment of a memory 800 is shown. More specifically, the memory 800 includes Figure 5 , Figure 6 and Figure 7 A device 500 of the type shown and Figure 3 Devices 300 of the type shown. For example, three devices 500 are shown.

[0119] Device 500 is located in two adjacent rows of a memory cell matrix. Switch 120_1 and Figure 3 The switches of the device 300 of the type shown are identical or similar and are arranged in an identical or similar manner. In particular, the switch 120_1 includes a transistor 120T_1, the source regions 234_1 of the transistor 120T_1 being connected to each other via the region 302. The switch 120_2 and the Figure 3 The switches of the device 300 of the type shown are identical or similar and are arranged in an identical or similar manner. Likewise, the switch 120_2 comprises a transistor 120T_2 , the source regions 234_2 of which are connected to each other via a region 302 .

[0120] Preferably, the two adjacent rows shown are symmetrical relative to each other about an axis D orthogonal to the front. Preferably, on both sides of the row shown, the memory comprises other rows similar to the row shown. Therefore, preferably each device 300 is included as in reference Figure 4 In the defined bar 404.

[0121] Preferably, the two cells of each device 500 in the device 500 are located in the same column of the matrix. In each device 500, the gates 220_1 and 220_2 are coupled to each other, preferably by Figure 4 The defined lines WLa, WLb, WLc are coupled.

[0122] Since the memory 800 comprises both the device 300 and the device 500, it provides a particularly high level of protection against unauthorized persons reading the contents.

[0123] Preferably, the conductive regions 510 defining the gates 210_1 and 210_2 of the memory points constitute a common conductive region 810. The region 810 preferably has an elongated shape in the trench direction, for example a stripe shape extending in the row direction when viewed from above.

[0124] Thus, the region 810 electrically connects all gates of the memory points of two adjacent rows to each other. This represents an additional difficulty for an attacker trying to gain access to the memory contents. Thus, the level of protection can be increased by providing a common region 810 to prevent unauthorized persons from reading the contents of the memory.

[0125] Although specific examples of switches 120_1 and 120_2 have been described, these switches may be switches of any circuit, or be replaced by any circuit, which is configured to select one of the memory cells of the matrix, and program the selected cell and / or read data in the selected cell. For example, a memory including elements that are the same as the elements of the memory 800 and arranged in the same manner may be implemented, except that the region 302 is not provided. For example, the regions 234_1 and 234_2 of the same column of the matrix are therefore connected to each other by a track, and the gates 220_1 or 220_2 of the same row of the matrix are connected to each other by a track, or preferably, constitute a common conductive region.

[0126] Fig. 9 One embodiment of a device 900 including a memory cell 110A is schematically shown.

[0127] Memory cell 110A comprises two irreversibly programmable memory points 902 and 904 electrically connected in parallel between node 906 and node HV. The parallel connection and switch 120 are coupled in series, preferably connected in series between nodes HV and BL for applying a programming voltage.

[0128] Preferably, the resistance of each memory point 902, 904 is lower after programming than before programming. Preferably, each memory point comprises a dielectric, and programming of the memory point is achieved by breakdown of the dielectric. The dielectrics preferably have the same breakdown voltage.

[0129] In order to program the cell 110A, the programming voltage is preferably applied in such a way that the reduction in resistance of one of the memory points at the moment of its programming triggers a reduction in voltage at the terminal of the other memory point, which voltage reduction is sufficient to prevent the programming of the other memory point. This can be achieved, for example, by defining the resistance of the conductive element of the node 906, and / or the resistance of the switch 120 in a passable state, and / or the resistance of a resistor element, for example, external to the device 900. Thus, only one of the memory points 904 and 906 is programmed in the memory cell. Since the programming voltage is applied in parallel at the two memory points, the only memory point programmed in the cell is a random one or the other of the memory points 902, 904. The programming voltage can be applied in any other way, by means of which the possibility of programming two memory points at the same time can be limited.

[0130] It can be provided that a plurality of electronic chips are implemented, each electronic chip comprising one or more devices 900 and preferably a memory. The devices 900 of each chip are, for example, identical. The devices 900 of the chip are then programmed. After programming, the programmed memory points 902 or 904 are different in different chips.

[0131] A read circuit may also be provided in each chip, the read circuit being configured to supply, for each device 900, a value having a first logic level if one of the memory points is programmed and a second logic level if the other memory point is programmed. Fig.11 A specific example of a circuit for supplying such a value using device 900 is described. Each of the values ​​supplied by the reading circuit constitutes, for example, a bit of a unique code for each chip, the code corresponding to a physically unclonable function. Preferably, each chip uses this code to encrypt the data stored in its memory.

[0132] Thus, by means of this programming performed in the same manner on each device 900, one or the other of the memory points 902, 904 can be randomly programmed in each device. Thus, the bits of a physically unclonable function can be defined in a chip without providing the chip with information, such as random logic levels, originating from a device external to the chip and permitting the definition of these bits. An unauthorized person wishing to decrypt data stored in the chip memory will not be able to use an external device, or a communication link between an external device and the chip, to obtain the unique code of the chip. As a result, a chip using device 900 to generate a physically unclonable function has a particularly high level of protection from unauthorized persons reading the data.

[0133] Fig.10 Show Fig. 9 A partial and schematic cross-sectional view of one example of a device of the type shown is device 900 .

[0134] The connection node 906 comprises a doped semiconductor region 910 connecting the memory points 902 and 904. The region 910 is, for example, doped n-type. Preferably, each memory point 902, 904 comprises a respective gate 922, 924 on a respective gate insulator 923, 925, which covers the semiconductor regions 913, 915. The regions 913 and 915 are preferably in contact with the region 910.

[0135] The operation of memory points 902 and 904 is similar to that of reference Figure 5 The operation of the memory points 502_1 and 502_2 described above, in particular, programming of the memory points is achieved by applying a programming voltage between the nodes HV and 906, the regions 913 and 915 being conductive, or by a breakdown of the gate insulator caused by making the regions 913 and 915 conductive by a field effect. Preferably, the region 910 and the regions 913 and 915 are as described in reference Figure 2 The portions of the same semiconductor layer 206 are defined.

[0136] The device also includes a doped semiconductor region 912. Region 912 is electrically connected to region 913. Region 912 is preferably separated from region 910, so that regions 910 and 912 are separated by region 913. Preferably, region 912 is only in electrical contact with region 913. For example, region 912 is located on the side of region 913 opposite to region 910. Therefore, regions 910 and 912 are located on both sides of the vertical alignment with gate 922. Region 912 is preferably part of layer 206. For example, regions 910 and 912 have the same doping type and the same doping level.

[0137] Preferably, the device includes a doped semiconductor region 914 electrically connected to region 915. Region 914 is preferably separated from region 910, so that regions 910 and 914 are separated by region 915. Preferably, region 912 is only in electrical contact with region 913. For example, region 914 is located on the side of region 915 opposite to region 910. Thus, regions 910 and 914 are located on both sides of the vertical alignment with gate 924. Region 912 is preferably part of layer 206. For example, regions 910, 912, and 914 have the same doping type and the same doping level.

[0138] The device includes a switch 120_1 connected between region 912 and node BL1. More specifically, in layer 206, only region 912 or a portion of region 912 is electrically connected in series with switch 120_1 and region 913 between memory point 902 and node BL1.

[0139] Preferably, the device comprises a switch 120_2 connected between region 914 and node BL2. More specifically, in layer 206, only region 914 or a portion of region 914 is electrically connected in series with switch 120_2 and region 915 between memory point 904 and node BL2.

[0140] Preferably, the device includes a switch 120_3 connected between region 910 (e.g., a central portion of region 906) and node BL3. More specifically, in layer 206, only a portion of region 910 is electrically connected in series with region 913 and switch 120_3 between memory point 902 and node BL3. Similarly, in layer 206, only a portion of region 910 is electrically connected in series with region 915 and switch 120_3 between memory point 904 and node BL3. Preferably, switch 120_3 is symmetrically located between doped regions 913 and 915, that is, the portion of the electrical series connection of region 910 between the switch and the memory point is symmetrical.

[0141] To program one or the other of the memory points, a programming voltage is preferably applied between nodes HV and BL3, and switch 120_3 is made passable. As a variant, a programming voltage may be applied between nodes HV and BL1, and switch 120_1 may be made passable. In this variant, switch 120_3 may be omitted.

[0142] In order to obtain a value stored in device 900, such as a bit value of a physically unclonable function, switch 120_1 is closed. The resistance between nodes HV and BL1 is compared with a threshold value. If the memory point being programmed is memory point 904, the resistance between nodes HV and BL1 is higher than the resistance when the memory point being programmed is memory point 902. The difference in resistance when memory point 904 or 902 is programmed, in particular, originates from the resistance of regions 910 and 913. In particular, the form and level of doping in region 910 are selected to obtain a resistance difference, whereby it can be distinguished which of memory points 902 and 904 is programmed. In addition, although region 910 has only one doping level in this example, portions of region 910 may be provided with different doping levels.

[0143] As a variant, switch 120_1 may be omitted in case switch 120_3 is provided. At least one of memory points 902 and 904 is programmed and the stored value may be read by comparison with a threshold value in series of switch 120_3 and memory cell 110A.

[0144] Fig.11 Schematically shows the method for reading Fig.10 1. More specifically, in the example where switch 120_2 is provided in device 900, read circuit 1100 provides the value of a physically unclonable functional bit. Circuit 1100 is coupled, preferably connected, to nodes BL1 and BL2.

[0145] The circuit 1100 includes a switch 1111 that couples the node BL1 to the node 1121, and a resistor element 1131 that couples the node 1121, preferably to a node for applying a reference potential, such as ground GND. The circuit 1100 also includes a switch 1112 that couples the node BL2 to the node 1122, and a resistor element 1132 that couples the node 1122, preferably to ground. The circuit 1100 also includes a current source 1140 that is coupled to the nodes 1121 and 1122 through respective switches 1151 and 1152. The nodes 1121 and 1122 are coupled to the non-inverting (+) input and the inverting (-) input of the comparator 1160, respectively. The output of the comparator is coupled to the input of a logic gate or mutex 1170, and the second input of the logic gate or mutex 1170 receives the signal INV.

[0146] During operation, a voltage is applied between node HV and ground that is lower than the breakdown voltage of the gate insulators of memory points 902 and 904 .

[0147] In a first working embodiment of the circuit 1100, switches 1151 and 1111 are passable, and switches 1152 and 1112 are open. The signal INV is at a low logic level. Therefore, when the current I1 flowing from the node BL1 is greater than a threshold value corresponding to the current drawn by the source 1140, a high signal OUT is obtained at the output of the logic gate 1170. If the current I1 is lower than the threshold value, the signal OUT is low. Therefore, when the programmed memory point is the memory point 902, the output OUT has a high logic level, and when the programmed memory point is the memory point 904, the output OUT has a low logic level.

[0148] In a second working embodiment of circuit 1100, switches 1152 and 1112 are passable, and switches 1151 and 1111 are open. Signal INV is at a high logic level. When current I2 flowing from node BL2 exceeds a threshold, signal OUT is high. If current I2 is below a threshold, signal OUT is low. Therefore, when the programmed memory point is memory point 904, output OUT has a high logic level, and when the programmed memory point is memory point 902, output OUT has a low logic level.

[0149] Thus, in the first and second working embodiments, the circuit supplies the bit values ​​of a physically unclonable function.

[0150] In the third working embodiment, switches 1151 and 1152 are disconnected, and switches 1111 and 1112 are passable. Signal INV is at a low logic level. When the value of current I1 flowing from node BL1 exceeds the value of current I2 flowing from node BL2, the obtained signal OUT is at a high logic level. When the value of current I1 is lower than the value of current I2, the obtained signal OUT is at a low logic level. Therefore, when the programmed memory point is memory point 902, output OUT has a high logic level, and when the programmed memory point is memory point 904, output OUT has a low logic level.

[0151] In the third working embodiment, the circuit 1100 provides the same physically unclonable function value as the first and second working embodiments. The third working embodiment also presents the advantage of comparing the currents in the memory points 902 and 904 with each other. Thus, changes in the read value due to changes in the resistance of the programmed memory point 902 or 904, or changes in the threshold value compared with this resistance, can be avoided. There is a risk of such changes occurring, for example, when the temperature changes. This avoids the risk that the data encrypted by means of the unclonable function becomes unrecognizable, for example due to temperature changes.

[0152] According to a further advantage of the third working embodiment, if the programmed memory point is memory point 902, and if the programmed memory point is memory point 904, the sum of the currents I1 and I2 flowing in memory points 902 and 904 is substantially the same. Thus, it is possible to prevent an attacker from being able to infer a physically unclonable function value based on a measurement of the current supplied by the power supply.

[0153] According to the advantages of the circuit 1100, each node BL1 and BL2 can be connected by the switch 120 ( Figure 1 ) is coupled to, preferably connected to, the memory unit 110 ( Figure 1 ). Thus, by means of the circuit 1100, when the switches 120_1 and 120_2 of the device are open and the switch 120 connected to the memory cell to be read is closed, in the respective first and second working embodiments, the content of the memory cell 110 coupled to the nodes BL1 and BL2 can be read. Thus, the same circuit 1100 can be used to read the content of the memory cell 110 and / or provide a physically unclonable functional bit.

[0154] Reference Fig.11 , a specific read circuit 1100 is described. In order to provide a physically unclonable functional bit using device 900, circuit 1100 may be replaced by any circuit that can:

[0155] comparing a resistor R1 connected in series with the switch 120_1 and in parallel with the memory point 902 to a threshold value; and / or

[0156] comparing a resistor R2 connected in series with the switch 120_2 and in parallel with the memory point 902 to a threshold value; and / or

[0157] The resistances R1 and R2 are compared with each other, for example, by applying voltages between the terminals HV and BL1 and between the terminals HV and BL2 , and by comparing the values ​​of the currents I1 and I2 flowing in the switches 120_1 and 120_2 .

[0158] Fig.12 Shown with Fig. 9 FIG. 1 is a partial and schematic top view of an example of a device 1200 of the same type as device 900 shown. Device 1200 includes Fig.10 Elements that are identical to the elements of the examples shown, or are arranged in the same or similar manner, except that Fig.10 The nodes WL1 and WL2 of the illustrated example are replaced by a common node WLa.

[0159] The switch 120_1 includes a transistor T1, which includes a source region 234_1, which contacts the doped semiconductor region 214_1 and is located under the conductive gate 210_1. Region 912 defines the source region of the transistor T1. The switch 120_2 includes a transistor T2, which includes a source region 234_2, which contacts the doped semiconductor region 214_2 and is located under the conductive gate 210_2. Region 914 defines the drain region of the transistor T1. The switch 120_3 includes a transistor T3, which includes a source region 234_3, which contacts the doped semiconductor region 214_3 and is located under the conductive gate 210_3. Region 910 defines the drain region of the transistor T3. The source regions of the transistors T1, T2 and T3 are coupled, preferably connected to the corresponding nodes BL1, BL2, BL3.

[0160] The gates 210_1 and 210_2 of the transistors constitute a common conductive region 1202. The region 1202 has, for example, an elongated shape, preferably a straight strip shape when viewed from above. The strip extends in the width direction of the transistors T1 and T2.

[0161] The gates 922 and 924 of the memory points 902 and 904 constitute a common conductive region 1204. The region 1204 has, for example, an elongated shape, preferably a stripe shape parallel to the width direction of the transistors T1 and T2 when viewed from above.

[0162] The gate 210_3 of transistor T3 extends in the width direction of transistor T3, and the width direction of transistor T3 is parallel to the width direction of transistors T1 and T2. Transistors T1 and T2 preferably have the same width, which is less than half the width of transistor T3. Preferably, device 1200 is symmetrical about a plane S12-S12 that crosses transistor T3 and passes between transistors T1 and T2.

[0163] A circuit for generating a physically unclonable function may include a plurality of devices 1200 .

[0164] For example, the device 1200 is arranged in the form of a matrix, and the width direction of the transistor corresponds to the row direction of the matrix.

[0165] Therefore, each device 1200 of a row can share the node WLa. In each device 1200 of a row, the node BL1 is separated, and in each device 1200 of a row, the node BL2 is separated. The devices 1200 of a matrix column share nodes BL1, BL2, and BL3. Therefore, a common circuit 1100 can be provided to generate a physically unclonable functional bit using the devices 1200 of a column.

[0166] As a variant, the devices 1200 are arranged in lines in the width direction of the transistors in the same way as in the matrix rows.

[0167] Fig.13 A partial and schematic top view of one embodiment of a memory 1300 is shown. More specifically, the memory includes a physically unclonable function generator.

[0168] The memory comprises a component 100, as shown in FIG. Figure 1 As described, each module includes a memory cell 110 connected in series with a switch. The modules 100 are arranged in a matrix, except that for pairs of adjacent cells 110 of the matrix, the pairs of adjacent cells 110 have been Fig. 9 For example, two rows and three columns of the device 110 are shown, and the cell pairs in the center column are replaced with memory cells 110A. Preferably, the number of rows and columns is greater than in this example.

[0169] In this example, two rows of memory cells 110 are adjacent. To this end, switches 120 are arranged on the side of each row opposite to the other row. In a matrix comprising more than two rows, pairs of rows having the same arrangement as the rows of this example may be repeated. Thus, memory cells of adjacent rows are preferably arranged about an axis such as D ( Figure 4) axis. In each row, the switch 120 connects the memory cell to the nodes BLa, BLb. The nodes BLa, BLb of different rows are separated. In each column, the control terminal of the switch 120 is connected to the nodes WLa, WLc. The nodes WLa, WLc of different rows are separated.

[0170] In the example shown, the matrix comprises a single cell 110A, however, the matrix preferably comprises a plurality of cells 110A. The cell 110A occupies the same space as the space of two adjacent cells. In other words, the memory comprises spaces arranged in the form of a matrix; two adjacent cells 110 occupy two of these spaces, while the cell 110A occupies the other two of these spaces. The spaces of the cells 110A are preferably in the same column.

[0171] Unit 110A includes and reference Fig.10 The memory points 902 and 904 and the semiconductor regions 910, 912 and 914 which are identical or similar to those described and arranged in an identical or similar manner. Preferably, a common conductive region 1204 defines the gates of the memory points 902 and 904. The region 1204 has, for example, an elongated shape, preferably in the form of a strip when viewed from above, which extends in the direction of the row.

[0172] Region 910 is connected to node BLa via switch 120_3. The control terminal of switch 120_3 is coupled, preferably connected to node WLb. Region 912 is connected to node BLa via switch 120_1. The control terminal of switch 120_1 is coupled, preferably connected to node WLb. Preferably, switch 120_1 is identical to switch 120 of the same row, in other words, switches 120_1 and 120 form a series of identical switches regularly arranged in the row in question. Likewise, switch 120_3 is preferably identical to switch 120 of the same row.

[0173] In the memory 1300, the programming of only one of the memory points 902 and 904 in the cell 110A is implemented in the same way as the programming of the memory cell 110 coupled to the switch 120_3 instead of the cell 110A. The physically unclonable function bit can be obtained from the cell 110A in the same way as the content of the cell 110 is read, which is coupled to the switch 120_1 instead of the cell 110A. Thus, the programming of the cells 110A and 110 can be realized simply. In addition, the generation of the physically unclonable function from the content of the cell 110A and the reading of the content of the cell 110 can be implemented in a simple manner, preferably by the same circuit. An attacker may try to obtain the unique code of the physically unclonable function by monitoring the activity of the reading circuit, but he cannot distinguish between the physically unclonable function bit and the data read in the memory. Therefore, the memory 1300 has a particularly high level of protection against unauthorized persons reading the data it contains.

[0174] Preferably, the units 110A are dispersed in various locations of the matrix, which increases the difficulty for an attacker to distinguish between physically unclonable functional bits and stored data, thereby increasing the level of protection.

[0175] Preferably, the circuit for reading the contents of the memory cells and for generating the physically unclonable function includes an error correction function. According to one advantage, error correction codes can be applied to the physically unclonable function using the memory 1300 without the need for additional error correction circuitry. The memory 1300 is compatible with known error correction codes.

[0176] The switches 120, 120_1 and 120_3 and the nodes BLa, BLb, WLa, WLb, WLc may be any circuit capable of selecting one of the spaces in the matrix and programming and / or reading the memory cells located in the selected space. Preferably, the switches 120, 120_1 and / or 120_3 in the same row include transistors 120T, as shown in FIG. Figure 3 As described, the sources of transistors 120T are coupled together through semiconductor region 302. In a variation, nodes BLa in the same row are separated, nodes BLa and BLb in the same column are connected to each other, nodes WLa, WLb, and WLc in the same column are separated, and nodes WLa, WLb, and WLc in the same row are connected to each other.

[0177] Although the cells 110A of the illustrated example occupy adjacent spaces of the matrix located in the same column, in a variation, the cells 110A occupy adjacent spaces located in the same row.

[0178] Fig.141400 is a partial and schematic top view of an embodiment of the memory 1400. More specifically, the memory 1400 is Fig.13 The memory 1300 shown is of the same type. The memory 1400 includes Figure 8 The memory 800 of the device 500 is identical to the memory 800 and is arranged in the same manner, except that the two memory cells 110_1 and 110_2 of at least one device 500 are Fig. 9 The device 900 is shown replaced by the memory cell 110A.

[0179] Preferably, the memory unit 110A includes a reference Fig.13 The memory cell 110 is composed of the same elements or the same or similar elements arranged in the same or similar manner. Region 910 and region 912 define the drain region of transistor 120T. Conductive region 510 and conductive region 1204 constitute a common region 1402, conductive region 510 defines the gate of the memory point of device 500, and conductive region 1204 defines the gate of the memory point of device 900.

[0180] Because memory 1400 is of the same type as memory 1300 and includes device 500, memory 1400 has a particularly high level of protection for the data it contains.

[0181] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily recognize other variations.

[0182] Finally, actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art based on the functional description provided above.

Claims

1. A device comprising: at least three memory cells; for each memory cell, a first doped semiconductor region and a switch coupling the cell to the first doped semiconductor region; a plurality of first doped semiconductor regions, connecting the first doped semiconductor regions together, wherein each cell comprises one or more irreversibly programmable memory points, each irreversibly programmable memory point comprising a second semiconductor region and a gate located on the second semiconductor region; as well as A conductive track connects the first doped semiconductor regions together. 2 . The device of claim 1 , wherein the plurality of first doped semiconductor regions and the first doped semiconductor region are located in the same semiconductor layer. 3 . The device of claim 1 , wherein the plurality of first doped semiconductor regions and the first doped semiconductor area are located in a semiconductor layer covering an insulating layer. 4 . The device of claim 1 , wherein each switch comprises a transistor having gates, the gates of the transistors having collinear elongated shapes and being separated from each other.

5. The device of claim 1, comprising a conductive region defining the gate of the irreversibly programmable memory point.

6. The device of claim 5, wherein each switch comprises a transistor having an elongated gate that is collinear with the gates of the other transistors, and wherein the conductive region and the gates of the transistors have the same elongated direction.

7. A memory comprising: a plurality of memory cells arranged in a matrix of rows and columns, each row comprising at least three memory cells; a plurality of first doped semiconductor regions, each first doped semiconductor region being associated with a respective memory cell; a plurality of switches, each switch coupling an associated first doped semiconductor region with a corresponding one of the memory cells; as well as A plurality of first doped semiconductor regions in each row, the plurality of first doped semiconductor regions connecting the first doped semiconductor regions of the row, wherein each cell comprises a programmable memory point, the programmable memory point comprising a second semiconductor region and a gate located on the second semiconductor region, and wherein each row comprises a conductive region defining the gate of the memory point. 8 . The memory according to claim 7 , wherein the plurality of first doped semiconductor regions and the plurality of first doped semiconductor areas are located in a semiconductor layer covering an insulating layer.

9. The memory according to claim 7, wherein two adjacent rows are arranged symmetrically about the axis.

10. The memory of claim 7, wherein the conductive areas of two adjacent rows in the matrix of rows are defined by a common conductive area.

11. The memory according to claim 10, wherein the second semiconductor regions of two memory points respectively located in the two adjacent rows and located in the same column of the matrix alternately contact semiconductor regions arranged on both sides of the vertical alignment with the common conductive region. 12 . The memory of claim 7 , wherein each switch comprises a transistor having a gate, the gates of the transistor having a collinear elongated shape and being separated from each other.

13. The memory of claim 7, comprising a conductive region of the gate defining the programmable memory point.

14. The memory of claim 13, wherein each switch comprises a transistor having an elongated gate collinear with the gates of the other transistors, and wherein the conductive region and the gates of the transistor have the same elongated direction.

15. A memory comprising: a plurality of memory cells arranged in a matrix of rows and columns, each row comprising at least three memory cells, wherein each memory cell comprises an irreversibly programmable memory point; a plurality of first doped semiconductor regions, each first doped semiconductor region being associated with a respective memory cell; a plurality of switches, each switch coupling an associated first doped semiconductor region with a corresponding one of the memory cells, wherein each switch comprises a transistor having a gate, the gates of the transistors of each row having a collinear elongated shape and being separated from each other; a plurality of first conductive tracks, each first conductive track connecting a corresponding row of the plurality of first doped semiconductor regions; a plurality of second conductive tracks, each second conductive track connected to the gates of the transistors of a corresponding column; as well as A plurality of first doped semiconductor regions in each row, each of the plurality of first doped semiconductor regions connecting a first doped semiconductor region of the plurality of first doped semiconductor regions in a corresponding row.

16. The memory according to claim 15, comprising: A circuit configured to select one of the cells and cause the selected cell to be programmed. 17 . The memory of claim 15 , wherein the plurality of first doped semiconductor regions and the plurality of first doped semiconductor areas are located in a semiconductor layer covering an insulating layer.

18. The memory of claim 15, wherein each irreversibly programmable memory point comprises a second semiconductor region and a gate located on the second semiconductor region, the gate of the memory point being defined by a conductive region.

19. The memory of claim 18, wherein for each row, the conductive region and the gate of the transistor have the same elongated direction.

20. The memory of claim 15, wherein two adjacent rows are arranged symmetrically about the axis.

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