Method for rewriting memory device, memory controller and control method thereof

Abstract

A method for rewriting a memory device, a memory controller and a control method thereof are provided. The memory controller includes: an error checking and correction (ECC) engine for performing error detection on data read from the memory device; and a data operation manager. The data operation manager is used to: based on the result of a test read operation of the memory device on the test unit, control a first rewrite operation of the memory device on a selected memory unit so as to compensate for the drift of the distribution of the selected memory unit; when an ECC decoding operation corresponding to a normal read operation of the memory device is successfully performed by using the ECC engine, determine a distribution adjustment degree based on the result of the normal read operation; and control a second rewrite operation of the memory device based on the determined distribution adjustment degree.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0167887, filed on December 21, 2018 in the Korean Intellectual Property Office, and entitled “Method of Rewriting Data of Memory Device, Memory Controller Controlling the Memory Device, and Controlling Method of the Memory Controller” is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a method of rewriting data of a memory device, a memory controller, and a method of controlling a memory device by using the memory controller, and more particularly, to a memory device for performing a data rewriting operation, a memory controller for controlling the memory device, and a control method of the memory controller. Background Art

[0004] As non-volatile memory devices (including flash memory), resistive memory devices such as phase change RAM (PRAM), nano floating gate memory (NFGM), polymer RAM (PoRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), and resistive RAM (RRAM) are well known. Resistive memory has the high speed of DRAM and the non-volatile characteristics of flash memory.

[0005] In a resistive memory, the threshold voltage fluctuation or resistance distribution fluctuation of a memory cell may be relatively large. Since the resistance distribution fluctuation of a memory cell may cause errors in data read operations, a method for compensating for the resistance distribution fluctuation is needed. Summary of the invention

[0006] According to one aspect, a memory controller configured to control a memory device is provided, the memory controller comprising: an error checking and correction (ECC) engine configured to perform error detection on data read from the memory device; and a data operation manager configured to: based on the result of a test read operation of the memory device on the test cell, control a first rewrite operation of the memory device on a selected memory cell so as to compensate for a drift in the distribution of the selected memory cell; when an ECC decoding operation corresponding to a normal read operation of the memory device is successfully performed by using the engine, determine a distribution adjustment degree based on the result of the normal read operation; and control a second rewrite operation of the memory device based on the determined distribution adjustment degree.

[0007] According to another aspect, a control method of a memory controller is provided, the method comprising: controlling a first rewrite operation of the memory device to compensate for a drift of a distribution relative to a selected memory cell based on a result of a test read operation on a test cell stored in the memory device; controlling a normal read operation performed by the memory device on the selected memory cell by using a normal read pulse; and controlling a second rewrite operation of the memory device relative to the selected memory cell based on a degree of distribution adjustment determined according to the result of the normal read operation.

[0008] According to another aspect, a method for rewriting data of a memory device may include: performing a normal data write operation including a normal reset operation and a normal set operation on a selected memory cell, the normal reset operation being used to form a normal distribution of a reset state by using a normal reset pulse, and the normal set operation being used to form a normal distribution of a set state by using a normal set pulse; when a drift of the distribution of a memory cell is detected according to a test read operation on a test cell, performing a partial rewrite operation on the selected memory cell to compensate for the drift; performing a normal read operation on the selected memory cell by using a normal read pulse; identifying a degradation direction of the distribution of the memory cell, the direction being identified according to performing a normal read operation; and performing an adaptive rewrite operation based on the normal distribution in the reset state and the normal distribution in the set state, for forming a distribution in a direction opposite to the identified degradation direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 A data processing system according to an example embodiment is shown;

[0011] Figure 2 A memory controller according to an example embodiment is shown;

[0012] Figure 3 A memory device according to an example embodiment is shown;

[0013] Figure 4A and Figure 4B A circuit diagram is shown as an example of a memory cell array;

[0014] FIG. 5A to FIG. 5C Graphs each showing a pulse as a function of time, a pulse for a normal reset operation, a normal set operation, and a normal read operation;

[0015] Fig. 6A and Figure 6B Each shows a graph for describing distribution degradation;

[0016] Figure 7 A flowchart for describing a control method of a memory controller according to an example embodiment is shown;

[0017] Figure 8 A memory system according to an example embodiment is shown;

[0018] Fig. 9 A flow chart for describing a method of controlling a first rewrite operation is shown;

[0019] Fig. 10A and Fig. 10B each showing a distribution of memory cells for describing a first condition;

[0020] Fig.11 A diagram showing a partial rewrite pulse and a normal read pulse as a function of time according to an example embodiment;

[0021] Fig.12 shows a graph of a partial rewrite pulse according to time, a graph of a cell current according to time, and a change in distribution according to example embodiments;

[0022] Fig.13 A memory system according to an example embodiment is shown;

[0023] Fig.14 A flow chart showing a method of controlling a second rewrite operation;

[0024] Fig.15 shows a distribution of memory cells for describing a second condition according to an example embodiment;

[0025] Fig.16 A flow chart showing a method of controlling a second rewrite operation;

[0026] Fig.17 showing a graph of an adaptive reset pulse, an adaptive set pulse, a normal reset pulse, and a normal set pulse over time;

[0027] Fig.18 A graph showing the fluctuation of the adaptive set pulse and distribution over time;

[0028] Fig.19 A graph showing fluctuations of adaptive reset pulses and distributions over time;

[0029] Fig. 20 shows a distribution of memory cells for describing a second condition according to an example embodiment;

[0030] Fig.21 A flow chart showing a method of controlling a second rewrite operation;

[0031] Fig.22A and Fig. 22B shows distribution adjustment information according to an example embodiment; and

[0032] Fig.23 A flow chart showing a control method of a memory controller is shown. DETAILED DESCRIPTION

[0033] Figure 1 A data processing system 10 according to an example embodiment is shown. The data processing system 10 may include a host 100 and a memory system 400. The memory system 400 may include a memory controller 200 and a memory device 300. The data processing system 10 may be used in one of various electronic devices, such as an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a handheld game console, a navigation system, a black box, a digital camera, etc.

[0034] The data processing system 10 may be embodied in various forms. For example, the host 100, the memory controller 200, and the memory device 300 may all be provided as a chip, a package, or a module. However, in one implementation, the memory controller 200 and the memory device 300 may be provided together as a memory system 400 or a storage device.

[0035] In addition, the memory system 400 may be included in a PC card, a CompactFlash card, a smart media card, a memory stick, a multimedia card (MMC), an SD card, a universal flash memory (UFS), etc. In one embodiment, the memory system 400 may be included in a solid state disk / drive (SSD). In the following, for ease of explanation, it is assumed that the memory system 400 is embodied as a storage device.

[0036] The host 100 may send a data operation request REQ and an address ADDR to the memory controller 200, and may also exchange data DATA with the memory controller 200. The host 100 and the memory controller 200 may communicate with each other through various protocols. For example, the host 100 and the memory controller 200 may communicate with each other through at least one of various interface protocols such as a universal storage bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small device interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0037] The memory controller 200 may control the memory device 300. For example, the memory controller 200 may control the memory device 300 to read data DATA stored in the memory device 300 or write data DATA to the memory device 300 in response to a data operation request REQ received from the host 100. The memory controller 200 may control data operations including write operations and read operations of the memory device 300 by providing an address ADDR, a command CMD, and a control signal to the memory device 300. In addition, data DATA for the above-mentioned data operations may be transmitted or received between the memory controller 200 and the memory device 300.

[0038] The memory device 300 may include a memory cell array 310 and a read / write circuit 360. In one embodiment, the memory cell array 310 may include a resistive memory cell, and in this case, the memory device 300 may be referred to as a "resistive memory device". Hereinafter, an embodiment in which the memory device 300 is a resistive memory device will be mainly described. However, the embodiments may also be applied to various types of memory devices, including nonvolatile memory devices such as flash memory devices or volatile memory devices.

[0039] The read / write circuit 360 connected to the memory cell array 310 through the bit line and / or the word line can write data to the memory cell or read data from the memory cell. In one embodiment, the read / write circuit 360 can be connected to a plurality of word lines and / or a plurality of bit lines and write or read data. For example, in a read operation, the read / write circuit 360 can apply a voltage corresponding to a read pulse to a selected memory cell; and in a write operation, the read / write circuit 360 can apply a current corresponding to a reset pulse or a set pulse to a selected memory cell.

[0040] The memory controller 200 according to an embodiment may include a data operation manager 240 , and may also store condition information CI and distribution adjustment information DAI.

[0041] The data operation manager 240 may control data operations of the memory device 300, such as read operations and write operations. The data operation manager 240 may be referred to as a data operation management circuit. In one embodiment, the data operation manager 240 may control a rewrite operation of the memory device 300. The rewrite operation may include a first rewrite operation and a second rewrite operation. The first rewrite operation (also referred to as a partial rewrite operation) indicates a data operation for compensating for a drift in the resistance distribution of the memory cell. Figures 8 to 12 The first rewrite operation is described in more detail. The second rewrite operation (which may be referred to as an adaptive rewrite operation) indicates a data operation of adaptively rewriting data according to the characteristics of the memory cell. Figures 13 to 22B The second rewrite operation is described in more detail.

[0042] Throughout the specification, in order to distinguish from the first rewrite operation and the second rewrite operation, the usual read operation and write operation may be referred to as a normal read operation and a normal write operation, respectively. Throughout the specification, for ease of explanation, the resistance distribution of the memory cell is referred to as the distribution of the memory cell.

[0043] In one embodiment, based on the result of the test read operation on the test cells stored in the memory cell array 310, the data operation manager 240 may control the first rewrite operation of the memory device 300. For example, the data operation manager 240 may use the result of the test read operation to identify the distribution of the memory cells. When the distribution of the test cells satisfies the first condition indicating that the distribution is degraded, the data operation manager 240 may control the memory device 300 to perform the first rewrite operation. The first condition that may be included in the condition information CI may include: a case where the number of error cells detected in the test read operation using the first read level is greater than the first threshold value and a case where the number of conduction cells corresponding to the test read operation using the second read level is greater than the second threshold value. The first read level may be the same as or similar to the normal read level. The value of the second read level may be greater than the value of the first read level.

[0044] In the first rewrite operation of the memory device 300, the data operation manager 240 may control the memory device 300 to apply a voltage corresponding to a partial rewrite pulse to the selected memory cell. In one embodiment, the partial rewrite pulse may have a higher voltage level and a shorter duration than a normal read pulse. However, in one implementation, the voltage level of the partial rewrite pulse may be similar to or lower than the voltage level of the normal read pulse. In addition, in one implementation, the duration of the partial rewrite pulse may be equal to or similar to the time period consumed by precharging during a normal read operation. In one embodiment, the voltage level of the partial rewrite pulse may be lower than the voltage level of the pulse used in the write operation.

[0045] The data operation manager 240 may control a normal read operation of the memory device 300 on selected memory cells stored in the memory cell array 310 .

[0046] The data operation manager 240 can identify the distribution of the selected memory cells by using the result of the normal read operation, and determine the distribution adjustment degree based on the distribution of the selected memory cells. The distribution adjustment degree can indicate the degree to which the distribution of the memory cells is adjusted in the second rewrite operation of the memory device 300. In one implementation, when the set state memory cells in the selected memory cells have a higher resistance distribution than the set state normal distribution, the data operation manager 240 can determine the distribution adjustment degree so that the set state memory cells in the selected memory cells have a lower resistance distribution than the set state normal distribution. In one implementation, the data operation manager 240 can determine the distribution adjustment degree based on the distribution adjustment information DAI. Similarly, in one implementation, when the reset state memory cells in the selected memory cells have a lower resistance distribution than the reset state normal distribution, the data operation manager 240 can determine the distribution adjustment degree so that the reset state memory cells in the selected memory cells have a higher resistance distribution than the reset state normal distribution.

[0047] Here, the set state normal distribution may indicate the distribution after a normal set operation using a normal set pulse is performed on the memory cell and before degradation. Similarly, the reset state normal distribution may indicate the distribution after a normal reset operation using a normal reset pulse is performed on the memory cell and before degradation. In other words, the set state normal distribution may indicate an ideal distribution of the set state memory cells, and the reset state normal distribution may indicate an ideal distribution of the reset state memory cells.

[0048] The data operation manager 240 may control a second rewrite operation of the memory device 300 based on the determined distribution adjustment degree. The second rewrite operation may be performed in a data comparison write (DCW) off mode.

[0049] By using the data processing system 10 according to the example embodiment, a first rewrite operation of the memory device 300 can be controlled based on the result of a test operation on the test cell, a fluctuation (or degradation) in the distribution of the memory cell can be compensated by controlling a second rewrite operation based on the result of a normal read operation, and read errors caused by the fluctuation in the distribution of the memory cell can be reduced.

[0050] In addition, the memory cells may have different characteristics (e.g., drift characteristics, characteristics affected by adjacent cells, etc.) respectively. By performing the second rewrite operation to adjust the position of the distribution in consideration of fluctuation (or degradation) of the future distribution, the data processing system 10 according to the example embodiment can adaptively control the characteristics of the memory cells.

[0051] Figure 2A memory controller 200 according to an example embodiment is shown. The memory controller 200 may include a system bus 210, a processor 220, an internal memory 230, a data operation manager 240, an error checking and correction (ECC) engine 250, a host interface 260, and a memory interface 270. The memory controller 200 may also include various components, for example, a command generation module that generates a command CMD for controlling memory operations. With respect to the memory controller 200, the previous references will be omitted. Figure 1 The description given. Figure 1 describe Figure 2 .

[0052] The system bus 210 may provide a channel between internal components of the memory controller 200. The system bus 210 may be operated based on one of various bus protocols.

[0053] The processor 220 may control all operations of the memory controller 200. The processor 220 may include at least one processing device, such as a central processing unit (CPU), a microprocessing unit (MCU), etc. The processor 220 may drive software and / or firmware to control the memory controller 200. For example, a portion of the software and / or firmware may be loaded in the internal memory 230 and driven by the processor 220.

[0054] The internal memory 230 may be used as one of various memories, for example, an operating memory, a buffer memory, a cache memory, etc. To this end, the internal memory 230 may be embodied in various memories, for example, at least one of a dynamic random access memory (DRAM), a static random access memory (SRAM), a phase change random access memory (PRAM), a flash memory, etc.

[0055] The internal memory 230 according to the example embodiment may store condition information CI and distribution adjustment information DAI. In one implementation, the control information CI may include first condition information for determining whether to perform a first rewrite operation and second condition information for determining whether to perform a second rewrite operation. The first condition information for determining whether to perform the first rewrite operation may be referred to as a first condition. The second condition information for determining whether to perform the second rewrite operation may be referred to as a second condition.

[0056] Reference Fig. 10A and Fig. 10B The first condition is described in more detail and will be referred to Figures 15 to 20 The second condition is described in more detail. The distribution adjustment information DAI is information for determining the degree of distribution adjustment. Fig.22A and Fig. 22B The distribution adjustment information DAI is described in more detail.

[0057] The data operation manager 240 may control the data operation of the memory device 300. The data operation manager 240 may include a first rewrite manager 242 and a second rewrite manager 244. The first rewrite manager 242 may control a first rewrite operation of the memory device 300. The second rewrite manager 244 may control a second rewrite operation of the memory device 300.

[0058] The data operation manager 240 may be embodied in the memory controller 200 in various forms, and according to an embodiment, the data operation manager 240 may be embodied in the form of hardware or software. For example, when the data operation manager 240 is embodied in the form of hardware, the data operation manager 240 may include a circuit for controlling the data operation of the memory device 300. As another example, when the data operation manager 240 is embodied in the form of software, the program (or instruction) stored in the memory controller 200 may be executed by the processor 220, so that the data operation may be controlled. In one implementation, the data operation manager 240 may be embodied as a combination of software and hardware, such as firmware. In one embodiment, the data operation manager 240 may be fully or partially included in a flash translation layer (FTL).

[0059] The ECC engine 250 may perform an operation of checking and correcting errors of the data DATA read from the memory device 300. The operation of checking and correcting errors may be referred to as an ECC decoding operation. For example, the data DATA read from the memory device 300 may include normal data and parity data constituting a codeword. The ECC engine 250 may perform an ECC decoding operation by using the parity data.

[0060] The host interface 260 may provide an interface between the host 100 and the memory controller 200. The memory controller 200 may receive a data operation request REQ, an address ADDR, etc. from the host 100 via the host interface 260, and may exchange data DATA with the host 100.

[0061] The memory interface 270 may provide an interface between the memory device 300 and the memory controller 200. For example, data DATA processed by the processor 220 may be stored in the memory device 300 via the memory interface 270. Alternatively, the data DATA stored in the memory device 300 may be provided to the processor 220 via the memory interface 270. The memory controller 200 may send a command CMD, an address ADDR, etc. to the memory device 300 via the memory interface 270, and may also exchange data DATA with the memory device 300.

[0062] By using the memory controller 200, the first rewrite operation of the memory device 300 can be controlled based on the result of the test operation on the test cell, the fluctuation (or degradation) of the distribution of the memory cell can be compensated by controlling the second rewrite operation based on the result of the normal read operation, and the read error caused by the fluctuation of the distribution of the memory cell can be reduced.

[0063] In addition, the memory cells may have different characteristics (e.g., drift characteristics, characteristics affected by adjacent cells, etc.) respectively. The memory controller 200 can adaptively control the characteristics of the memory cells by performing a second rewrite operation to adjust the position of the distribution in consideration of fluctuations (or degradation) of the future distribution based on the result of the normal read operation.

[0064] Figure 3 Memory device 300 according to an example embodiment is shown. Memory device 300 may include memory cell array 310, row decoder 320, column decoder 330, voltage generator 340, control logic 350, and read / write circuit 360. Figure 3 The memory device 300, omitting the previous reference Figure 1 The description given. Figure 1 describe Figure 3 .

[0065] The memory cell array 310 may include a plurality of memory cells respectively located at locations where a plurality of first signal lines and a plurality of second signal lines intersect each other. In an example embodiment, the plurality of first signal lines may be word lines WL, and the plurality of second signal lines may be bit lines BL. The memory device 300 including the memory cell array 310 may be referred to as a cross-point memory device. In one embodiment, the memory cell array 310 may have a plurality of memory cells respectively located at locations where a plurality of first signal lines and a plurality of second signal lines intersect each other. In an example embodiment, the plurality of first signal lines may be word lines WL, and the plurality of second signal lines may be bit lines BL. Figure 4A and Figure 4B The same structure as shown.

[0066] The row decoder 320 may select some word lines WL based on a row address X-ADDR provided by the control logic 350. The row decoder 320 may provide voltages to the word lines. The column decoder 330 may select some bit lines BL based on a column address Y-ADDR provided by the control logic 350.

[0067] The voltage generator 340 can generate various voltages required by the memory device based on the voltage control signal CTRL_vol provided by the control logic 350. For example, the voltage generator 340 can generate a write voltage Vwrite for a write operation and a read voltage Vread for a read operation. The write voltage Vwrite and the read voltage Vread can be provided to the bit line and / or the word line. In addition, in one embodiment, the voltage generator 340 can generate voltages required for the first rewrite operation and the second rewrite operation.

[0068] The control logic 350 may generate various internal control signals for writing data to or reading data from the memory cell array 310 based on the command CMD, the address ADDR, and the control signal CTRL received from the memory controller 200. In other words, the control logic 350 may control all operations of the memory device 300. The various internal control signals generated in the control logic 350 may be provided to the row decoder 320, the column decoder 330, the voltage generator 340, and the like. For example, the control logic 350 may provide the row address X-ADDR to the row decoder 320, the column address Y-ADDR to the column decoder 330, and the voltage control signal CTRL_vol to the voltage generator 340.

[0069] The read / write circuit 360 may perform a read operation and a write operation on the memory cell. The read / write circuit 360 may be connected to the memory cell through the bit line BL, and may include a write driver and a sense amplifier for writing data to the memory cell.

[0070] Figure 3 The case where the read / write circuit 360 is connected to the memory cell array 310 via the bit line BL is shown. However, according to an embodiment, the read / write circuit 360 may be connected to the memory cell array 310 via the word line WL. In this case, the signal line connected to the read / write circuit 360 is not the bit line BL but the word line WL.

[0071] The memory device 300 according to example embodiments may perform a test read operation, a first rewrite operation, a normal read operation, and a second rewrite operation under the control of the memory controller 200 .

[0072] The memory device 300 performs a first rewrite operation based on the result of the test read operation on the test cell, and performs a second write operation based on the result of the normal read operation. Therefore, the fluctuation (or degradation) of the distribution of the memory cell can be compensated, and the read error caused by the fluctuation of the distribution of the memory cell can be reduced.

[0073] The memory cells may have different characteristics, respectively. The memory controller 200 may adaptively control the characteristics of the memory cells by performing the second rewrite operation based on the result of the normal read operation to adjust the position of the distribution in consideration of fluctuation (or degradation) of the future distribution.

[0074] Figure 4A and Figure 4B A circuit diagram of an embodiment of a memory cell array 310 is shown. Figure 4A and Figure 4B Each shows the case where the memory cell is a PRAM. Figure 4A The memory cell array 310 shown in FIG. 3 may correspond to a cell block.

[0075] The memory cell array 310 may be a two-dimensional memory cell array having a horizontal structure including a plurality of word lines WL1 to WLn, a plurality of bit lines BL1 to BLm, and a plurality of memory cells MC. The memory cell array 310 may include a plurality of memory blocks. In each memory block, a plurality of memory cells may be arranged in rows and columns. Here, various modifications may be made to the number of word lines WL, the number of bit lines BL, and the number of memory cells MC according to circumstances. In one implementation, the memory cell array 310 may be a three-dimensional memory cell array having a vertical structure.

[0076] According to an embodiment, a plurality of memory cells MC may each include a variable resistor device R and a switch device SW. Here, the variable resistor device R may be referred to as a variable resistor material, and the switch device SW may be referred to as a selection device.

[0077] In one embodiment, the variable resistor device R is connected between one of the plurality of bit lines BL1 to BLm and the switching device SW, and the switching device SW may be connected between the variable resistor device R and one of the plurality of word lines WL1 to WLn. However, in one implementation, the switching device SW may be connected between one of the plurality of bit lines BL1 to BLm and the variable resistor device R, and the variable resistor device R may be connected between the switching device SW and one of the plurality of word lines WL1 to WLn.

[0078] The switching device SW may be connected between one of a plurality of word lines WL1 to WLn and the variable resistor device R, and may control current supply to the variable resistor device R in response to voltages applied to the word line and the bit line connected thereto. Figure 4A The case where the switching device SW is a diode is shown, but any suitable switching device may be used.

[0079] refer to Figure 4B , the memory cell MC may include a variable resistor device R and a switch device SW. The switch device SW may be implemented by using various devices such as a transistor or a diode. The variable resistor device R may include: a phase change layer 11 including a combination (GST) of germanium (Ge), antimony (Sb), and tellurium (Te); an upper electrode 12 above the phase change layer 11; and a lower electrode 13 below the phase change layer 11.

[0080] The upper electrode 12 and the lower electrode 13 may each include various metals, metal oxides, metal nitrides, etc. The upper electrode 12 and the lower electrode 13 may each include aluminum (Al), copper (Cu), titanium nitride (TiN), titanium aluminum nitride (TixAl1yNz), iridium (Ir), platinum (Pt), silver (Ag), gold (Au), polysilicon, tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), nickel (Ni), cobalt (Co), chromium (Cr), antimony (Sb), iron (Fe), molybdenum (Mo), palladium (Pd), tin (Sn), zirconium (Zr), zinc (Zn), iridium oxide (IrO 2 ), strontium zirconate oxide (StZrO 3 )wait.

[0081] The phase change layer 11 may include a bipolar resistance memory material or a unipolar resistance memory material. Due to the polarity of the material, the bipolar resistance memory material can be programmed to a set state or a reset state. Perovskite-based materials can be used for bipolar resistance memory materials. The unipolar resistance memory material can be programmed to a set state or a reset state by a current having the same polarity, and a transition metal oxide (e.g., NiOx, TiOx, etc.) can be used for the unipolar resistance memory material.

[0082] The GST material can be programmed between an amorphous state having a relatively high resistivity and a crystalline state having a relatively low resistivity. The GST material can be programmed by heating. The magnitude and duration of the heating can determine whether the GST material remains in the amorphous state or the crystalline state. The high resistivity and low resistivity can be represented by programming values ​​of logic "0" and logic "1", respectively, and can be detected by measuring the resistivity of the GST material. Conversely, the high resistivity and low resistivity can be represented by programming values ​​of logic "1" and logic "0", respectively.

[0083] exist Figure 4B In the embodiment, when the write current I is applied to the memory cell MC, the applied write current I flows through the lower electrode 13. When the write current I is applied to the memory cell MC for a very short period of time, only the layer adjacent to the lower electrode 13 is heated by Joule heat. At this time, due to the difference in heating curves, some phase change layers 11 may be in a crystalline state (or a set state) or an amorphous state (or a reset state).

[0084] FIG. 5A to FIG. 5C 1 and 2 show pulses over time for a normal reset operation, a normal set operation, and a normal read operation, respectively. Figures 1 to 4B describe FIG. 5A to FIG. 5C .

[0085] Figure 5ASpecifically shows the time-temperature diagram of the memory cell in the write operation and the read operation. The write operation may include a reset operation and a set operation. Figure 5A In the reset operation, in order to put the phase change layer 11 in an amorphous state (or a "RESET" state), a reset pulse is applied to the memory cell MC for a short period of time and then removed. When the reset pulse is applied to the memory cell MC, the temperature of the memory cell MC becomes equal to or higher than the melting point Tmelt. When the reset pulse is removed, the temperature of the memory cell MC drops. In the set operation, in order to put the phase change layer 11 in a crystalline state (or a "SET" state), a set pulse with a low level is applied to the memory cell MC, and after a period of time, the applied set pulse is removed so that the phase change layer 11 is crystallized. When the set pulse is applied to the memory cell MC, the temperature of the memory cell MC becomes equal to or higher than the crystallization temperature Tcrys. When the set pulse is removed from the memory cell MC, the temperature of the memory cell MC drops. Therefore, based on the above method, the memory cell MC is set to one of the crystalline state or the amorphous state. The level of the read pulse can be lower than the levels of the set pulse and the reset pulse.

[0086] Figure 5B Specifically shown is a time-current curve of a normal reset pulse of a normal reset operation and a normal set pulse of a normal set operation. Figure 5A The temperature pulse shown must be Figure 5B The pulse-shaped current shown is applied to the memory cell MC. Throughout the specification, the level of a pulse may indicate the height of a pulse, and the duration of a pulse may indicate the time for maintaining the pulse (eg, the width of the pulse). The duration of a pulse may also be referred to as the time duration of the pulse.

[0087] In order to convert the memory cell MC to the RESET state, a current corresponding to a normal reset pulse is applied to the memory cell MC. The normal reset pulse may have a normal reset current level I_nrs and a normal reset time duration TD_nrs. In order to convert the memory cell MC to the SET state, a current corresponding to a normal set pulse is applied to the memory cell. The normal set pulse may have the characteristics of a normal set current level I_ns and a normal set time duration TD_ns. The normal set time duration TD_ns may be longer than the normal reset time duration TD_nrs, and the normal reset current level I_nrs may be higher than the normal set current level I_ns. In other words, the normal reset pulse may be higher and narrower than the normal set pulse.

[0088] Figure 5CThe time-voltage diagram of a normal read pulse for a read operation is specifically shown. In order to distinguish the SET state and the RESET state of the memory cell MC, the memory device 300 may apply the voltage of the normal read pulse to the memory cell MC. The normal read pulse may have a normal read voltage level V_nrd and a normal read time duration TD_nrd. The normal read voltage level V_nrd may be greater than the SET state threshold voltage and less than the RESET state threshold voltage.

[0089] Fig. 6A and Figure 6B Graphs for describing degradation of distribution according to example embodiments are each shown. A memory cell MC may indicate one of a first program state S1 and a second program state S2. The first program state S1 may be a SET state, and the second program state S2 may be a reset state.

[0090] Fig. 6A Specifically, the case where the distribution degrades in the direction in which the resistance value of the distribution increases, that is, the case where the distribution degrades in the direction of the positive resistance axis. The first programming state S1 and the second programming state S2 can be converted into a degraded first programming state S1′ and a degraded second programming state S2′, respectively. For example, the resistance level of a memory cell can increase over time or due to continuous stress, and the increase can be referred to as a drift of the resistance distribution. Fig. 6A In the embodiment of the present invention, when the memory device performs a read operation using a read voltage level corresponding to the reference resistance Rref, a read error may occur due to the memory cells included in the first region A1. The memory cells in the first region A1 may indicate memory cells that are converted from an original set state to a reset state due to degradation of the resistance distribution. Each memory cell in the first region A1 is referred to as a set-to-reset (STR) error cell. Fig. 6A The degradation of the distribution shown may generate STR error cells. Therefore, read errors may occur.

[0091] Figure 6B Specifically, the case where the resistance distribution deteriorates in the direction in which the resistance value of the distribution decreases, that is, (the case where the distribution deteriorates in the direction of the negative resistance axis). The first programming state S1 and the second programming state S2 can be converted into a degraded first programming state S1″ and a degraded second programming state S2″, respectively. For example, over time, the resistance level of the memory cell may decrease due to data operations performed on adjacent cells. Figure 6BIn the embodiment of the present invention, when the memory device performs a read operation using a read voltage level corresponding to the reference resistance Rref, a read error may occur due to the memory cells included in the second area A2. The memory cells in the second area A2 may indicate memory cells that are converted from an original reset state to a set state due to degradation of the resistance distribution. Each memory cell in the second area A2 is referred to as a reset to set (RTS) error cell. Figure 6B The distribution shown is degraded and may generate RTS error cells. Therefore, read errors may occur.

[0092] Figure 7 is a flowchart for describing a control method of a memory controller. Figures 1 to 3 describe Figure 7 .

[0093] In operation S120, the memory controller 200 may control the memory device 300 to perform a first rewrite operation based on a result of the read operation on the test unit. In one embodiment, when the memory system is powered on after power failure, the memory controller 200 may control a test read operation of the memory device 300, which is performed on the test unit. The memory controller 200 may control the first rewrite operation of the memory device 300 based on a result of the test read operation. Figures 8 to 12 Operation S120 is described in more detail.

[0094] In operation S140, the memory controller 200 may control the memory device 300 to perform a normal read operation. In other words, the memory controller 200 may control the normal read operation of the memory device 300.

[0095] In operation S160, the memory controller 200 may determine the degree of distribution adjustment based on the read result according to the normal read operation. In one embodiment, the memory controller 200 may identify the direction of distribution degradation of the memory cell by using the result of the normal read operation, and may determine the degree of distribution adjustment so that the distribution moves in the direction opposite to the direction of distribution degradation identified based on the normal state. The memory controller 200 may determine the degree of distribution adjustment by using distribution adjustment information DAI stored in the memory controller 200.

[0096] In operation S180, the memory controller 200 may control the memory device 300 to perform a second rewrite operation based on the determined distribution adjustment degree. In other words, the memory controller 200 may control the second rewrite operation of the memory device 300. Some characteristics of the second rewrite operation may be different from the characteristics of the normal set operation and the normal reset operation according to the general normal write operation. For example, in the second rewrite operation, the level and / or duration of the set pulse may be different from the level and / or duration of the normal set pulse, or the level and / or duration of the reset pulse may be different from the level and / or duration of the normal reset pulse. In one embodiment, the second rewrite operation may be performed in a DCW off mode. For example, the DCW off mode may refer to a mode of writing data without comparing the written data with the data to be written.

[0097] Reference Figures 13 to 23 Operations S160 and S180 are described in more detail.

[0098] Figure 8 4 shows a memory system 400 according to an example embodiment. More specifically, Figure 8 More details are shown for describing Figure 7 The configuration of the memory system 400 of operation S120 is shown.

[0099] The memory controller 200 may include a first rewrite manager 242 , an ECC engine 250 , and a cell counter 280 , and may store first condition information CI_1 . A memory cell array 310 in the memory device 300 may include a test data area 312 .

[0100] When the memory system 400 is powered on after power failure, the first rewrite manager 242 may control a test read operation indicating a read operation of a test cell stored in the test data area 312. The read test data may be provided to the memory controller 200. In one embodiment, the ECC engine 250 may perform an ECC decoding operation by using a plurality of test data and generate an ECC result Res_ECC. The ECC engine 250 may provide the ECC result Res_ECC to the first rewrite manager 242. In one embodiment, the ECC result Res_ECC may include information about the number of error cells. In one embodiment, the cell counter 280 may perform a cell counting operation by using a plurality of test data and provide the cell counting result Res_CNT to the first rewrite manager 242. The cell counting result Res_CNT may include information about the number of on cells.

[0101] Hereinafter, the reason why the test read operation is performed when the memory system 400 is powered on after power failure is described. The memory cell array 310 includes a plurality of memory cells that are written at different times and have different characteristics. Therefore, a reference cell is required for determining whether to perform the first rewrite operation. Therefore, the memory cell array 310 includes a test data area 312 for storing the test cell, and the memory device 300 performs a test read operation on the test cell. According to an embodiment, the test read operation is performed when the memory system 400 is powered on again. In one implementation, the memory controller 200 may control the memory device 300 to perform a test read operation in each predetermined time period.

[0102] The first rewrite manager 242 may control a first rewrite operation of the memory device 300 based on the ECC result Res_ECC and / or the cell count result Res_CNT. In one embodiment, the first rewrite manager 242 may determine whether the first condition is satisfied by comparing the ECC result Res_ECC and / or the cell count result Res_CNT with the first condition information CI_1. When the first condition is satisfied, the first rewrite manager 242 may control the first rewrite operation of the memory device 300. The first rewrite operation may be performed by applying a voltage corresponding to a partial rewrite pulse to a selected memory cell. The partial rewrite pulse may have a higher voltage level and a shorter duration than a normal read pulse.

[0103] Fig. 9 is a flow chart of a method of controlling a first rewrite operation. Fig. 9 Can especially Figure 7 A more detailed flowchart of operation S120 in FIG. Figure 8 describe Fig. 9 .

[0104] In operation S122, the memory controller 200 may send a read command for the test cells stored in the test data area 312 to the memory device 300. In response to the read command, the memory device 300 may read a plurality of test data from the test cells. The memory device 300 may send a plurality of test data to the memory controller 200.

[0105] In operation S124 , the memory controller 200 may receive a plurality of pieces of test data from the memory device 300 .

[0106] In operation S126, the memory controller 200 may determine whether the distribution of the plurality of test data satisfies a first condition indicating degradation of the distribution. Fig. 10A and Fig. 10B Whether the first condition is satisfied is described in more detail.

[0107] In operation S128 , when the first condition is satisfied, the memory controller 200 may control the memory device 300 to perform a first rewrite operation to compensate for the drift of the resistance distribution.

[0108] Fig. 10A and Fig. 10B 2 and 3 show a distribution of memory cells for describing a first condition according to an example embodiment. Figure 8 describe Fig. 10A and Fig. 10B .

[0109] Fig. 10A A method for determining whether a first condition is satisfied when a drift occurs in the resistance distribution of a memory cell is shown. When the resistance distribution in the first programming state S1 degrades and is changed to the resistance distribution in the degraded first programming state S1′, the ECC engine 250 may generate an ECC result Res_ECC according to the ECC decoding operation after performing an ECC decoding operation according to the test data read by the test read operation using the first read level Read Level 1, thereby providing the ECC result Res_ECC to the first rewrite manager 242. The ECC result Res_ECC may include the number of error cells Nerr. The first rewrite manager 242 may compare the number of error cells Nerr with a predetermined first threshold value Nth1. The first threshold value Nth1 may be included in the first condition information CI_1. The first threshold value Nth1 may be a predetermined value and may be changed according to circumstances. When the number of error cells Nerr is greater than the first threshold value Nth1, the first rewrite manager 242 may determine that the first condition is satisfied.

[0110] Fig. 10B A method for determining whether a first condition is satisfied when a drift occurs in the resistance distribution of a memory cell is described. The cell counter 280 may first perform a cell counting operation on the test data read according to the test read operation using the second read level Read Level 2, and generate a cell counting result Res_CNT according to the cell counting operation, thereby providing the cell counting result Res_CNT to the first rewrite manager 242. The cell counting result Res_CNT may include the number of on-cells Non. Here, the on-cell may be a cell having a resistance value greater than the resistance of the reference level. The first rewrite manager 242 may compare the number of on-cells Non with a predetermined second threshold value Nth2. The second threshold value Nth2 may be included in the first condition information CI_1. The second threshold value Nth2 may be a predetermined value and may be changed according to the situation. When the number of on-cells Non is greater than the second threshold value Nth2, the first rewrite manager 242 may determine that the first condition is satisfied.

[0111] Fig.11A graph showing partial overwrite pulses and normal read pulses over time according to example embodiments is shown. Fig.11 Specifically shown in reference Fig. 9 The voltage pulse applied to the selected memory cell by the read / write circuit 360 in operation S128 is described. Figure 8 describe Fig.11 .

[0112] The first rewrite operation may also be referred to as a partial rewrite operation. The partial rewrite pulse applied to the selected memory cell in the first rewrite operation may have a higher voltage level and a shorter duration than a normal read pulse. In other words, assuming that the partial rewrite pulse has characteristics of a partial rewrite voltage level V_prw and a partial rewrite time duration TD_prw, the partial rewrite voltage level V_prw may be higher than the normal read voltage level V_nrd, and the partial rewrite time duration TD_prw may be shorter than the normal read time duration TD_nrd. In one embodiment, the partial rewrite voltage level V_prw may be higher than the reset state threshold voltage level Vth_reset. Reference Fig.12 The changes that occur when a partial rewrite pulse is applied to a selected memory cell are described.

[0113] The partial rewrite pulse may have various forms. In one implementation, the voltage level of the partial rewrite pulse may be similar to or lower than the voltage level of the normal read pulse. In other words, the partial rewrite voltage level V_prw may be similar to or lower than the normal read voltage level V_nrd. In one implementation, the duration of the partial rewrite pulse may be equal to or similar to the time period consumed by precharging during a normal read operation. In one embodiment, the voltage level of the partial rewrite pulse may be lower than the voltage level of the pulse used in a write operation.

[0114] Fig.12 A graph showing a partial overwrite pulse over time, a graph of a cell current over time, and a change in distribution according to example embodiments are shown. Fig.12 Specifically shows that when Fig.11 An example of the changes that occur when a rewrite pulse is applied to a memory cell is shown. Figure 8 describe Fig.12 Assume a case where the resistance distribution of the selected memory cell deteriorates from S1 and S2 to S1′ and S2′.

[0115] exist Fig. 9 After operations S122, S124, and S126 in the above, in operation S128, the data operation manager 240 may apply a partial rewrite pulse to the selected memory cells. In this case, the cells to which the partial rewrite pulse is applied may include reset state cells and set state cells in the selected memory cells.

[0116] When a partial rewrite pulse is applied to a selected memory cell, a current having a sharp pulse shape may be temporarily formed in the selected memory cell compared to the square wave pulse of the partial rewrite pulse. When the partial rewrite voltage level V_prw is higher than the reset state threshold voltage level Vth_reset, a current having a pulse shape may be formed in the reset state cell in the selected memory cell. The current having a sharp pulse shape temporarily formed in the selected memory cell may move the resistance distribution of the set state cell in the selected memory cell from S1′ to S1″′, and move the resistance distribution of the reset state cell in the selected memory cell from S2′ to S2″′. In other words, through the first rewrite operation, the first rewrite manager 242 may compensate for the drift occurring in the memory cell array 310.

[0117] Fig.13 4 shows a memory system 400 according to an example embodiment. More specifically, Fig.13 A more detailed description is shown Figure 7 The memory system 400 is configured in operation S160.

[0118] The memory controller 200 may include a second rewrite manager 244, an ECC engine 250, and a cell counter 280, and may also store second condition information CI_2 and distribution adjustment information DAI.

[0119] The second rewrite manager 244 can be used by Figure 7 The result of the normal read operation in operation S140 shown in the figure determines the distribution adjustment degree, and the second rewrite operation of the memory device 300 can be controlled based on the determined distribution adjustment degree. In one embodiment, the ECC engine 250 can use the multiple data read from the normal read operation to perform an ECC decoding operation and generate an ECC result Res_ECC. The ECC engine 250 can provide the ECC result Res_ECC to the second rewrite manager 244. In one embodiment, the ECC result Res_ECC may include the number of STR error cells and the number of RTS error cells. In one embodiment, the cell counter 280 can use the multiple data read in the normal read operation to perform a cell counter operation and provide the cell count result Res_CNT to the second rewrite manager 244. The cell count result Res_CNT may include information about the number of on cells.

[0120] The second rewrite manager 244 may determine the distribution adjustment degree based on the ECC result Res_ECC and / or the cell count result Res_CNT, and may control the second rewrite operation of the memory device 300 according thereto. In one embodiment, the second rewrite manager 244 may determine the distribution adjustment degree by using the distribution adjustment information DAI. In one embodiment, the second rewrite manager 244 may determine whether the second condition is satisfied by comparing the ECC result Res_ECC and / or the cell count result Res_CNT with the second condition information CI_2. When the second condition is satisfied, the second rewrite manager 244 may control the second rewrite operation of the memory device 300.

[0121] Fig.14 is a flowchart for describing a method of controlling the second rewrite operation. Fig.14 Can be used especially to describe reference Figure 7 A more detailed flowchart of operation S160 is described in detail. Fig.13 describe Fig.14 .

[0122] In operation S162 , the memory controller 200 may receive a plurality of pieces of read data according to a normal read operation from the memory device 300 .

[0123] In operation S164, the memory controller 200 may determine whether the distribution of the plurality of pieces of read data satisfies a second condition indicating degradation of the distribution. Figures 15 to 20 Describes whether the second condition is satisfied.

[0124] In operation S166, when the second condition is met, the memory controller 200 may determine the degree of distribution adjustment based on the information about the distribution of the plurality of read data. The information about the distribution of the plurality of read data may include the degradation direction and the degradation degree of the resistance distribution. In one implementation, the information about the distribution of the plurality of read data may include at least one of the number of STR error cells, the number of RTS error cells, and the number of on cells.

[0125] Fig.15 FIG. 2 shows a distribution of memory cells for describing a second condition according to an example embodiment. Fig.14 describe Fig.15 .

[0126] Fig.15 The upper figure shows the degradation of the memory cell in the direction of the positive resistance axis. Fig.15 The figure below shows the degradation of the memory cell in the negative resistance axis direction. Fig.15 In the example, it is assumed that the normal read operation is a read operation using the third read level Read Level 3. The third read level may be the same as or similar to the normal read level.

[0127] refer to Fig.15 In the above figure, the ECC engine 250 can identify the number of error cells Nerr by performing ECC decoding operations on multiple read data. More specifically, in Fig.15 In the above figure, the error cell can indicate a STR error cell that transitions from the original set state to the reset state.

[0128] refer to Fig.15 , the ECC engine 250 can identify the number of error cells Nerr by performing an ECC decoding operation on a plurality of read data. More specifically, Fig.15 In the following figure, the error cell can indicate the RTS error cell transitioning from its original reset state to the set state.

[0129] The second rewrite manager 244 may compare the number of error cells Nerr with a predetermined third threshold value Nth3. The third threshold value Nth3 may be included in the second condition information CI_2. The third threshold value Nth3 may be a predetermined value and may be changed according to occasions. When the number of error cells Nerr is greater than the third threshold value Nth3, the second rewrite manager 244 may determine that the second condition is satisfied.

[0130] Fig.16 is a flowchart for describing a method of controlling the second rewrite operation. Fig.16 It may be specifically used to describe the reference when the number of error cells is used to control the second rewrite operation. Fig.14 A more detailed flowchart of operation S166 is described in detail. Fig.14 describe Fig.16 .

[0131] In operation S210 , the memory controller 200 may obtain the number of STR error cells transitioned from an original set state to a reset state and the number of RTS error cells transitioned from an original reset state to a set state based on the ECC result Res_ECC received from the ECC engine 250 .

[0132] In operation S220 , the memory controller 200 may compare the number of STR error cells with the number of RTS error cells.

[0133] In operation S230, different methods of performing the second rewrite operation may be determined depending on whether the number of STR error cells is greater than the number of RTS error cells. In other words, when there are more STR error cells than RST error cells, the configuration pulse may be adjusted or adapted for the second rewrite operation, and when there are more RST error cells than STR error cells, the reset pulse may be adjusted or adapted for the second rewrite operation.

[0134] In operation S240, when the number of STR error cells is greater than the number of RTS error cells, the memory controller 200 may determine a distribution adjustment degree so that the set state cells have a resistance distribution lower than a normal distribution of the set state. Fig.18 Operation S240 is described in more detail.

[0135] In operation S250, when the number of STR error cells is not greater than the number of RTS error cells, the memory controller 200 may determine a distribution adjustment degree so that the reset state cells have a resistance distribution higher than a normal distribution of the reset state. Fig.19 Operation S250 is described in more detail.

[0136] Fig.17 A graph of an adaptive reset pulse, an adaptive set pulse, a normal reset pulse, and a normal set pulse as a function of time is shown. Fig.17 Specifically shown in reference Fig.16 The current applied to the selected memory cell by the read / write circuit 360 in operations S240 and S250 described above. Fig.14 describe Fig.17 .

[0137] The second rewrite operation may also be referred to as an adaptive rewrite operation. The adaptive reset pulse applied to the selected memory cell in the second rewrite operation may have a higher voltage level and a shorter duration than the normal reset pulse. In other words, assuming that the adaptive reset pulse has the characteristics of an adaptive reset current level I_ars and an adaptive reset time duration TD_ars, the adaptive reset current level I_ars may be higher than the normal reset current level I_nrs, and the adaptive reset time duration TD_ars may be shorter than the normal reset time duration TD_nrs. The adaptive set pulse applied to the selected memory cell in the second rewrite operation may have a lower voltage level and a longer duration than the normal set pulse. In other words, assuming that the adaptive set pulse has the characteristics of an adaptive set current level I_as and an adaptive set time duration TD_as, the adaptive set current level I_as may be lower than the normal set current level I_ns, and the adaptive set time duration TD_as may be longer than the normal set time duration TD_ns. In one embodiment, the adaptive set current level I_as may be higher than the crystallization current level I_crys. Reference Fig.18 describes the changes that occur when an adaptive set pulse is applied to a selected memory cell, and refers to Fig.19 Describes the changes that occur when an adaptive reset pulse is applied to a selected memory cell.

[0138] Fig.18A graph showing the fluctuation of the adaptive set pulse and distribution as a function of time is shown. Fig.18 Specifically shows that when Fig.17 The adaptive set pulse shown changes when applied to the memory cell. Fig.14 describe Fig.18 Assume a case where the resistance distribution of the selected memory cell deteriorates from S1 and S2 to S1′ and S2′.

[0139] exist Fig.16 After operations S210 , S220 , and S230 as shown, in operation S240 , the data operation manager 240 may apply an adaptive set pulse to a set-state memory cell among the selected memory cells.

[0140] When an adaptive set pulse is applied to a set state cell in the selected memory cell, the resistance distribution of the set state cell in the selected memory cell may move from S1′ to S11. When a pulse having a lower level and a longer duration is applied to the set state cell, the set state cell may have a resistance distribution lower than S1 (i.e., a set state normal distribution). In the memory cell that has moved from S1 to S1′, a drift may occur in the resistance distribution. The second rewrite manager 244 according to the example embodiment may form a distribution of the selected memory cell in consideration of a drift that may occur in the future, according to a degradation trend of the memory cell.

[0141] At the same time, a normal reset pulse can be applied to the reset state cell in the selected memory cell, so that a normal reset operation can be performed. Therefore, the resistance distribution of the reset state cell in the selected memory cell can be moved from S2′ to S21. The resistance distribution of S21 can be equal to or slightly lower than the resistance distribution of S2.

[0142] Fig.19 A graph showing an adaptive reset pulse and distribution fluctuations as a function of time is shown. Fig.19 Specifically shows that when Fig.17 Shown is the change that occurs when an adaptive reset pulse is applied to a memory cell. Fig.14 describe Fig.19 Assume a case where the resistance distribution of the selected memory cell deteriorates from S1 and S2 to S1 ″ and S2 ″.

[0143] exist Fig.16 Following operations S210 , S220 , and S230 as shown, in operation S250 , the second rewrite manager 244 may apply an adaptive reset pulse to reset state cells among the selected memory cells.

[0144] When an adaptive reset pulse is applied to the reset state cells in the selected memory cells, the resistance distribution of the reset state cells in the selected memory cells may move from S2″ to S22. Since a pulse with a higher level and a shorter duration is applied to the reset state cells, the reset state cells may have a resistance distribution higher than S2, that is, a reset state normal distribution. According to experience, in memory cells that have moved from S2 to S2″, the resistance distribution may deteriorate in the negative direction of the resistance axis below. Taking into account the degradation that may occur later, the second rewrite manager 244 according to the example embodiment may form a distribution of memory cells.

[0145] At the same time, a normal set pulse may be applied to the set state cells in the selected memory cells, and thus a normal set operation may be performed. Therefore, the resistance distribution of the set state cells in the selected memory cells may be moved from S1″ to S12. The resistance distribution of S12 may be equal to or slightly higher than the resistance distribution of S1.

[0146] Fig. 20 FIG. 2 shows a distribution of memory cells for describing a second condition according to an example embodiment. Fig.14 describe Fig. 20 .

[0147] Fig. 20 The figure above shows the Fig. 6A The corresponding memory cell degradation, and Fig. 20 The following figure shows the Figure 6B The degradation of the corresponding memory cell.

[0148] Reference Fig. 20 , after performing a cell counting operation on a plurality of read data read according to a normal read operation of a fourth read level Read Level 4, the cell counter 280 may provide a cell counting result Res_CNT to the second rewrite manager 244 by generating a cell counting result Res_CNT according to the cell counting operation. The cell counting result Res_CNT may include the number of on cells Non. The fourth read level may be higher than the normal read level.

[0149] The second rewrite manager 244 may compare the number of on-cells Non with a fourth threshold value Nth4 and a fifth threshold value Nth5 as predetermined values. The fourth threshold value Nth4 and the fifth threshold value Nth5 may be included in the second condition information CI_2. The fifth threshold value Nth5 may be less than the fourth threshold value Nth4. The fourth threshold value Nth4 and the fifth threshold value Nth5 may be predetermined values ​​and may be changed according to circumstances. When the number of error cells Nerr is greater than the fourth threshold value Nth4 or less than the fifth threshold value Nth5, the second rewrite manager 244 may determine that the second condition is satisfied.

[0150] Fig.21 is a flowchart for describing a method of controlling the second rewrite operation. Fig.21 It may be when the second rewrite operation is controlled by using the number of on cells, specifically for describing Fig.14 A more detailed flowchart of operation S166 is shown in FIG. Fig.14 describe Fig.21 .

[0151] In operation S310 , the memory controller 200 may obtain the number of on-cells based on the cell counting result Res_CNT received from the cell counter 280 .

[0152] In operation S320, different methods of performing the second rewrite operation may be determined depending on whether the number of the on-cells is greater than the fourth threshold value Nth4. In other words, when the number of the on-cells is greater than the fourth threshold value Nth4, the set pulse may be adjusted or adapted for the second rewrite operation, otherwise the reset pulse may be adjusted or adapted for the second rewrite operation.

[0153] In operation S330, when the number of on cells is greater than the fourth threshold value Nth4, the memory controller 200 may determine the distribution adjustment degree so that the set state cells have a resistance distribution lower than the normal distribution of the set state. Fig.18 As shown, a second rewrite operation may be performed to apply an adaptive set pulse to a set state cell among selected memory cells.

[0154] In operation S340, when the number of on-cells is not greater than the fourth threshold value Nth4, the memory controller 200 may determine a distribution adjustment degree so that the reset state cells have a resistance distribution higher than a normal distribution of the reset state. Fig. 20 After the operation shown in FIG. 1 , the number of on-cells not greater than the fourth threshold value Nth4 may indicate that the number of on-cells is less than the fifth threshold value Nth5. Fig.19 As shown, a second rewrite operation may be performed to apply an adaptive reset pulse to the reset state cells in the selected memory cells.

[0155] Fig.22A and Fig. 22B Distribution adjustment information DAI according to an example embodiment is shown. Fig.22A Specifically shows that according to Fig.15 and Fig.16 The corresponding embodiment has the distribution adjustment information DAI. Fig. 22B Specifically shows that according to Fig. 20 and Fig.21 The corresponding embodiment has the distribution adjustment information DAI.

[0156] Fig.14 The second rewrite manager 244 shown can be implemented by using Fig.22A and Fig. 22B The second rewrite manager 244 can determine the degree of distribution adjustment by comparing the ECC result Res_ECC from the ECC engine 250 with the distribution adjustment information DAI shown in FIG. Fig.22A As another example, the second rewrite manager 244 can determine the degree of distribution adjustment by comparing the cell count result Res_CNT from the cell counter 280 with the distribution adjustment information DAI shown in FIG. Fig. 22B The distribution adjustment information DAI shown is compared to determine the degree of distribution adjustment.

[0157] Reference Fig.22A The distribution adjustment information DAI may include: a table including distribution adjustment degrees, each distribution adjustment degree corresponding to a value subtracted from the number of STR error cells by the number of RTS error cells. A negative distribution adjustment degree indicates that the second rewrite operation is performed so that the resistance of the set state distribution is less than the resistance of the set state normal distribution, such as Fig.18 A positive distribution adjustment degree indicates that a second rewrite operation is performed so that the resistance of the reset state distribution is greater than the resistance of the reset state normal distribution, as shown in FIG. Fig.19 Hereinafter, for convenience of explanation, a value of subtracting the number of RTS error cells from the number of STR error cells is referred to as a "gap between the numbers of error cells".

[0158] The distribution adjustment information DAI may include a plurality of reference values ​​Nref_11, Nref_12, ..., Nref_1k, Nref_21, Nref_22, ..., Nref_2m for determining the degree of distribution adjustment. For example, when the gap between the number of error cells corresponds to a value between the reference value Nref_11 and the reference value Nref_12, the degree of distribution adjustment may be determined as -DEG_11. As another example, when the gap between the number of error cells corresponds to a value between the reference number -Nref_23 and the reference number -Nref_22, the degree of distribution adjustment may be determined as +DET_22.

[0159] refer to Fig. 22B The distribution adjustment information DAI may include: a table including the distribution adjustment degree corresponding to the number of conductive cells. The distribution adjustment information DAI may include a plurality of reference values ​​Nref_31, N_ref32, .., Nref_3n, Nref_41, Nref_42, ..., Nref_4p for determining the distribution adjustment degree. The reference value Nref_31 may be equal to Fig. 20The fourth threshold value Nth4 shown, and the reference value Nref_41 may be equal to Fig. 20 For example, when the number of on-cells corresponds to a value between the reference value Nref_32 and the reference value Nref_33, the distribution adjustment degree may be determined as -DEG_32. As another example, when the number of on-cells is less than the reference value Nref_4p, the distribution adjustment degree may be determined as +DET_4p.

[0160] Fig.23 is a flowchart for describing a control method of a memory controller. Fig.23 In this paper, the main description will be Figure 7 For example, operations S410, S420, S450, and S460 may correspond to Figure 7 Operations S120, S140, S160 and S180 are shown. Figures 1 to 3 describe Fig.23 Additional operations.

[0161] In operation S430, the memory controller 200 may perform an ECC decoding operation using a plurality of pieces of data read according to a normal read operation. For example, the ECC engine 250 may perform an ECC decoding operation by using a plurality of pieces of data read from a normal read operation.

[0162] In operation S440, different methods may be determined according to whether the ECC decoding is successfully performed.

[0163] When the ECC decoding is successfully performed, operations S450 and S460 may be performed.

[0164] When the ECC decoding operation is not successfully performed, in operation S470 , the memory controller 200 may control the memory device 300 by changing a read voltage level so that the memory device 300 retries the read operation.

[0165] refer to Fig.23 Only an embodiment completed after operation S470 is described. In one implementation, according to a result of operation S470, when an ECC decoding operation is successfully performed after a retried read operation, operations S450 and S460 may be performed.

[0166] The embodiments provide a method for rewriting data performed by a memory device, a memory controller, and a control method of the memory controller, thereby reducing read errors due to fluctuations in distribution of memory cells and performing control operations adapted to characteristics of memory cells.

[0167] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and will be interpreted only in a general descriptive sense and not for purposes of limitation. In some cases, as will be appreciated by those of ordinary skill in the art submitting this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in other embodiments, unless expressly stated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A memory controller for controlling a memory device, the memory controller comprising: an error checking and correction (ECC) engine for performing error detection on data read from the memory device; as well as Data Operations Manager for: Based on the result of the test read operation of the memory device on the test cell, controlling the first rewrite operation of the memory device on the selected memory cell to compensate for the drift of the distribution of the selected memory cell, When an ECC decoding operation corresponding to a normal read operation of the memory device is successfully performed by using the ECC engine, determining a distribution adjustment degree based on a result of the normal read operation, and A second rewrite operation of the memory device is controlled based on the determined distribution adjustment degree.

2. The memory controller according to claim 1, wherein: The data operation manager is used to control the memory device to perform a test read operation when a memory system is powered on after being powered off. The memory system includes the memory device and the memory controller.

3. The memory controller according to claim 1, wherein: The data operation manager is used to control the memory device to perform the first rewrite operation in the following situations: when the number of error cells detected in a test read operation by using a first read level is greater than a first threshold; or when the number of conduction cells according to a test read operation by using a second read level higher than the first read level is greater than a second threshold.

4. The memory controller according to claim 1, wherein: The data operation manager is used to control the memory device to apply a voltage of a partial rewrite pulse to the selected memory cell, wherein the partial rewrite pulse has a higher level and a shorter duration than a level and a duration of a normal read pulse used in the normal read operation.

5. The memory controller according to claim 1, wherein: When the set state distribution of the selected memory cells before the second rewrite operation is located on the right side of the set state normal distribution along the positive resistance axis, the data operation manager is used to control the second rewrite operation so that the set state distribution of the selected memory cells is on the left side of the set state normal distribution.

6. The memory controller according to claim 1, wherein: When the reset state distribution of the selected memory cells before the second rewrite operation is located on the left side of the reset state normal distribution along the positive resistance axis, the data operation manager is configured to control the second rewrite operation so that the reset state distribution of the selected memory cells is on the right side of the reset state normal distribution.

7. A method for controlling a memory controller, the method comprising: controlling a first rewrite operation of the memory device to compensate for a drift of a distribution of selected memory cells based on a result of a test read operation on a test cell included in the memory device; controlling the memory device to perform a normal read operation on a selected memory cell, the normal read operation using a normal read pulse; as well as Based on the distribution adjustment degree determined according to the result of the normal read operation, a second rewrite operation of the memory device on the selected memory cell is controlled.

8. The method according to claim 7, wherein: Controlling the first rewriting operation includes: sending a read command for the test unit to the memory device; receiving a plurality of test data corresponding to the read command from the memory device; determining whether distribution of the plurality of pieces of test data satisfies a first condition indicating degradation of distribution; and When the first condition is met, the memory device is controlled to perform the first rewrite operation.

9. The method according to claim 8, wherein: Determining whether the distribution of the plurality of pieces of test data satisfies the first condition includes determining whether the number of error cells detected according to a test read operation using a first read level is greater than a first threshold.

10. The method according to claim 8, wherein: Determining whether the distribution of the plurality of pieces of test data satisfies the first condition includes determining whether the number of turned-on cells according to the test read operation using a second read level is greater than a second threshold.

11. The method according to claim 8, wherein: Controlling the memory device to perform the first rewrite operation includes controlling the memory device to apply a partial rewrite pulse to a selected memory cell, wherein the partial rewrite pulse has a higher voltage level and a shorter duration than the normal read pulse.

12. The method according to claim 7, wherein: Controlling the second rewriting operation includes: receiving a plurality of read data according to the normal read operation; determining whether distribution of the plurality of pieces of read data satisfies a second condition indicating degradation of distribution; and Based on the information about the distribution of the plurality of pieces of read data, when the second condition is satisfied, a distribution adjustment degree is determined.

13. The method according to claim 12, wherein: Determining whether the distribution of the plurality of pieces of read data satisfies the second condition includes determining whether the number of error cells detected in the normal read operation is greater than a third threshold.

14. The method according to claim 13, wherein: Determining the distribution adjustment degree includes: obtaining, based on the ECC result provided from the error checking and correcting ECC engine, a number of first error cells converted from an original set state to a reset state and a number of second error cells converted from an original reset state to a set state; comparing the number of the first error units with the number of the second error units; When the number of the first error cells is greater than the number of the second error cells, determining the distribution adjustment degree so that the set state cells in the selected memory cells have a resistance distribution lower than a normal distribution of the set state; and When the number of the first error cells is not greater than the number of the second error cells, the distribution adjustment degree is determined so that reset state cells in the selected memory cells have a resistance distribution higher than a reset state normal distribution.

15. The method according to claim 14, wherein: When the number of the first error cells is greater than the number of the second error cells, controlling the second rewrite operation also includes: controlling the memory device to apply a pulse corresponding to an adaptive set pulse to a set state cell in a selected memory cell, wherein the adaptive set pulse has at least one of a lower current level and a longer duration than a normal set pulse.

16. The method according to claim 14, wherein: When the number of the first error cells is not greater than the number of the second error cells, controlling the second rewrite operation also includes: controlling the memory device to apply a current corresponding to an adaptive reset pulse to a reset state cell in a selected memory cell, the adaptive reset pulse having at least one of a higher current level and a shorter duration than a normal reset pulse.

17. The method according to claim 12, wherein: Determining whether the distribution of the plurality of read data satisfies the second condition includes determining whether the number of on-cells corresponding to the normal read operation is greater than a fourth threshold or less than a fifth threshold, the fifth threshold being less than the fourth threshold.

18. The method according to claim 17, wherein: Determining the distribution adjustment degree includes: obtaining the number of the on-cells based on a cell counting result provided from a cell counter; When the number of the on-cells is greater than the fourth threshold, determining the distribution adjustment degree so that the set state cells in the selected memory cells have a resistance distribution lower than a normal distribution of the set state; and When the number of the on-cells is less than the fifth threshold, the distribution adjustment degree is determined so that the reset state cells in the selected memory cells have a resistance distribution higher than a reset state normal distribution.

19. A method for rewriting data of a memory device, the method comprising: performing a normal data write operation including a normal reset operation and a normal set operation on the selected memory cell, wherein the normal reset operation is used to form a normal distribution of reset states by using a normal reset pulse, and the normal set operation is used to form a normal distribution of set states by using a normal set pulse; When a drift of the distribution of the selected memory cell is detected according to a test read operation on the test cell, performing a partial rewrite operation on the selected memory cell to compensate for the drift; performing a normal read operation on the selected memory cell using a normal read pulse; determining a degradation direction of a distribution of the selected memory cell according to the normal read operation; as well as An adaptive rewrite operation is performed based on the reset state normal distribution and the set state normal distribution to form a distribution shifted in a direction opposite to the determined degradation direction.

20. The method according to claim 19, wherein: The performing of the adaptive rewrite operation comprises: When the number of first error cells transitioning from an original set state to a reset state is greater than the number of second error cells transitioning from an original reset state to a set state, applying a current corresponding to an adaptive set pulse having at least one of a lower current level and a longer duration than the normal set pulse to a set state cell among the selected memory cells; and When the number of the first error cells is not greater than the number of the second error cells, a current corresponding to an adaptive reset pulse having at least one of a higher current level and a shorter duration than the normal reset pulse is applied to a reset state cell in the selected memory cell.

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