Power device and method for manufacturing a power device

Abstract

The present invention discloses a power device and a method for manufacturing a power device. The power device includes: an epitaxial layer, the epitaxial layer includes a drift region with a predetermined thickness between a second surface and a first surface, the drift region is configured to be of a first conductivity type, and the epitaxial layer has a plurality of cell structures in a lateral direction perpendicular to the thickness direction; each cell structure includes: redundant emitter trenches, two redundant emitter trenches are arranged at intervals from each other, the redundant emitter trenches extend from the first surface to the drift region, and redundant emitters are disposed in the redundant emitter trenches; a gate trench, disposed between the two redundant emitter trenches, the gate trench extends from the first surface to the drift region, and a gate is disposed in the gate trench; a body region, located between the two redundant emitter trenches, the body region is configured to be of a second conductivity type; a floating region, located on a side of each redundant emitter trench facing away from the gate trench, the floating region is configured to be of a second conductivity type, wherein the depth of the floating region is greater than the depth of the redundant emitter trench.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and particularly to a power device and a method for manufacturing the power device. Background Art

[0002] Semiconductor power devices are basic electronic components for energy control and conversion in power electronic systems. The continuous development of power electronics technology has opened up a wide range of application fields for semiconductor power devices. Semiconductor power devices marked by Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and Insulated Gate Bipolar Transistors (IGBTs) are the mainstream devices in the current power electronics field.

[0003] How to further improve the performance of semiconductor power devices has become an urgent problem to be solved at present. Summary of the Invention

[0004] The present invention provides a power device and a method for manufacturing the power device, so as to improve the performance of the power device.

[0005] On the one hand, an embodiment of the present invention provides a power device, which includes: an epitaxial layer having opposite first and second surfaces in its thickness direction. The epitaxial layer includes a drift region with a predetermined thickness between the second surface and the first surface. The drift region is configured to be of a first conductivity type. The epitaxial layer has a plurality of cell structures in the lateral direction perpendicular to the thickness direction. Each cell structure includes: redundant emitter trenches, two redundant emitter trenches are arranged at intervals. The redundant emitter trenches extend from the first surface to the drift region, and redundant emitters are arranged in the redundant emitter trenches; gate trenches, at least one gate trench is arranged between the two redundant emitter trenches. The gate trenches extend from the first surface to the drift region, and gates are arranged in the gate trenches; a body region located between the two redundant emitter trenches, the body region is configured to be of a second conductivity type; a floating region located on a side of each redundant emitter trench facing away from the gate trench, the floating region is configured to be of a second conductivity type, wherein the depth of the floating region is greater than the depth of the redundant emitter trench.

[0006] According to any of the foregoing embodiments of one aspect of the present invention, the depths of the redundant emitter trenches and the gate trenches are the same.

[0007] According to any of the foregoing embodiments of one aspect of the present invention, the cell structure further includes a carrier storage region located between the body region and the drift region, and the carrier storage region is configured to be of a first conductivity type.

[0008] According to any of the aforementioned embodiments of an aspect of the present invention, the thickness of the carrier storage region is 1.5 micrometers to 4 micrometers.

[0009] According to any of the aforementioned embodiments of one aspect of the present invention, the cell structure includes a gate trench and two redundant emitter trenches, and the lateral spacing between adjacent gate trenches and redundant emitter trenches is 1 micron to 3 microns; the trench width of the gate trench and the redundant emitter trench is 1 micron to 3 microns; and the depth of the gate trench and the redundant emitter trench is 3 microns to 6 microns.

[0010] According to any of the aforementioned embodiments of one aspect of the present invention, the sum of the widths of the gate trench, the redundant emitter trench, and the area between the gate trench and the redundant emitter trench in the lateral direction accounts for 1 / 2 of the width of the original cell structure.

[0011] According to any of the aforementioned embodiments of one aspect of the present invention, the redundant emitter trenches are symmetrically distributed on both sides of the gate trench.

[0012] According to any of the aforementioned embodiments of one aspect of the present invention, the unit cell structure further includes: an emitter region located on a side of the body region away from the second surface and laterally adjacent to the gate trench, the emitter region being configured as a heavily doped region of the first conductivity type.

[0013] According to any of the aforementioned embodiments of one aspect of the present invention, the unit cell structure further includes: a contact region, located on the side of the body region facing away from the second surface, and arranged between the adjacent gate trench and the redundant emitter trench on the side close to the redundant emitter, and the contact region is configured as a heavily doped region of the second conductivity type.

[0014] According to any of the aforementioned embodiments of an aspect of the present invention, a dielectric layer covers the first surface of the epitaxial layer, a contact opening is provided on the dielectric layer to expose at least part of the emitter region, and the contact opening is provided between the adjacent gate trench and the redundant emitter trench on a side close to the redundant emitter; and an emitter interconnect is located on a side of the dielectric layer away from the second surface and is coupled to the contact region and the emitter region through the contact opening.

[0015] According to any of the aforementioned embodiments of an aspect of the present invention, the epitaxial layer further includes: a field termination region, located on a side of the drift region away from the first surface, the field termination region being configured as a first conductivity type; and a collector region, located on a side of the field termination region away from the first surface, the collector region being configured as a second conductivity type.

[0016] According to any of the aforementioned embodiments of an aspect of the present invention, the method further comprises: a collector interconnect coupled to a side of the collector region facing away from the first surface.

[0017] On the other hand, this aspect provides a method for manufacturing a power device, including: providing a semiconductor substrate having a first surface and a second surface opposite to each other along its thickness direction, the semiconductor substrate including a drift region with a predetermined thickness between the first surface and the second surface, the drift region being configured with a first conductivity type, and multiple cell structure regions being distributed in the lateral direction perpendicular to the thickness direction of the epitaxial layer; performing a first doping of a second conductivity type on the semiconductor substrate to form floating regions arranged at intervals relative to each other in the cell structure regions; performing a second doping of the second conductivity type on the semiconductor substrate to form a body region between the floating regions; patterning the semiconductor substrate to form redundant emitter trenches arranged at intervals and at least one gate trench located between two redundant emitter trenches, wherein both the redundant emitter trenches and the gate trench extend from the first surface towards the drift region; forming a gate in the gate trench and forming redundant emitters in the redundant emitter trenches.

[0018] According to any of the foregoing embodiments of one aspect of the present invention, after the step of patterning the semiconductor substrate to form redundant emitter trenches arranged at intervals and at least one gate trench located between two redundant emitter trenches, the method further includes: performing high-energy particle implantation on the side of the drift region facing the first surface to form a carrier storage region located between the body region and the drift region, the carrier storage region being configured with a first conductivity type.

[0019] According to any of the foregoing embodiments of one aspect of the present invention, in the step of performing high-energy particle implantation on the side of the drift region facing the first surface, the implantation dose of the high-energy particle implantation is 1e13 atoms per square centimeter to 6e13 atoms per square centimeter, and the implantation energy is 1.5 MeV to 6 MeV.

[0020] According to any of the foregoing embodiments of one aspect of the present invention, performing high-energy particle implantation on the side of the drift region facing the first surface further includes: performing a drive-in for 20 minutes to 30 minutes at 800 °C to 1000 °C.

[0021] For the power device of this embodiment, by providing a floating region on the side of each redundant emitter trench facing away from the gate trench, the floating region is provided to increase the distribution of carriers and is also conducive to the broadening of the space charge region, so that the power device has good forward conduction characteristics and blocking characteristics. The depth of the floating region is greater than the depth of the redundant emitter trench, which can optimize the electric field distribution at the bottom of the gate trench and prevent the power device from being prematurely broken down due to too strong electric field at the bottom of the gate trench. And redundant emitter trenches are provided on both sides of the gate trench, improving the consistency of the gate trench and reducing the gate capacitance Cies, output capacitance Coes and reverse transfer capacitance Cres of the power device. Due to the shielding effect of the redundant emitters in the redundant emitter trenches, the negative gate capacitance effect during gate turn-on can be effectively improved, and the electromagnetic interference resistance of the device can be optimized. Description of the Drawings

[0022] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which like or similar reference numerals designate like or similar features and which are not drawn to scale.

[0023] Figure 1 is a top view of a power device provided by an embodiment of the present invention;

[0024] Figure 2 yes Figure 1 AA cross-section of

[0025] Figure 3 is a flow chart of a method for preparing a power device provided by an embodiment of the present invention;

[0026] Figures 4 to 12 Schematic diagram of the cross-sectional structure of the unit cell structure at different stages in the power device manufacturing method provided by an embodiment of the present invention;

[0027] Figure 13 is a Figure 1 Schematic diagram of the location of the floating area corresponding to the middle B part;

[0028] Figure 14 is another Figure 1 Schematic diagram of the location of the floating area corresponding to the middle B part;

[0029] Figure 15 is a Figure 1 Schematic diagram of the carrier storage injection window position corresponding to part B in the middle;

[0030] Figure 16 is another Figure 1 Schematic diagram of the carrier storage injection window position corresponding to part B in the middle;

[0031] Figure 17 It is a Figure 1 Schematic diagram of the location of the N-type heavily doped injection window corresponding to the middle B part;

[0032] Figure 18 is another Figure 1 Schematic diagram of the position of the N-type heavily doped injection window corresponding to part B in the middle. DETAILED DESCRIPTION

[0033] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by showing examples of the present invention.

[0034] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0035] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or region will be "below" or "beneath" the other layer or another region.

[0036] The embodiments of the present invention provide a power device. In this application, the term "power device" refers to the general term of the entire power device formed in each step of manufacturing the power device, including all the layers or regions that have been formed.

[0037] The power device of the embodiments of the present invention may be a power metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), etc. In the following, the structure of IGBT will be used as an example to illustrate the power device. It can be understood that the power device of the embodiments of the present invention may also be various types of semiconductor power devices with similar structures to IGBT.

[0038] Figure 1 It is a top view of a power device provided by an embodiment of the present invention. Figure 2 It is Figure 1 a cross-sectional view taken along line A-A of Figure 1 The power device 100 may include an active region AA and a terminal region NA surrounding at least a part of the outer periphery of the active region AA. A plurality of cell structures arranged in an array are distributed in the active region AA. As shown in Figure 2 a schematic diagram of a cell (pitch) structure of the active region of the power device 100 is shown. Herein, the cell structure refers to the smallest repeating unit of the conductive structure of the active region AA of the power device. The schematic diagrams of the structures in this application are all schematic in terms of the structural principle, and the actual sizes, detailed positions, etc. of the various components included in the power device can be adjusted according to the actual situation.

[0039] The power device 100 includes an epitaxial layer 110. The epitaxial layer 110 has opposite first surface S1 and second surface S2 in its own thickness direction. The epitaxial layer 110 includes a drift region 111 with a predetermined thickness between the second surface S1 and the first surface S2. The drift region 111 is configured to be of the first conduction type, for example, it is N-type. In some embodiments, the drift region 111 is lightly doped N-type.

[0040] In the lateral direction perpendicular to its thickness direction Z of the epitaxial layer 110, there are a plurality of cell structures. The cell structure includes two redundant emitter trenches T2 arranged at intervals and at least one gate trench T1 located between the two redundant emitter trenches T2. Both the redundant emitter trench T1 and the gate trench T2 extend from the first surface S1 of the epitaxial layer 110 to the drift region 111. A gate P1 is provided in the gate trench T1, and a redundant emitter P2 is provided in the redundant emitter trench T2.

[0041] The cell structure further includes a body region 113 and a floating region 112. Among them, the body region 113 is located between the redundant emitter trenches T1, and the body region 113 is configured to be of the second conduction type. For example, it is P-type. The floating region 112 is located on a side of each redundant emitter trench T2 facing away from the gate trench T1. The floating region 112 is configured to be of the second conduction type, for example, it is P-type. The depth of the floating region 112 is greater than the depth of the redundant emitter P2.

[0042] It should be noted that one of the first conduction type and the second conduction type is N-type, and the other is P-type. Herein, an example is given where the first conduction type is N-type and the second conduction type is P-type. Those skilled in the art should understand that the teachings herein can be equally applied to devices with conduction types opposite to the above examples.

[0043] The power device 100 of this embodiment has a floating region 112 provided on the side of each redundant emitter trench T2 facing away from the gate trench T1. The floating region 112 is configured to increase the carrier distribution and is also conducive to the broadening of the space charge region, enabling the power device 100 to have good forward conduction characteristics and blocking characteristics. The depth of the floating region 112 is greater than the depth of the redundant emitter trench T2, which can optimize the electric field distribution at the bottom of the gate trench T1 and prevent the power device 100 from being prematurely broken down due to too strong electric field at the bottom of the gate trench T1. Moreover, redundant emitter trenches T2 are provided on both sides of the gate trench T1, improving the consistency of the gate trench T1 and reducing the gate capacitance Cies, output capacitance Coes, and reverse transfer capacitance Cres of the power device 100. Due to the shielding effect of the redundant emitter P2 in the redundant emitter trench T2, the negative gate capacitance effect of the gate P1 turning on can be effectively improved, optimizing the electromagnetic interference resistance ability of the power device 100.

[0044] In some embodiments, a floating region 112 may be provided in the terminal region NA. The floating region 112 can form a voltage withstand ring in the terminal region NA to provide voltage withstand protection for each cell structure in the active region AA. The floating region 112 can be continuously distributed or discontinuous between each cell structure.

[0045] In some embodiments, the depth of the redundant emitter trench T2 is the same as that of the gate trench T1, so that the redundant emitter trench T2 and the gate trench T1 can be formed simultaneously in the manufacturing process, simplifying the manufacturing process and improving the manufacturing efficiency.

[0046] In some embodiments, each cell structure may include two redundant emitter trenches T2 and one gate trench T1. This can reduce the trench density in the cell structure, simplify the manufacturing process, and the design of one gate can significantly reduce the gate capacitance Cies and reverse transfer capacitance Cres, improving the switching speed of the power device 100 and reducing the loss.

[0047] The lateral spacing between adjacent gate trenches T1 and redundant emitter trenches T2 is 1 to 3 micrometers, that is, the width of the stud between the gate trench T1 and the redundant emitter trench T2 is 1 to 3 micrometers. The trench widths of both the redundant emitter trench T2 and the gate trench T1 are 1 to 3 micrometers, and the depths are both 3 to 6 micrometers. The sum of the lateral widths of the redundant emitter trench T2, the gate trench T1, and the region between the redundant emitter trench T2 and the gate trench T1 accounts for 1 / 2 of the width of the cell structure. In some embodiments, the redundant emitter trenches T2 are symmetrically distributed on both sides of each gate trench T1.

[0048] The power device 100 further includes an emitter region 115, a contact region 116, a dielectric layer 120, and an emitter interconnect 130.

[0049] The emitter region 115 is configured as a heavily doped region of the first conductivity type, for example, an N-type heavily doped region. The emitter region 115 is located on one side of the second surface of the body region 113 facing away from the epitaxial layer 110, and is adjacent to the gate trench T1 in the lateral direction.

[0050] The contact region 116 is configured as a heavily doped region of the second conductivity type, for example, a P-type heavily doped region. The contact region 116 is located within the body region 113, and is disposed in the lateral direction between the adjacent gate trench T1 and the redundant emitter trench T2, and is closer to the side of the redundant emitter trench T2. In this embodiment, the contact region 116 adopts an eccentric design, that is, it is not located in the middle of the gate trench T1 and the redundant emitter trench T2, but is disposed closer to the side of the redundant emitter trench T2, so that there is a relatively large distance between the contact region 116 and the gate trench T1, greatly improving the requirements for the process. Under the characteristic process capabilities, the cell size can be further reduced, and the size between adjacent channels can be reduced.

[0051] The dielectric layer 120 covers the first surface of the epitaxial layer 110, and a contact opening for exposing at least a part of the emitter region 115 is provided on the dielectric layer 120.

[0052] The emitter interconnect 130 is located on the side of the dielectric layer 120 facing away from the second surface, and is coupled to the contact region 116 and the emitter region 115 through the contact opening. In some embodiments, the contact hole may also penetrate through the emitter region 115. The position of the contact region 116 in the body region 113 corresponds to the position of the contact hole. By providing the contact region 116 doped with the conductivity type, a good ohmic contact can be formed, improving the anti-latch-up ability of the IGBT.

[0053] In some embodiments, the cell structure may further include a carrier storage region 114. The carrier storage region 114 is located between the body region 113 and the drift region 111, and the carrier storage region 114 is configured as the first conductivity type, for example, N-type. The thickness of the carrier storage region 114 is 1.5 micrometers to 4 micrometers. The smaller the distance between the trenches of the cell, the higher the concentration of the carrier storage region 114 can be. During the reverse voltage application process of the IGBT, due to the protection of the redundant emitter P2, the carrier storage region 114 can be emptied without reducing the breakdown voltage of the power device 100. In the forward conduction state of the IGBT, the carrier storage region 114 can block the extraction of holes from the emitter. Therefore, the hole concentration in the bottom region of the gate trench T1 will be significantly increased, which will promote the enhancement of the front electron injection efficiency, and thus the forward voltage drop Vcesat of the IGBT will be greatly improved.

[0054] In some embodiments, the epitaxial layer 110 further includes a field stop region 117 and a collector region 118. The field stop region 117 is located on a side of the drift region 111 away from the first surface. The field stop region 117 is configured to be of a first conductivity type, for example, N-type. The field stop layer can be formed by ion implantation. The thickness of the field stop region 117 can be from 1.5 micrometers to 30 micrometers.

[0055] The collector region 118 is located on a side of the field stop region 117 away from the first surface. The collector region 118 is configured to be of a second conductivity type, for example, N-type.

[0056] The power device 100 further includes a collector interconnect 140, and the collector interconnect 140 is coupled to a side of the collector region 118 away from the first surface.

[0057] In the above embodiments, the power device 100 is taken as an example of an IGBT for illustration. However, according to the teachings of the embodiments of the present invention, its principle can be equally applied to devices with a structure similar to the above example. For example, in some embodiments, the power device 100 is a double-diffused metal-oxide-semiconductor field-effect transistor (DMOS). Its general structure is the same as the IGBT structure in the above embodiments. Among them, the source interconnect in this DMOS is the emitter interconnect 130 of the above IGBT, and the drain interconnect in this DMOS is the collector interconnect 140 of the above IGBT.

[0058] The embodiments of the present invention further provide a method for manufacturing a power device. This method for manufacturing a power device is applied in the process of forming the power device in the above embodiments of the present invention. Hereinafter, the method for manufacturing a power device will be described by taking the formation process of the above power device as an example.

[0059] Figures 3 to 12 , Figure 3 is a flowchart of the method for manufacturing a power device according to the embodiments of the present invention, Figures 4 to 12 is a schematic cross-sectional structure diagram of a cell structure at different stages in the method for manufacturing a power device provided by the embodiments of the present invention. The power device 100 can include an active region AA and a terminal region NA surrounding at least a part of the outer periphery of the active region AA. In the accompanying drawings herein, only a part of the structure of the active region AA of the power device 100 is mainly shown, for example, a cell structure.

[0060] Step 101, provide a semiconductor substrate.

[0061] For the cross-sectional view of the cell structure corresponding to this step, please refer to Figure 4As shown. The semiconductor substrate has a first surface S1 and a second surface S2 opposite to each other in its own thickness direction. The semiconductor substrate can be of the first conduction type, for example, N-type. The semiconductor substrate includes a drift region with a predetermined thickness between the first surface and the second surface. The semiconductor substrate can be an epitaxial layer 110 grown on a wafer.

[0062] The semiconductor substrate can use an FZ wafer substrate with low defects and low oxygen concentration, or an MCZ wafer substrate. The MCZ wafer substrate has the advantages of good resistivity consistency, high mechanical strength and small thermal stress, and has certain advantages in large wafer sizes. However, this substrate has a high oxygen content and more defects than the FZ wafer, which increases the difficulty of controlling the sample reliability and yield. The structure application of the present invention can select an FZ wafer or an MCZ wafer according to actual situations. In actual applications, an EPI wafer with a CZ substrate can also be selected.

[0063] The power device can include an active region and a terminal region surrounding at least part of the outer periphery of the active region. A plurality of cell structure regions are distributed in the lateral direction perpendicular to the thickness direction of the epitaxial layer in the active region.

[0064] The following will mainly describe the processing process for the active region AA of the power device. The processing method of the terminal region NA can be a common method in the art.

[0065] Step 102: Perform a first doping of the second conduction type on the semiconductor substrate to form floating regions arranged at relatively spaced intervals in the cell structure regions.

[0066] For the cross-sectional view of the cell structure corresponding to this step, please refer to Figure 5 As shown. In this step, the second conduction type doping can be, for example, P-type doping. Specifically, it includes the etching of the semiconductor substrate (such as a silicon wafer) and alignment marks. Then, a masking (screen) oxide layer is grown on the front surface of the silicon wafer by thermal oxidation, and the growth temperature is 800°C - 1050°C. Photoresist is applied and exposed and developed to form an implantation window. This deep P-type implantation window exists in both the active region AA and the terminal region NA. A breakdown voltage ring (Ring) is formed in the terminal region NA, and a relatively deep floating region 112 (Deep floating body) is formed in the cell structure regions, which is the floating region 112 in Figure 2 , specifically a floating P-type region. Doping element boron is implanted on the semiconductor substrate, with an implantation energy of 50 Kev - 120 Kev and an implantation dose of 1e13 / cm 2 ~5e14 / cm 2 . As shown in Figure 13 and Figure 14, showing the position of the floating P-type region. The floating P-type region forms a breakdown voltage ring or a junction termination extension region (JTE) (to control the electric field on the surface of high-voltage devices) in the terminal region and forms a floating P-type region in the active region cell structure region. The floating P-type region can be continuous in the strip trench cell region (Strippitch), as shown in Figure shown, or discontinuous, as shown in ​ shown. The floating P-type region has a spacing or no spacing with the Ring at the chip edge. In the case of a spaced design, it will not be connected to the edge Ring after the junction push, and the spacing will not be too large to affect the device breakdown voltage. The width and spacing of the floating P-type region need to be determined according to the junction depth of the floating P-type region. After the junction push of the floating P-type region, the floating P-type regions that need to be spaced are not connected together, and the spacing cannot be too large, otherwise it cannot protect the bottom of the trench, and the chip breakdown voltage will be reduced due to too strong electric field. Usually, the layout width of the floating P-type region is 1μm - 5μm, the spacing of the spaced floating P-type region layout is 5μm - 15μm; the layout length of the floating P-type region is 2μm - 10μm.

[0067] It also includes a photoresist removal step. The floating P-type region undergoes a junction push, and the junction depth is determined according to the trench etching depth, and the depth of the floating P-type region is slightly deeper than the trench depth. This can optimize the electric field distribution at the bottom of the Trench and prevent the IGBT from breaking down prematurely due to too strong electric field at the bottom of the Trench. The junction push temperature is 1100°C - 1200°C, and the junction push time is 50min - 500min, depending on the trench depth. The trench depth is generally 3μm - 6μm.

[0068] Step 103, perform a second doping of the second conductivity type on the semiconductor substrate to form a body region between the floating regions.

[0069] For the cross-sectional view of the corresponding cell structure of this step, please refer to ​ shown. In this step, if the second conductivity type doping is, for example, P-type doping, then the body region is a P well. Specifically, field oxide growth can be carried out first, with a thickness of The growth temperature is 900°C - 1100°C, and wet oxygen or a combination of wet and dry is used to form a silicon dioxide oxide layer. This process can grow an oxide layer of the required thickness on the entire surface of the silicon wafer through the field oxide process, and then open the active region through a dry process, a wet process, or a combination of both; or through the Local Oxidation of Silicon (LOCOS) process. A thin oxide layer is grown on the silicon wafer first, with a thickness of Then a layer of Si3N4 is deposited, with a thickness of Open the Si3N4 in the area where the long oxide layer is required, and grow the oxide layer with the required thickness, so that the LOCOS morphology with bird's mouth will be formed at the edge of LOCOS. After that, after opening the field oxide or LOCOS process to etch away the Si3N4 in the active region AA, confirm that the surface oxide layer thickness is It is also possible to oxidize the silicon surface and then regrow the Screen oxide layer after etching it clean. It is also possible to etch away the thick oxide layer by dry or wet etching and retain the oxide layer with this thickness as the implantation masking layer. Perform P well implantation, implant the doping element Boron, with an implantation energy of 50 Kev to 120 Kev and an implantation dose of 5e12 to 5e13 per cm 2 . Then perform implant drive-in, determine the thermal process according to the required junction depth of the Pwell. Generally, the junction depth is 1.5μm to 3.5μm, the drive-in temperature is 1100°C to 1150°C, and the drive-in time is 50 min to 300 min.

[0070] Step 104, pattern the semiconductor substrate to form redundant emitter trenches arranged at intervals and at least one gate trench located between two redundant emitter trenches. Among them, both the redundant emitter trenches and the gate trenches extend from the first surface to the drift region.

[0071] For the cross-sectional view of the unit cell structure corresponding to this step, please refer to ​ as shown. In this step, first deposit hard mask silicon dioxide, and the thickness is determined according to the IGBT Trench etching masking requirement. Generally, the thickness is Then, a photoresist is deposited, and exposure, development, and etching of the gate trench T1 and the redundant emitter trench T2 are performed. In some embodiments, the gate trench T1 and the redundant emitter trench T2 have the same shape and size. The trenches (Trench) mentioned in this article include the gate trench T1 and the redundant emitter trench T2. The Trench etching process uses anisotropic dry etching. After the etching is completed, a corner round process is required to round the bottom of the Trench. Three or more Trenches are provided, and the pitch between trenches is the same (pitch size), generally 1 μm to 3 μm. The width after the trenches are completed (the sum of the gate trench, the redundant emitter trench, and the area between the trenches) is approximately 0.5 times the pitch size. The spacer between the Trench and the trenches is approximately 0.5 times the pitch size. In the design of three trenches, one is the gate trench (Gate Trench), and the other two are arranged on the left and right sides of the Gate Trench and are redundant emitter trenches (DummyEmitter Trench). The Gate Trench can be designed as one or multiple. Whether the Gate Trench is arranged in one or multiple rows is not restricted and is set according to the design requirements of the power device. The number of Dummy Emitter Trenches arranged on both sides of the Gate Poly can be one or multiple. In order to reduce the Trench density, in the embodiments of the present invention, it can be set to one, but it is not limited to the design of one. One Dummy Emitter Trench is arranged on each side of the Gate Trench electrode.

[0072] In some embodiments, a corner round can also be performed on each trench, and sacrificial oxidation is carried out. Sacrificial oxidation needs to remove the defects formed during the Trench etching process and at the same time smooth the relatively sharp (sharp) Silicon surface at the top. The thickness of the sacrificial oxidation The sacrificial oxidation temperature is 1050 °C to 1150 °C. Sacrificial oxidation generally uses dry oxidation or a dry and humid oxidation process. In the design of power devices, if there is a gate (Gate Poly) on a relatively sharp Silicon surface, a strong electric field is likely to be generated at this point, and the gate breakdown voltage of the device will be affected and reduced. Generally, sacrificial oxidation at a higher temperature is used to repair the steep silicon surface morphology. In actual processes, to repair the steep silicon surface morphology, a common method is also to anneal the device in a hydrogen atmosphere.

[0073] Step 105: Form a gate in the gate trench and form a redundant emitter in the redundant emitter trench.

[0074] Please refer to the cross-sectional view of the primitive cell structure corresponding to this step ​ as shown. In this step, the gate oxide layer can be grown in the gate trench T1 and the redundant emitter trench T2. The oxidation thickness of the gate electrode is generally The oxidation temperature is 800 °C to 1150 °C. The oxide layer generally uses dry oxidation or a process of dry oxidation first and then wet oxidation to ensure the quality of the oxide layer and low interface charge. Then, the metal and etch-back steps are carried out. Gate Poly is deposited, and a highly doped phosphorus polysilicon film layer is deposited by CVD to fill the Trench. The doping concentration of the polysilicon is 1e20 cm 3 ~2e20 / cm 3 , and the filling thickness of the polysilicon The polysilicon filling temperature is 550 °C to 600 °C. After polysilicon filling, annealing treatment can be carried out. The annealing temperature is 900 °C to 1150 °C, and the time is 30 min to 100 min. Gate Poly etch-back, the polysilicon etch-back uses a method of combining anisotropic etching first and then anisotropic and isotropic etching to ensure that there is no polysilicon residue in the area with LOCOS or FOX small steps in the terminal region. In the active region AA, after polysilicon etch-back, the depth of the polysilicon surface from the silicon surface (recess) For N-type heavy doping (N plus), arsenic (As) is implanted, and the recess depth For N plus, phosphorus (P) is implanted, and the recess depth The inner electrode in the Trench formed by this process, the middle one is Gate Poly, which is the gate electrode, and the electrodes in the two Trenches close to the floating P-type region will be connected to the emitter Emitter, which is the redundant emitter.

[0075] In some embodiments, the method for preparing a power device further includes performing high-energy particle implantation on the side of the drift region 111 facing the first surface S1 to form a carrier storage region 114 located between the body region 113 and the drift region 111. The carrier storage region 114 is configured as the first conduction type. The first conduction type can be, for example, N-type.

[0076] Please refer to the cross-sectional view of the primitive cell structure corresponding to this step ​ as shown. In this embodiment, it can specifically include the processes of photolithography and implantation. First, photoresist is applied. The thickness of the photoresist is determined according to the implantation energy, and the thickness of the photoresist is generally 3 μm to 8 μm. The phosphorus implantation depth requirement for the carrier storage region 114 is 1.5 μm to 4.0 μm, the implantation energy is 1.5 M to 6 Mev, and the implantation dose is 1e13 per / cm 2 ~6e13 per / cm 2。The smaller the Pitch Mesa of the active region (the smaller the Trench to Trench distance), the higher the concentration of the carrier storage region 114 can be. During the reverse voltage application process of the power device 100, due to the shielding effect of the redundant emitter T2, the carrier storage region 114 can be depleted without reducing the device breakdown voltage. In the forward conduction state of the IGBT, the carrier storage region 114 can block the extraction of holes from the emitter. Therefore, in the bottom region of the Trench, with the design of the carrier storage region 114, the hole concentration at this place will be significantly increased, which will promote the enhancement of the front electron injection efficiency, and thus the forward voltage drop Vcesat of the IGBT will be greatly improved. Of course, too high carrier storage concentration will lead to a reduction in the device breakdown voltage. During the turn-off process, the high carrier storage concentration will also block the extraction of minority holes, resulting in a reduction in the switching speed of the IGBT. In device design, a proper trade-off design is required. In the embodiment of the present invention, the injection of the carrier storage region 114 is adjusted to be injected after the Trench, and a small thermal process is used to push the junction. In some embodiments, the junction pushing can be carried out at 800 °C to 1000 °C for 20 minutes to 30 minutes, which can greatly optimize the thickness and concentration distribution of the carrier storage region 114. Compared with the traditional carrier storage region 114 injection using a large thermal process to push the junction after the Trench, the main difference is that the carrier storage concentration from the entire silicon surface to the bottom of the Trench formed by the traditional carrier storage region 114 injection and junction pushing is very high, making it very difficult to form a deeper P well channel subsequently. However, the design of the injection process of the carrier storage region 114 in the embodiment of the present invention can greatly optimize the control of the Pwell junction depth, greatly reduce the P well injection dose and the thermal process after the Trench process, so as to better cooperate with the optimization of the thermal stress of the silicon wafer.

[0077] In some embodiments, it also includes the secondary injection and junction pushing of the body region 113. After the formation of the carrier storage region 114, the secondary injection and junction pushing of the body region 113 are carried out. The body region 113 is, for example, P-type. After the phosphorus injection of the carrier storage region 114, the body region is injected secondarily. Of course, the carrier storage region 114 can also be injected after the body region 113 is injected. If in the actual process, the injection energy of the carrier storage region 114 is not high (the injection energy is limited by the equipment to be between 1.5Mev and 3.0Mev), and the injection dose of the carrier storage region 114 is relatively high, the originally formed body region 13 channel region will be shortened due to impurity compensation. In order to ensure the body region 113 channel length, a second body region injection is introduced here, with an injection energy of 600Kev to 1Mev and an injection dose of 1e13 per / cm 2 ~3e13 per / cm 2, the secondary implantation in the second region serves the purpose of controlling the channel length in the implementation region and adjusting the threshold. After the secondary implantation in the body region, the photoresist is removed. The body region is pushed for annealing, with the annealing temperature ranging from 1050 °C to 1100 °C and the time from 50 min to 120 min. The thermal process during this pushing should be controlled within a relatively small range while meeting the requirement for uniform impurity distribution in the carrier storage region. Otherwise, the power device 100 will have its breakdown voltage reduced because the high-concentration carrier storage region 114 cannot be depleted. If the thermal process is too large, the channel length of the device body region 113 will be reduced, and the thickness of the carrier storage region 114 will increase, resulting in a deterioration of the carrier storage effect. At the same time, a high thermal process will further increase the thermal stress of the silicon wafer, leading to more serious warping of the silicon wafer, which affects the lithography and alignment accuracy of subsequent processes.

[0078] The carrier storage implantation window 210 can be continuous, as shown in ​ ; or it can be discontinuous, as shown in ​ ; specifically, it can be designed according to the actual needs of the IGBT short-circuit current. The width and spacing of the discontinuous carrier storage window are adjusted according to process requirements and are usually also affected by the width and spacing of the floating region 112. Usually, the carrier storage window 210 is implanted between the redundant emitter trenches T2, covering the entire area of the gate trench T1. The length of the carrier storage region 114 is 2 μm to 10 μm, and the spacing of the carrier storage implantation window 210 is 5 μm to 30 μm. In some embodiments, the design of the carrier storage region 114 adopts an intermittent design, which is more conducive to the extraction of holes during device turn-off and improves the turn-off speed of the power device 100. In some embodiments, the carrier storage implantation window 210 is continuous, which is beneficial to blocking the hole extraction path and greatly improves the Vcesat of the IGBT during forward conduction. Therefore, the above design can achieve a better balance (trade off) between the two.

[0079] In some embodiments, it may further include the step of forming an emitter region. The emitter region 115 is configured as a heavily doped region of the first conductivity type, for example, an N-type heavily doped region (N plus). For the cross-sectional view of the corresponding cell structure of this step, please refer to ​ shown. This step may specifically include N plus lithography and the step of forming the emitter region. The N plus implantation is for forming the lead contact of the IGBT emitter. The N Plus is formed on both sides of the gate trench (Gate Poly Trench) T1. On both sides of the redundant emitter trench T2, N plus implantation may not be performed, or N plus implantation may be retained. To further adjust the magnitude of the IGBT short-circuit current, the N plus can be arranged at intervals in a two-dimensional square. The N plus adopts the process of arsenic (As) implantation, with an implantation energy of 50 Kev to 120 Kev and an implantation dose of 1e15 atoms / cm 2 ~1e16 atoms / cm 2。N plus can also be formed by phosphorus (P) implantation or phosphorus plus arsenic implantation. For the process conditions of phosphorus implantation, since the implantation depth of phosphorus is deeper than that of arsenic, this will cause the overlapping area between Gate Poly and N plus to increase, and the input capacitance of the IGBT to increase. At the same time, due to the relatively deep implantation depth of phosphorus, it is beneficial to the etching of Gate Poly, and the requirement for the accuracy of the recess depth of Gate Poly will be reduced; Arsenic implantation for N plus can form a high-concentration N+ contact on the device surface. The depth of N plus in the arsenic implantation process is 0.2μm - 0.3μm, and the requirement for the accuracy of the recess depth of Gate Poly and the silicon surface is higher. While the depth of N plus in the phosphorus implantation process is 0.3μm - 0.5μm. To form a high-concentration N plus on the surface and have a relatively deep N plus junction depth, arsenic plus phosphorus implantation is usually adopted. According to the process control capabilities of different production lines, N plus can adopt the arsenic implantation process or the process of phosphorus plus arsenic implantation. The annealing temperature after Nplus implantation is generally 900°C - 950°C, and the annealing time is 30min - 60min.

[0080] The N-type heavily doped implantation windows 220 can be arranged continuously in the lateral direction of the Gate Trench, such as ​ shown; or they can be spaced apart, such as ​ shown. If the N-type heavily doped implantation windows 220 are designed to be spaced apart, refer to ​ shown for the relationship with the floating P-type region implantation windows. In some embodiments, there may of course be no floating P-type region implantation windows in the area between Trench and Trench.

[0081] In some embodiments, it further includes the step of forming the dielectric layer 120. The dielectric layer is deposited on the first surface S1 of the semiconductor substrate by CVD. The film quality of the dielectric layer 120 is USG (undoped silicon dioxide) or PSG (phosphosilicate glass) or BPSG (boron, phosphosilicate glass). The purpose of depositing PSG and BPSG is that this material can reflux at a relatively low temperature to form a non-steep contact hole 230. However, the phosphorus in PSG and the boron phosphorus in BPSG are prone to diffuse to the silicon surface and affect the device characteristics. Therefore, the usual combination is USG plus PSG or USG plus BPSG. There are also some processes that use thin SiO2 plus Si3N4 instead of USG. Usually, the lower layer USG uses The upper layer PSG or BPSG uses This can form a good isolation layer and, during the etching or reflow process of the contact hole 230, form a relatively smooth contact hole 230, facilitating metal filling and avoiding the formation of voids in the hole during metal filling. In the process of the embodiment of the present invention, since the pitch is small (0.8 μm to 3 μm) and the size of the contact hole 230 is also small (0.2 μm to 1.5 μm), the tungsten filling process can be used for the contact hole, which can easily fill the steep and small-sized holes. Therefore, the dielectric layer 120 is entirely made of USG, or the ILD uses the CMP process to form a flat interface.

[0082] In some embodiments, it further includes the step of forming a contact hole and a contact area. For the cross-sectional view of the corresponding primitive cell structure, please refer to ​ as shown. Specifically, it includes photolithography to form the contact hole 230, etching the contact hole 230 with glue, using anisotropic dry etching (etching atmosphere Ar / CHF3 / CF4), or isotropic etching with a certain composition to slightly round the opening of the contact hole (USG + PSG / BPSG, a smooth contact hole opening can be formed through the reflow process). Then, silicon etching is performed. The depth of silicon etching is generally determined according to the depth of N plus and the depth of Gate Poly recess. Then, contact implantation is carried out. Contact implantation can be performed once, twice, or three times. The purpose of contact implantation is to form a good ohmic contact and improve the anti-latch-up ability (latch up) of the IGBT. For one-time contact implantation, a high-concentration surface contact is formed. Boron fluoride (BF2) is implanted with an energy of 20 Kev to 60 Kev and an implantation dose of 5e14 / cm 2 ~5e15 / cm 2 ; for two-time contact implantation, the latch-up ability is improved. Boron is implanted with an energy of 50 Kev to 1 Mev and an implantation dose of 5e12 / cm 2 ~2e15 / cm 2 , and reasonable conditions need to be set according to the distance from the contact to the trench. The implantation order of the first, second, and third times can be exchanged. Then, a reflow process is performed on the contact hole. The reflow temperature is 900 °C to 950 °C, and the time is 30 min to 60 min. For the CMP (chemical mechanical polishing) process using USG, the reflow treatment can be not carried out, but the contact implantation needs to be activated. Activation can be performed using a furnace tube or rapid thermal annealing (RTA).

[0083] In this embodiment, in the small pitch design, a self-aligned contact hole design is not adopted. The distance between the contact hole and the Trench is generally 0.2 μm to 0.5 μm, which poses relatively high requirements for the alignment of the contact hole. This patent proposes that in the contact hole design, in the design with 1 Gate trench, an off-center contact hole design can be adopted; making the distance between the contact and the Gate Trench larger and the distance from the Dummy Emitter Trench smaller. This greatly improves the requirements for the process, and under specific process capabilities, the pitch size can be further reduced (the distance between Trenches is reduced).

[0084] In some embodiments, it may further include the step of forming emitter interconnections. For the cross-sectional view of the cell structure corresponding to this step, please refer to ​ as shown. Due to the small pitch and small contact hole size, directly depositing metallic aluminum cannot fill the small-sized contact holes. Metallic aluminum (including aluminum-copper or aluminum-silicon-copper) filling can generally fill contact holes larger than 2 μm (the filling ability is related to the dielectric layer thickness and the contact hole morphology), and hot aluminum can fill contact holes with a size above 1.0 μm (the filling ability is related to the dielectric layer thickness and the contact hole morphology). For contact holes smaller than 1 μm, generally, a Ti / TiN or TiW dielectric film is deposited first, and then heat treatment is performed to form titanium silicide. The heat treatment can be carried out using a furnace tube or rapid thermal annealing at a temperature of 600 °C to 700 °C to improve the ohmic contact resistance. Then, tungsten (Tungsten) is deposited, and the thickness is adjusted according to the depth and size of the hole, generally and then tungsten is etched back to etch away the tungsten outside the contact area. Of course, the etch-back treatment can also be not performed. Then, metallic aluminum (including aluminum-copper or aluminum-silicon-copper) is deposited, and generally aluminum-silicon-copper is used to prevent the electromigration of aluminum at high temperatures. In actual processes, since the aluminum-copper process is also often used, the aluminum-copper process requires a barrier layer of aluminum, such as TiN, to be deposited under the aluminum-copper to prevent the electromigration of aluminum in silicon. The thickness of the aluminum layer is 3 μm to 10 μm, and 4 μm is most commonly used. After the metallic aluminum is deposited, annealing treatment is performed in a nitrogen / hydrogen atmosphere at an annealing temperature of 350 °C to 450 °C and an annealing time of 30 min to 90 min.

[0085] In some embodiments, it further includes a passivation layer deposition and etching step. To optimize the reliability of the IGBT device, a passivation layer is generally required for the IGBT. The passivation layer is made of silicon nitride (Si3N4) or carbon dioxide, or nitrogen-doped carbon dioxide, with a thickness of 0.8 μm to 1.5 μm. In actual processes, a polyimide organic film (Polyimide) is also used as the passivation layer, with a thickness of 2 μm to 20 μm. Then, photolithography and etching are performed on the passivation layer to form the emitter pad (Emitter PAD) and gate pad (GatePAD) of the IGBT, which are used to lead out the metal wire bonding.

[0086] In some embodiments, it may further include a back thinning process of the semiconductor substrate, and the semiconductor substrate uses a wafer. The narrow cell size low trench IGBT adopts field termination technology, and the IGBT is a thin slice. The thickness of the 1200V IGBT silicon is 100 μm to 130 μm; the thickness of the 600V IGBT silicon is 50 μm to 70 μm; therefore, the TAKIO process or the Bonding-Debonding process is used for thinning. In the TAKIO process, a circle around the edge of the wafer, about 3 mm to 7 mm wide, is not thinned, only the inside of the wafer is thinned, and the thicker part at the edge plays a supporting role. The Bonding-Debonding process is to stick a glass sheet on the front side of the silicon wafer to play a supporting role. After the overall thinning of the silicon wafer, the backside implantation and annealing process are completed to play a supporting role to avoid fragmentation, and then the front-side glass sheet is removed, and PVD backside metal AL / Ti / Ni / Ag is performed. After back grinding and thinning, generally 5 μm to 10 μm of silicon is etched by pure wet etching to remove the defects caused by grinding to the silicon material. The roughness of the silicon wafer grinding will affect the subsequent metal aluminum deposition and device characteristics, so the roughness of the silicon wafer grinding needs to be strictly controlled.

[0087] In some embodiments, it may further include a step of forming a field termination region, specifically including backside field termination implantation and annealing. The field termination region is configured as the first conductivity type, for example, N-type. After wet etching of the silicon wafer thinning, a backside field termination region needs to be formed. Except that an epitaxial process has already formed a field termination layer before the front process. For silicon wafers using FZ or MCZ, a field termination region needs to be formed after thinning. Because the front process has been completed, a large thermal process cannot be introduced during this process. Usually, the field termination region is formed by high-energy particle implantation to form an N-type doped layer with a certain concentration and thickness. The thickness of the field termination region is 1.5 μm to 30 μm, and the concentration of the field termination layer is 1e14 / cm 3 ~1e17 / cm 3, the thicker the field stop region, the relatively lower its concentration can be, while the thinner the field stop region, the higher the concentration required to prevent the device from punch-through when the IGBT is reverse-biased to the highest voltage. The field stop region is formed by particle implantation, and impurities that can form N-type doping such as hydrogen (H) implantation, phosphorus (P) implantation, and selenium (Se) implantation can be used. For example, in hydrogen implantation, due to the light atomic mass of hydrogen, less energy can be used to implant to a deep depth. With an energy of 2 MeV, the implantation depth can be about 50 μm. For phosphorus implantation with an energy of 2 MeV, the implantation depth is about 3 μm. The implantation dose is determined according to the doping concentration of the N-type field stop region, and the dose ranges from 1e12 atoms / cm 2 ~5e13 atoms / cm 2 , and it can be implanted once or multiple times to form a doping distribution with a certain gradient. It is also possible to implant with high energy and high dose first, or to implant with low energy and high dose first. That is, the implantation energy and dose can be arbitrarily combined according to the device performance requirements to form the N-type field stop region. By high-energy implantation to form the field stop region, one is to form a certain doping distribution through doping, and the other function is to form a defective layer in a certain area. The defects are not completely repaired during the annealing process of the N-type field stop region. The local defective layer has a lower minority carrier lifetime, which can adjust the injection efficiency of the IGBT back emitter and optimize the IGBT switching process, greatly shortening the current tail during the IGBT turn-off process.

[0088] After the IGBT front process is completed, large thermal processes are not allowed, and the maximum allowed thermal process cannot be higher than 450 °C. Therefore, after the back field stop region is implanted, if furnace annealing is used, the annealing temperature is required to be lower than 450 °C. For example, when annealing at 300 °C for 60 min, this annealing temperature cannot make the activation rate of N-type doping lower than 10%, and at the same time, the defects formed by implantation cannot be completely repaired. Laser annealing can also be used. The laser spot irradiates the silicon surface on the back of the IGBT, and there is a certain overlap between the spots. For example, the overlap is 50%. After each independent spot covers the entire back area of the silicon wafer, the back activation of one wafer is completed. The size and power of the laser spot can be adjusted. The temperature on the outermost surface of the silicon wafer back can reach just the temperature to melt silicon, and the temperature gradient gradually decreases from the back to the silicon wafer surface. The temperature transmitted to the front surface of the silicon wafer does not exceed 300 °C. In this way, the activation rate of the N-type implanted impurities in the field stop region exceeds 80%. To retain some regions with implanted defects without activation, after high-power laser annealing, one or more field stop region defect implantations can be carried out again. Other parameters of laser annealing also include the laser wavelength, such as 527 nm; the pulse width, such as 246 nS; the energy density of 1.8 J / cm2 or 2.3 J / cm 2 , the delay between pulses is 1 μS; the pulse overlap rate is 50% and other parameters.

[0089] In some embodiments, a collector region may also be formed on a side of the field stop region facing away from the first surface. The collector region is configured to be of a second conductivity type, for example, a P-type. Specifically, it includes implanting and annealing a P-type region on the back of the IGBT to form the collector region of the IGBT. The P-type region on the back requires a thin junction depth so that electrons in the drift region and the field termination region can directly penetrate the P-type region on the back to reach the collector, which will reduce the carrier concentration that needs direct electron-hole recombination, improve the switching loss of the IGBT, and reduce the tail current of the IGBT. Therefore, the P-type region on the back of the IGBT is also called the transparent emitter region. The thickness of the P-type region on the back is 0.1 μm to 0.5 μm, and the concentration is 1e16 / cm 3 ~1e18 / cm 3 . Boron (B) or boron fluoride (BF2) is implanted into the P-type region on the back, the implantation energy is 10 Kev to 60 Kev, and the implantation dose is 1e12 / cm 2 ~1e14 / cm 2 . The processes and conditions of implantation annealing and field termination region annealing are the same. The annealing of the P-type region on the back can be completed separately or annealed together with the N-type field termination region. The implantation order can also be exchanged with the N-type field termination region. In order to optimize the design of the IGBT, if laser annealing is used for the P-type region on the back, lower energy laser annealing conditions can be used than for the N-type field termination region, so as to form a P-type collector region with a shallower junction depth to improve the performance of the IGBT.

[0090] In some embodiments, it also includes the step of forming a collector interconnect. Specifically, physical vapor deposition (PVD) / sputtering of backside metal is used, and the backside metal is AL / Ti / Ni / Ag. The thickness of AL / Ti / Ni The thickness of Ag In the IGBT process, sputtering or evaporation of backside metal aluminum is a key process, which requires aluminum to form an alloy with the P-type region on the back to improve the ohmic contact between the backside metal and the low-concentration P-type region. Therefore, whether physical vapor deposition (PVD) or sputtering of backside metal aluminum is used, the temperature of sputtering and evaporation needs to be controlled to form a good alloy. The Ti / Ni / Ag metals are metal layers for forming the IGBT welding process. Ti is also a metal for forming an alloy with lower resistivity, Ni is a barrier layer, and Ag is a metal for direct solder wetting.

[0091] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor limit the invention to only the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A power device, characterized in that: include: an epitaxial layer having a first surface and a second surface opposite to each other along a thickness direction thereof, the epitaxial layer including a drift region of a predetermined thickness between the second surface and the first surface, the drift region being configured as a first conductivity type, the epitaxial layer having a plurality of unit cell structures in a lateral direction perpendicular to the thickness direction, the unit cell structures being arranged in a plurality of rows along a column direction, and the plurality of unit cell structures being spaced apart in the row direction; Each of the primitive cell structures comprises: Redundant emitter trenches, wherein two redundant emitter trenches are spaced apart from each other in the column direction, the redundant emitter trenches extend from the first surface to the drift region, and a redundant emitter is disposed in the redundant emitter trenches; a gate trench, wherein at least one gate trench is disposed between the two redundant emitter trenches, the gate trench extends from the first surface to the drift region, and a gate is disposed in the gate trench; a body region located between the two redundant emitter trenches, wherein the body region is configured as a second conductivity type; A floating region is located on the side of each redundant emitter trench facing away from the gate trench, and the floating region is configured as the second conductivity type, wherein the depth of the floating region is greater than the depth of the redundant emitter trench, and the floating region located between adjacent unit cell structures is intermittently arranged in the row direction.

2. The power device according to claim 1, wherein: The redundant emitter trench has the same depth as that of the gate trench.

3. The power device according to claim 1, wherein: The unit cell structure further includes a carrier storage region, the carrier storage region is located between the body region and the drift region, and the carrier storage region is configured as the first conductivity type.

4. The power device according to claim 3, characterized in that The thickness of the carrier storage region is 1.5 microns to 4 microns.

5. The power device according to claim 1, wherein: The unit cell structure includes one gate trench and two redundant emitter trenches, and the spacing between adjacent gate trenches and redundant emitter trenches in the lateral direction is 1 micron to 3 microns; The width of the gate trench and the redundant emitter trench is 1 micron to 3 microns; The depth of the gate trench and the redundant emitter trench is 3 microns to 6 microns.

6. The power device according to claim 5, characterized in that The sum of the widths of the gate trench, the redundant emitter trench, and the area between the gate trench and the redundant emitter trench in the lateral direction accounts for 1 / 2 of the width of the original cell structure.

7. The power device according to claim 1, wherein: The redundant emitter trenches are symmetrically distributed on both sides of the gate trench.

8. The power device according to claim 1, wherein: The primitive cell structure further includes: An emitter region is located on a side of the body region away from the second surface and is adjacent to the gate trench in the lateral direction. The emitter region is configured as a heavily doped region of the first conductivity type.

9. The power device according to claim 8, characterized in that The primitive cell structure further includes: The contact region is located on a side of the body region away from the second surface and is located between the adjacent gate trench and the redundant emitter trench and close to the redundant emitter. The contact region is configured as a heavily doped region of the second conductivity type.

10. The power device according to claim 9, characterized in that: Also includes: a dielectric layer covering the first surface of the epitaxial layer, wherein the dielectric layer is provided with a contact opening exposing at least a portion of the emitter region, the contact opening being provided between the adjacent gate trench and the redundant emitter trench and close to a side of the redundant emitter; as well as The emitter interconnect is located on a side of the dielectric layer away from the second surface and is coupled to the contact region and the emitter region through the contact opening.

11. The power device according to claim 1, wherein: The epitaxial layer further comprises: a field termination region, located on a side of the drift region facing away from the first surface, wherein the field termination region is configured as a first conductivity type; The collector region is located on a side of the field termination region facing away from the first surface, and the collector region is configured as a second conductivity type.

12. The power device according to claim 11, characterized in that: Also includes: A collector interconnect is coupled to a side of the collector region facing away from the first surface.

13. A method for preparing a power device, characterized in that: include: A semiconductor substrate formed of an epitaxial layer grown on a wafer is provided, the semiconductor substrate having a first surface and a second surface opposite to each other along its thickness direction, the semiconductor substrate including a drift region of predetermined thickness located between the first surface and the second surface, the drift region being configured as a first conductivity type, a plurality of unit cell structure regions distributed in a lateral direction perpendicular to the thickness direction of the epitaxial layer, the unit cell structure regions being arranged in a plurality of rows along a column direction, and the plurality of unit cell structure regions being spaced apart in the row direction; Performing a first second conductivity type doping on the semiconductor substrate to form floating regions that are relatively spaced apart in the column direction in the cell structure region, and the floating regions are discontinuously arranged in the row direction; performing a second doping of the second conductivity type on the semiconductor substrate to form body regions between the floating regions in the column direction; Patterning the semiconductor substrate to form redundant emitter trenches spaced apart from each other and at least one gate trench located between two of the redundant emitter trenches, wherein both the redundant emitter trenches and the gate trenches extend from the first surface toward the drift region; A gate is formed in the gate trench, and a redundant emitter is formed in the redundant emitter trench.

14. The method for preparing a power device according to claim 13, wherein: Also includes: High-energy particles are implanted on the side of the drift region facing the first surface to form a carrier storage region between the body region and the drift region, wherein the carrier storage region is configured as a first conductivity type.

15. The method for preparing a power device according to claim 14, wherein: In the step of performing high-energy particle implantation on the side of the drift region facing the first surface, the implantation dose of the high-energy particle implantation is 1e13 atoms per square centimeter to 6e13 atoms per square centimeter, and the implantation energy is 1.5 MeV to 6 MeV.

16. The method for preparing a power device according to claim 13, wherein: The injecting high-energy particles into the drift region toward the first surface further comprises: performing push-in at 800 degrees Celsius to 1000 degrees Celsius for 20 minutes to 30 minutes.

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