Latch comparator circuit and method

Abstract

The latch comparator includes a preamplifier circuit and a latch circuit. The preamplifier circuit amplifies the differential input signal pair and generates a preamplified differential signal pair. The latch circuit receives the preamplified differential signal pair, compares the preamplified differential signal pair, and generates a latched comparison signal pair. The latch circuit includes a latch and a switch circuit. The first and second input terminals of the latch receive the preamplified differential signal pair. The switch circuit includes a switch coupled to one of the first and second input terminals of the latch. The switch receives one of the latched comparison signal pairs as a control signal and switches in response to the latched comparison signal pair.

Description

Technical Field

[0001] The present invention relates to a latched comparator and more particularly to a latched comparator that reduces kickback noise. Background Art

[0002] Comparators are used in analog circuits and analog-to-digital converter (Analog-to-Digital converter) circuits. Figure 1 A latch comparator 100 is shown, which includes a preamplifier 102 and a latch 104. The preamplifier 102 receives differential input signals in_p, in_m and generates a preamplified differential signal. The preamplified differential signal is provided to the latch 104. The latch 104 compares the preamplified signals and generates latched differential signals out_p, out_m. The latch 104 also receives a latch signal at its enable terminal. The latch signal configures the latch 104 to operate in a reset mode or a latch mode. In the reset mode, the output signals out_p and out_m are reset; in the latch mode, the latch 104 operates as a normal latch circuit.

[0003] A major concern with latching comparator 100 is the kick-back effect, where the operation of latch 104 affects the operation of preamplifier 102, such that the output of preamplifier 102 may be affected, which may cause latch 104 to latch an incorrect value.

[0004] Therefore, it is necessary to provide a latch comparator that copes with the kick-back effect. Summary of the invention

[0005] This Summary is provided to introduce a selected, simplified version of the concepts that are detailed in the Detailed Description below. This Summary is not intended to identify key or essential features of the claims nor is it intended to limit the scope of the claims.

[0006] According to one embodiment, a latch comparator is provided, comprising:

[0007] A pre-amplifier circuit receives a differential input signal (in_p, in_m) and generates a pre-amplified differential signal (x0, y0);

[0008] A latch circuit connected to the pre-amplifier circuit receives the pre-amplified differential signal; the latch circuit compares the pre-amplified differential signal pair and generates a pair of latched comparison signals (out_p, out_m); wherein the latch circuit includes:

[0009] a latch having a first input terminal and a second input terminal connected to the preamplifier circuit to receive the preamplified differential signal; and

[0010] A switch circuit includes a switch coupled between one of the first and second input terminals of the latch and the pre-amplifier circuit, wherein the switch receives one of the latched comparison signal pair as a control signal and switches in response to the received one of the latched comparison signals.

[0011] By way of example, the latch circuit further includes an input circuit coupled between the pre-amplifier circuit and the switch circuit, the input circuit including first and second PMOS transistors (P41), the first PMOS transistor having a gate terminal connected to the pre-amplifier circuit to receive the first of the pre-amplified differential signal pair, and the second PMOS transistor having a gate terminal connected to the pre-amplifier circuit to receive the second of the pre-amplified differential signal pair.

[0012] Illustratively, the latch circuit further includes a setting circuit connected to the input circuit, the setting circuit receiving the latch signal and setting the output of the input circuit in response to the latch signal.

[0013] Illustratively, the latch includes:

[0014] first and second NMOS transistors (N41), wherein:

[0015] The sources of the first and second NMOS transistors are connected to the switch circuit,

[0016] The gate of the first NMOS transistor is connected to the source of the second NMOS transistor,

[0017] The gate of the second NMOS transistor is connected to the source of the first NMOS transistor, the drains of the first and second NMOS transistors are connected to ground, and

[0018] The sources of the first and second NMOS transistors provide a latched comparison signal pair.

[0019] Illustratively, the switch circuit is coupled between sources of the first and second NMOS transistors and the pre-amplifier circuit, and the switch circuit receives the latched comparison signals provided by the first and second NMOS transistors.

[0020] By way of example, the switch circuit further includes another switch coupled between the source of the first NMOS transistor and the pre-amplifier circuit, wherein the another switch receives the latched comparison signal provided by the second NMOS transistor as the control signal.

[0021] Illustratively, the switch and the further switch are PMOS transistors (P42) each having a gate connected to receive the latched comparison signal, a drain connected to the first and second inputs of the latch, and a source connected to the pre-amplifier circuit.

[0022] Illustratively, the latch circuit further includes a reset circuit connected to the latch, the reset circuit receiving the latch signal, and resetting the output of the latch in response to the latch signal.

[0023] Illustratively, the latch circuit further includes an output circuit connected to the latch, the output circuit receiving an output of the latch and generating a latched comparison signal pair.

[0024] Illustratively, the switch is closed in response to receiving one of a pair of latched comparison signals generated by the output circuit when the output of the latch is reset.

[0025] By way of example, the latch circuit further comprises a conduction circuit coupled between the switch circuit and the pre-amplifier circuit, wherein the conduction circuit receives the latch signal, and

[0026] During a latching phase of the latch circuit indicated by the latching signal, the conduction circuit is closed; and

[0027] During a reset phase of the latch circuit indicated by the latch signal, the conduction circuit is opened.

[0028] For example, the conduction circuit includes:

[0029] a PMOS transistor (P43) having a source connected to receive one of the pre-amplified differential signal pair, a drain connected to the switch circuit, and a gate receiving an inverted signal of the latch signal; and

[0030] The NMOS transistor (N42) has a gate receiving an inverted signal of the latch signal, and a source and a drain coupled to the first and second input terminals of the latch, respectively.

[0031] In another embodiment, a method for latching and comparing a differential input signal pair in_p and in_m is provided, comprising:

[0032] Pre-amplifying the differential input signal pair in_p and in_m to generate a pre-amplified differential signal pair x0 and y0;

[0033] Comparing the pre-amplified differential signal pair x0 and y0 by a latch to generate a latched comparison signal pair; and

[0034] One of the latched comparison signal pair is received by a switch of the switching circuit, and the switch is switched in response to the one of the latched comparison signal pair.

[0035] For example, the method further comprises:

[0036] Receiving the pre-amplified differential signal pair x0 and y0 by an input circuit;

[0037] receiving a latch signal by a set circuit connected to an output terminal of the input circuit; and

[0038] In the reset mode indicated by the latch signal, the output at the output terminal of the input circuit is set by the setting circuit.

[0039] For example, the latch performs:

[0040] receiving a first one of the pre-amplified differential signal pair at a source of the first NMOS transistor;

[0041] receiving, at a source of the second NMOS transistor, a second of the pair of pre-amplified differential signals passing through the switch circuit;

[0042] connecting the gate of the first NMOS transistor to the source of the second NMOS transistor, and connecting the gate of the second NMOS transistor to the source of the first NMOS transistor; and

[0043] The latched comparison signal pair is provided to sources of the first and second NMOS transistors.

[0044] Illustratively, a switch receiving one of the latched comparison signal pair performs:

[0045] connecting a switch between the preamplifier circuit and the source of the second NMOS transistor; and

[0046] The latched comparison signal of the source of the first NMOS transistor is provided to the switch as a control signal.

[0047] For example, the method further comprises:

[0048] coupling another switch of the switch circuit between the preamplifier circuit and the source of the first NMOS transistor; and

[0049] The latched comparison signal of the source of the second NMOS transistor is provided to another switch as a control signal.

[0050] For example, the method further comprises:

[0051] In response to the latch signal indicating a reset mode, an output of the latch is reset by a reset circuit connected to the latch.

[0052] For example, the method further comprises:

[0053] receiving the output of the latch by the output circuit; and

[0054] The output circuit uses the output of the latch to produce a latched comparison signal pair.

[0055] For example, the method further comprises:

[0056] In response to the latch signal indicating a latch mode, latching the pre-amplified differential signal pair x0 and y0 in the latch by the conduction circuit; and

[0057] In response to the latch signal indicating the reset mode, the provision of the pre-amplified differential signal pair x0 and y0 to the latch is switched by the conduction circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to make the foregoing of the present invention understood in a more specific manner, a further detailed description of the present invention can be obtained with reference to the embodiments, some of which are shown by the attached illustrations. The accompanying illustrations only show typical embodiments of the present invention, and because the present invention can have other equally effective embodiments, the accompanying illustrations should not be construed as limiting the scope of the present invention. The accompanying drawings are drawn for ease of understanding rather than for measuring the present invention. For those skilled in the art, the benefits of the claimed subject matter will be readily understood after reading this description and in conjunction with the accompanying illustrations. In the accompanying drawings, similar reference numerals are used to indicate similar elements, and:

[0059] Figure 1 It is a schematic diagram of a latching comparator;

[0060] Figure 2 is a schematic diagram of a latch comparator according to an embodiment of the present invention;

[0061] Figure 3 yes Figure 2 The circuit diagram of the latch comparator in FIG.

[0062] Figure 4 yes Figure 2 , Figure 3 A schematic diagram of waveforms of signals of a latched comparator in FIG.

[0063] Figure 5 The figure is a waveform diagram of a signal of an existing latched comparator. DETAILED DESCRIPTION

[0064] Reference now Figure 2 , which shows a latch comparator 200 according to an exemplary embodiment of the present invention. The latch comparator 200 includes a pre-amplifier circuit 202 and a latch circuit 204. Figure 1Similar to the preamplifier 102 of the latch comparator 100 in FIG. 2 , the preamplifier circuit 202 has a first input terminal and a second input terminal, which receive differential input signals in_p and in_m. The preamplifier circuit 202 amplifies the differential input signals in_p and in_m and generates a pre-amplified differential signal. The latch circuit 204 is connected to the preamplifier circuit 202 and receives the pre-amplified differential signal. The latch circuit 204 compares the pre-amplified differential signal and generates a pair of latched comparison signals out_p and out_m as the output of the latch comparator 200. The latch circuit 204 also receives a latch signal. The latch signal configures the latch circuit 204 to operate in a reset mode or a latch mode. In the reset mode, the outputs out_p and out_m of the latch comparator 200 are reset.

[0065] The latch circuit 204 includes an input circuit 206 , a latch 208 , an output circuit 210 , a switch circuit 212 , a reset circuit 214 , a turn-on circuit 216 , and a set circuit 218 .

[0066] The input circuit 206 is connected to the pre-amplifier circuit 202 to receive the pre-amplified differential signal. The input circuit 206 level-shifts (or amplifies) the pre-amplified differential signal pair and generates a level-shifted signal pair. The level-shifted signal pair is provided to the latch 208 through the conduction circuit 216 and the switch circuit 212.

[0067] The latch 208 has a first and a second input terminal, which receives a level-shifted signal pair. The latch 208 uses the level-shifted signal pair to generate a pair of latched comparison signals. The output circuit 210 is connected to the latch 208 to receive the latched comparison signal and provide the latched comparison signal as the output out_p, out_m of the latched comparator 200. Preferably, the output circuit 210 amplifies and delays the output of the latch 208, and then provides it as the latched comparison signal out_p, out_m.

[0068] The switch circuit 212 is coupled between the input circuit 206 and the latch 208, and is also connected to the output circuit 210. The switch circuit 212 receives the latched comparison signals out_p and out_m as control signals (for opening and closing the switch). In response to the latched comparison signals out_p and out_m, the switch in the switch circuit 212 is closed or opened to connect or disconnect the connection between the input circuit 206 and the latch 208. Figure 22 shows that the switch circuit 212 includes two switches respectively connected to the input terminals of the latch 208. However, in other embodiments, the switch circuit 212 may include one switch connected to one input terminal of the latch 208. Since the latch comparator 200 receives a differential input signal (i.e., a differential signal pair), in the application where the switch in the switch circuit 212 is implemented as a transistor, the transistor receives the latched comparison signal as a gate control signal, and the two switch transistors in the switch circuit 212 respectively connected to the input terminals of the latch 208 ensure that at least one switch transistor is disconnected to prevent voltage conduction into the pre-amplifier circuit 202.

[0069] The reset circuit 214 is connected to the output of the latch 208. The reset circuit 214 also receives the latch signal and resets the output of the latch 208 in a reset mode in response to the latch signal.

[0070] The conduction circuit 216 is connected between the input circuit 206 and the switch circuit 212. The conduction circuit 216 receives a latch signal, which indicates a latch mode or a reset mode. In the latch mode, the conduction circuit 216 allows the level-shifted differential signal to be provided to the latch 208; in the reset mode, the conduction circuit 216 cuts off the level-shifted differential signal from being transmitted to the latch 208.

[0071] The set circuit 218 is connected to the input circuit 206. The set circuit 218 receives the latch signal and sets the output of the input circuit 206 in a reset mode in response to the latch signal.

[0072] Figure 3 Shows Figure 2 2 is a circuit diagram of a latch comparator 200. The preamplifier circuit 202 includes a PMOS bias transistor P20, a pair of PMOS transistors P21, and a pair of NMOS transistors N21. The bias transistor P20 has a gate terminal for receiving a bias signal, a source terminal connected to a supply voltage, and a drain terminal for providing a bias current. The PMOS transistors P21 each have a gate terminal for receiving one of the input signal pairs in_p, in_m, a source terminal connected to the drain terminal of the bias transistor P20 to receive the bias current, and a drain terminal connected to one of the NMOS transistor pair N21. The drain terminal of the PMOS transistor pair P21 provides the pair of pre-amplified differential signals.

[0073] Each of the NMOS transistors N21 has a gate terminal connected to its source terminal and a drain terminal of a corresponding one of the PMOS transistor pair P21. The drain terminal of the NMOS transistor N21 is grounded. Thus, the NMOS transistor N21 is connected as a diode to ground.

[0074] The input circuit 206 includes a pair of PMOS transistors P41. Each PMOS transistor P41 has a gate terminal connected to the drain terminal of a corresponding one of the PMOS transistor pair P21 to receive one of the pre-amplified differential signals. Each of the PMOS transistors P41 also has a source terminal connected to a supply voltage and a drain terminal providing one of the level-shifted signals x1, y1 to the pass circuit 216.

[0075] The latch 208 includes a pair of NMOS transistors N41 connected to each other. The source terminals of the NMOS transistor pair N41 serve as input terminals of the latch 208, which receive the level-shifted differential signal from the input circuit 206. The gate terminal of one of the NMOS transistor pair N41 is connected to the source terminal of the other of the NMOS transistor pair N41. The latched comparison signal generated by the latch 208 is provided at the source terminal of the NMOS transistor pair N41. The drain terminal of the NMOS transistor pair N41 is grounded.

[0076] Each of the NMOS transistor pairs N41 of the latch 208 is connected to a corresponding part of the output circuit 210. Since these corresponding parts are the same, only one of them is described here. Each part includes a first inverter 302 and a second inverter 304. The first inverter 302 is connected to the latch 208 to receive a latched comparison signal (a signal in the differential pair). In the illustrated embodiment, the first inverter 302 includes three transistors connected in series, which receive a latched comparison signal at the gate terminal. The fourth transistor is connected to a pair of nodes between the three transistors connected in series. The second inverter 304 is connected to the first inverter 302 (through one of the nodes and the gate of the fourth transistor). The second inverter 304 provides the output signal out_p or out_m of the latched comparator 200 at its output terminal. The first and second inverters 302 and 304 delay and amplify the latched comparison signal.

[0077] The switch circuit 212 includes a pair of PMOS transistors P42, each having a source terminal connected to the conduction circuit 216, a drain terminal connected to the latch 208 (i.e., the source terminal of the transistor N41), and a gate terminal connected to the output of the second inverter 304 of the output circuit 210 to receive the output signal (out_p or out_m) as a control signal. The PMOS transistor pair P42 thus operates to be turned on to cause equal voltages between the output terminal of the input circuit 206 (i.e., the drain terminal of the PMOS transistor P41) and the output terminal of the latch 208 (i.e., the source terminal of the NMOS transistor N41), or operates to be turned off to cause unequal voltage levels.

[0078] The conduction circuit 216 includes a pair of PMOS transistors P43 and an NMOS transistor N42. The gate terminal of the PMOS transistor pair P43 is connected to the inverter 306, and the inverter 306 receives the latch signal and generates an inverted signal of the latch signal. The source terminal of the PMOS transistor pair P43 is connected to the input circuit 206, and the drain terminal of the PMOS transistor pair is connected to the source terminal of the PMOS transistor pair P42 of the switch circuit 212. The gate terminal of the NMOS transistor N42 also receives the inverted signal of the latch signal from the inverter 306. The source terminal and the drain terminal of the NMOS transistor N42 are connected to the drain terminal of the PMOS transistor P43.

[0079] In the reset mode, the latch signal is low (i.e., a logic low state), and the gate terminal of the PMOS transistor pair P43 in the conduction circuit 216 receives the inverted signal of the latch signal from the inverter 306, so that the PMOS transistor pair P43 is turned off, preventing the output of the input circuit 206 from being provided to the latch 208. However, since the inverted latch signal is high and provided to the gate terminal of the NMOS transistor N42, the NMOS transistor N42 is turned on, so that the voltage levels at the output terminals of the latch 208 are kept equal.

[0080] On the other hand, in the latch mode, the latch signal is high and the inverted latch signal is low, so that the PMOS transistor P43 is turned on, which allows the level-shifted differential signals x1 , y1 generated by the input circuit 206 to be provided to the latch 208 .

[0081] The reset circuit 214 includes a pair of NMOS transistors N43 each having a gate terminal connected to the inverter 306 to receive the inverted latch signal, a source terminal of each connected to the output terminal of the latch 208, ie, the source terminal of the NMOS transistor N41, and a drain terminal of each grounded.

[0082] In the reset mode, the latch signal is low, the inverted latch signal generated by the inverter 306 is high and is provided to the NMOS transistor N43, causing the NMOS transistor N43 to be turned on to pull the voltage on the output terminal of the latch 208 (i.e., the voltage at the source terminal of the NMOS transistor N41) to the ground, so that the output signals out_p and out_m of the latch comparator 200 are reset (set to zero). The output signals out_p and out_m are fed back to the switch circuit 212, i.e., the gate of the transistor P42.

[0083] The setting circuit 218 includes a pair of PMOS transistors P44 connected to the output terminal of the input circuit 206. For each PMOS transistor P44, its gate terminal receives the latch signal, its source terminal is connected to the supply voltage, and its drain terminal is connected to the drain terminal of the PMOS transistor P41 of the input circuit 206.

[0084] In the reset mode, the latch signal is low, and the PMOS transistor P44 is turned on, pushing the output of the input circuit 206 high. However, since the pass circuit 216 is disconnected in the reset mode, the high state output from the input circuit 206 does not affect the output of the latch 208. In the latch mode, the PMOS transistor P44 is turned off, so that the input circuit 206 operates normally and provides its output to the latch 208.

[0085] Figure 2 , Figure 3 The operation of the latching comparator 200 will be described with reference to Figure 4 The signal waveform shown is explained. For comparison, Figure 5 Shown does not include Figure 2 , Figure 3 The switching circuit 212 shown in FIG. 2 latches a signal in the comparator. Figure 4 and Figure 5 The signal in is interpreted as:

[0086] Latch: latch signal;

[0087] x0, y0: signals at the output of the preamplifier circuit;

[0088] x1, y1: signals at the output end of the input circuit;

[0089] x2, y2: Signals at the output end of the conducting circuit.

[0090] refer to Figure 5 In the first reset mode, before time t51, the setting circuit 218 pushes the signals x1, y1 at the output of the input circuit 206 high. Since the reset circuit 214 pushes the output signal of the latch 208 low to ground, and as described above, Figure 5 Shown are the signals in the latched comparator excluding the switch circuit 212, and the signal at the output of the conduction circuit 216 is low.

[0091] In the first latch mode between time t51 and t52, the differential pair input signals in_p and in_m are outputted as x0, y0 by the preamplifier circuit 202, and as signals x1, y1 by the input circuit 206. Since the conduction circuit 216 is on in the latch mode, and since Figure 5 The illustrated diagram shows the signals in the latch comparator excluding the switch circuit 212 , and the signals x1 and y1 are outputted as x2 and y2 by the conduction circuit 216 .

[0092] For example, if the pre-amplified input signal x0 provided by the pre-amplifier circuit 206 to the left PMOS transistor P41 is lower than the signal y0 provided to the right PMOS transistor P41 (provided as a differential signal, one of which is higher and the other is lower), the left PMOS transistor P41 will have a higher conduction level than the right PMOS transistor P41, resulting in a current flowing through the source of the left NMOS transistor N41 of the latch 208 being higher than the current flowing through the source of the right NMOS transistor N41. The higher current causes the voltage at the source terminal of the left NMOS transistor N41 to rise faster, so that the right NMOS transistor N41, which receives the rapidly rising voltage as the gate control signal, enters conduction faster and presents a lower resistance, which will pull the voltage at the source terminal of the right NMOS transistor N41 lower. Finally, the latch 208 outputs the voltage VDD (i.e., the supply voltage) on the left and the ground voltage on the right. The voltage of the signal y1 at the right output terminal of the input circuit 206 is slightly higher than the ground voltage and the voltage of the signal y2 , which is due to the conduction voltage drop of the turned-on PMOS transistor P43 in the conduction circuit 216 .

[0093] At time t52, the reset mode is entered, and the latch signal changes from high to low. As described above, the PMOS transistor P44 of the setting circuit 218 turns on, which pulls up the voltage of the signals x1 and y1 at the output end of the input circuit 206. For the right PMOS transistor P41 of the input circuit 206, the voltage on its drain rises from a level slightly higher than the ground voltage to a level around the power supply voltage VDD. Since the right PMOS transistor P41 has an inherent gate-drain capacitance Cgd, the voltage of the signal y0 on its gate, that is, the voltage of the signal on the right output end of the pre-amplifier circuit 202, will have ripples, such as Figure 5 As shown, the voltage of signal y0 increases after time t52. If the difference between the differential input signal pair is small, the ripple may be relatively large compared to the difference, thereby causing the latch comparator 200 to be unable to recognize the difference and operate incorrectly. On the other hand, due to the capacitor Cgd, the pre-amplified differential signal y0 of the pre-amplifier circuit 202 needs a period of time to recover. If the time required for the recovery is long, so that the recovery process is not completed when the next high-level latch signal arrives, the latch circuit 204 will operate incorrectly because the pre-amplified differential input signals x0 and y0 are affected by the ripple.

[0094] refer to Figure 4 In the present invention, the latch comparator 200 includes a switch circuit 212, and the operation of the latch comparator 200 before the time t41 in the first reset mode is different from that of the latch comparator 200. Figure 5In the first reset mode, the switch transistor P42 of the switch circuit 212 is turned on in response to the received low latched comparison signal from the output circuit 210.

[0095] In the subsequent first latch mode between time t41 and time t42, the latched comparison signal out_p provided by the left NMOS transistor N41 of the latch 208 turns high, while the latched comparison signal out_m provided by the right NMOS transistor N41 turns low. In response, the right PMOS transistor P42 in the switch circuit 212 that receives the high-bit latched comparison signal out_p is turned off. The cut-off right PMOS transistor P42 keeps the signal voltage on the source of the right NMOS transistor N41 in the latch 208 low, while the voltage of the signal y1 on the right output terminal of the input circuit 206 gradually turns high, because under the control of the gate control signal y0, the right PMOS transistor P41 has a certain degree of conduction. On the other side, the low-bit latched comparison signal received by the left switch transistor P42 turns on the left switch transistor P42, thereby having no effect on the operation of the left branch. By Figure 4 It can be seen that shortly after time t41 and before time t42, both signals x1 and y1 go high. At the same time, signal x2 turns high, while signal y2 turns low (to ground potential).

[0096] After time t42, in the second reset mode between time t42 and time t43, the PMOS transistor P44 of the setting circuit 218 becomes conductive to set the signals x1, y1 to high. However, as described above, since the signal voltage on the right output terminal of the input circuit 206 is already high, no voltage change will occur. Thus, in the second reset mode, no voltage ripple will appear on the output terminal of the preamplifier circuit 202.

[0097] Depend on Figure 4 It can be seen that at each latch mode switch, a small ripple appears on the signal y0, for example, at time t41, t43, etc. This is because the increasing output signal out_p turns off the right PMOS transistor P42 in the switch circuit 212, while the signal y1 is falling to ground. In response to the right PMOS transistor P42 being turned off, the signal y1 turns from falling to a high level and begins to grow to a high level, as shown by the signal y1 at around time t41 in the signal waveform. The change of the signal y1 on the drain of the right PMOS transistor P41, as shown in Figure 5As described in the above, the ripple of the pre-amplified differential signal y0 is caused. However, the change of the above signal y1 is relatively mild. This is because when the right PMOS transistor P42 is turned off, the signal y1 itself is in the process of falling and has not reached the ground level, which means that the change of the signal y1 is quite small and is not enough to cause a large ripple on the signal y0. In addition, the pre-amplified differential signal y0 will not be used in the comparison of the next cycle, which facilitates the signal y0 to recover from the smaller ripple almost equivalent to the entire cycle of the latch signal.

[0098] Output circuit 210 introduces a delay into the output signal generated by latch 208 so that switching transistor P42 is switched after the latched comparison signal in latch 208 has the correct logic state. The introduced delay prevents transistor P42 from switching before normal operation of latch 208 is complete.

[0099] In the above-described embodiments, for example, the signal x0 is lower than the signal y0. In other applications, the signal x0 may be higher than the signal y0. The switch circuit 212 includes a pair of switch transistors P42 to cover the high-low relationship between the differential input signals in_p and in_m. Although the latch comparator 200 described in the above-described embodiments has a symmetrical structure, in other embodiments, when the latch comparator 200 receives a single signal (relative to the differential signal), the latch comparator may include only the left half or only the right half of the above-described symmetrical structure.

[0100] Various exemplary embodiments are described herein with reference to specific illustrated examples. The illustrative examples are selected to assist those skilled in the art to form a clear understanding of and implement the various embodiments. However, the scope of systems, structures, and devices that can be constructed to include one or more embodiments, as well as the scope of methods implemented according to one or more embodiments, are not limited by the illustrative examples shown. On the contrary, those skilled in the art will understand based on this specification that many other configurations, structures, and methods can be implemented according to the various embodiments.

[0101] It should be understood that, with respect to the various positional indications used in the foregoing description of the present invention, such as top, bottom, upper, and lower, those indications are given only with reference to the corresponding drawings, and other positional relationships may be substituted when the orientation of the device changes during manufacture or operation. As mentioned above, those positional relationships are described only for the sake of clarity and are not limiting.

[0102] The foregoing description of this specification is with reference to specific embodiments and specific drawings, but the invention should not be limited thereto, but should be given by the claims. The various drawings described are exemplary and non-restrictive. In the drawings, the dimensions of the various elements may be exaggerated for illustrative purposes and may not be drawn to a specific scale. This description should also include discontinuous changes in tolerances and properties of various components and working methods. Various weakened implementations of the invention should also be included.

[0103] The word "comprising" used in this description and claims does not exclude other elements or steps. Unless otherwise specified, when the singular form such as "one" or "an" is used to refer to a certain or uncertain element, the plural number of the element should be included. Thus, the word "comprising" should not be understood to be limited to the items listed thereafter, and should not be understood to exclude other elements or steps; the scope of the description "the device includes items A and B" should not be limited to a device that only includes elements A and B. This description indicates that, for the purpose of this description, only elements A and B of the device are relevant. "Connect", "couple", "couple" all indicate that there is an electrical connection between coupled or connected elements, and do not mean that there are no intermediate elements between them. When describing transistors and their connections, the words gate, drain, and source are interchangeable with gate, drain, source, and gate terminal, drain terminal, and source terminal.

[0104] It will be apparent to those skilled in the art that various detailed changes may be made without departing from the scope of the claims of the present invention.

Claims

1. A latch comparator, characterized in that: The invention comprises a pre-amplifier circuit and a latch circuit connected to the pre-amplifier circuit, wherein: The preamplifier circuit is configured to receive a differential input signal and generate a preamplified differential signal pair; The latch circuit is configured to receive the pre-amplified differential signal pair; the latch circuit compares the pre-amplified differential signal pair and generates a pair of latched comparison signals; wherein the latch circuit includes: an input circuit coupled to the preamplifier circuit, the input circuit comprising first and second PMOS transistors, the first PMOS transistor having a gate terminal and a drain terminal, the gate terminal of the first PMOS transistor being connected to the preamplifier circuit to receive a first of the preamplified differential signal pair, and a second PMOS transistor having a gate terminal and a drain terminal, the gate terminal of the second PMOS transistor being connected to the preamplifier circuit to receive a second of the preamplified differential signal pair; a switch circuit comprising a first switch coupled to a drain terminal of a first PMOS transistor of an input circuit and a second switch coupled to a drain terminal of a second PMOS transistor of the input circuit, wherein the first switch receives a first one of a pair of latched comparison signals as a control signal and switches in response to the first one of the received pair of latched comparison signals, and the second switch receives a second one of the pair of latched comparison signals as a control signal and switches in response to the second one of the received pair of latched comparison signals; and A latch has a first input terminal coupled to the first switch of the switch circuit and a second input terminal coupled to the second switch of the switch circuit; and the latch provides a pair of latched comparison signals.

2. The latch comparator according to claim 1, characterized in that: The latch circuit further includes a setting circuit connected to the input circuit, the setting circuit receiving the latch signal and setting an output of the input circuit in response to the latch signal.

3. The latch comparator according to claim 1, characterized in that: The first switch has a first terminal and a second terminal, the first terminal of the first switch being coupled to the drain terminal of the first PMOS transistor of the input circuit; The second switch has a first terminal and a second terminal, the first terminal of the second switch being coupled to the drain terminal of the second PMOS transistor of the input circuit; as well as The latches include: first and second NMOS transistors, wherein: The source of the first NMOS transistor is connected to the second end of the first switch of the switch circuit, the source of the second NMOS transistor is connected to the second end of the second switch of the switch circuit, The gate of the first NMOS transistor is connected to the source of the second NMOS transistor, The gate of the second NMOS transistor is connected to the source of the first NMOS transistor, The drains of the first and second NMOS transistors are connected to ground, and The sources of the first and second NMOS transistors provide a pair of latched comparison signals.

4. The latch comparator according to claim 3, characterized in that: A first switch of the switch circuit is coupled to a source of the second NMOS transistor, the first switch of the switch circuit has a control terminal, and the control terminal of the first switch receives a first one of a pair of latched comparison signals provided by the second NMOS transistor; The second switch of the switch circuit is coupled to the source of the first NMOS transistor. The second switch of the switch circuit has a control terminal. The control terminal of the second switch receives the second one of the pair of latched comparison signals provided by the first NMOS transistor.

5. The latch comparator according to claim 1, wherein: The latch circuit further includes a reset circuit connected to the latch, the reset circuit receiving the latch signal and resetting the output of the latch in response to the latch signal.

6. The latch comparator according to claim 1, wherein: The latch circuit further includes an output circuit connected to the latch, the output circuit receiving an output of the latch and generating a latched comparison signal pair.

7. A method for latching and comparing a differential input signal pair, characterized in that: include: pre-amplifying the differential input signal pair to generate a pre-amplified differential signal pair; receiving a first one of the pre-amplified differential signal pair at a gate terminal of a first PMOS transistor of an input circuit; receiving a second one of the pre-amplified differential signal pair at a gate terminal of a second PMOS transistor of the input circuit; receiving a first one of the latched comparison signal pair as a control signal by a first switch of the switch circuit, and switching the first switch in response to the first one of the latched comparison signal pair; receiving a second one of the latched comparison signal pair as a control signal by a second switch of the switch circuit, and switching the second switch in response to the second one of the latched comparison signal pair; as well as A latch is coupled to a first switch of a switching circuit to receive a first one of a pair of pre-amplified differential signals and a second switch of a switching circuit to receive a second one of a pair of pre-amplified differential signals, and the latch compares the pre-amplified differential signal pairs to generate first and second ones of a pair of latched comparison signals.

8. The method according to claim 7, characterized in that: Switching circuit execution: A first end of a first switch of the switching circuit receives a first one of the latched comparison signal pair; A first terminal of a second switch of the switching circuit receives a second one of the latched comparison signal pair; as well as Latch execution: coupling a source of the first NMOS transistor to a second terminal of the first switch of the switching circuit to receive a first of the pair of pre-amplified differential signals passing through the first switch of the switching circuit; coupling a source of the second NMOS transistor to a second terminal of a second switch of the switching circuit to receive a second one of the pre-amplified differential signal pair passing through the second switch of the switching circuit; connecting the gate of the first NMOS transistor to the source of the second NMOS transistor, and connecting the gate of the second NMOS transistor to the source of the first NMOS transistor; and The sources of the first and second NMOS transistors provide a latched comparison signal pair.

9. The method according to claim 8, characterized in that The first switch receiving the first of the latched comparison signal pair performs: connecting a first switch between the preamplifier circuit and a source of the first NMOS transistor; as well as providing a first of the pair of latched comparison signals of the source of the second NMOS transistor to the first switch as a control signal; The second switch receiving the second of the latched comparison signal pair performs: connecting a second switch between the preamplifier circuit and the source of the second NMOS transistor; as well as The second one of the pair of latched comparison signals of the source of the first NMOS transistor is provided to the second switch as a control signal.

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