Display Devices

Abstract

The present application relates to a display device. The display device includes a display panel and a display filter, wherein: the display panel includes display pixels; the display filter overlaps the display panel and includes filter pixels, the filter pixels are larger in number than the display pixels, wherein, in units of frames, each of the display pixels is configured to emit light at a brightness corresponding to one grayscale, and wherein, in units of subframes, each of the filter pixels is configured to switch to a transmissive state or a non-transmissive state, wherein each of the subframes is shorter in period than a corresponding frame in a frame.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0172884, filed on Dec. 28, 2018, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. Technical Field

[0003] One or more aspects of embodiments of the present disclosure relate to a display device. Background Art

[0004] As information technology develops, the importance of display devices that provide a connection medium between users and information has been emphasized. For this reason, the use of display devices such as liquid crystal display devices, organic light emitting display devices, and / or plasma display devices has been increasing.

[0005] In a head mounted display (HMD) worn by a user, the distance between the user's eyes and the display panel is closer than in other display devices. Therefore, there is a problem that a non-luminous area in the display panel where no display pixels exist can be visually recognized as a black net by the user's eyes. Summary of the invention

[0006] One or more aspects of embodiments of the present disclosure are directed to a display device capable of preventing or reducing a non-light emitting area of ​​a display panel from being visually recognized and preventing or reducing a moiré phenomenon.

[0007] According to an example embodiment, a display device may include a display panel and a display filter, wherein: the display panel includes display pixels; the display filter overlaps the display panel and includes filter pixels, wherein the filter pixels are greater in number than the display pixels, wherein, in units of frames, each of the display pixels may be configured to emit light at a brightness corresponding to a grayscale; wherein, in units of subframes, each of the filter pixels may be configured to switch to a transmissive state or a non-transmissive state, and wherein each of the subframes is shorter in period than a corresponding frame in a frame.

[0008] Each of the filter pixels may be smaller in area than a corresponding one of the display pixels.

[0009] Each of the filter pixels may include a liquid crystal capacitor and a first transistor, wherein: the liquid crystal capacitor has one electrode connected to a first common electrode and another electrode connected to a first node; the first transistor has a gate electrode connected to a first filter line, one electrode connected to a second common electrode, and another electrode connected to the first node.

[0010] During each period in a frame, a first DC voltage may be supplied to the first common electrode, and during each period in a frame, a second DC voltage having a magnitude different from that of the first DC voltage may be supplied to the second common electrode.

[0011] Each of the filter pixels may further include a second transistor having a gate electrode connected to the second filter line, one electrode connected to the third common electrode, and the other electrode connected to the first node.

[0012] During each period in a frame, a third DC voltage having a magnitude different from that of the second DC voltage may be supplied to the third common electrode.

[0013] During each period in a frame, voltages of different magnitudes may be supplied to the first filter line and the second filter line.

[0014] Voltages of different magnitudes may be alternately supplied to the first filter line and the second filter line in units of subframes.

[0015] The display filter may include a liquid crystal layer, a first substrate, and a second substrate, wherein the first substrate is located between the liquid crystal layer and the display panel; and the second substrate is located on the first substrate and the liquid crystal layer.

[0016] The spacing between the filter pixels in the transmissive state may be set based on the thickness of the first substrate, the refractive index of the first substrate, the spacing between the display pixels, and the target wavelength.

[0017] The spacing between filter pixels in the transmissive state (pch_f) may be set to satisfy the following Equation 1:

[0018] Equation 1

[0019]

[0020] Wherein, GT is the thickness of the first substrate, GN is the refractive index of the first substrate, pch_p is the interval between display pixels, and WL is the target wavelength.

[0021] The first and second groups of filter pixels may overlap corresponding ones of the display pixels, and the second group of filter pixels may be in a non-transmissive state when the first group of filter pixels is in a transmissive state.

[0022] When the first set of filter pixels are in the non-transmissive state, the second set of filter pixels may be in the transmissive state. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings illustrate example embodiments of the inventive concept and, together with the description, serve to explain the principle of the inventive concept. The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification.

[0024] Figure 1 is a block diagram for explaining a display device according to an embodiment of the present invention.

[0025] Figure 2 is a circuit diagram for explaining a display pixel according to an embodiment of the present invention.

[0026] Figure 3 It is used to illustrate Figure 2 A timing diagram of an exemplary driving method for a display pixel.

[0027] Figure 4 and Figure 5 FIG. 1 is a diagram for explaining a display filter according to the conventional technology.

[0028] Figure 6 FIG. 1 is a diagram for explaining a display filter according to an embodiment of the present invention.

[0029] Figure 7 is a circuit diagram for explaining a filter pixel according to an embodiment of the present invention.

[0030] Figure 8 FIG. 1 is a diagram for explaining a display filter according to another embodiment of the present invention.

[0031] Fig. 9 is a circuit diagram for explaining a filter pixel according to another embodiment of the present invention.

[0032] Fig.10 and Fig.11 FIG. 1 is a diagram for explaining a relationship between a display filter and a display panel according to an embodiment of the present invention.

[0033] Fig.12 is a timing chart for explaining a method of driving a display filter according to an embodiment of the present invention.

[0034] Fig.13 and Fig.14 FIG. 1 is a diagram for explaining a method of driving a display filter according to an embodiment of the present invention.

[0035] Fig.15 FIG. 1 is a diagram for explaining a display filter according to another embodiment of the present invention. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The following embodiments are provided so that those skilled in the art will be able to fully understand the present invention. The embodiments can be modified in various ways. The scope of the present invention is not limited to the embodiments described below.

[0037] In order to clearly illustrate the present invention, parts (eg, elements) not related to the description are not provided, and the same or similar components are indicated by the same reference numerals throughout the specification and all the drawings. Therefore, the reference numeral may be used in one or more drawings.

[0038] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and therefore the present invention is not necessarily limited to the size and thickness shown in the drawings. In the drawings, the thickness may be exaggerated to clearly show layers and / or regions.

[0039] Figure 1 is a block diagram for explaining a display device according to an embodiment of the present invention.

[0040] refer to Figure 1 , a display device 10 according to an embodiment of the present invention may include a timing controller 11 , a data driver 12 , a scan driver 13 , an emission driver 14 , a display panel 15 , a display filter 16 , and a filter driver 17 .

[0041] The timing controller 11 may provide the data driver 12 with grayscale values, clock signals, control signals, etc. In addition, the timing controller 11 may provide each of the scan driver 13 , the emission driver 14 , and the filter driver 17 with clock signals, control signals, etc.

[0042] The data driver 12 may generate data signals to be supplied to the data lines D1, D2, D3, ..., Dn by using the grayscale values ​​and the control signal received from the timing controller 11. For example, the data driver 12 may sample the grayscale values ​​using the clock signal and supply data signals corresponding to the grayscale values ​​to the data lines D1 to Dn on a display pixel row basis, where n may be a natural number.

[0043] The scan driver 13 may receive a clock signal, a control signal, etc. from the timing controller 11 to generate a scan signal to be supplied to the scan lines S1, S2, S3, ..., Sm. For example, the scan driver 13 may sequentially supply a scan signal having a pulse of a conduction level to the scan lines S1 to Sm. For example, the scan driver 13 may generate a scan signal in a manner that sequentially transmits a pulse of a conduction level to a next-level circuit according to a clock signal, where m may be a natural number. For example, the scan driver 13 may be configured in the form of a shift register.

[0044] The emission driver 14 may receive a clock signal, a control signal, etc. from the timing controller 11 to generate an emission signal to be supplied to the emission lines E1, E2, E3, ..., Eo. For example, the emission driver 14 may sequentially supply an emission signal having a pulse of an off level to the emission lines E1 to Eo. In another example, the emission driver 14 may sequentially supply an emission signal having a pulse of an on level to the emission lines E1 to Eo, where o may be a natural number. For example, the emission driver 14 may generate an emission signal in a manner that sequentially transmits a pulse of an off level or a pulse of an on level to a next-stage circuit according to a clock signal. For example, the emission driver 14 may be configured in the form of a shift register.

[0045] The display panel 15 may include display pixels. Each of the display pixels may be connected to a data line, a scan line, and an emission line corresponding thereto. When a scan signal of a conduction level is supplied to the scan line, each of the display pixels may store a data signal of the data line. In addition, when an emission signal of a conduction level is supplied to the emission line, each of the display pixels may emit light having a brightness corresponding to the gray scale of the stored data signal. At this time, each of the display pixels may emit light having a brightness corresponding to one gray scale in units of one frame.

[0046] The display filter 16 may be arranged (e.g., positioned) to overlap the display panel 15, and may include a greater number of filter pixels than display pixels. In some embodiments, each of the filter pixels may be switched to a transmissive state or a non-transmissive state in units of subframes, each of which has a period shorter than that of a corresponding frame.

[0047] The filter driver 17 may receive a control signal or the like from the timing controller 11, and generate a filter signal to be supplied to the filter lines F1, F2, F3, ..., Fp, where p may be a natural number. For example, the filter driver 17 may supply voltages of different magnitudes alternately to the first group of filter lines and the second group of filter lines on a subframe basis. For example, the filter driver 17 may supply a high logic level voltage to the first group of filter lines in the first subframe, and a low logic level voltage to the second group of filter lines. Next, the filter driver 17 may supply a low logic level voltage to the first group of filter lines in the second subframe, and a high logic level voltage to the second group of filter lines. Next, the filter driver 17 may supply a high logic level voltage to the first group of filter lines in the third subframe, and a low logic level voltage to the second group of filter lines.

[0048] In one embodiment, the first group of filter lines may be odd-numbered filter lines, and the second group of filter lines may be even-numbered filter lines. In another embodiment, the first group of filter lines may be even-numbered filter lines, and the second group of filter lines may be odd-numbered filter lines, but embodiments of the present invention are not limited thereto. The filter pixels are controlled by a filter signal applied to the filter lines so that each of the filter pixels can be switched to a transmissive state or a non-transmissive state in units of subframes, each of which is shorter in period than a corresponding frame in a frame.

[0049] Although for convenience, Figure 1 It is shown that the filter lines F1, F2, F3, ..., Fp extend in a direction orthogonal to (or intersecting with) the scan lines S1, S2, S3, ..., Sm, but the extending direction of the filter lines F1, F2, F3, ..., Fp and the extending direction of the scan lines S1, S2, S3, ..., Sm may be independent of each other. Therefore, in one embodiment, the filter lines F1, F2, F3, ..., Fp may extend in the same direction as the scan lines S1, S2, S3, ..., Sm.

[0050] Figure 2 is a circuit diagram for explaining a display pixel according to an embodiment of the present invention.

[0051] refer to Figure 2 , the display pixel PXij according to the embodiment of the present invention may include transistors M1 to M7 , a storage capacitor Cst, and a light emitting diode LD.

[0052] In one embodiment, transistors M1 to M7 may be P-type transistors (e.g., PMOS). However, those skilled in the art will be able to construct (obtain) display pixels that perform the same (or substantially the same) function by replacing at least some of transistors M1 to M7 with N-type transistors (e.g., NMOS).

[0053] The first transistor M1 may have a gate electrode connected to the scan line Si, one electrode connected to the data line Dj, and the other electrode connected to one electrode of the second transistor M2. The first transistor M1 may be referred to as a scan transistor, a switching transistor, or the like.

[0054] The storage capacitor Cst may have one electrode connected to the first power line ELVDD and the other electrode connected to the gate electrode of the second transistor M2 .

[0055] The second transistor M2 may have a gate electrode connected to the other electrode of the storage capacitor Cst, one electrode connected to the other electrode of the first transistor M1, and the other electrode connected to the other electrode of the third transistor M3. The second transistor M2 may be referred to as a driving transistor.

[0056] The third transistor M3 may have a gate electrode connected to the scan line Si, one electrode connected to the gate electrode of the second transistor M2, and another electrode connected to the other electrode of the second transistor M2. The third transistor M3 may be referred to as a diode-connected transistor.

[0057] The fourth transistor M4 may have a gate electrode connected to the emission line Ei, one electrode connected to the first power line ELVDD, and the other electrode connected to one electrode of the second transistor M2. The fourth transistor M4 may be referred to as an emission control transistor.

[0058] The fifth transistor M5 may have a gate electrode connected to the scan line S(i-1), one electrode connected to the gate electrode of the second transistor M2, and the other electrode connected to the initialization voltage line VINT. The fifth transistor M5 may be referred to as a gate initialization transistor.

[0059] The sixth transistor M6 may have a gate electrode connected to the emission line Ei, one electrode connected to the other electrode of the second transistor M2, and the other electrode connected to the anode of the light emitting diode LD. The sixth transistor M6 may be referred to as an emission control transistor.

[0060] The light emitting diode LD may have an anode connected to the other electrode of the sixth transistor M6 and a cathode connected to the second power line ELVSS. For example, the light emitting diode LD may be an organic light emitting diode or an inorganic light emitting diode.

[0061] The seventh transistor M7 may have a gate electrode connected to the scan line S(i-1), one electrode connected to the initialization voltage line VINT, and another electrode connected to the anode of the light emitting diode LD. The seventh transistor M7 may be referred to as an anode initialization transistor. In another embodiment, the gate electrode of the seventh transistor M7 may be connected to another scan line.

[0062] Figure 3 It is used to illustrate Figure 2 A timing diagram of an exemplary driving method for a display pixel.

[0063] First, when a scan pulse of the on-level is supplied to the scan line S(i-1), transistors M5 and M7 may be turned on. Hereinafter, a pulse of the on-level may refer to a pulse having a voltage level capable of turning on a transistor supplied with a corresponding pulse. In the present embodiment, transistors M1 to M7 may be P-type transistors, and thus transistors M1 to M7 may be turned on at a low level voltage and may be turned off at a high level voltage. When the fifth transistor M5 is turned on, the gate electrode of the second transistor M2 is connected to the initialization voltage line VINT, and the voltage accumulated in the gate electrode of the second transistor M2 may be initialized. In addition, when the seventh transistor M7 is turned on, the anode of the light emitting diode LD is connected to the initialization voltage line VINT, and the light emitting diode LD may be initialized by discharging or precharging. The initialization voltage supplied to the initialization voltage line VINT may be equal to the second voltage supplied to the second power line ELVSS. The second voltage may have a voltage level lower than the first voltage supplied to the first power line ELVDD.

[0064] Subsequently, when a scan pulse of a conduction level is supplied to the scan line Si, the transistors M1 and M3 may be turned on. At this time, the second transistor M2 whose gate electrode voltage is initialized may be turned on. Therefore, the data signal DATAij supplied to the data line Dj may be transferred to the other electrode of the storage capacitor Cst via the first transistor M1, the second transistor M2, and the third transistor M3. At this time, the voltage of the data signal DATAij supplied to the other electrode of the storage capacitor Cst may reduce the threshold voltage of the second transistor M2.

[0065] Thereafter, when the emission signal of the on level is supplied to the emission line Ei, the transistors M4 and M6 may be turned on, and a drive current path may be formed through the first power line ELVDD, the fourth transistor M4, the second transistor M2, the sixth transistor M6, the light emitting diode LD, and the second power line ELVSS. The light emitting diode LD may emit light having a brightness corresponding to the amount of the drive current flowing along the drive current path. The amount of the drive current may depend on the voltage level of the data signal DATAij supported by the other electrode of the storage capacitor Cst. At this time, since the drive current flows through the second transistor M2, the threshold voltage reduction reflected in the data signal DATAij at the other electrode of the storage capacitor Cst can be mitigated or offset. Therefore, according to the display pixel PXij of the present embodiment, the drive current may flow regardless of the process variation of the threshold voltage of the second transistor M2.

[0066] Figure 4 and Figure 5 FIG. 1 is a diagram for explaining a display filter according to the conventional technology.

[0067] Figure 41 is a plan view showing a portion of the display panel 15 and a portion of the related art display filter 16 a with reference to the first direction DR1 and the second direction DR2 . Figure 5 is along Figure 4 2 is a cross-sectional view of a portion of the display panel 15 and a portion of the display filter 16a taken along line II' in FIG. The first direction DR1, the second direction DR2, and the third direction DR3 may be orthogonal to (or intersect with) each other.

[0068] The display panel 15 may include a plurality of display pixels, including a display pixel PXij. Here, the position of each of the display pixels may correspond to the position of the light emitting diode LD of each of the display pixels. A portion of the display panel 15 where no display pixel exists may correspond to the non-luminous area NEA. For example, the display panel 15 may include a pixel defining layer that defines the position of the light emitting diode LD, and a portion of the pixel defining layer where the light emitting diode LD does not exist may be the non-luminous area NEA.

[0069] Figure 4 The positions of the display pixels shown in FIG. 1 are examples, and the embodiments of the present disclosure are not limited thereto. The display pixels may be arranged in various suitable manners such as a stripe structure, a pentile structure, an S-stripe structure, and the like.

[0070] The display filter 16a may include a plurality of holes, including holes hl1 and holes hl2. The plurality of holes hl1 and hl2 may be arranged at regular intervals with respect to each of the first direction DR1 and the second direction DR2, respectively. For example, the display filter 16a may be composed of an inorganic film and / or an organic film, and the plurality of holes may be formed by etching the inorganic film and / or the organic film.

[0071] For example, when the display pixel PXij emits light, the diffracted light wave lw1 may be emitted through the hole hl1, and the diffracted light wave lw2 may be emitted through the hole hl2. Figure 5 For example, based on the coordinates of the first direction DR1, the intensities of the diffracted light waves lw1 and lw2 are shown in the third direction DR3. Therefore, when the display device of the related art includes the display filter 16a, an image can be displayed on a portion corresponding to the non-luminous area NEA where the display pixel PXij does not exist, and the black mesh shape caused by the non-luminous area NEA may not be visible to the user.

[0072] However, when the holes hl1, hl2, ... have Figure 4 and Figure 5When the fixed shape shown in FIG. 1 is used, a moiré phenomenon may occur when the display pixel displays an image of a specific pattern. That is, when an image of a specific pattern is displayed, a moiré pattern in the shape of stripes can be visually recognized by the user, while diffracted light emitted from adjacent display pixels may cause constructive interference and destructive interference. When the relative positions of the display pixels and the holes hl1, hl2, ... are fixed Figure 4 and Figure 5 This problem cannot be solved in the implementation method of .

[0073] Figure 6 FIG. 1 is a diagram for explaining a display filter according to an embodiment of the present invention. Figure 7 is a circuit diagram for explaining a filter pixel according to an embodiment of the present invention.

[0074] refer to Figure 6 , the display filter 16b may include filter lines F(q-2) to F(q+2) and filter pixels FX(q-1)(r-1) to FX(q+1)(r+1), where q and r may be natural numbers.

[0075] In this embodiment, at least some of the filter pixels located in the same row may be connected to different filter lines. For example, although the filter pixels FXq(r-1), FXqr, and FXq(r+1) are located in the same qth row, the filter pixel FXqr may be connected to the filter line Fq, and the filter pixels FXq(r-1) and FXq(r+1) may be connected to the filter line F(q+1).

[0076] refer to Figure 7 , the filter pixel FXqr may include a first transistor T1 and a liquid crystal capacitor Clc.

[0077] The liquid crystal capacitor Clc may have one electrode connected to the first common electrode Vcom1 and another electrode connected to the first node N1. A dielectric layer of the liquid crystal capacitor Clc may be a liquid crystal layer.

[0078] The first transistor T1 may have a gate electrode connected to the first filter line Fq, one electrode connected to the second common electrode Vcom2 , and the other electrode connected to the first node N1 .

[0079] The first common electrode Vcom1 and the second common electrode Vcom2 may be commonly provided to the filter pixel. During each of a plurality of frames including one frame, a first direct current (DC) voltage may be supplied to the first common electrode Vcom1, and during each of the plurality of frames, a second DC voltage may also be supplied to the second common electrode Vcom2. In another embodiment, the first DC voltage and the second DC voltage may be different from each other.

[0080] In one embodiment, when the first transistor T1 is turned off and the first node N1 is in a floating state, the characteristics of the liquid crystal capacitor Clc may be set so that the filter pixel FXqr is in a non-transmitting state. In this case, the filter pixel FXqr may be implemented as a normally black type (eg, a black filter pixel).

[0081] When the first transistor T1 is turned on and an electric field is formed according to a voltage difference between both ends of the liquid crystal capacitor Clc, the filter pixel FXqr may be in a transmission state.

[0082] In another embodiment, when the first transistor T1 is turned off and the first node N1 is in a floating state, the characteristics of the liquid crystal capacitor Clc may be set so that the filter pixel FXqr is in a transmissive state. In this case, the filter pixel FXqr may be implemented as a normally white type (eg, a white filter pixel).

[0083] When the first transistor T1 is turned on and an electric field is formed according to a voltage difference between both ends of the liquid crystal capacitor Clc, the filter pixel FXqr may be in a non-transmitting state.

[0084] The characteristics of the liquid crystal capacitor Clc can be set according to (for example, can depend on) the following: the kind (or type) of liquid crystal molecules, the interface orientation of the liquid crystal molecules (for example, the pre-tilt angle with the substrate), the polarization axis direction of at least one polarizing film, the physical position relationship between the constituent electrodes of the first node N1 and the first common electrode Vcom1, etc.

[0085] For example, the characteristics of the liquid crystal capacitor Clc may be set by various suitable modes such as IPS (In-Plane Switching) mode, FFS (Fringe Field Switching) mode, TN (Twisted Nematic) mode, and / or VA (Vertical Alignment) mode.

[0086] Figure 8 FIG. 1 is a diagram for explaining a display filter according to another embodiment of the present invention.

[0087] Fig. 9 is a circuit diagram for explaining a filter pixel according to another embodiment of the present invention.

[0088] refer to Figure 8 , the display filter 16b' may include filter lines F(q-2) to F(q+2) and filter pixels FX(q-1)(r-1)' to FX(q+1)(r+1)'.

[0089] In this embodiment, the filter pixels located in the same row may be connected to the same filter line. For example, the filter pixels FXq(r-1)', FXqr' and FXq(r+1)' may be located in the same qth row, and the filter pixels FXq(r-1)', FXqr' and FXq(r+1)' may be connected to the same filter lines Fq and F(q+1).

[0090] refer to Fig. 9 , the filter pixel FXqr' may include a first transistor T1', a second transistor T2', and a liquid crystal capacitor Clc'.

[0091] The liquid crystal capacitor Clc' may have one electrode connected to the first common electrode Vcom1 and another electrode connected to the first node N1'. A dielectric layer of the liquid crystal capacitor Clc' may be a liquid crystal layer.

[0092] The first transistor T1 ′ may have a gate electrode connected to the first filter line Fq, one electrode connected to the second common electrode Vcom2 , and the other electrode connected to the first node N1 ′.

[0093] The second transistor T2 ′ may have a gate electrode connected to the second filter line F(q+1), one electrode connected to the third common electrode Vcom3 , and the other electrode connected to the first node N1 ′.

[0094] During each of a plurality of frames including one frame, a first DC voltage may be supplied to the first common electrode Vcom1, and during each of the plurality of frames, a second DC voltage may be supplied to the second common electrode Vcom2. In addition, during each of the plurality of frames, a third DC voltage may be supplied to the third common electrode Vcom3.

[0095] In one embodiment, the magnitudes (levels) of the second DC voltage and the third DC voltage may be different from each other. For example, one of the second DC voltage and the third DC voltage may have the same magnitude as the first DC voltage. In this article, the case where the third DC voltage has the same magnitude as the first DC voltage will be described, but the embodiments of the present disclosure are not limited thereto.

[0096] refer to Figure 7 and Fig. 9 When a voltage difference between the first DC voltage and the second DC voltage is generated at both ends of the liquid crystal capacitor Clc' as described above, an electric field may be generated, and the filter pixel FXqr' may be in a transmission state or a non-transmission state.

[0097] In this embodiment, the first DC voltage and the third DC voltage may be supplied to both ends of the liquid crystal capacitor Clc', and since there is no voltage difference across the liquid crystal capacitor Clc', no electric field may be generated. Figure 7 In the embodiment of the present invention, the discharge is faster, so the switching speed between the transmission state and the non-transmission state of the filter pixel FXqr' can be accelerated.

[0098] Fig.10 and Fig.11 FIG. 1 is a diagram for explaining a relationship between a display filter and a display panel according to an embodiment of the present invention.

[0099] The display filter 16b may include a greater number of filter pixels FXq(r-1), FXqr, FXq(r+1), etc. than the display pixel PXij, etc. For example, four or more filter pixels FXq(r-1), FXqr, FXq(r+1), etc. may overlap with one display pixel PXij. Although an embodiment has been described in which nine filter pixels FXq(r-1), FXqr, FXq(r+1), etc. overlap with one display pixel PXij, the number of overlapping filter pixels FXq(r-1), FXqr, FXq(r+1), etc. may be changed in another embodiment. The area of ​​each of the filter pixels FXq(r-1), FXqr, FXq(r+1), etc. may be smaller than the area of ​​the display pixel PXij.

[0100] The display filter 16 b may include a first substrate 161 , a liquid crystal layer 162 , and a second substrate 163 .

[0101] The first substrate 161 may be disposed between the liquid crystal layer 162 and the display panel 15. The second substrate 163 may be disposed on the first substrate 161 and the liquid crystal layer 162. For example, the first substrate 161 and the second substrate 163 may cover the liquid crystal layer 162 to seal the liquid crystal layer 162.

[0102] In one embodiment, the first common electrode Vcom1 may be located on one side of the second substrate 163. Each of the filter pixels FXq(r-1), FXqr (or FXqr'), FXq(r+1), etc. may be defined by a corresponding filter electrode of the filter electrodes feq(r-1), feqr, feq(r+1), etc. Each of the filter electrodes feq(r-1), feqr, feq(r+1), etc. may be a conductor corresponding to the first node N1 (or N1') of each of the filter pixels. Each of the liquid crystal capacitors Clc (or Clc') may be composed of the filter electrodes feq(r-1), feqr, feq(r+1), etc., the first common electrode Vcom1, and the liquid crystal layer 162. In one embodiment, the corresponding filter electrodes feq(r-1), feqr, feq(r+1), etc. may be located on one side of the first substrate 161.

[0103] exist Fig.11 In the embodiment, the element is shown based on the TN mode, VA mode, etc., but in the IPS mode, FFS mode, etc., the filter electrode and the first common electrode can be located on the same substrate. In addition, a polarizing film can be provided on at least one of the first substrate 161 and the second substrate 163.

[0104] Hereinafter, a case where the filter pixels FXq(r-1) and FXq(r+1) are in a transmission state and the filter pixel FXqr is in a non-transmission state will be described, but the embodiments of the present disclosure are not limited thereto. At this time, diffracted light may be emitted through the filter pixels FXq(r-1) and FXq(r+1). The description of diffracted light may be combined with Figure 5 Same description provided.

[0105] Referring to Equation 1 below, the interval pch_f between the filter pixels FXq(r-1) and FXq(r+1) in the transmission state can be determined by the thickness GT of the first substrate 161, the refractive index GN of the first substrate 161, the interval pch_p between the display pixel PXij and the display pixel PXi(j+1), and the target wavelength WL.

[0106] Equation 1

[0107]

[0108] The target wavelength WL may refer to a wavelength when the non-luminous area NEA of the display panel 15 is not visible. The target wavelength WL may be set to one of the wavelengths in the visible light band. For example, the target wavelength WL may be 656 nm so that the diffraction effect on red light appears well. In some embodiments, for example, the target wavelength WL may be 555 nm so that the diffraction effect on green light appears well. In some embodiments, for example, the target wavelength WL may be 454 nm so that the diffraction effect on blue light appears well.

[0109] The interval pch_f between the filter pixel FXq(r-1) in the transmission state and the filter pixel FXq(r+1) can be the interval between the centers of the closest transmission state filter pixels FXq(r-1) and FXq(r+1), or the interval between the centers of the filter electrodes feq(r-1) and feq(r+1) of the closest transmission state filter pixels FXq(r-1) and FXq(r+1).

[0110] In some embodiments, the interval pch_p between the display pixel PXij and the display pixel PXi(j+1) may be the interval between the centers of the most adjacent display pixels PXij and PXi(j+1).

[0111] Fig.12 is a timing chart for explaining a method of driving a display filter according to an embodiment of the present invention. Fig.13 and Fig.14 FIG. 1 is a diagram for explaining a method of driving a display filter according to an embodiment of the present invention.

[0112] Each of the display pixels according to the present embodiment can emit light having a brightness corresponding to a grayscale in one frame unit. For example, any display pixel can store a first data signal corresponding to a first grayscale in a first frame FR1, and store a second data signal corresponding to a second grayscale in a second frame FR2. Therefore, any display pixel can emit light having a brightness corresponding to a first grayscale in a first frame FR1, and emit light having a brightness corresponding to a second grayscale in a second frame FR2. The generation time point of the conduction level pulse of the scanning signal for storing the data signal can be different for each of the scanning lines. Therefore, each frame period can be different for each scanning line.

[0113] Each of the filter pixels according to the present embodiment can be switched to a transmissive state or a non-transmissive state in units of subframes, each of which is shorter in period than a corresponding frame. Voltages of different magnitudes can be alternately supplied to the first group of filter lines Fq and F(q+2) and the second group of filter lines F(q-1) and F(q+1) in units of subframes.

[0114] refer to Fig.12 and Fig.13 For example, in the first subframe SF1, the filter signal of the cut-off level (high level voltage) can be supplied to the first group of filter lines Fq and F(q+2), and the filter signal of the on level (low level voltage) can be supplied to the second group of filter lines F(q-1) and F(q+1). Assuming the normally white mode, in the first subframe SF1, the first transistor T1 (see Figure 7 ) whose gate electrodes are connected to the filter pixels FX(q-1)(r-1), FX(q-1)(r+1), FXqr, FX(q+1)(r-1), and FX(q+1)(r+1) of the first group of filter lines Fq and F(q+2) become non-transmissive states, and the gate electrodes of the first transistors T1 are connected to the filter pixels FX(q-1)r, FXq(r-1), FXq(r+1), and FX(q+1)r of the second group of filter lines F(q-1) and F(q+1) become transmissive states. The same description may be applied to the third subframe SF3.

[0115] refer to Fig.12 and Fig.14 For example, in the second subframe SF2, the filter signal of the on level may be supplied to the first group of filter lines Fq and F(q+2), and the filter signal of the off level may be supplied to the second group of filter lines F(q-1) and F(q+1). Assuming the normally white mode, in the second subframe SF2, the filter pixels FX(q-1)(r-1), FX(q-1)(r+1), FXqr, FX(q+1)(r-1), and FX(q+1)(r+1) whose gate electrodes of the first transistor T1 are connected to the first group of filter lines Fq and F(q+2) become the transmission state, and the filter pixels FX(q-1)r, FXq(r-1), FXq(r+1), and FX(q+1)r whose gate electrodes of the first transistor T1 are connected to the second group of filter lines F(q-1) and F(q+1) become the non-transmission state. The same description may be applied to the fourth subframe SF4.

[0116] Fig.13 The positions of the filter pixels FX(q-1)r, FXq(r-1), FXq(r+1), and FX(q+1)r in the transmission state overlapping with the display pixel PXij in the first subframe SF1 and the third subframe SF3 may correspond to Figure 4 Therefore, according to this embodiment, the positions of the holes hl1, hl2, etc. overlap with the display pixels PXij. Figure 4 Similarly, it is possible to prevent or reduce the black screen shape caused by the non-light emitting area NEA from being visible to the user.

[0117] However, according to the embodiments of the present disclosure, Figure 4 The fixing holes are different, such as Fig.14 As shown in, by changing the positions of the filter pixels FX(q-1)(r-1), FX(q-1)(r+1), FXqr, FX(q+1)(r-1), and FX(q+1)(r+1) in the transmission state in the second subframe SF2 and the fourth subframe SF4, the moiré phenomenon can be prevented or reduced. According to this embodiment, in the second subframe SF2 and the fourth subframe SF4, the interval pch_f between the filter pixels FX(q-1)(r-1), FX(q-1)(r+1), FXqr, FX(q+1)(r-1), and FX(q+1)(r+1) in the transmission state can be maintained (refer to the description of Equation 1), so that the black mesh shape in the non-luminous area NEA with respect to the target wavelength WL can be prevented or reduced from being seen by the user.

[0118] Fig.15 FIG. 1 is a diagram for explaining a display filter according to another embodiment of the present invention.

[0119] refer to Fig.15 , a case where a plurality of sub-filter pixels constitute one filter pixel mFXqr is shown by way of example. The plurality of sub-filter pixels constituting the filter pixel mFXqr may be in a transmission state at the same time or may be in a non-transmission state at the same time. Fig.15 The case where the filter pixel mFXqr is in a non-transmissive state is shown.

[0120] According to the present embodiment, the filter pixel mFXqr may be in the form of a rhombus rather than a rectangle. However, in another embodiment, the shape and position of the filter pixel mFXqr may be determined in various ways, and the embodiments of the present disclosure are not limited thereto.

[0121] The display device according to the embodiment of the present invention can prevent or reduce the non-light emitting area of ​​the display panel from being visually recognized by the user, and can prevent or reduce the moiré phenomenon.

[0122] As used herein, the terms "use," "using," and "used" may be understood as synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0123] It will be understood that when an element is referred to as being "on," "connected to," or "coupled to" another element, it may be directly on, directly connected to, or directly coupled to the other element, or there may be one or more intervening elements. When an element is referred to as being "directly" "on," "directly connected to," or "directly coupled to" another element, there are no intervening elements. For example, when a first element is described as being "coupled to" or "connected to" a second element, the first element may be directly coupled or connected to the second element, or the first element may be indirectly coupled or connected to the second element via one or more intervening elements.

[0124] It will be further understood that the terms “comprises” and / or “comprising” as used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0125] When following a list of elements, expressions such as “at least one of,” “one of,” and “selected from,” modify the entire list of elements rather than the individual elements of the list. In addition, “may,” when used in describing embodiments of the present invention, means “one or more embodiments of the present invention.”

[0126] The display device and / or any other related device or component according to the embodiment of the present invention described herein can be implemented using any appropriate hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of the device can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of the device can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of the device can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components for performing various functions described herein. Computer program instructions are stored in a memory that can be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM). Computer program instructions can also be stored in other non-temporary computer-readable media, such as, for example, a CD-ROM, a flash drive, etc. In addition, those skilled in the art will recognize that, without departing from the scope of the exemplary embodiments of the present invention, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a specific computing device can be distributed to one or more other computing devices.

[0127] The accompanying drawings and the detailed description of the present invention referred to so far are only illustrations of the present invention. It will be understood that the present invention is disclosed only for illustrative purposes and is not intended to limit the scope of the present invention. Therefore, it will be understood by those skilled in the art that various modifications and equivalent embodiments are feasible without departing from the scope of the present invention. Therefore, the true scope of the present invention should be determined by the attached claims and their equivalent technical concepts.

Claims

1. Display equipment, including: A display panel including display pixels; as well as a display filter overlapping the display panel and comprising filter pixels, wherein the filter pixels are greater in number than the display pixels, Wherein, each of the filter pixels comprises: a liquid crystal capacitor having one electrode connected to the first common electrode and another electrode connected to the first node; a first transistor having a gate electrode connected to the first filter line, one electrode connected to the second common electrode, and another electrode connected to the first node; and a second transistor having a gate electrode connected to the second filter line, one electrode connected to the third common electrode, and another electrode connected to the first node, Wherein, in units of frames, each of the display pixels is configured to emit light at a brightness corresponding to a grayscale, wherein each of the filter pixels is configured to switch to a transmissive state or a non-transmissive state in units of subframes, and Each of the subframes is shorter in period than a corresponding frame in the frames.

2. The display device according to claim 1, wherein: Each of the filter pixels is smaller in area than a corresponding one of the display pixels.

3. The display device according to claim 1, wherein: During each period of the frame, a first DC voltage is supplied to the first common electrode, and During each period in the frame, a second DC voltage having a magnitude different from that of the first DC voltage is supplied to the second common electrode.

4. The display device according to claim 3, wherein: During each period in the frame, a third DC voltage having a magnitude different from that of the second DC voltage is supplied to the third common electrode.

5. The display device according to claim 4, wherein: During each period in the frame, voltages of different magnitudes are supplied to the first filter line and the second filter line, and The voltages of different magnitudes are alternately supplied to the first filter line and the second filter line in units of subframes.

6. The display device according to claim 1, wherein: The display filters include: Liquid crystal layer; A first substrate, located between the liquid crystal layer and the display panel; and The second substrate is located on the first substrate and the liquid crystal layer.

7. The display device according to claim 6, wherein: the spacing between the filter pixels in the transmissive state is set based on the thickness of the first substrate, the refractive index of the first substrate, the spacing between the display pixels, and the target wavelength, Wherein the spacing (pch_f) between the filter pixels in the transmissive state is set to satisfy Equation 1: Equation 1 Wherein, GT is the thickness of the first substrate, GN is the refractive index of the first substrate, pch_p is the interval between the display pixels, and WL is the target wavelength.

8. The display device according to claim 1, wherein: The filter pixels of a first group and the filter pixels of a second group overlap corresponding ones of the display pixels, and when the filter pixels of the first group are in the transmissive state, the filter pixels of the second group are in the non-transmissive state, and Wherein, when the filter pixels of the first group are in the non-transmitting state, the filter pixels of the second group are in the transmissive state.

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