Method, Circuit and Clock Generation Device for Preventing Clock Overshoot

Abstract

The present invention relates to a method, a circuit and a clock generating device for preventing clock overshoot. The method for preventing clock overshoot includes: obtaining a post-division control signal of a phase-locked loop and determining whether the post-division control signal changes; when the post-division control signal changes, obtaining an input signal and a feedback signal of the phase-locked loop, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, where the states of the phase-locked loop include a locked state and an unlocked state; when the current state is the unlocked state, performing a frequency reduction process on the output signal of the phase-locked loop and using the signal after the frequency reduction process as a clock signal; when the current state is the locked state, directly using the output signal of the phase-locked loop as the clock signal. Implementing the technical solution of the present invention can provide an available clock at a lower cost, more reliably and more quickly, improve the software operation efficiency and save power consumption.

Description

Technical Field

[0001] The present invention relates to the field of phase-locked loops, and particularly to a method, a circuit and a clock generating device for preventing clock overshoot. Background Art

[0002] A phase-locked loop is a feedback control circuit, called a phase-locked loop (PLL for short). It uses an externally input reference signal to control the frequency and phase of the internal oscillation signal of the loop. In the process of processing electronic signals, because the phase-locked loop can realize the automatic tracking of the output signal frequency to the input signal frequency, the phase-locked loop is usually widely used in closed-loop tracking circuits. In the field of clocks, clock phase-locked loops are widely used in the generation of clocks.

[0003] As Figure 1 shown, a clock phase-locked loop usually consists of several parts: a phase detector PD, a loop filter LPF, a voltage-controlled oscillator VCO, a loop divider LPDIV, and a post divider PSTDIV. The post divider PSTDIV can make the clock output range wider, or greatly reduce the working range of the voltage-controlled oscillator VCO. Therefore, the design difficulty can be reduced and the reliability can be improved.

[0004] The phase detector PD is a unit that completes phase comparison. Its function is to compare the phase difference between the input signal Fin and the feedback signal Fback. Its output voltage is proportional to the phase difference between the two input signals.

[0005] The low-pass filter LPF is an active or passive low-pass filter. Its function is to filter out the high-frequency components (including mixing and other high-frequency noises) in the output voltage of the phase detector, play a role of smoothing filtering, and finally output a control signal Vc. It is usually composed of resistors, capacitors or inductors, and sometimes also includes an operational amplifier.

[0006] The voltage-controlled oscillator VCO is an oscillator whose oscillation frequency is controlled by a control voltage, and there is a linear relationship between its oscillation frequency and the control voltage. The oscillator VCO outputs a corresponding oscillation frequency Fosc according to the control signal Vc.

[0007] The loop divider LPDIV determines the ratio of the input and oscillation clocks, which can be an integer or a decimal. The relationship is Fosc = N(lpdiv)*Fin.

[0008] The post divider PSTDIV re-determines how Fosc needs to be adjusted before output, which can be an integer or a decimal. Finally, the clock output Fout = [N(lpdiv) / N(pstdiv)]*Fin.

[0009] Generally speaking, after the PLL clock is locked, since the phase difference between the feedback clock and the input clock is stable, a stable clock can be output. When we want to change the output frequency Fout of the PLL, we only need to change the division factor REG_LOOP corresponding to the loop divider and the division factor REG_POST corresponding to the post divider.

[0010] As we all know, the equation describing a second-order phase-locked loop is a second-order nonlinear differential equation. In a second-order phase-locked loop system, the voltage-controlled oscillator VCO can be regarded as an ideal integrator. Therefore, from the perspective of the system, if the low-pass filter LPF is first-order, the phase-locked loop PLL can be regarded as a second-order system. For a second-order system, there are a natural frequency ωn and a damping coefficient ξ. If the internal parameters of the system are suddenly changed, an eigen-damped oscillation will occur according to the characteristics of the system. Under the same LPF conditions, the higher the VCO sensitivity, the smaller ξ, the faster the locking, but the larger the amplitude of the damped oscillation; the larger ξ, the smaller the amplitude of the damped oscillation, and there is no damped oscillation when it is greater than 1, but the locking time becomes very long. Since the damping factor cannot be accurately controlled and usually the PLL needs to lock as soon as possible, there is a certain amplitude of damped oscillation in the output.

[0011] When the system changes the division ratio, the PLL needs to relock, and the locking behavior takes a certain amount of time. Generally, for a PLL, its second-order response characteristic within the locking range is characterized by the damping factor. For faster locking, the damping factor is small and a larger overshoot appears; even if an ordinary damping factor of 0.45 to 0.7 is selected, there is still a certain degree of overshoot.

[0012] In theory and in practice, the conventional overshoot will not be very large, for example, 10%-20%. Therefore, if the system provides enough safety margin, it will not cause too big a problem.

[0013] The post divider has a very obvious characteristic: since it is not within the loop and does not have the loop bandwidth characteristic of a second-order system, its relative output Fout is an impulse-like instantaneous response, so it directly affects the output and will cause serious overshoot problems in many cases.

[0014] Combined with Figure 2, Assume: the input clock is 12.5 MHz, and the clock generation relationship is: Fout = [N(lpdiv) / N(pstdiv)] * Fin. The system requires the clock to be increased from 375 MHz to 387.5 MHz, only a 12.5 MHz increase is needed. The frequency switching is achieved by changing the division factors of the loop divider and the post divider: Before switching, the loop division factor is 60 and the post division factor is 2; after switching, the loop division factor becomes 31 and the post division factor becomes 1. During the frequency switching process, the frequency of Fosc can only be gradually changed through the loop. The loop filter has a fixed bandwidth, and Vc controls the oscillator to gradually change from 750 MHz to 387.5 MHz; while the post division factor can change instantaneously from 2 to 1, resulting in Fout directly changing from the current 375 MHz to 750 MHz, thus causing a serious overshoot. The system stabilizes to 387.5 MHz only after a long period of huge overshoot. If the subsequent CPU cannot operate at such a high frequency, for example, it can only work at a maximum frequency of 500 MHz, it will directly cause the system to freeze.

[0015] If the CPU can only operate at a maximum frequency of 500 MHz at 1V (although there is a very large margin for 375 MHz), then the overshoot frequency of 750 MHz of the above PLL will inevitably cause the system to malfunction. To prevent the system from crashing, it is required to significantly increase the voltage. However, in many cases, even if the voltage is increased, the CPU operating speed cannot always be increased, for example, it cannot be doubled. Summary of the Invention

[0016] The technical problem to be solved by the present invention is to provide a method, circuit and clock generation device for preventing clock overshoot, which can reduce the overshoot risk, aiming at the defect of overshoot occurring when adjusting the PLL output clock by changing the division factors of the loop divider and the post divider in the prior art.

[0017] The technical solution adopted by the present invention to solve its technical problem is: to construct a method for preventing clock overshoot, which is applied to a phase-locked loop with a post divider. The phase-locked loop includes a phase detector, a low-pass filter, a voltage-controlled oscillator, a loop divider and a post divider. When changing the frequency of the output signal of the phase-locked loop by changing the division factors of the loop divider and the post divider, the following steps are carried out:

[0018] Obtain the post divider control signal of the phase-locked loop and determine whether the post divider control signal changes;

[0019] When the post divider control signal changes, obtain the input signal and the feedback signal of the phase-locked loop, and determine the current state of the phase-locked loop according to the input signal and the feedback signal. The states of the phase-locked loop include a locked state and an unlocked state;

[0020] When the current state is the unlocked state, the output signal of the phase-locked loop is frequency-divided downward, and the frequency-divided signal is used as the clock signal;

[0021] When the current state is the locked state, the output signal of the phase-locked loop is directly used as the clock signal.

[0022] Preferably, obtaining the post-division control signal of the phase-locked loop and determining whether the post-division control signal changes includes:

[0023] Obtaining the post-division control signal and the loop division control signal of the phase-locked loop, and determining whether the post-division control signal and the loop division control signal change.

[0024] Preferably, determining the current state of the phase-locked loop according to the input signal and the feedback signal includes:

[0025] Comparing the input signal with the feedback signal and determining whether the difference between the two is less than a threshold;

[0026] If the difference between the two is less than the threshold within a preset period, it is determined that the current state of the phase-locked loop is the locked state;

[0027] If the difference between the two is not less than the threshold within a preset period, it is determined that the current state of the phase-locked loop is the unlocked state.

[0028] Preferably, frequency-dividing the output signal of the phase-locked loop downward includes:

[0029] Frequency-dividing the output signal of the phase-locked loop by a frequency-dividing device, and moreover, the following conditions are satisfied:

[0030] N(safdiv)≥N(lpdiv) / N(lpdiv_new),

[0031] wherein, N(safdiv) is the frequency-division coefficient of the frequency-dividing device, N(lpdiv) is the frequency-division coefficient before the loop frequency divider is changed, and N(lpdiv_new) is the frequency-division coefficient after the loop frequency divider is changed.

[0032] The present invention also constructs a circuit for preventing clock overshoot, which is applied to a phase-locked loop with post-division. The phase-locked loop includes a phase detector, a low-pass filter, a voltage-controlled oscillator, a loop frequency divider, and a post-divider. The circuit for preventing clock overshoot includes:

[0033] A control detection module for obtaining the post-division control signal of the phase-locked loop and determining whether the post-division control signal changes;

[0034] A status detection module, configured to obtain an input signal and a feedback signal of a phase-locked loop when the post-division control signal changes, and determine the current status of the phase-locked loop according to the input signal and the feedback signal, where the status of the phase-locked loop includes a locked status and an unlocked status;

[0035] A safety frequency reduction module, configured to perform frequency reduction processing on the output signal of the phase-locked loop and use the frequency-reduced signal as a clock signal when the current status is the unlocked status; and directly use the output signal of the phase-locked loop as the clock signal when the current status is the locked status.

[0036] Preferably, the control detection module includes a third delay element and an exclusive-NOR gate. The input end of the third delay element is connected to the control end of the post-division frequency divider for inputting the post-division control signal. The output end of the third delay element is connected to the first input end of the exclusive-NOR gate. The second input end of the exclusive-NOR gate is connected to the control end of the post-division frequency divider. The output end of the exclusive-NOR gate is connected to the status detection module.

[0037] Preferably, the status detection module includes: a first delay element, a second delay element, a first D flip-flop, a second D flip-flop, and an AND gate. The input end of the first delay element is connected to the input end of the phase-locked loop for inputting the input signal of the phase-locked loop. The output end of the first delay element is connected to the clock end of the first D flip-flop. The data input end of the first D flip-flop is connected to the feedback end of the phase-locked loop for inputting the feedback signal of the phase-locked loop. The data output end of the first D flip-flop is connected to the first input end of the AND gate. The input end of the second delay element is connected to the feedback end of the phase-locked loop for inputting the feedback signal of the phase-locked loop. The output end of the second delay element is connected to the clock end of the second D flip-flop. The data input end of the second D flip-flop is connected to the input end of the phase-locked loop for inputting the input signal of the phase-locked loop. The data output end of the second D flip-flop is connected to the second input end of the AND gate. The output end of the AND gate is used to output a status signal. The reset ends of the first D flip-flop and the second D flip-flop are respectively connected to the output end of the exclusive-NOR gate. Preferably, the safety frequency reduction module includes a frequency reduction device and a switching switch. The input end of the frequency reduction device and the first input end of the switching switch are both connected to the output end of the phase-locked loop for inputting the output signal of the phase-locked loop. The output end of the frequency reduction device is connected to the second input end of the switching switch. The control end of the switching switch is connected to the output end of the AND gate. The output end of the switching switch is used to output the clock signal.

[0038] Preferably, it further includes:

[0039] The frequency reduction control module is used to, when the post-division control signal changes, obtain the changed division coefficient of the loop divider according to the loop division control signal of the phase-locked loop, and determine the frequency reduction coefficient of the frequency reduction device according to the division coefficient before the change of the loop divider and the division coefficient after the change. Moreover, the frequency reduction coefficient of the frequency reduction device satisfies the following conditions:

[0040] N(safdiv)≥N(lpdiv) / N(lpdiv_new),

[0041] where N(safdiv) is the frequency reduction coefficient of the frequency reduction device, N(lpdiv) is the division coefficient of the loop divider before the change, and N(lpdiv_new) is the division coefficient of the loop divider after the change.

[0042] The present invention also constructs a clock generation device, including a phase-locked loop, and the phase-locked loop includes a phase detector, a low-pass filter, a voltage-controlled oscillator, a loop divider, and a post-divider. It is characterized in that the clock generation device further includes the above-mentioned circuit for preventing clock overshoot.

[0043] Implementing the technical solution of the present invention, when adjusting the frequency of the output signal of the phase-locked loop by changing the division coefficients of the loop divider and the post-divider, if it is detected that the division coefficient of the post-divider changes, it is possible to determine whether the current is in an unlocked state or a locked state according to the input signal and the feedback signal. And in the unlocked state, the output signal of the phase-locked loop is frequency-reduced to eliminate the risk of overshoot. Once it is determined that the state is locked, the stable target frequency signal is output. Therefore, each frequency switching time is adaptive and is the shortest in the system. Moreover, during the switching period, the highest-speed safe clock that can be provided currently can be provided to the system at zero cost, giving play to the CPU processing ability, so as to run the subsequent software program at the highest speed and safely. Therefore, compared with the prior art, it can provide an available clock at lower cost, more reliably, and more quickly, improve the software operation efficiency, and save power consumption. Description of the Drawings

[0044] In order to more clearly illustrate the embodiments of the present invention, the drawings required for description in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts. In the drawings:

[0045] Figure 1 is the logic structure diagram of a phase-locked loop in the prior art;

[0046] Figure 2 is Figure 1 the simulation diagram of the clock signal and time during the relocking process of the phase-locked loop in;

[0047] Figure 3 is the flowchart of the first embodiment of the method for preventing clock overshoot in the present invention;

[0048] Figure 4 is the one adopted Figure 3 in the method, the simulation diagram of the clock signal and time during the relocking process of the phase-locked loop;

[0049] Figure 5 is the logical structure diagram of the first embodiment of the clock generation device of the present invention;

[0050] Figure 6 is Figure 5 the logical structure diagram of the first embodiment of the control and detection module in

[0051] Figure 7 is Figure 5 the logical structure diagram of the first embodiment of the status detection module in

[0052] Figure 8 is Figure 5 the logical structure diagram of the second embodiment of the status detection module in

[0053] Figure 9 is Figure 5 the logical structure diagram of the third embodiment of the status detection module in

[0054] Figure 10 is Figure 5 the logical structure diagram of the fourth embodiment of the status detection module in

[0055] Figure 11 is Figure 5 the logical structure diagram of the fifth embodiment of the status detection module in

[0056] Figure 12 is Figure 5 the logical structure diagram of the first embodiment of the safe frequency reduction module in Detailed implementation manners

[0057] The following will describe in detail the specific implementation manners of the present invention with reference to the accompanying drawings.

[0058] The specific implementation manners / embodiments recorded herein are specific specific implementation manners of the present invention, used to illustrate the concept of the present invention, and are all explanatory and exemplary, and should not be construed as limiting the implementation manners of the present invention and the scope of the present invention. Except for the embodiments recorded herein, those skilled in the art can also adopt other obvious technical solutions based on the content disclosed in the claims and the specification of this application. These technical solutions include technical solutions that make any obvious substitutions and modifications to the embodiments recorded herein, and are all within the protection scope of the present invention.

[0059] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other.

[0060] Figure 3 FIG. 4 is a flowchart of the first embodiment of the method for preventing clock overshoot in the present invention. The method of this embodiment is applied to a phase-locked loop with post-division. The phase-locked loop includes a phase detector, a low-pass filter, a voltage-controlled oscillator, a loop divider, and a post-divider. In this embodiment, when changing the output signal frequency of the phase-locked loop by changing the division coefficient of the loop divider and the division coefficient of the post-divider, the following steps are performed:

[0061] Step S10. Obtain the post-division control signal of the phase-locked loop, and determine whether the post-division control signal changes;

[0062] In this step, if it is monitored that the post-division control signal changes, a simple pulse signal can be issued.

[0063] Step S20. When the post-division control signal changes, obtain the input signal and the feedback signal of the phase-locked loop, and determine the current state of the phase-locked loop according to the input signal and the feedback signal. The states of the phase-locked loop include a locked state and an unlocked state;

[0064] In this step, it should be noted first that when the phase-locked loop is in the locked state, the rising edges of its input signal and feedback signal are aligned (the phase difference is constant). When the division coefficient of the loop divider changes, the feedback signal of the phase-locked loop will change. By detecting the change of the feedback signal (the frequency of the input signal remains unchanged), it can be determined whether the current state is in the locked state or the unlocked state.

[0065] Step S30. When the current state is the unlocked state, perform a frequency reduction process on the output signal of the phase-locked loop, and use the signal after the frequency reduction process as the clock signal;

[0066] In this step, since the phase-locked loop will have overshoot in the unlocked state, the output signal of the phase-locked loop in the unlocked state can be frequency-reduced, that is, the damped oscillation frequency is forced to be reduced, and then used as the clock signal, which can reduce the overshoot risk.

[0067] Step S30. When the current state is the locked state, directly use the output signal of the phase-locked loop as the clock signal.

[0068] Combine Figure 4, First, assume that the frequency of the input signal of the phase-locked loop is 12.5 MHz, and the clock generation relationship is: Fout = [N(lpdiv) / N(pstdiv)] * Fin. The system requires the clock to be increased from 375 MHz to 387.5 MHz, and the frequency switching is achieved by changing the division factors of the loop divider and the post divider: Before switching, the division factor of the loop divider is 60, and the division factor of the post divider is 2; after switching, the division factor of the loop divider becomes 31, and the division factor of the post divider becomes 1. It can be clearly seen from the figure that in the unlocked state, since the output signal is down-converted, the original overshoot frequency point of 750 MHz does not appear. Moreover, after the phase-locked loop is re-stabilized, the output signal with a frequency of 387.5 MHz is output.

[0069] Implementing the technical solution of this embodiment, when adjusting the frequency of the output signal of the phase-locked loop by changing the division factors of the loop divider and the post divider, if it is detected that the division factor of the post divider changes, it is possible to determine whether the current state is the unlocked state or the locked state based on the input signal and the feedback signal, and in the unlocked state, the output signal of the phase-locked loop is down-converted to eliminate the risk of overshoot. Once it is determined that the state is the locked state, the stable target frequency signal is output. Therefore, each frequency switching time is adaptive and the shortest in the system. Moreover, during the switching period, the highest-speed safe clock that can be provided currently can be provided to the system at zero cost, giving play to the CPU processing ability, so as to run the subsequent software program at the highest speed and safe frequency. Therefore, compared with the prior art, it can provide available clocks at lower cost, more reliably, and more quickly, improve the software operation efficiency, and save power consumption.

[0070] In an alternative embodiment, step S10 is: obtaining the post divider control signal and the loop divider control signal of the phase-locked loop, and determining whether the post divider control signal and the loop divider control signal have changed. In this embodiment, the post divider control signal and the loop divider control signal can be obtained simultaneously, and it is determined whether these two signals have changed, because generally, the post divider control signal and the loop divider control signal are issued simultaneously. Of course, in other embodiments, only the post divider control signal can be obtained and detected, because even if the loop divider control signal is not captured, it is possible to determine whether the loop divider control signal has changed by detecting the input signal and the feedback signal of the phase-locked loop in step S20.

[0071] In an alternative embodiment, in step S20, the current state of the phase-locked loop can be determined according to the following method: comparing the input signal with the feedback signal, and determining whether the difference between the two is less than a threshold; if the difference between the two is less than the threshold within a preset period, it is determined that the current state of the phase-locked loop is the locked state; if the difference between the two is not less than the threshold within a preset period, it is determined that the current state of the phase-locked loop is the unlocked state.

[0072] It should be noted that the determination of the threshold is related to the characteristics of the PLL and the requirements for locking accuracy, etc., and can be set as needed, such as one clock cycle of the oscillator.

[0073] In an alternative embodiment, in step S30, the frequency reduction process can be performed in the following manner: the output signal of the phase-locked loop is frequency-reduced by a frequency reduction device, and moreover, the following conditions are satisfied:

[0074] N(safdiv)≥N(lpdiv) / N(lpdiv_new),

[0075] where N(safdiv) is the frequency reduction coefficient of the frequency reduction device, N(lpdiv) is the frequency division coefficient before the loop frequency divider is changed, and N(lpdiv_new) is the frequency division coefficient after the loop frequency divider is changed.

[0076] In this embodiment, due to the existence of the post-frequency divider in the phase-locked loop, according to Fout = [N(lpdiv) / N(pstdiv)]*Fin, where Fin is the frequency of the input signal of the phase-locked loop, Fout is the frequency of the output signal of the phase-locked loop, N(lpdiv) is the frequency division coefficient of the loop frequency divider, and N(pstdiv) is the frequency division coefficient of the post-frequency divider. When the frequency division coefficient of the post-frequency divider is adjusted to N(pstdiv_new), the output frequency Fosc of the voltage-controlled oscillator does not change immediately and remains Fosc = N(lpdiv)*Fin. Therefore, the frequency of the output signal changes instantaneously to Fout_over = [N(lpdiv) / N(pstdiv_new)]*Fin, and the ratio of the overshoot frequency to the final output frequency is K = Fout_over / Fout_new = N(lpdiv) / N(lpdiv_new). When the frequency reduction coefficient N(safdiv) is greater than or equal to K, there is just no overshoot. Since the numerical range of the frequency division coefficient of the loop frequency divider is different each time, the corresponding K value can be calculated each time. Of course, the K value can also be simply set as: lpdiv(max) / lpdiv(min).

[0077] In addition, it should be noted that for a phase-locked loop with post-division, if the output signal frequency is changed only by changing the division factor of its loop divider, that is, the division factor of the post-divider remains unchanged, theoretically, to reduce the output signal frequency by X times is sufficient. According to the actual circuit, the conventional overshoot will only be between 10% and 20%. Therefore, as long as X is set to be greater than 1.1, the overshoot risk can be eliminated. Preferably, X can be selected as 1.5. Therefore, for a phase-locked loop with post-division, if some application scenarios require changing the output signal frequency only by changing the division factor of its loop divider, while some other application scenarios require changing the output signal frequency by changing the division factors of both its loop divider and post-divider, then for the down-frequency coefficient N(safdiv) of the down-frequency device, as long as it is ensured to be greater than the larger value of X and K.

[0078] Figure 5 FIG. 4 is a logic structure diagram of the first embodiment of the clock generation device of the present invention. The clock generation device of this embodiment includes a phase-locked loop 10 and a circuit for preventing clock overshoot. Among them, the phase-locked loop 10 is a phase-locked loop with post-division, and specifically includes a phase detector 11, a low-pass filter 12, a voltage-controlled oscillator 13, a loop divider 14, and a post-divider 15. It should be understood that the functions, specific implementations, and logical relationships of the phase detector 11, low-pass filter 12, voltage-controlled oscillator 13, loop divider 14, and post-divider 15 in the phase-locked loop 10 can adopt well-known practices in the art and will not be elaborated here. The circuit for preventing clock overshoot specifically includes a control detection module 40, a state detection module 20, and a safety down-frequency module 30. Moreover, the control detection module 40 is used to obtain the post-division control signal of the phase-locked loop and determine whether the post-division control signal changes; the state detection module 20 is used to obtain the input signal and feedback signal of the phase-locked loop when the post-division control signal changes, and determine the current state of the phase-locked loop according to the input signal and the feedback signal. The states of the phase-locked loop include a locked state and an unlocked state; the safety down-frequency module 30 is used to down-frequency the output signal of the phase-locked loop when the current state is the unlocked state, and use the down-frequency processed signal as the clock signal; when the current state is the locked state, directly use the output signal of the phase-locked loop as the clock signal.

[0079] In this embodiment, in combination with Figure 5, the control detection module 40 receives the post - divider control signal REG_POST; if it monitors a change in this signal, it sends a signal, such as a simple pulse signal, to the state detection module 20. The state detection module 20 compares the input signal Fin and the feedback clock Fback, and outputs a state signal LCK according to the difference between the two. For example, LCK being 0 represents an unlocked state, and LCK being 1 represents a locked state. The safety frequency - reduction module 30 decides whether to perform frequency - reduction processing on the output signal of the post - divider 15 according to the locked - state signal LCK, and directly outputs the output signal of the post - divider 15 only after relocking.

[0080] In an alternative embodiment, the state detection module 20 is configured to compare the input signal with the feedback signal, and determine whether the difference between the two is less than a threshold. If the difference between the two is less than the threshold within a preset time period, that is, if the requirement is continuously met within a certain time, it indicates locking. At this time, the current state of the phase - locked loop is determined to be the locked state; if the difference between the two is not less than the threshold within the preset time period, the current state of the phase - locked loop is determined to be the unlocked state.

[0081] In an alternative embodiment, combined with Figure 6 , the control detection module includes a third delay element 41 and an exclusive - NOR gate 42. Among them, the input end of the third delay element 41 is connected to the control end of the post - divider for inputting the post - division control signal REG_POST. The output end of the third delay element 41 is connected to the first input end of the exclusive - NOR gate 42. The second input end of the exclusive - NOR gate 42 is connected to the control end of the post - divider. The output end of the exclusive - NOR gate 42 is used to output a reset signal Rst and is connected to the state detection module. In this embodiment, as long as the post - division control signal REG_POST changes, the exclusive - NOR gate 42 will generate a negative pulse with a time width equal to the delay time of the third delay element 42.

[0082] In an alternative embodiment, combined with Figure 7, the state detection module of this embodiment is implemented using a cross-delay latch structure. Specifically, the state detection module includes: a first delay element 21, a second delay element 22, a first D flip-flop 23, a second D flip-flop 24, and an AND gate 25. Regarding the first delay element 21 and the second delay element 22, it should be noted that their delay times should be greater than the setup time of the D flip-flop and less than the period of the output signal. In practical applications, the delay times of the two delay elements can be designed within a reasonable range. In this embodiment, the input end of the first delay element 21 is connected to the input end of the phase-locked loop for inputting the input signal Fin of the phase-locked loop. The output end of the first delay element 21 is connected to the clock end of the first D flip-flop 23. The data input end of the first D flip-flop 23 is connected to the feedback end of the phase-locked loop for inputting the feedback signal Fback of the phase-locked loop. The data output end of the first D flip-flop 23 is connected to the first input end of the AND gate 25. The input end of the second delay element 22 is connected to the feedback end of the phase-locked loop for inputting the feedback signal Fback of the phase-locked loop. The output end of the second delay element 22 is connected to the clock end of the second D flip-flop 24. The data input end of the second D flip-flop 24 is connected to the input end of the phase-locked loop for inputting the input signal Fin of the phase-locked loop. The data output end of the second D flip-flop 24 is connected to the second input end of the AND gate 25. The output end of the AND gate 25 is used to output the state signal LCK. The reset ends of the first D flip-flop 23 and the second D flip-flop 24 are respectively connected to the output end of the exclusive-NOR gate 42 for inputting the reset signal.

[0083] It should be noted that the connection relationships in this application include, but are not limited to, the connection relationships generated by two input ends for receiving the same input signal, the connection relationships generated by the connection between the output end and the input end, etc.

[0084] The following combination Figure 5 - 7Describe the working process of the phase-locked loop state detection: During the locking period of the phase-locked loop, the rising edges of the input signal Fin and the feedback signal Fback are aligned (constant phase difference). Delaying the rising edge of either side can capture the high level of the other. The output signals of the two D flip-flops 23 and 24 are always 1. When the division factor of the post-divider changes, that is, when the post-division control signal changes, the two D flip-flops 23 and 24 will be reset briefly. Then, due to the change in the division factor of the loop divider, the output signal Fback of the phase-locked loop changes, and its new rising edge will be different from the input signal Fin by one or more periods of the output signal Fosc. If the phase-locked loop increases the output frequency, that is, the division factor increases (for example, from N to N+K), then Fback will be delayed by K periods compared to Fin. At this time, the first D flip-flop 23 will output 0, so that the LCK signal output by the AND gate 25 is 0, that is, a signal indicating loss of lock is issued. Then, the output signal Fosc gradually speeds up under the action of the loop until overshoot occurs. At this time, the edge of the feedback signal Fback will lead the edge of the input signal Fin, and the second D flip-flop 24 will output 0 again, so that the LCK signal continuously output by the AND gate 25 is 0. Only when the edges of the feedback signal Fback and the input signal Fin are realigned within a certain range, the two D flip-flops 23 and 24 will output 1 again, so that the LCK signal output by the AND gate is 1, that is, a locking signal is issued.

[0085] In an alternative embodiment, referring to Figure 8 , the state detection module of this embodiment includes: an exclusive-OR gate 221, a pulse swallowing module 222, and an inverter 223. The first input terminal of the exclusive-OR gate 221 is used to input the input signal Fin of the phase-locked loop, the second input terminal of the exclusive-OR gate 221 is used to input the feedback signal Fback of the phase-locked loop, the output terminal of the exclusive-OR gate 221 is connected to the input terminal of the pulse swallowing module 222, the output terminal of the pulse swallowing module 222 is connected to the input terminal of the inverter 223, and the output terminal of the inverter 223 is connected to the control terminal of the safety frequency reduction module 30 for outputting the state signal LCK to the safety frequency reduction module 30.

[0086] In an alternative embodiment, referring to Figure 9, the state detection module of this embodiment includes: an exclusive-OR gate 231, a resistor R1, a capacitor C1, and an inverter 232. The first input terminal of the exclusive-OR gate 231 is used to input the input signal Fin of the phase-locked loop, the second input terminal of the exclusive-OR gate 231 is used to input the feedback signal Fback of the phase-locked loop, the output terminal of the exclusive-OR gate 231 is connected to one end of the resistor R1, the other end of the resistor R1 is respectively connected to one end of the capacitor C1 and the input terminal of the inverter 232, the other end of the capacitor C1 is grounded, and the output terminal of the inverter 232 is connected to the control terminal of the safety frequency reduction module 30 for outputting a state signal LCK to the safety frequency reduction module 30.

[0087] In an alternative embodiment, referring to Figure 10 , the state detection module of this embodiment includes: an exclusive-OR gate 241, a delay unit 242, an AND gate 243, and an inverter 244. The first input terminal of the exclusive-OR gate 241 is used to input the input signal Fin of the phase-locked loop, the second input terminal of the exclusive-OR gate 241 is used to input the feedback signal Fback of the phase-locked loop, the output terminal of the exclusive-OR gate 241 is respectively connected to the input terminal of the delay unit 242 and the first input terminal of the AND gate 243, the output terminal of the delay unit 242 is connected to the second input terminal of the AND gate 243, the output terminal of the AND gate 243 is connected to the input terminal of the inverter 244, and the output terminal of the inverter 244 is connected to the control terminal of the safety frequency reduction module 30 for outputting a state signal LCK to the safety frequency reduction module 30.

[0088] In an alternative embodiment, referring to Figure 11, the state detection module of this embodiment includes: an exclusive - OR gate 251, a PMOS transistor M1, an NMOS transistor M2, a capacitor C2, and a delay unit 252. The first input terminal of the exclusive - OR gate 251 is used to input the input signal Fin of the phase - locked loop, and the second input terminal of the exclusive - OR gate 251 is used to input the feedback signal Fback of the phase - locked loop. The output terminal of the exclusive - OR gate 251 is connected to the gates of the PMOS transistor M1 and the NMOS transistor M2 respectively. The source of the PMOS transistor M1 is connected to the power supply terminal and one end of the capacitor C2 respectively. A constant current source is connected between the source of the NMOS transistor M2 and the ground. After the drains of the PMOS transistor M1 and the NMOS transistor M2 are connected, they are respectively connected to the other end of the capacitor C2 and the input terminal of the delay unit 252. The output terminal of the delay unit 252 is used as the output terminal of the state detection module and is connected to the control terminal of the safe frequency - reduction module, for outputting a state signal LCK to the safe frequency - reduction module. The delay unit 252 can be implemented by a cache. In this embodiment, optionally, the delay unit 252 can be omitted, that is, the drains of the PMOS transistor M1, the drains of the NMOS transistor M2, and the other end of the capacitor C2 are connected and used as the output terminal of the state detection module, for outputting the state signal LCK to the safe frequency - reduction module.

[0089] In an alternative embodiment, in combination with Figure 12 , the safe frequency - reduction module of this embodiment includes a frequency - reduction device 31 and a switching switch 32. Among them, the input terminal of the frequency - reduction device 31 and the first input terminal of the switching switch 32 are both connected to the output terminal of the phase - locked loop, for inputting the output signal of the phase - locked loop, that is, the output signal Fpst of the post - divider. The output terminal of the frequency - reduction device 31 is connected to the second input terminal of the switching switch 32. The control terminal of the switching switch 32 is connected to the output terminal of the AND gate 25. The output terminal of the switching switch 32 is used to output a clock signal Fout.

[0090] Furthermore, the circuit for preventing clock overshoot of the present invention may further include a frequency - reduction control module. This frequency - reduction control module is used to, when the post - division control signal changes, obtain the changed division coefficient of the loop divider according to the loop division control signal of the phase - locked loop, and determine the frequency - reduction coefficient of the frequency - reduction device according to the division coefficient before the change and the division coefficient after the change of the loop divider. Moreover, the frequency - reduction coefficient of the frequency - reduction device satisfies the following conditions:

[0091] N(safdiv)≥N(lpdiv) / N(lpdiv_new),

[0092] where N(safdiv) is the frequency - reduction coefficient of the frequency - reduction device, N(lpdiv) is the division coefficient of the loop divider before the change, and N(lpdiv_new) is the division coefficient of the loop divider after the change.

[0093] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims

1. A method for preventing clock overshoot, which is applied in a phase-locked loop with post-division, the phase-locked loop includes a phase detector, a low-pass filter, a voltage-controlled oscillator, a loop divider and a post-divider, and is characterized in that, When changing the frequency of the output signal of the phase-locked loop by changing the frequency division coefficient of the loop divider and the frequency division coefficient of the post divider, the following steps are performed: The phase-locked loop further includes a control detection module, which obtains the post divider control signal of the phase-locked loop based on the control detection module and determines whether the post divider control signal changes; the control detection module includes a third delay element and an exclusive-NOR gate. Among them, the input end of the third delay element is connected to the control end of the post divider for inputting the post divider control signal, the output end of the third delay element is connected to the first input end of the exclusive-NOR gate, the second input end of the exclusive-NOR gate is connected to the control end of the post divider, and the output end of the exclusive-NOR gate is connected to the state detection module; When the post divider control signal changes, the state detection module obtains the input signal and the feedback signal of the phase-locked loop and determines the current state of the phase-locked loop according to the input signal and the feedback signal. The states of the phase-locked loop include a locked state and an unlocked state; When the current state is the unlocked state, the output signal of the phase-locked loop is frequency-reduced, and the frequency-reduced signal is used as the clock signal; When the current state is the locked state, the output signal of the phase-locked loop is directly used as the clock signal; Obtaining the post divider control signal of the phase-locked loop and determining whether the post divider control signal changes includes: Obtaining the post divider control signal and the loop divider control signal of the phase-locked loop and determining whether the post divider control signal and the loop divider control signal change.

2. The method for preventing clock overshoot according to claim 1, wherein Determining the current state of the phase-locked loop according to the input signal and the feedback signal includes: Comparing the input signal with the feedback signal and determining whether the difference between the two is less than a threshold; If the difference between the two is less than the threshold within a preset period, it is determined that the current state of the phase-locked loop is the locked state; If the difference between the two is not less than the threshold within a preset period, it is determined that the current state of the phase-locked loop is the unlocked state.

3. The method for preventing clock overshoot according to claim 1, wherein, Frequency-reducing the output signal of the phase-locked loop includes: Frequency-reducing the output signal of the phase-locked loop through a frequency reduction device, and moreover, the following conditions are satisfied: N(safdiv)≥N(lpdiv) / N(lpdiv_new), where N(safdiv) is the frequency reduction coefficient of the frequency reduction device, N(lpdiv) is the frequency division coefficient before the loop divider changes, and N(lpdiv_new) is the frequency division coefficient after the loop divider changes.

4. A circuit for preventing clock overshoot, which is applied in a phase-locked loop with post-division, the phase-locked loop includes a phase detector, a low-pass filter, a voltage-controlled oscillator, a loop divider and a post-divider, and is characterized in that, The circuit for preventing clock overshoot includes: A control detection module for obtaining the post divider control signal of the phase-locked loop and determining whether the post divider control signal changes; A state detection module for obtaining the input signal and the feedback signal of the phase-locked loop when the post divider control signal changes and determining the current state of the phase-locked loop according to the input signal and the feedback signal. The states of the phase-locked loop include a locked state and an unlocked state; A safety frequency reduction module, which is used to reduce the frequency of the output signal of the phase-locked loop when the current state is the unlocked state, and use the frequency-reduced signal as the clock signal; when the current state is the locked state, directly use the output signal of the phase-locked loop as the clock signal; The control and detection module includes a third delay element and an exclusive-NOR gate. Among them, the input end of the third delay element is connected to the control end of the post-divider for inputting the post-division control signal. The output end of the third delay element is connected to the first input end of the exclusive-NOR gate. The second input end of the exclusive-NOR gate is connected to the control end of the post-divider, and the output end of the exclusive-NOR gate is connected to the state detection module.

5. The circuit for preventing clock overshoot according to claim 4, characterized in that, The state detection module includes: a first delay element, a second delay element, a first D flip-flop, a second D flip-flop, and an AND gate. Among them, the input end of the first delay element is connected to the input end of the phase-locked loop for inputting the input signal of the phase-locked loop. The output end of the first delay element is connected to the clock end of the first D flip-flop. The data input end of the first D flip-flop is connected to the feedback end of the phase-locked loop for inputting the feedback signal of the phase-locked loop. The data output end of the first D flip-flop is connected to the first input end of the AND gate; the input end of the second delay element is connected to the feedback end of the phase-locked loop for inputting the feedback signal of the phase-locked loop. The output end of the second delay element is connected to the clock end of the second D flip-flop. The data input end of the second D flip-flop is connected to the input end of the phase-locked loop for inputting the input signal of the phase-locked loop. The data output end of the second D flip-flop is connected to the second input end of the AND gate. The output end of the AND gate is used to output the state signal. The reset ends of the first D flip-flop and the second D flip-flop are respectively connected to the output end of the exclusive-NOR gate.

6. The circuit for preventing clock overshoot according to claim 5, characterized in that, The safety frequency reduction module includes a frequency reduction device and a switching switch. The input end of the frequency reduction device and the first input end of the switching switch are both connected to the output end of the phase-locked loop for inputting the output signal of the phase-locked loop. The output end of the frequency reduction device is connected to the second input end of the switching switch. The control end of the switching switch is connected to the output end of the AND gate, and the output end of the switching switch is used to output the clock signal.

7. The circuit for preventing clock overshoot according to claim 6, wherein, It further includes: A frequency reduction control module, which is used to, when the post-division control signal changes, obtain the changed division ratio coefficient of the loop divider according to the loop division ratio control signal of the phase-locked loop, and determine the frequency reduction coefficient of the frequency reduction device according to the division ratio coefficient before the change and the changed division ratio coefficient of the loop divider. Moreover, the frequency reduction coefficient of the frequency reduction device satisfies the following conditions: N(safdiv)≥N(lpdiv) / N(lpdiv_new), where N(safdiv) is the frequency reduction coefficient of the frequency reduction device, N(lpdiv) is the division ratio coefficient before the change of the loop divider, and N(lpdiv_new) is the changed division ratio coefficient of the loop divider.

8. A clock generating device, comprising a phase-locked loop, the phase-locked loop including a phase detector, a low-pass filter, a voltage-controlled oscillator, a loop divider and a post divider, characterized in that, The clock generating device further includes the circuit for preventing clock overshoot according to any one of claims 5-7.

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