Mismatch Compensation in an Analog-to-Digital Converter Reconfigured Using a Reference Path

Abstract

This disclosure relates to an analog-to-digital converter (ADC) and a method. The ADC has a quantizer. The quantizer includes: a linear feedback shift register (LFSR); a decoder configured to provide a plurality of switch control signals at a plurality of decoder outputs, the plurality of switch control signals responsive to LFSR values output by the LFSR; an electrical reference having a plurality of reference outputs, the electrical reference configured to provide a plurality of reference levels at the plurality of reference outputs; a first switch providing a first switch output and a second switch output; and a comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output, and the second reference input connected to the second switch output.

Description

Technical Field

[0001] The present disclosure generally relates to data conversion between analog and digital forms, and more particularly to mismatch compensation for data conversion circuits. Background Art

[0002] If data conversion circuits such as analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) could be perfectly fabricated from ideal components, the data conversion circuits could perform in a completely and exactly accurate manner. However, non-ideal environments may degrade the performance of viable data conversion circuits.

[0003] For example, in a radar system, harmonic distortion of an ADC may generate intermodulation distortion (IMD) products, which may appear as false targets returned by the radar system. For example, when such a radar system is used to control the braking of a vehicle, a false target may activate the automatic braking function, causing the vehicle to stop without an apparent reason.

[0004] As can be found in sigma-delta ADCs, the harmonic distortion of a continuous-time sigma-delta modulator is mainly caused by element mismatches of the DAC current sources. This is a well-known problem and is typically solved using dynamic element matching techniques. However, such dynamic element matching techniques may have undesirable consequences, such as increasing the semiconductor die area occupied by the circuit, increasing power consumption, increasing noise generation, and causing excessive loop delay that leads to stability problems. Therefore, a technique that avoids these drawbacks would be an improvement over the prior art. Summary of the Invention

[0005] According to a first aspect of the present invention, there is provided an analog-to-digital converter (ADC) comprising a quantizer for receiving an analog signal input and providing a quantizer output, the quantizer comprising:

[0006] a linear feedback shift register (LFSR) that provides an LFSR output;

[0007] a decoder connected to the LFSR, the decoder having a plurality of decoder outputs, each decoder output for providing a switch control signal in response to an LFSR value of the LFSR output;

[0008] an electrical reference having a plurality of reference outputs, each reference output for providing a reference level signal;

[0009] A first switch having a first switch output and a second switch output, where the first switch output is connected to a first reference output among the reference outputs when a first switch control signal in the switch control signals is in a first state and is connected to a second reference output among the reference outputs when the first switch control signal is in a second state, and the second switch output is connected to the second reference output when the first control signal is in the first state and is connected to the first reference output when the first control signal is in the second state; and

[0010] A comparator having a signal input, a first reference input, and a second reference input, where the first reference input is connected to the first switch output and the second reference input is connected to the second switch output.

[0011] In one or more embodiments, the decoder includes:

[0012] A mode selection input configured to receive a mode selection value, where the mode selection value determines a first switching operation of a second switch for switching a third reference output and a fourth reference output among the plurality of reference outputs in response to a second switch control signal among the plurality of switch control signals.

[0013] In one or more embodiments, when the mode selection value indicates a first operation mode, the first switching operation is not exactly the same as a second switching operation of the first switch, and when the mode selection value indicates a second operation mode, the first switching operation is exactly the same as the second switching operation.

[0014] In one or more embodiments, when the mode selection value indicates a third operation mode, the first switching operation depends on a first LFSR bit value in the LFSR value, and the second switching operation depends on a second LFSR bit value in the LFSR value.

[0015] In one or more embodiments, the decoder is connected to a quantizer digital output, where the first switch control signal depends on a quantizer digital output value of at least one bit of the quantizer digital output.

[0016] In one or more embodiments, the state of the LFSR is advanced at a programmable LFSR clock frequency.

[0017] In one or more embodiments, the ADC is selected from the group consisting of a sigma-delta ADC and a pipelined ADC.

[0018] According to a second aspect of the present invention, a method is provided, including:

[0019] Advance the state of a random number generator;

[0020] Decode one or more random number generator bits provided by the random number generator to select one or more comparator pairs to be swapped;

[0021] Switch a reference input between comparators in each of the one or more selected comparator pairs to be swapped;

[0022] Provide a quantizer digital output of a quantizer that utilizes the one or more selected comparator pairs to a digital-to-analog converter (DAC);

[0023] Provide analog-to-digital conversion using an analog output of the DAC.

[0024] In one or more embodiments, the decoding is performed at least in part based on a mode selection value received from a mode selection input, wherein a first switching operation for swapping a first comparator pair among the comparator pairs is determined by the one or more random number generator bits, and wherein the mode selection value determines a second switching operation for swapping a second comparator pair among the comparator pairs.

[0025] In one or more embodiments, in a case where the mode selection value indicates a first operation mode, the second switching operation is not exactly the same as the first switching operation, and in a case where the mode selection value indicates a second operation mode, the second switching operation is exactly the same as the first switching operation.

[0026] In one or more embodiments, in a case where the mode selection value indicates a third operation mode, the first switching operation depends on a first random number generator bit among the one or more random number generator bits, and the second switching operation depends on a second random number generator bit among the one or more random number generator bits.

[0027] In one or more embodiments, the decoding depends on a quantizer digital output value of at least one bit of the quantizer digital output.

[0028] In one or more embodiments, the advancing of the state of the random number generator is performed at a programmable LFSR clock frequency.

[0029] According to a third aspect of the present invention, there is provided an analog-to-digital converter (ADC) comprising:

[0030] A digital-to-analog converter (DAC) having a digital input and an analog output; and

[0031] A quantizer having a quantizer digital output connected to the digital input, the quantizer comprising:

[0032] A random number generator circuit that provides a random output;

[0033] A decoder connected to the random number generator circuit and configured to provide a plurality of switch control signals at a plurality of decoder outputs, the switch control signals responsive to random output values of the random output;

[0034] An electrical reference having a plurality of reference outputs, each reference output for providing a reference level signal;

[0035] A first switch having a first switch output and a second switch output, the first switch output connected to a first reference output among the reference outputs when a first switch control signal among the switch control signals is in a first state and connected to a second reference output among the reference outputs when the first switch control signal is in a second state, and the second switch output connected to the second reference output when the first control signal is in the first state and connected to the first reference output when the first control signal is in the second state; and

[0036] A comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output, and the second reference input connected to the second switch output.

[0037] In one or more embodiments, the decoder includes:

[0038] A mode selection input configured to receive a mode selection value, wherein the mode selection value determines a first switching operation of a second switch for switching a third reference output and a fourth reference output among the plurality of reference outputs in response to a second switch control signal among the plurality of switch control signals.

[0039] In one or more embodiments, when the mode selection value indicates a first operating mode, the first switching operation is not exactly the same as a second switching operation of the first switch, and when the mode selection value indicates a second operating mode, the first switching operation is exactly the same as the second switching operation.

[0040] In one or more embodiments, when the mode selection value indicates a third operating mode, the first switching operation depends on a first LFSR bit value among the LFSR values, and the second switching operation depends on a second LFSR bit value among the LFSR values.

[0041] In one or more embodiments, the decoder is connected to the digital output of the quantizer, where the first switch control signal depends on the quantizer digital output value of at least one bit of the quantizer digital output.

[0042] In one or more embodiments, the state of the random number generator circuit is advanced at the programmable random number generator clock frequency.

[0043] In one or more embodiments, the ADC is selected from the group consisting of a sigma-delta ADC and a pipelined ADC.

[0044] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The present disclosure can be better understood by reference to the accompanying drawings, and numerous features and advantages of the present disclosure will be apparent to those skilled in the art.

[0046] Figure 1 is a block diagram showing a circuit according to at least one embodiment.

[0047] Figure 2 is a flowchart showing a method according to at least one embodiment.

[0048] Figure 3 is a block diagram showing an analog-to-digital converter according to at least one embodiment.

[0049] The same reference numerals are used in different drawings to indicate similar or identical items. DETAILED DESCRIPTION

[0050] A method and apparatus use a reference path to reconfigure mismatch compensation in an analog-to-digital converter (ADC). An exchange of reference lines of comparator pairs is performed to provide mismatch compensation.

[0051] An ADC converts an analog signal into a digital signal. Although an analog signal can vary within a voltage range and is not limited to values within a finite set of discrete voltage levels, the analog signal is quantized to a particular discrete level within a finite set of discrete levels during a sampling period. Since the particular discrete level does not exactly match the actual level of the analog signal being sampled during the sampling period and varies from the actual level of the analog signal being sampled during the sampling period by at least an infinitesimal amount, quantization introduces an error. If the error is uncorrelated with the signal, the effect of the error may be limited to the particular sample in which the error occurs. However, if the error is correlated with the signal, the occurrence of the error can be deterministic and periodic. The periodic effect of the correlated error can include a so-called tone in a manner similar to how the periodic variation of an audio waveform can produce a tone that is heard by the ear. The occurrence of such a tone is not limited to audio but can span the spectrum, including, for example, radio frequency (RF) below or at microwave and millimeter frequencies, such as can be used, for example, to implement a radar system.

[0052] To reduce the determinism and periodicity of quantization error, a non-deterministic (random) adjustment can be applied to the quantization process and apparatus. This effective random adjustment is called dithering and the effective random adjustment can be, for example, random or pseudo-random in nature. By introducing dithering as a form of intentionally applied noise for randomizing quantization error, the periodic effect of quantization error can be mitigated. Dithering can be used to reduce distortion caused by component mismatches in ADCs, particularly pipelined ADCs and cyclic ADCs (single-stage ADCs in which the output of a sum is sampled and held and fed back to the input of the ADC). According to at least one embodiment, dithering can be added to the reference path (rather than the signal path) in a continuous-time sigma-delta ADC. The technique can be used for any multi-bit sigma-delta ADC for any application and provides a mechanism for improving the spurious-free dynamic range (SFDR). If desired, this technique can be used in addition to other known mechanisms for further improvement since this technique does not preclude the application of other known mechanisms. At least one embodiment implements dithering by swapping comparator references to reduce tones in the ADC spectrum. Swapping comparator references has the effect of randomizing comparator offsets and DAC component mismatches.

[0053] Dithering can be added via comparator reference swapping to improve distortion performance within a very short development time frame without affecting die area, excessive loop delay, and stability, but with minimal additional power and noise generation. Incorporate at least one embodiment into a multi-bit sigma-delta ADC. Incorporate at least one embodiment into a pipelined ADC. Incorporate at least one embodiment into a cyclic ADC. At least one embodiment utilizes a programmable dithering value (such as a dither amplifier value). The programmable dithering value allows selection of the operating mode of the decoder. The operating mode of the decoder can specify attributes such as the number of bits of the linear feedback shift register (LFSR) on which decoding depends, the number of comparators to be reconfigured, or both.

[0054] Dithering is added by swapping the reference lines of comparator pairs. This provides an elegant solution that requires little or no additional die area when the comparator pairs are naturally laid out adjacent to each other and use the same reference line. The swap is done at the start of the "hold" time of the comparator, thus allowing time for the reference to settle before being used. A programmable method of selecting how many comparator pairs are allowed to swap within a given time adds the ability to trade off signal-to-noise ratio (SNR) degradation for distortion and intermodulation performance. Since the dithering is added to the reference path, this avoids possible problems of adding dithering to the signal path. Adding dithering to the reference path also has the effect of randomizing the quantizer transition points to some extent, which can reduce or eliminate tones due to non-ideal comparators in the quantizer.

[0055] Also included is the programmability of the frequency at which the swap is done, which allows for additional trade-offs with the randomization of DAC elements and the DAC glitch energy generated during element swapping. The dithering implemented in this way can be used with or without other common dynamic element matching techniques that change the connections between comparators and DAC elements.

[0056] Thus, improved ADC accuracy can be provided, which represents a technical improvement to ADC performance. This improved accuracy can be reflected in reduced harmonic distortion of the ADC, which can, for example, reduce IMD products. This reduction in IMD products can, for example, reduce false targets in a radar system. It will be understood that the embodiments described below represent specific types of ADC circuits to which the teachings of the present disclosure are applied. It will be further understood that other types of ADC circuits can be similarly improved by incorporating reference path dithering as described in the present disclosure. Specifically, flash converters or sigma-delta ADCs can reasonably be expected to benefit from the application of the teachings of the present disclosure.

[0057] Figure 3 is a block diagram showing an analog-to-digital converter according to at least one embodiment. Although the following will refer to Figure 1 and Figure 2Discuss more detailed aspects, but Figure 3 An overview is provided in the context of an exemplary embodiment of an ADC 300, within which a circuit 100 and Figure 1 can be implemented Figure 2 a method 200. The ADC 300 includes a combiner 301, a loop filter 302, a quantizer 303, and a digital-to-analog converter (DAC) 304. An analog input 307 is connected to a first input of the combiner 301. The DAC output 312 is connected to a second input of the combiner 301. The combiner 301 adjusts the analog input signal at the analog input 307 by an adjustment signal at the DAC output 312. For example, the combiner 301 can be an addition circuit that adjusts the input signal at the analog input 307 by the adjustment signal at the DAC output 312 such that the combiner output 308 of the combiner 301 is the sum of the analog input value of the analog input signal and the adjustment value of the adjustment signal.

[0058] The combiner 301 is connected to the loop filter 302 and provides the combiner output 308 to an input of the loop filter 302. The loop filter 302 provides a filtered signal at a filtered output 309, which is connected to an input of the quantizer 303. The quantizer 303 includes a dither circuit 305 and a comparator 306 as well as other elements as shown in Figure 1 The dither circuit 305 includes switches 911, 912, and 913 as well as other switches represented by ellipses. The comparator 306 includes comparators 109 and 110, 111 and 112, and 113 and 114 as well as other comparators represented by ellipses. The comparator 306 receives the filtered signal or a signal obtained from the filtered signal. Each dither circuit in the dither circuit 305 receives a corresponding pair of reference levels and exchanges or does not exchange the comparator reference level inputs for the corresponding pair of comparators of its comparator 306. A digital signal is provided at a digital output 310 as the comparator output signal of one or more comparators in the comparator 306 or as a signal obtained from the comparator output signal of one or more comparators 306. The digital output 310 is connected to and provided to an input of the DAC 304. The DAC 304 provides an adjustment signal at the DAC output 312 from one or more of its digital inputs, and the DAC output 312 is connected to the second input of the combiner 301. In a particular embodiment, the input 307 and one or more of the outputs 308, 309, and 312 are differential signals as required or desired.

[0059] Figure 1 is a block diagram showing a circuit according to at least one embodiment. The circuit 100 includes a quantizer such as the quantizer 303 (to the left of the interconnections 189, 190, 191, 192, 193, and 194) and such as Figure 3 and a quantizer (to the left of the interconnections 189, 190, 191, 192, 193, and 194) and such asFigure 3 a digital-to-analog converter (DAC) 304 and other DACs (on the right side of the same interconnection). The quantizer includes a linear feedback shift register (LFSR) 101, a decoder 102, inverters 103, 104, and 105, inverters 106, 107, and 108, switches 911, 912, and 913, comparators 109, 110, 111, 112, 113, and 114, and latches 115, 116, 117, 118, 119, and 120. The DAC includes latches 121, 122, 123, 124, 125, and 126, current sources 127, 128, 129, 130, 131, and 132, and switches 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, and 156. The quantizer also includes a plurality of voltage references, which are shown to be implemented using a series resistor network including resistors 159, 160, 163, 164, 169, 170, and 173.

[0060] A voltage divider circuit is formed between a first reference voltage source connected to interconnection 157 and a second voltage source connected to interconnection 158. The first reference voltage source, such as a corrected reference voltage source labeled vrefp, is connected to interconnection 157, which is connected to the first end of resistor 159. The second end of resistor 159 is connected to interconnection 161, which is connected to the first end of resistor 163. The second end of resistor 163 is connected to interconnection 165, which is connected to a resistor in an unshown portion of the voltage divider circuit. Another resistor in the unshown portion of the voltage divider circuit is connected to interconnection 167, which is connected to the first end of resistor 169. The second end of resistor 169 is connected to interconnection 171, which is connected to the first end of resistor 173. The second end of resistor 173 is connected to interconnection 172, which is connected to the first end of resistor 170. The second end of resistor 170 is connected to interconnection 168, which is connected to a resistor in an unshown portion of the voltage divider circuit. Another resistor in the unshown portion of the voltage divider circuit is connected to interconnection 166, which is connected to the first end of resistor 164. The second end of resistor 164 is connected to interconnection 162, which is connected to the first end of resistor 160. The second end of resistor 160 is connected to interconnection 158, which is connected to a second reference voltage source, such as a more negative reference voltage source labeled vrefm.

[0061] Interconnection 161 is connected to the first input of switch 911. Interconnection 162 is connected to the second input of switch 911. The first output of switch 911 is connected to the non-inverting reference input of comparator 109 and the inverting reference input of comparator 110. The second output of switch 911 is connected to the inverting reference input of comparator 109 and the non-inverting reference input of comparator 110. Interconnection 165 is connected to the first input of switch 912. Interconnection 166 is connected to the second input of switch 912. The first output of switch 912 is connected to the non-inverting input of comparator 111 and the inverting input of comparator 112. The second output of switch 912 is connected to the inverting input of comparator 111 and the non-inverting input of comparator 112. Interconnection 171 is connected to the first input of switch 913. Interconnection 172 is connected to the second input of switch 913. The first output of switch 913 is connected to the non-inverting input of comparator 113 and the inverting input of comparator 114. The second output of switch 913 is connected to the inverting input of comparator 113 and the non-inverting input of comparator 114.

[0062] LFSR 101 provides a digital output at interconnection 904. In the example shown, interconnection 904 is labeled LFSR[7:0] to represent an eight-bit parallel digital output from LFSR7 as its most significant bit (MSB) to LFSR0 as its least significant bit (LSB). Interconnection 904 is connected to the input of decoder 102, thereby providing the digital output of LFSR 101 to decoder 102. Decoder 102 is connected to interconnection 905 and receives a dither amplifier input from interconnection 905, which is labeled DITHER_AMP[1:0] in the example shown to represent a two-bit parallel digital input. The DITHER_AMP[1:0] input can be used to selectively balance harmonic reduction against noise, which can be regarded as a variation in the noise floor. Decoder 102 is connected to interconnection 906 and receives a Q input from interconnection 906, which is labeled Q[15:0] in the example shown to represent a 16-bit parallel digital input. Decoder 102 is connected to interconnection 907 and provides a digital output to interconnection 907, which is labeled S[7:0] in the example shown to represent an eight-bit digital output. The bits of the digital output at interconnection 907 can be used to swap or not swap to the reference inputs of the comparators, such as comparators 109, 110, 111, 112, 113, and 114.

[0063] The decoder 102 uses the DITHER_AMP bits and the LFSR bits to determine the S bits that it provides as its output. Optionally, when determining the S bits that the decoder 102 provides as its output, the decoder 102 may include the Q bits from the output of one or more of the comparators 109, 110, 111, 112, 113, and 114. As an example, the output of the comparator may be applied to the input of an exclusive OR (XOR) gate to generate the Q bits to be provided to the decoder 102. The Q bits used by the decoder 102 may propagate noise out of band, thus simplifying additional processing, such as by allowing simple filtering to remove the noise.

[0064] For example, the decoder 102 may use the DITHER_AMP bits to determine how many references to swap and may use at least a portion of the LFSR bits to determine the locations of those references to swap. As a first example, DITHER_AMP bits having a binary value of 00 may indicate exactly one pair of references to swap, e.g., such that exactly one of the switches (e.g., switches 911, 912, 913, and any other switches that may be included between switches 912 and 913, as indicated by the ellipsis in Figure 1 changes to an opposite state, leaving all other switches in their previous states. As a second example, DITHER_AMP bits having a binary value of 01 may indicate exactly two pairs of references to swap, e.g., such that exactly two of the switches (e.g., switches 911, 912,..., 913) change to an opposite state, leaving all other switches in their previous states. As a third example, DITHER_AMP bits having a binary value of 10 may indicate exactly four pairs of references to swap, e.g., such that exactly four of the switches (e.g., switches 911, 912,..., 913) change to an opposite state, leaving all other switches in their previous states.

[0065] At least one embodiment may utilize a particular value of the DITHER_AMP bits (e.g., binary value 11) to allow the use of the LFSR output bits to directly determine the S bits output by the decoder 102. Thus, the number of dither instances may be determined by the number of bits in the LFSR output bits having a particular state (e.g., binary value 1), and when the particular direct output value of the DITHER_AMP bits is present, the locations of those dither instances may be determined by the locations of those bits in the LFSR output bits having the particular state. A table showing these examples is set forth below.

[0066] DITHER_AMP-1: 0 LSFR-2: 0 S[7：0] 00 111 10000000 00 110 01000000 00 101 00100000 … … … 01 111 11000000 01 110 01100000 01 101 00110000 … … … 10 111 11110000 10 110 01111000 10 101 00111100 … … … 11 xxx S[7:0] = LSFR[7:0]

[0067] In addition, according to at least one embodiment, an option may be provided to turn off all dithering instances, thereby restoring the switches (e.g., switches 911, 912, ..., 913) to their previous state (e.g., by outputting s[7:0] equal to the binary value 00000000). By completely turning off the dithering, an optimal signal-to-noise ratio (SNR) can be provided at the cost of increased harmonic content. If it is preferred to reduce the harmonic content and a certain reduction in SNR is tolerable, the dithering can be implemented in any of the various ways described herein.

[0068] For example, the least significant bit (LSB) of S[7:0] labeled S[0] is provided to the D input of the inverter flip-flop 103 via the interconnect 908, the second least significant bit of S[7:0] labeled S[1] is provided to the D input of the inverter flip-flop 104 via the interconnect 909, and the most significant bit (MSB) of S[7:0] labeled S[7] is provided to the D input of the inverter flip-flop 105 via the interconnect 910. The inverter flip-flop 103 provides a digital switch control output at its Q output to the interconnect 174, which is inverted by the inverter 106 to provide an inverted digital switch control output at the interconnect 175. The inverter flip-flop 104 provides a digital switch control output at its Q output to the interconnect 176, which is inverted by the inverter 107 to provide an inverted digital switch control output at the interconnect 177. The inverter flip-flop 105 provides a digital switch control output at its Q output to the interconnect 178, which is inverted by the inverter 108 to provide an inverted digital switch control output at the interconnect 179. The inverter flip-flops 103, 104, and 105 operate to provide an output that changes to a state opposite to that before the clock edge at the clock edge when the input is high, but maintains its original state after the clock edge when the input is low. In a particular embodiment, the inverter flip-flops 103, 104, and 105 are implemented using latches (e.g., D flip-flops) and multiplexers. Here, the Q output of the latch is connected to the first input of the multiplexer, the inverted Q output (QB) of the latch is connected to the second input of the multiplexer, the output of the multiplexer is connected to the input of the latch, and the select input of the multiplexer is connected to the corresponding bit of S[7:0]. The analog signal to be converted is referred to as SIG and may include, for example, a differential signal having a non-inverted signal SIG+ and an inverted signal SIG-. The non-inverted signal labeled SIG+ is provided at the interconnect 180, which is connected to the non-inverted signal input of each of the comparators 109, 110, 111, 112, 113, and 114. The inverted signal labeled SIG- is provided at the interconnect 181, which is connected to the inverted signal input of each of the comparators 109, 110, 111, 112, 113, and 114.

[0069] Switch 911 includes switches 133, 134, 135, and 136. Interconnect 161 is connected to the first ends of switches 133 and 135. Interconnect 162 is connected to the first ends of switches 134 and 136. The second ends of switches 133 and 136 are connected to the non-inverting reference input of comparator 109 and the inverting reference input of comparator 110. The second ends of switches 134 and 135 are connected to the inverting reference input of comparator 109 and the non-inverting reference input of comparator 110. Interconnect 174 is connected to the control ends of switches 133 and 134. Interconnect 175 is connected to the control ends of switches 135 and 136.

[0070] Switch 912 includes switches 137, 138, 139, and 140. Interconnect 165 is connected to the first ends of switches 137 and 139. Interconnect 166 is connected to the first ends of switches 138 and 140. The second ends of switches 137 and 140 are connected to the non-inverting reference input of comparator 111 and the inverting reference input of comparator 112. The second ends of switches 138 and 139 are connected to the inverting reference input of comparator 111 and the non-inverting reference input of comparator 112. Interconnect 176 is connected to the control ends of switches 137 and 138. Interconnect 177 is connected to the control ends of switches 139 and 140.

[0071] Switch 913 includes switches 141, 142, 143, and 144. Interconnect 171 is connected to the first ends of switches 141 and 143. Interconnect 172 is connected to the first ends of switches 142 and 144. The second ends of switches 141 and 144 are connected to the non-inverting reference input of comparator 113 and the inverting reference input of comparator 114. The second ends of switches 142 and 143 are connected to the inverting reference input of comparator 113 and the non-inverting reference input of comparator 114. Interconnect 178 is connected to the control ends of switches 141 and 142. Interconnect 179 is connected to the control ends of switches 143 and 144.

[0072] Comparator 109 compares an analog input signal to be converted into digital form with a reference signal and provides a comparator output at interconnect 182. The analog input signal includes, for example, signal SIG which includes a non-inverting signal SIG+ at interconnect 180 and an inverting signal SIG- at interconnect 181. The reference signal is a differential reference signal including a non-inverting reference signal and an inverting reference signal provided by switch 911. Comparator 110 compares an analog input signal to be converted into digital form with a reference signal and provides a comparator output at interconnect 183. The analog input signal includes, for example, signal SIG which includes a non-inverting signal SIG+ at interconnect 180 and an inverting signal SIG- at interconnect 181. The reference signal is a differential reference signal including a non-inverting reference signal and an inverting reference signal provided by switch 911. Comparator 111 compares an analog input signal to be converted into digital form with a reference signal and provides a comparator output at interconnect 184. The analog input signal includes, for example, signal SIG which includes a non-inverting signal SIG+ at interconnect 180 and an inverting signal SIG- at interconnect 181. The reference signal is a differential reference signal including a non-inverting reference signal and an inverting reference signal provided by switch 912. Comparator 112 compares an analog input signal to be converted into digital form with a reference signal and provides a comparator output at interconnect 185. The analog input signal includes, for example, signal SIG which includes a non-inverting signal SIG+ at interconnect 180 and an inverting signal SIG- at interconnect 181. The reference signal is a differential reference signal including a non-inverting reference signal and an inverting reference signal provided by switch 912. Comparator 113 compares an analog input signal to be converted into digital form with a reference signal and provides a comparator output at interconnect 187. The analog input signal includes, for example, signal SIG which includes a non-inverting signal SIG+ at interconnect 180 and an inverting signal SIG- at interconnect 181. The reference signal is a differential reference signal including a non-inverting reference signal and an inverting reference signal provided by switch 913. Comparator 114 compares an analog input signal to be converted into digital form with a reference signal and provides a comparator output at interconnect 188. The analog input signal includes, for example, signal SIG which includes a non-inverting signal SIG+ at interconnect 180 and an inverting signal SIG- at interconnect 181. The reference signal is a differential reference signal including a non-inverting reference signal and an inverting reference signal provided by switch 913.

[0073] The comparator output of comparator 109 is connected to the input of latch 115 via interconnect 182. The comparator output of comparator 110 is connected to the input of latch 116 via interconnect 183. The comparator output of comparator 111 is connected to the input of latch 117 via interconnect 184. The comparator output of comparator 112 is connected to the input of latch 118 via interconnect 185. The comparator output of comparator 113 is connected to the input of latch 119 via interconnect 187. The comparator output of comparator 114 is connected to the input of latch 120 via interconnect 188.

[0074] The output of latch 115 labeled Q[0] is connected to the D input of latch 121 via interconnect 189. The output of latch 116 labeled Q[1] is connected to the D input of latch 122 via interconnect 190. The output of latch 117 labeled Q[2] is connected to the D input of latch 123 via interconnect 191. The output of latch 118 labeled Q[3] is connected to the D input of latch 124 via interconnect 192. The output of latch 119 labeled Q

[14] is connected to the D input of latch 125 via interconnect 193. The output of latch 120 labeled Q

[15] is connected to the D input of latch 126 via interconnect 194.

[0075] The Q output of latch 121 is connected as a control input to switch 145, and the QB output is connected as a control input to switch 146. The Q output of latch 122 is connected as a control input to switch 147, and the QB output is connected as a control input to switch 148. The Q output of latch 123 is connected as a control input to switch 149, and the QB output is connected as a control input to switch 150. The Q output of latch 124 is connected as a control input to switch 151, and the QB output is connected as a control input to switch 152. The Q output of latch 125 is connected as a control input to switch 153, and the QB output is connected as a control input to switch 154. The Q output of latch 126 is connected as a control input to switch 155, and the QB output is connected as a control input to switch 156.

[0076] The first current output line 902 labeled ioutp is connected to the first end of each of the switches 145, 147, 149, 151, 153, and 155. The second current output line 903 labeled ioutm is connected to the first end of each of the switches 146, 148, 150, 152, 154, and 156. The second end of each of the switches 145 and 146 is connected to the first end of the current source 127. The second end of the current source 127 is connected to a fixed reference voltage such as ground. The second end of each of the switches 147 and 148 is connected to the first end of the current source 128. The second end of the current source 128 is connected to a fixed reference voltage such as ground. The second end of each of the switches 149 and 150 is connected to the first end of the current source 129. The second end of the current source 129 is connected to a fixed reference voltage such as ground. The second end of each of the switches 151 and 152 is connected to the first end of the current source 130. The second end of the current source 130 is connected to a fixed reference voltage such as ground. The second end of each of the switches 153 and 154 is connected to the first end of the current source 131. The second end of the current source 131 is connected to a fixed reference voltage such as ground. The second end of each of the switches 155 and 156 is connected to the first end of the current source 132. The second end of the current source 132 is connected to a fixed reference voltage such as ground.

[0077] In operation, the comparators 109, 110, 111, 112, 113, and 114 compare a signal including the non-inverting signal SIG+ and the inverting signal SIG- with the reference signals from 911, 912, and 913 to produce a comparison result, which is timed by the latches 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, and 126 to control the selective connection of the current sources 127, 128, 129, 130, 131, and 132 to the complementary current output lines 902 and 903. The provided current output signals include the current output signal ioutp and the current output signal ioutm. In a particular embodiment, the latches 115, 116, 117, 118, 119, and 120 add only one delay cycle from the comparator output to the DAC switch. In a particular embodiment, flip-flops may be utilized instead of the latches 115, 116, 117, 118, 119, and 120. Here, it will be noted that depending on the actual implementation of the clock circuit, the use of flip-flops will add additional clock cycles to the operation, which would be undesirable. Thus, those skilled in the art will understand that careful design of the implementation of the clock circuit will be required to avoid adding clock cycles between the comparator output and the DAC switch.

[0078] Because the comparison results depend on the reference signals provided to comparators 109, 110, 111, 112, 113, and 114, defects in the elements providing these reference signals and / or comparator offsets may affect the comparison results, and such comparison results may affect the accuracy of the ADC. By providing switches such as switches 911, 912, and 913 to switch the reference signals provided to comparators 109, 110, 111, 112, 113, and 114, circuit 100 can dynamically exchange reference signals, thereby allowing any unwanted variations between the reference signals to be canceled out over time. This additionally improves the offsets of comparators 109, 110, 111, 112, 113, and 114 and improves the mismatches of current sources 127, 128, 129, 130, 131, and 132.

[0079] The above embodiments utilize reference path dithering, in which the reference signals are voltage signals. However, it will be further understood that the teachings of the present disclosure are not necessarily limited to dithering on voltage signals, but can be similarly applied in cases where the ADC circuit utilizes current as a reference.

[0080] Figure 2 is a flowchart showing a method according to at least one embodiment. Method 200 starts at block 201 and proceeds to block 202. At block 202, the state of the random number generator is advanced to the next state. The random number generator can be, for example, a pseudo-random number generator. For example, the random number generator can utilize a linear feedback shift register (LFSR). Method 200 proceeds from block 202 to block 203. At block 203, one or more random number generator bits are decoded to select the comparator reference pairs to be swapped. Method 200 proceeds from block 203 to block 204. At block 204, the reference inputs are switched between the selected comparators. Method 200 proceeds from block 204 to block 205. At block 205, the output of the quantizer utilizing the swapped comparator pairs is provided to a digital-to-analog converter (DAC). Method 200 proceeds from block 205 to block 206. At block 206, the output of the DAC is used to provide analog-to-digital conversion.

[0081] According to at least one embodiment, the comparator outputs in the quantizer are directly connected to the respective current sources in the DAC (ignoring the latches for signal timing). The references for the comparators are swapped randomly in pairs 15 / 0, 14 / 1, 13 / 2, 12 / 3, 11 / 4, 10 / 5, 9 / 6, 8 / 7. This has the effect of randomizing the quantizer / DAC differential nonlinearity (DNL).

[0082] The frequency of comparator swapping is controlled by a decoder, and the input of the decoder comes from an LFSR. The frequency at which the LFSR provides output data can be programmable. For example, the LFSR can be programmed to provide output data at the LFSR output for every 1, 2, 4, 8, etc. samples obtained by the ADC. A first logic level from the decoder, such as a logic level representing zero (0), does not swap the comparator, while a second logic level from the decoder, such as a logic level representing one (1), swaps the comparator. The decoder has the following four different swapping settings:

[0083] 00 - One pair per cycle

[0084] 01 - Two pairs per cycle

[0085] 10 - Four pairs per cycle

[0086] 11 - Which pairs and how many pairs (0 - 8 pairs) are controlled by the LFSR bits.

[0087] According to at least one embodiment, the bits LFSR[7:0] are intentionally selected to not be adjacent to each other in the shift register. The clock of the LFSR is programmable to allow for a trade-off between randomness and DAC glitch energy. An inverter flip-flop doubles the length of the random code from the LFSR, thus reducing the frequency of spurs caused by the repetition rate of the pseudo-random numbers.

[0088] At least one embodiment does not modify the reference value on the reference line. Instead, the connection of the reference line is changed to reconfigure the way the reference line carrying the unchanged reference value is connected to the comparator. Depending on the various embodiments or a single embodiment providing mode selectivity, various numbers of reference line pairs can be switched, such as a single pair, two pairs, four pairs, up to all pairs, thus increasing randomness. Fewer than all the reference connections can be switched at any given time.

[0089] At least one embodiment can avoid adding jitter in the signal path. The input signal can be provided to the signal input of the comparator without having to pass through a jitter circuit. The comparator reference voltage can be used for mismatch compensation without changing the signal path.

[0090] At least one embodiment avoids the need for additional instances of existing components, such as multiple input transistors in a comparator, to generate jitter. By avoiding the need for additional input transistors, the area occupied by the circuit on the semiconductor die can be avoided from being unnecessarily increased.

[0091] At least one embodiment can avoid generating jitter when switching between two quantizer circuits. By avoiding increasing the number of comparators in the quantizer circuit, the area occupied by the circuit on the semiconductor die can be avoided from being unnecessarily increased.

[0092] According to at least one embodiment, an analog-to-digital converter (ADC) includes a quantizer configured to receive an analog signal input and provide a quantizer output. The quantizer includes: a linear feedback shift register (LFSR) that provides an LFSR output; a decoder connected to the LFSR, the decoder having a plurality of decoder outputs, each decoder output configured to provide a switch control signal in response to an LFSR value of the LFSR output; an electrical reference having a plurality of reference outputs, each reference output configured to provide a reference level signal; a first switch having a first switch output and a second switch output, the first switch output connected to a first reference output among the reference outputs when a first switch control signal among the switch control signals is in a first state and connected to a second reference output among the reference outputs when the first switch control signal is in a second state, and the second switch output connected to the second reference output when the first control signal is in the first state and connected to the first reference output when the first control signal is in the second state; and a comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output, and the second reference input connected to the second switch output.

[0093] According to at least one embodiment, the decoder includes a mode selection input configured to receive a mode selection value, where the mode selection value determines a first switching operation of a second switch to switch a third reference output and a fourth reference output among the plurality of reference outputs in response to a second switch control signal among the plurality of switch control signals. According to at least one embodiment, when the mode selection value indicates a first operating mode, the first switching operation is not exactly the same as a second switching operation of the first switch, and when the mode selection value indicates a second operating mode, the first switching operation is exactly the same as the second switching operation. According to at least one embodiment, when the mode selection value indicates a third operating mode, the first switching operation depends on a first LFSR bit value of the LFSR value, and the second switching operation depends on a second LFSR bit value of the LFSR value. According to at least one embodiment, the decoder is connected to the quantizer digital output, where the first switch control signal depends on a quantizer digital output value of at least one bit of the quantizer digital output. According to at least one embodiment, the state of the LFSR is advanced at a programmable LFSR clock frequency. According to at least one embodiment, the ADC is selected from the group consisting of a sigma-delta ADC and a pipelined ADC.

[0094] According to at least one embodiment, a method includes: advancing a state of a random number generator; decoding one or more random number generator bits provided by the random number generator to select one or more comparator pairs to be swapped; switching a reference input between comparators in each of the one or more comparator pairs selected to be swapped; providing a quantizer digital output of a quantizer utilizing the one or more comparator pairs selected to be swapped to a digital-to-analog converter (DAC); providing an analog output of the DAC for analog-to-digital conversion. According to at least one embodiment, the decoding is performed based at least in part on a mode selection value received from a mode selection input, wherein a first switching operation for swapping a first comparator pair among the comparator pairs is determined by the one or more random number generator bits, and wherein the mode selection value determines a second switching operation for swapping a second comparator pair among the comparator pairs. According to at least one embodiment, in a case where the mode selection value indicates a first operation mode, the second switching operation is made not identical to the first switching operation, and in a case where the mode selection value indicates a second operation mode, the second switching operation is made identical to the first switching operation. According to at least one embodiment, in a case where the mode selection value indicates a third operation mode, the first switching operation depends on a first random number generator bit among the one or more random number generator bits, and the second switching operation depends on a second random number generator bit among the one or more random number generator bits. According to at least one embodiment, the decoding depends on a quantizer digital output value of at least one bit of the quantizer digital output. According to at least one embodiment, the advancing of the state of the random number generator is performed at a programmable LFSR clock frequency.

[0095] According to at least one embodiment, an analog-to-digital converter (ADC) includes: a digital-to-analog converter (DAC) having a digital input and an analog output; and a quantizer having a quantizer digital output connected to the digital input. The quantizer includes: a random number generator circuit that provides a random output; a decoder connected to the random number generator circuit and configured to provide a plurality of switch control signals at a plurality of decoder outputs, the switch control signals in response to a random output value of the random output; an electrical reference having a plurality of reference outputs, each reference output for providing a reference level signal; a first switch having a first switch output and a second switch output, the first switch output being connected to a first reference output among the reference outputs when a first switch control signal among the switch control signals is in a first state and being connected to a second reference output among the reference outputs when the first switch control signal is in a second state, and the second switch output being connected to the second reference output when the first control signal is in the first state and being connected to the first reference output when the first control signal is in the second state; and a comparator having a signal input, a first reference input, and a second reference input, the first reference input being connected to the first switch output, and the second reference input being connected to the second switch output.

[0096] According to at least one embodiment, the decoder includes a mode selection input configured to receive a mode selection value, where the mode selection value determines a first switching operation of a second switch for switching a third reference output and a fourth reference output among the plurality of reference outputs in response to a second switch control signal among the plurality of switch control signals. According to at least one embodiment, in a case where the mode selection value indicates a first operation mode, the first switching operation is not exactly the same as a second switching operation of the first switch, and in a case where the mode selection value indicates a second operation mode, the first switching operation is exactly the same as the second switching operation. According to at least one embodiment, in a case where the mode selection value indicates a third operation mode, the first switching operation depends on a first LFSR bit value of an LFSR value, and the second switching operation depends on a second LFSR bit value of the LFSR value. According to at least one embodiment, the decoder is connected to the quantizer digital output, where the first switch control signal depends on a quantizer digital output value of at least one bit of the quantizer digital output. According to at least one embodiment, the state of the random number generator circuit is advanced at a programmable random number generator clock frequency. According to at least one embodiment, the ADC is selected from the group consisting of a sigma-delta ADC and a pipelined ADC.

[0097] The concepts of the present disclosure have been described with reference to specific embodiments. However, those of ordinary skill in the art will understand that various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure.

[0098] Advantages, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, an advantage, a benefit, a solution to a problem, or any one or more features that may cause any advantage, benefit, or solution to occur or become more pronounced should not be construed as a critical, required, or essential feature of any or all of the claims.

Claims

1. An analog-to-digital converter (ADC), characterized in that, A quantizer for receiving an analog signal input and providing a quantizer output, the quantizer comprising: A linear feedback shift register (LFSR) that provides an LFSR output; A decoder connected to the LFSR, the decoder having a plurality of decoder outputs, each decoder output for providing a switch control signal in response to an LFSR value of the LFSR output; An electrical reference having a plurality of reference outputs, each reference output for providing a reference level signal; A first switch having a first switch output and a second switch output, the first switch output being connected to a first reference output among the reference outputs when a first switch control signal among the switch control signals is in a first state and being connected to a second reference output among the reference outputs when the first switch control signal is in a second state, and the second switch output being connected to the second reference output when the first switch control signal is in the first state and being connected to the first reference output when the first switch control signal is in the second state; and A comparator having a signal input, a first reference input, and a second reference input, the first reference input being connected to the first switch output, and the second reference input being connected to the second switch output; The decoder comprises: A mode selection input configured to receive a mode selection value, wherein the mode selection value determines a first switching operation of a second switch for switching a third reference output and a fourth reference output among the plurality of reference outputs in response to a second switch control signal among the plurality of switch control signals.

2. The ADC according to claim 1, wherein In a case where the mode selection value indicates a first operation mode, making the first switching operation not exactly the same as a second switching operation of the first switch, and in a case where the mode selection value indicates a second operation mode, making the first switching operation exactly the same as the second switching operation.

3. The ADC according to claim 2, wherein In a case where the mode selection value indicates a third operation mode, the first switching operation depends on a first LFSR bit value among the LFSR values, and the second switching operation depends on a second LFSR bit value among the LFSR values.

4. The ADC according to claim 1, characterized in that, The decoder is connected to a quantizer digital output, wherein the first switch control signal depends on a quantizer digital output value of at least one bit of the quantizer digital output.

5. The ADC according to claim 1, wherein Advancing the state of the LFSR at a programmable LFSR clock frequency.

6. The ADC according to claim 1, wherein The ADC is selected from the group consisting of a sigma-delta ADC and a pipelined ADC.

7. A mismatch compensation method for a data conversion circuit, characterized in that Comprising: Advancing the state of a random number generator; Decoding one or more random number generator bits provided by the random number generator to select one or more comparator pairs to be swapped; Switching reference inputs between comparators in each of the one or more comparator pairs to be swapped; Providing a quantizer digital output of a quantizer using the one or more comparator pairs to be swapped to a digital-to-analog converter (DAC); Providing analog-to-digital conversion using an analog output of the DAC; The decoding is performed based, in part, on a mode selection value received from a mode selection input, wherein a first switching operation for swapping a first pair of comparators in the pair of comparators is determined by the one or more random number generator bits, and wherein the mode selection value determines a second switching operation for swapping a second pair of comparators in the pair of comparators.

8. An analog-to-digital converter (ADC), characterized in that, Comprising: a digital-to-analog converter (DAC) having a digital input and an analog output; and a quantizer having a quantizer digital output connected to the digital input, the quantizer comprising: a random number generator circuit that provides a random output; a decoder connected to the random number generator circuit and configured to provide a plurality of switch control signals at a plurality of decoder outputs, the switch control signals responsive to random output values of the random output; an electrical reference having a plurality of reference outputs, each reference output for providing a reference level signal; a first switch having a first switch output and a second switch output, the first switch output being connected to a first reference output among the reference outputs when a first switch control signal among the switch control signals is in a first state and being connected to a second reference output among the reference outputs when the first switch control signal is in a second state, and the second switch output being connected to the second reference output when the first switch control signal is in the first state and being connected to the first reference output when the first switch control signal is in the second state; and a comparator having a signal input, a first reference input, and a second reference input, the first reference input being connected to the first switch output, and the second reference input being connected to the second switch output.

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