Analog-to-digital conversion circuit and signal conversion method thereof

Abstract

The present disclosure relates to an analog-to-digital conversion circuit and a signal conversion method thereof. A conventional analog-to-digital conversion circuit has a problem of being unable to suppress conversion errors. According to one embodiment, the analog-to-digital conversion circuit includes a first digital-to-analog conversion circuit 30 of a capacitance distribution type, a second digital-to-analog conversion circuit 31 of a capacitance distribution type, and a comparison circuit 32 for comparing the output voltages of the two digital-to-analog conversion circuits, and before performing a continuous comparison operation to continuously change the reference voltage applied to the first digital-to-analog conversion circuit, the analog-to-digital conversion circuit generates an intermediate digital value having a digital value corresponding to the voltage value of the analog input signal, determines the reference voltage to be applied to the second digital-to-analog conversion circuit 31 according to the intermediate digital value, and then performs a continuous comparison operation using the first digital-to-analog conversion circuit 30 while the state of the second digital-to-analog conversion circuit 31 is maintained.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2018-244120 filed on December 27, 2018 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to an analog-to-digital conversion circuit and a signal conversion method thereof, and for example, to an analog-to-digital conversion circuit that converts an analog input signal into a digital value by continuous comparison operation on a single-ended input, and a signal conversion method thereof. Background Art

[0004] When a semiconductor device such as a microcontroller is used to perform digital signal processing to process information obtained from a sensor, the information output from the sensor has an analog value, so it is necessary to convert the analog value into a digital value. In this case, there is an analog-to-digital conversion circuit as a circuit for generating a digital value corresponding to the analog value of the analog signal. There are various types of analog-to-digital conversion circuits, such as a continuous comparison type with excellent conversion process resolution and a flash memory type with excellent conversion speed. This analog-to-digital conversion circuit of the continuous comparison type will be described below. An example of this continuous comparison type analog-to-digital conversion circuit is disclosed in U.S. Patent No. 6,774,974.

[0005] The analog-to-digital conversion circuit described in U.S. Patent No. 6,774,974 has two binary weighted capacitor arrays (NDAC and PDAC). As a result, in the analog-to-digital conversion circuit disclosed in U.S. Patent No. 6,774,974, the common mode rejection ratio (CMRR) and the power supply rejection ratio (PSRR) are improved by switching the reference voltage to be applied to the two binary load capacitor arrays in the bit array. Summary of the invention

[0006] However, when the analog-to-digital conversion process is performed on a plurality of analog input signals in a time-division manner while switching the plurality of analog input signals, the input voltage input to the analog-to-digital conversion circuit may greatly change according to the switching of the selected analog input signals. In this case, there is a problem that the conversion error becomes large due to the dielectric relaxation phenomenon of the capacitor of the charge sharing type analog-to-digital conversion circuit having the capacitor array.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0008] According to one embodiment, an analog-to-digital conversion circuit includes a first digital-to-analog conversion circuit of a capacitance distribution type, a second digital-to-analog conversion circuit of a capacitance distribution type, and a comparison circuit for comparing the output voltages of the two digital-to-analog conversion circuits. Before performing a continuous comparison operation to continuously change a reference voltage applied to the first analog-to-digital conversion circuit, the analog-to-digital conversion circuit generates an intermediate digital value having a digital value corresponding to a voltage value of an analog input signal, determines a reference voltage to be applied to the second digital-to-analog conversion circuit based on the intermediate digital value, and then performs a continuous comparison operation using the first digital-to-analog conversion circuit while the state of the second digital-to-analog conversion circuit is maintained.

[0009] According to the first embodiment, it is possible to reduce a conversion error caused by a dielectric relaxation phenomenon in an analog-to-digital conversion circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a semiconductor device including an analog-to-digital conversion circuit according to a first embodiment;

[0011] Figure 2 is a circuit diagram of an analog-to-digital conversion circuit according to a first embodiment;

[0012] Figure 3 is a circuit diagram of an analog-to-digital conversion circuit according to a comparative example;

[0013] Figure 4 (a) is a circuit diagram showing an equivalent circuit of a capacitor for explaining the dielectric relaxation phenomenon, Figure 4 (b) shows a graph for explaining the frequency characteristics of a capacitor;

[0014] Figure 5 is a diagram showing conversion errors caused by dielectric relaxation phenomena;

[0015] Figure 6 is a block diagram showing changes in sampling voltage caused by a dielectric relaxation phenomenon;

[0016] Figure 7 is a timing chart for explaining the operation of analog-to-digital conversion according to the first embodiment;

[0017] Figure 8 is a circuit diagram for explaining the state of a switch in a first sampling process of the analog-to-digital conversion circuit according to the first embodiment;

[0018] Fig. 9 is a circuit diagram showing the state of a switch in a second sampling process of the analog-to-digital conversion circuit according to the first embodiment;

[0019] Fig.10 is a circuit diagram for explaining the state of a switch in a comparison process of the analog-to-digital conversion circuit according to the first embodiment;

[0020] Fig.11 is a graph showing the resolution of the sub-ADC in the analog-to-digital conversion circuit according to the first embodiment and the effect of eliminating the dielectric relaxation phenomenon;

[0021] Fig.12 is a circuit diagram showing a first embodiment of an analog-to-digital conversion circuit according to a second embodiment;

[0022] Fig.13 is a circuit diagram showing a second exemplary analog-to-digital conversion circuit according to the second embodiment;

[0023] Fig.14 is a circuit diagram of an analog-to-digital conversion circuit according to a third embodiment; and

[0024] Fig.15 is a timing chart for explaining the operation of the analog-to-digital conversion circuit according to the third embodiment. DETAILED DESCRIPTION

[0025] For the clarity of explanation, the following description and drawings are appropriately omitted and simplified. In addition, the elements described as function blocks for performing various processing in the drawings can be configured as CPU (central processing unit), memory and other circuits in hardware, and can be implemented by a program loaded into the memory in software. Therefore, it will be appreciated by those skilled in the art that these function blocks can be implemented in various forms by only hardware, only software or a combination thereof, and the present invention is not limited to any one of them. In the drawings, the same elements are represented by the same reference numerals, and their repeated description is omitted as required.

[0026] Moreover, various types of non-transitory computer-readable media can be used to store the above-mentioned program and provide it to the computer. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (e.g., floppy disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (read-only memory, CD-R, CD-R / W, semiconductor memories (e.g., shielded ROM, PROM (programmable ROM), EPROM (erasable PROM, flash ROM, RAM (random access memory)). The program can be provided to the computer via various types of transient computer-readable media. Examples of transient computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transient computer-readable media can provide the program to the computer via wired or wireless communication paths (such as wires and optical fibers).

[0027] <First Embodiment>

[0028] In the following description, an analog-to-digital conversion circuit according to a first embodiment will be described. Although the analog-to-digital conversion circuit can be operated as a single unit, an example of an analog-to-digital conversion circuit incorporated in a semiconductor device for performing digital signal processing will be described below. In such a semiconductor device, there may be multiple analog inputs to the analog-to-digital conversion circuit. In the analog-to-digital conversion circuit, when the analog input signal to be subjected to the analog-to-digital conversion process is switched by time division, the influence of the dielectric relaxation phenomenon is more obvious. In other words, the analog-to-digital conversion circuit according to the first embodiment is more effective in applications in which the analog input signal to be subjected to the analog-to-digital conversion process is switched by time division.

[0029] Figure 1 is a schematic diagram of a semiconductor device including an analog-to-digital conversion circuit according to a first embodiment. Figure 1 As shown, the semiconductor device 1 includes a bus 10, an arithmetic unit (e.g., a CPU 11), a RAM 12, a flash ROM 13, an I / O (input / output) port 14, a peripheral circuit 15, and an analog-to-digital conversion circuit 16. In the semiconductor device 1 according to the first embodiment, the CPU 11, the RAM 12, the flash ROM 13, the I / O port 14, the peripheral circuit 15, and the analog-to-digital conversion circuit 16 are interconnected through the bus 10.

[0030] The CPU 11 loads a program stored in a nonvolatile memory such as a flash ROM 13, and performs digital signal processing according to the content of the loaded program. The RAM 12 stores intermediate data generated in the processing of the CPU 11. The flash ROM 13 is a nonvolatile memory, and stores a program or setting value for operating the semiconductor device 1. The I / O port 14 is an input / output interface for transmitting and receiving data between the semiconductor device 1 and another semiconductor device. The peripheral circuit 15 is a circuit group having a specific function used by the CPU 11 such as a timer and a floating-point operation processor. The analog-to-digital conversion circuit 16 performs an analog-to-digital conversion process on an analog input signal provided from the outside, and generates a digital value corresponding to the voltage level of the analog input signal. Since the semiconductor device 1 according to the first embodiment has one of the features of the analog-to-digital conversion circuit 16, the analog-to-digital conversion circuit 16 will be described in more detail below.

[0031] like Figure 1 As shown, the analog-to-digital conversion circuit 16 includes a selection circuit such as a multiplexer 20, an ADC core 21, a continuous comparison ADC control circuit 22, and a register 23. The ADC core 21 selects one from a plurality of analog input signals input via input channels CH1 to CHm, where m is an integer representing the number of channels, and outputs the selected analog input signal to the ADC core 21. At this time, the multiplexer 20 may have, for example, a function of switching the analog input signal to be periodically selected.

[0032] The ADC core 21 is a circuit for performing an analog-to-digital conversion process to convert an analog input signal selected by the multiplexer 20 into a digital value. The ADC core 21 is a continuous comparison type analog-to-digital conversion circuit. The continuous comparison ADC control circuit 22 controls the continuous comparison operation of the ADC core 21 to sequentially switch the switch in the ADC core 21 according to the output value of the ADC core 21. The register 23 stores the final result output value Dadc determined by the continuous comparison ADC control circuit 22, and outputs the final result output value Dadc in response to a request to the CPU 11 or the like.

[0033] The semiconductor device 1 used for the first embodiment has, in particular, one of the characteristics of the structure of the ADC core 21. Therefore, the ADC core 21 will be described in more detail. Figure 2 FIG. 1 shows a circuit diagram of an analog-to-digital conversion circuit according to a first embodiment. Figure 2 In FIG. 2 , a multiplexer 20 and a successive comparison ADC control circuit 22 are also shown in order to show the relationship among the ADC core 21 , the multiplexer 20 and the successive comparison ADC control circuit 22 .

[0034] Figure 2 is a circuit diagram of an analog-to-digital conversion circuit according to a first embodiment.

[0035] like Figure 2 As shown, the ADC core 21 includes a first digital-to-analog conversion circuit (e.g., PDAC 30), a second digital-to-analog conversion circuit (e.g., NDAC 31), a comparison circuit 32, and a sub-ADC 33. Both the PDAC 30 and the NDAC 31 are charge redistribution type digital analog circuits. Here, in the ADC core 21, the main analog-to-digital conversion circuit is composed of the PDAC 30, the NDAC 31, and the comparison circuit 32.

[0036] The PDAC 30 includes a capacitor array 34 and a switch group 35. The capacitor array 34 includes a plurality of first capacitors (eg, capacitors CP0 to CPn, where n is an integer representing the resolution of the ADC core 21). When C is a unit capacitance, the capacitors CP0 and CP1 have a capacitance of 2. 0 The capacitance of capacitors CP2 to CPn is 2 1 C to 2 n-1 C. One end of the capacitors CP0 to CPn is connected to one of the differential inputs of the comparison circuit 32. The other ends of the capacitors CP0 to CPn are connected to common terminals of corresponding switches among the switches included in the switch group 35.

[0037] The switch group 35 has a plurality of switches corresponding to the number of capacitors included in the PDAC 30. More specifically, the switch group 35 includes a plurality of first switches, for example, switches PSW0 to PSWn. Each of the switches PSW0 to PSWn has a common terminal and a first terminal to a third terminal. The common terminal is connected to the other terminal of the corresponding capacitor. The first terminal is provided with a high-side reference voltage AVREFT (for example, 5V). The second terminal is provided with an analog input signal selected by the multiplexer 20. The third terminal is provided with a low-side reference voltage AVREFB, for example, a low-side reference voltage 0V.

[0038] The NDAC 31 includes a capacitor array 36 and a switch group 37. The capacitor array 36 includes a plurality of second capacitors (eg, capacitors CN0 to CNk, where k is an integer representing the resolution of the sub-ADC 33). When Ca is used as a unit capacitor, the capacitors CN0, CN1 have a capacitance of 2 n-k Capacitors CN2 to CNk have capacitance values ​​between 2 n-k+1 Ca to 2 n-1 One end of the capacitors CN0 to CNk is connected to the other differential input of the comparison circuit 32 . The other ends of the capacitors CN0 to CNk are connected to the common terminals of the corresponding switches included in the switch group 37 .

[0039] The capacitance value of the unit capacitance Ca is set to a value that matches the total capacitance of the capacitor array 34 (the sum of the capacitance values ​​of the capacitors CP0 to CPn) and the total capacitance of the capacitor array 36 (the sum of the capacitance values ​​of the capacitors CN0 to CNn). When the total capacitance of the capacitor array 34 and the total capacitance of the capacitor array 36 are combined, the capacitance values ​​of the unit capacitance Ca and the unit capacitance C are set to the same value. In the ADC core 21 according to the first embodiment, the resolution (k bits) of the sub-ADC 33 is set to be smaller than the resolution (n bits) of the ADC core 21. In other words, in the ADC core 21 according to the first embodiment, n≥k is satisfied.

[0040] The switch group 37 has a plurality of switches corresponding to the number of capacitors included in the NDAC 31. More specifically, the switch group 37 includes a plurality of second switches, for example, switches NSW0 to NSWk. Each of the switches NSW0 to NSWk has a common terminal and a first terminal to a third terminal. The common terminal is connected to the other terminal of the corresponding capacitor. The first terminal is provided with a high-side reference voltage AVREFT (for example, 5V). The second terminal is provided with an analog input signal selected by the multiplexer 20. The third terminal is provided with a low-side reference voltage AVREFB, for example, a low-side reference voltage 0V.

[0041] The comparison circuit 32 is a differential input comparison circuit. One end of the switch PSWcm is connected to one of the input terminals of the comparison circuit 32. One end of the switch NSWcm is connected to the other input terminal of the comparison circuit 32. The switch CSW is connected between the two input terminals of the comparison circuit 32. A common voltage VCM is applied to the other end of the switch PWScm and the other end of the switch NSWcm. The comparison circuit 32 compares the voltage output from the PDAC 30 with the voltage output from the NDAC 31, and outputs the comparison result as a comparison result voltage Rcmp to the continuous comparison ADC control circuit 22.

[0042] The sub-ADC 33 digitizes the analog input signal input to the PDAC 30 and the NDAC 31 at a k-bit resolution. Here, the resolution of the sub-ADC 33 is set equal to or less than n bits, which is the resolution of the analog-to-digital conversion circuit configured by the PDAC 30, the NDAC 31, and the comparison circuit 32. Figure 2 In the illustrated embodiment, the sub-ADC 33 is a flash memory type analog-to-digital conversion circuit, and the continuous comparison ADC control circuit 22 issues an operation start instruction for the sub-ADC 33 to perform a conversion process by using a control signal Ss. Since the sub-ADC 33 is also a portion that requires high speed, it is preferable to use a flash memory type analog-to-digital conversion circuit as the sub-ADC 33, but a continuous comparison type analog-to-digital conversion circuit may also be used as the sub-ADC 33.

[0043] In the analog-to-digital conversion circuit 16 according to the first embodiment, the continuous comparison ADC control circuit 22 switches the reference voltage selected by the switch included in the switch group 37 of the NDAC 31 based on the control signal Sn generated by decoding the ADC conversion result Rsa of the sub-ADC 33. In addition, the continuous comparison ADC control circuit 22 generates a control signal Sp based on the output comparison result signal Rcmp, and controls the continuous comparison operation by the control signal Sp to switch the reference voltage selected by the switch included in the switch group 35 of the PDAC 30. The continuous comparison ADC control circuit 22 controls the entire continuous comparison operation of the ADC core 21. The details of the operation of the ADC core 21 controlled by the continuous comparison ADC control circuit 22 will be described later.

[0044] Here, a dielectric relaxation phenomenon that becomes a problem in an analog-to-digital conversion circuit will be described. Therefore, a circuit configuration of an analog-to-digital conversion circuit according to a comparative example used in the description of the dielectric relaxation phenomenon will be described. Figure 3 is a circuit diagram of an ADC core 210 according to a comparative example.

[0045] Figure 3 is a circuit diagram of an analog-to-digital conversion circuit according to a comparative example. Figure 3As shown, in the ADC core 210 according to the comparative embodiment, reference Figure 2 The NDAC 31 and the sub-ADC 33 of the ADC core 21 described above are deleted, and an NDAC 310 is provided. The NDAC 310 has a capacitor array 360. The capacitor array 360 includes capacitors CN0 to CNn. When C is a unit capacitance, the capacitance of the capacitors CN0 and CN1 is 2 0 AC. The capacitance value of capacitors CN2 to CNn is 2 1 C to 2 n-1 C. One end of the capacitors CN0 to CNn is connected to the other differential input of the comparison circuit 32. Figure 3 In the example shown, the other ends of the capacitors CN0 to CNn are supplied with a low potential side reference voltage AVREFB.

[0046] Figure 4 (a) is a circuit diagram of an equivalent circuit of a capacitor for explaining the dielectric relaxation phenomenon, and Figure 4 (b) shows a graph for explaining the frequency characteristics of the capacitor. The sampling capacitor is formed using wiring capacitance. Therefore, Figure 4 As shown in (a), when it is assumed that the capacitor having the ideal characteristics of the sampling capacitor is an ideal capacitor Cstd, the sampling capacitor can be represented as an equivalent circuit in which a plurality of series circuits of parasitic resistors Rd and parasitic capacitors Cd are connected to the ideal capacitor Cstd (in Figure 4 In the example shown in (a), i) parallel connection is used. That is, a series circuit of a parasitic resistor Rd and a parasitic capacitor Cd parasitic to an ideal capacitor Cstd is connected to an actual sampling capacitor. The series circuit of a parasitic resistor Rd and a parasitic capacitor Cd is characterized in that a time constant is slower than a time constant of an ideal capacitor Cstd. In the sampling capacitor, a dielectric relaxation phenomenon occurs due to the series circuit of a parasitic resistor Rd and a parasitic capacitor Cd.

[0047] therefore, Figure 4 The frequency characteristics of the equivalent circuit shown in (a) are Figure 4 As shown in (b). Figure 4 (b) shows the variation value with respect to the capacitance value 0.002 which is the frequency value obtained by normalizing the frequency characteristic of the sampling capacitor having the parasitic resistor Rd and the parasitic capacitor Cd by the sampling frequency. Figure 4 As shown in (b), the capacitance of the ideal capacitor Cstd is constant and has nothing to do with the frequency. On the other hand, in the sampling capacitor having the parasitic resistor Rd and the parasitic capacitor Cd, the capacitance value tends to decrease as the normalized frequency increases. The sampling capacitor is also characterized in that it also includes a frequency component that is much slower than the operating frequency of the ADC core 21 (less than one thousandth of the sampling frequency).

[0048] Next, the conversion error caused by the dielectric relaxation phenomenon will be described. When multiple channels are switched in a time-division manner to perform analog-to-digital conversion on multiple unrelated independent analog input signals, the conversion error caused by the dielectric relaxation phenomenon becomes a problem, for example, Figure 2 The ADC core 21 and Figure 3 An ADC core 210 according to a comparative example is shown.

[0049] Figure 5 is a graph showing conversion errors caused by a dielectric relaxation phenomenon. Figure 5 , and all three graphs represent conversion errors when the signal level of the analog input signal input to the ADC core 210 according to the comparative example is swept.

[0050] Figure 5 The upper graph of shows the conversion error when the multiplexer 20 is not switching the analog input signal. Figure 5 As shown in the upper figure, the conversion error is suppressed to approximately ±2LSB.

[0051] Figure 5 The middle part of shows the conversion error when the conversion process is performed on another analog input signal after the conversion process is performed on the lower limit AVREFB of the amplitude that the analog input signal can take immediately before. In this case, the conversion error is suppressed to the extent of 2LSB in the portion close to the lower limit voltage AVREFB input immediately before, but as the voltage of the analog input signal becomes higher, the conversion error becomes larger.

[0052] Figure 5 The lower graph of shows the conversion error when the conversion process is performed on another analog input signal after the conversion process is performed on the upper limit voltage AVREFT of the amplitude that the analog input signal can take immediately before the conversion process. In this case, the conversion error is suppressed to the extent of 2LSB in the portion close to the upper limit voltage AVREFT input immediately before, but as the voltage of the analog input signal becomes lower, the conversion error becomes larger.

[0053] Usually, the frequency components of the input signal have sufficiently low frequencies with respect to the conversion frequency of the analog-to-digital conversion circuit, but since the channel to be converted is switched, a difference such as Figure 5 The difference between the input voltages shown in the middle and lower graphs. Figure 5The conversion errors shown in the middle and lower figures of are affected by the input analog voltage converted in the previous conversion cycle. The conversion error caused by the influence of the analog input signal converted in the conversion cycle of the previous cycle is caused by the dielectric relaxation phenomenon. Therefore, the dielectric relaxation phenomenon will be described with reference to a circuit model in which only the sampling capacitor is represented in a simplified manner.

[0054] therefore, Figure 6 is a block diagram showing changes in sampling voltage caused by a dielectric relaxation phenomenon. Figure 6 A circuit is shown in which a series circuit of a parasitic resistor Rd and a parasitic capacitor Cd causing a dielectric relaxation phenomenon is connected in parallel with a sampling capacitor Cs. Figure 6 The switch MSW1 and MSW2 for switching input and the switch S_SW for switching between the sampling state and the holding state of the analog-to-digital conversion circuit are shown. Figure 6 In the modeling circuit shown, switches MSW1 and MSW2 are connected in parallel with switch S_SW.

[0055] exist Figure 6 In the first conversion process, the analog input voltage Vch1 input from the channel CH1 is converted by the first conversion process. At this time, the voltage at the input terminal of the sampling capacitor Cs becomes the analog input voltage Vch1. In the first conversion process, the parasitic capacitance Cd causing the dielectric relaxation phenomenon is charged with the charge corresponding to the analog input voltage Vch1.

[0056] Thereafter, the channel into which the analog input voltage to be converted is input is switched from channel CH1 to channel CH2. Figure 6 , a modeling circuit in the analog-to-digital conversion process of the analog input voltage Vch2 input from the channel CH2 is shown as the second conversion process. Figure 6 As shown, in the second conversion process, the charge caused by the analog input signal Vch1 of the previous cycle remains in the parasitic capacitor Cd due to the parasitic relaxation phenomenon, and an error ΔVch1 is generated in the voltage on the input terminal side of the sampling capacitor Cs due to the residual charge, and in the second conversion process, the voltage on the input terminal side of the sampling capacitor Cs becomes Vch2+ΔVch1.

[0057] Here, the error voltage ΔVch1 will be described. Assuming that the sampling time is Ts, the error ΔVch1 remaining in the parasitic capacitor Cd can be expressed by equation (1).

[0058] ΔVch1=(Vch2-Vch1)EXP(-Ts / (Cd·Rd)) (1)

[0059] According to equation (1), when the sampling time Ts is sufficiently greater than the time constant (Cd·Rd) of the parasitic component (Ts>>Cd·Rd), ΔVch1 becomes a negligible small value. Figure 4 As can be clearly seen from the equivalent circuit shown, since the sampling capacitor Cs includes multiple time constants, the relationship Ts>>Cd·Rd does not hold, and ΔVch1 becomes an error component with a non-negligible size. A portion of the error charge ΔVch1 is discharged during the comparison operation of the ADC core 210 and becomes a conversion error.

[0060] The analog-to-digital conversion circuit 16 according to the first embodiment is based on Figure 2 The illustrated circuit configuration and the operation corresponding to the circuit configuration suppress the conversion error caused by the dielectric relaxation phenomenon. Figure 7 is a timing chart for explaining the operation of the analog-to-digital conversion circuit 16 according to the first embodiment.

[0061] Figure 7 1 is a timing chart for explaining the operation of the analog-to-digital conversion circuit according to the first embodiment. Figure 7 As shown, the analog-to-digital conversion circuit 16 according to the first embodiment outputs a final result output value Dadc, which is a digital value converted in the current sampling cycle, during a subsequent sampling cycle after the current sampling cycle is completed.

[0062] Will refer to Figure 7 The timing diagram shown in FIG. 1 is used to describe the operation of the analog-to-digital conversion circuit 16 within one sampling period. Figure 7 As shown, the ADC core 21 performs a sampling process during a period of timing T1 to T4, and performs a comparison process to determine a final result output value by continuously comparing operations by operating switches PSW0 to PSWn during a period of timing T4 to T5. In the analog-to-digital conversion circuit 16 according to the first embodiment, during the sampling process at timing T1 to T4, the switches PSW0 to PSWn in the PDAC 30 are caused to select an analog input signal, and the sampling process is performed to apply the analog input signal to the capacitors CP0 to CPn. In the analog-to-digital conversion circuit 16 according to the first embodiment, during the comparison process at timing T4 to T5, the continuous comparison ADC control circuit 22 operates the switches PSW0 to PSWn to perform a comparison process based on the comparison result Rcmp to determine whether the reference voltage to be applied to the capacitors CP0 to CPn is the high potential side reference voltage AVREFT or the low potential side reference voltage AVREFB.

[0063] The feature of the analog-to-digital conversion circuit 16 according to the first embodiment is that the analog-to-digital conversion circuit 16 performs processing using the sub-ADC 33 and the NDAC 31 during the timings T1 to T4. Figure 7As shown, the analog-to-digital conversion circuit 16 according to the first embodiment performs a first sampling process during a first period of timing T1 to T3 to sample the analog input signal NDAC 31. In a period of timing T1 to T2 in the first period, the sub-ADC 33 samples the input analog signal. Subsequently, during timing T2 to T3 in the first period, the sub-ADC 33 performs analog-to-digital conversion on the analog input signal sampled at timing T1 to T2.

[0064] At the timing T3, the sub-ADC conversion result Rsa outputted by the sub-ADC 33 is determined. Thereafter, in the second period from the timing T3 to T4, the analog-to-digital conversion circuit 16 according to the first embodiment outputs the control signal Sn to the continuous comparison ADC control circuit 22, operates the switches NSW0 to NSWk, and applies one of the high potential side reference voltage AVREFT and the low potential side reference voltage AVREFB to the other end of the capacitors CN0 to CNk according to the value of the sub-ADC conversion result Rsa. As a result, when the final result output value Dadc is determined by the ADC core 21, the charge amount stored in the capacitors CN0 to CNk of the NDAC 31 becomes the charge amount equal to the charge amount stored in the capacitors CP0 to CPn in the PDAC 30.

[0065] Then, the analog-to-digital conversion circuit 16 according to the first embodiment performs the bit determination process by the continuous comparison operation for performing the switching operation on the PDAC 30 while maintaining the state of the NDAC 31 determined before the timing T4 in the third period after the timing T4.

[0066] Here, the states of the circuits of the ADC core 21 in the first sampling process (first period), the second sampling process (second period), and the comparison process (third period) will be described. Figures 8 to 10 Describe the state of the circuit in each time period.

[0067] Figure 8 1 is a circuit diagram for explaining the state of the switch in the first sampling process of the analog-to-digital conversion circuit according to the first embodiment. Figure 8 As shown, in the first sampling process, switches PSW0 to PSWn and NSW0 to NSWk select the second terminal, and capacitors CP0 to CPn in the PDAC 30 and capacitors CN0 to CNk in the NDAC 31 are provided with the analog input signal VIN. In the first sampling process, switches PSWcm, NSWcm and CSW are closed, and the input terminal of the comparison circuit 32 is set to the common voltage VCM.

[0068] Fig. 9 1 is a circuit diagram showing the state of the switch in the second sampling process of the analog-to-digital conversion circuit according to the first embodiment. Fig. 9 As shown, in the second sampling process, the switches PSW0 to PSWn select the second terminal, and the analog input signal VIN is supplied to the capacitors CP0 to CPn of the PDAC 30. On the other hand, in the second sampling process, the high potential side reference voltage AVREFT or the low potential side reference voltage AVREFB is supplied to the switches NSW0 to NSWk at the other end of the capacitors CN0 to CNk based on the sub ADC conversion result Rsa output by the sub ADC 33. In the second sampling process, the switches PSWcm, NSWcm and CSW are closed, and the input terminal of the comparison circuit 32 is set to the common voltage VCM. As a result, the amount of charge accumulated in the capacitors CN0 to CNk of the NDAC 31 becomes the amount of charge corresponding to the voltage level of the analog input signal.

[0069] Fig.10 1 is a circuit diagram for explaining the state of switches during the comparison process of the analog-to-digital conversion circuit according to the first embodiment. Fig.10 As shown, in the comparison process, the states of the switches NSW0 to NSWk are maintained at the state when the second sampling process is completed. On the other hand, in the comparison process, based on the comparison result Rcmp, the switches PSW0 to PSWn are sequentially switched from the switch PSW0, and the high potential side reference voltage AVREFT or the low potential side reference voltage AVREFB is applied to the other end of the capacitors CP0 to CPn. In the comparison process, the switches PSWcm, NSWcm and CSW are turned off, and the supply of the common voltage VCM to the input terminal of the comparison circuit 32 is stopped.

[0070] Based on the above circuit configuration and operation, the analog-to-digital conversion circuit 16 according to the first embodiment suppresses the conversion error caused by the dielectric relaxation phenomenon, and the suppressing effect will be described in more detail.

[0071] First, in the first sampling process, the PDAC 30 and the NDAC 31 are connected to sample the analog input signal VIN. At this time, the common voltage VCM is applied to the input terminal of the comparison circuit 32. That is, in the first sampling process, the same charge is accumulated in the capacitors constituting the capacitor arrays in the PDAC 30 and the NDAC 31. In the first sampling process, the sub-ADC 33 also samples the analog input signal VIN. Then, at the end of the first sampling process, the conversion start signal of the sub-ADC 33 is issued by the control signal Sa, and the sub-ADC 33 quantizes the analog input signal VIN into k bits. Then, the k-bit sub-ADC conversion result Rsa is decoded by the continuous comparison ADC control circuit 22. Thereafter, the process moves to the second sampling process, and the continuous comparison ADC control circuit 22 generates the control signal Sn of the NDAC 31. The control signal Sn is generated so that the charge amount of the NDAC 31 is close to the relationship of equation (2).

[0072] (VIN-VCM)2 n C≒

[0073] (AVREFT-VCM)·(2 k -m)·2 n-k ·Ca+(AVREFB-VCM)·m·2n-k·Ca (2)

[0074] Where C is the minimum unit capacitance of LSB (least significant bit) on the PDAC 30 side, and Ca is the minimum unit capacitance of LSB (least significant bit) on the NDAC 31 side. m is the number of capacitors for selecting the low-side reference voltage AVREFB derived from the sub-ADC conversion result Rsa of the sub-ADC 33, and can be expressed as 0 to 2 k A positive integer.

[0075] Hereinafter, in the analog-to-digital conversion circuit 16 according to the first embodiment, after the second sampling process is completed in the comparison process, the NDAC 31 is kept as it is, and the PDAC 30 is continuously compared and controlled, thereby acquiring the final result output value Dadc.

[0076] Whether the influence of the dielectric relaxation phenomenon of the capacitor capacitance is reduced in the above operation will be described. First, if the error component in the parasitic component of dielectric relaxation remaining in the capacitor of the PDAC 30 is represented by ΔVch1_P, the error component ΔVch1_P is represented by equation (3).

[0077] ΔVch1_P=(Vch2-Vch1)EXP(-Ts / (Cdp·Rdp)) (3)

[0078] Wherein Ts is a sampling time obtained by adding a time required for a first sampling process and a time required for a second sampling process, and Cdp and Rdp are parasitic components causing a dielectric relaxation phenomenon of a capacitor in the PDAC 30 .

[0079] Based on equation (3), the error charge ΔQ_PDAC accumulated in the PDAC 30 can be expressed by equation (4).

[0080] ΔQ_PDAC=(Vch2-Vch1)EXP(-Ts / (Cdp·Rdp))·2 n C (4)

[0081] Next, the error component caused by the dielectric relaxation phenomenon in the NDAC 31 will be considered. Let Ts1 be the sampling time required for the first sampling process, and Ts2 be the time required for the second sampling process. That is, Ts=Ts1+Ts2. As a result, the error component ΔVch1_1_N generated in the NDAC 31 in the first sampling process can be expressed by equation (5). Note that Cdn and Rdn are generated components that cause dielectric relaxation of the capacitor in the NDAC 31.

[0082] ΔVch1_1_N=(Vch2-Vch1)EXP(-Ts1 / (Cdn·Rdn)) (5)

[0083] Next, the error after the transition to the second sampling process will be considered. During the second sampling process, the reference voltage applied to the other end of the capacitors CN0 to CNk is divided into a low potential side reference voltage AVREFB and a high potential side reference voltage AVREFT according to the sub ADC conversion result Rsa of the sub ADC 33.

[0084] At this time, the error charge ΔQT of the capacitor to which the high potential side reference voltage AVREFT is applied is expressed by equation (6), and the error charge ΔQB of the capacitor to which the low potential side reference voltage AVREFB is applied is expressed by equation (7).

[0085] ΔQT=(AVREFT-(Vch2-ΔVch1_1_N))·EXP(-Ts2 / (Cdn·Rdn))·(2 k -m)·2 n-k ·Ca· (6)

[0086] ΔQB=(AVREFB-(Vch2-ΔVch1_1_N))·EXP(-Ts2 / (Cdn·Rdn))·m·2 n-k ·Ca (7)

[0088] And the error charge of the NDAC 31 of equations (6) and (7) is expressed by equation (8).

[0089] ΔQ_NDAC=ΔQT+ΔQB=(AVREFT·(2 k -m)·2 n-k ·Ca+AVREFB·m·2 n-k ·Ca)+(ΔVch1_1_N-Vch2)·2 n ·Ca)·EXP(-Ts2 / (Cdn·Rdn)) (8)

[0090] Here, when the input conversion equivalent voltage of the charge amount generated by the NDAC 31 according to the sub ADC conversion result Rsa of the sub ADC 33 is expressed as Vch2_q, Vch2_q is expressed by equation (9).

[0091] Vch2_q=AVREFT·(2 k -m)+AVREFB·m (9)

[0092] When equation (9) is applied to equation (8), equation (8) becomes equation (10).

[0093] ΔQ_NDAC=(ΔVch1_1_N+Vch2_q-Vch2)·2 n Ca / EXP(-Ts2 / (Cdn·Rdn))=(Vch2-Vch1)EXP(-Ts / (Cdn·Rdn))·2 n Ca+(Vch2_q-Vch2)·2 n Ca·EXP(-Ts2 / (Cdn·Rdn))(10)

[0094] In the ADC core 21 according to the first embodiment, only the differential component of the error components of ΔQ_PDAC and ΔQ_NDAC affects the comparison result, and the in-phase component is eliminated by the comparison circuit. Therefore, when the differential component ΔQ_diff is obtained based on equations (4) and (10), the differential component ΔQ_diff is expressed by equation (11). In the calculation of equation (11), the unit capacitance Ca of the capacitor in the NDAC 31 is calculated as the same capacitance as the unit capacitance C of the capacitor in the PDAC 30.

[0095] ΔQ_diff=ΔQ_PDAC-ΔQ_NDAC=(Vch2_q-Vch2)·2nC·EXP(-Ts2 / (Cdn·Rdn))(11)

[0096] Then, in equation (11), when Vch2_q=Vch2, Rdp=Rdn and Cdp=Cdn, ΔQ_diff≈0 is obtained. In other words, it can be understood from equation (11) that by using the ADC core 21 according to the first embodiment, the error due to the dielectric relaxation component is eliminated.

[0097] However, in the ADC core 21 according to the first embodiment, when the resolution (k bits) of the sub-ADC 33 is set smaller than the resolution (n bits) of the ADC core 21, the residual amount of ΔQ_diff changes due to this resolution difference, so that the ADC core 21 according to the first embodiment cannot eliminate all errors due to the dielectric relaxation phenomenon, but can sufficiently attenuate the errors. Therefore, the relationship between the effect of eliminating the error caused by the dielectric relaxation phenomenon depending on the difference in the resolution of the sub-ADC 33 will be described.

[0098] Fig.11 : is a graph showing the resolution of the sub-ADC in the analog-to-digital conversion circuit according to the first embodiment and the effect of eliminating the dielectric relaxation phenomenon. Fig.11 In the figure, the vertical axis represents the size of the error component, and the horizontal axis represents the number of quantization bits of the ADC core. Fig.11 The upper graph of φ shows an error LSB generated in the analog-to-digital conversion circuit when the ADC core 210 according to the comparative example is used. Fig.11 The graph in the middle portion of shows an error LSB generated in the analog-to-digital conversion circuit when the ADC core 21 according to the first embodiment is used and the resolution of the sub-ADC 33 is 3 bits. Fig.11 The lower graph of φ shows an error LSB generated in the analog-to-digital conversion circuit when the ADC core 21 according to the first embodiment is used and the resolution of the sub-ADC 33 is 2 bits.

[0099] like Fig.11 As shown, when the ADC core 210 according to the comparative example is used, the error LSB is at most 4LSB. On the other hand, if the resolution of the sub-ADC 33 is 2 bits or 3 bits, the error LSB is equal to or less than ±1LSB. In addition, it can be understood that when the resolution of the sub-ADC 33 is improved, the size of the error LSB becomes smaller.

[0100] As described above, the analog-to-digital conversion circuit 16 according to the first embodiment uses the sub-ADC 33 to adjust the charge amount of the NDAC 31 at the time of the comparison process to the charge accumulation amount corresponding to the magnitude of the analog input signal. As a result, in the analog-to-digital conversion circuit 16 according to the first embodiment, the error caused by the dielectric relaxation of the capacitor in the PDAC 30 can be reduced.

[0101] Specifically, in the analog-to-digital conversion circuit 16 having the multiplexer 20 so that the analog input signal input through the conversion cycle has a discontinuous voltage value, there is a tendency that the conversion error caused by the dielectric relaxation phenomenon becomes larger. For this reason, when the multiplexer 20 is included in the analog-to-digital conversion circuit 16, the analog-to-digital conversion circuit 16 according to the first embodiment is more effective in reducing the error.

[0102] In the analog-to-digital conversion circuit 16 according to the first embodiment, the resolution of the sub-ADC 33 can be made smaller than the resolution of the ADC core 21. As a result, the time required for the conversion process of the sub-ADC 33 to be performed in the first period in the analog-to-digital conversion circuit 16 according to the first embodiment can be reduced.

[0103] In the analog-to-digital conversion circuit 16 according to the first embodiment, by making the resolution of the sub-ADC 33 smaller than the resolution of the ADC core 21 , the circuit size required for the sub-ADC 33 can be suppressed.

[0104] In the analog-to-digital conversion circuit 16 according to the first embodiment, the sum of the capacitance values ​​of the capacitors CP0 to CPn provided in the PDAC 30 matches the sum of the capacitance values ​​of the capacitors CN0 to CNk provided in the NDAC 31. As a result, the analog-to-digital conversion circuit 16 according to the first embodiment can reduce the conversion error caused by the in-phase component between the signal output by the PDAC 30 and the signal output by the NDAC 31.

[0105] <Second Embodiment>

[0106] In the second embodiment, ADC cores 21a and 21b will be described as another form of the ADC core 21 according to the first embodiment. In the description of the second embodiment, constituent elements described in the first embodiment are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

[0107] Fig.12 1 is a circuit diagram showing a first embodiment of an analog-to-digital conversion circuit according to a second embodiment. Fig.12 In the illustrated first embodiment, an analog input signal is input to the NDAC 31 and the sub-ADC 33 via the buffer 41 .

[0108] In this way, by supplying the analog input signal to the NDAC 31 via the buffer 41 and supplying the analog input signal to the sub ADC 33 , the time required for the first sampling process of the first period and the sampling process of the sub ADC 33 of the first period can be shortened.

[0109] Fig.13 is a circuit diagram showing a second exemplary analog-to-digital conversion circuit according to the second embodiment. Fig.13In the second embodiment shown, the analog input signal is input to the NDAC 31 through the buffer 42 .

[0110] In this way, by supplying the analog input signal to the NDAC 31 via the buffer 42 , the time required for the first sampling process of the first period can be shortened.

[0111] In addition, by applying the analog input signal to at least one of the NDAC 31 and the sub-ADC 33 through the buffer, the impedance seen from the input terminal of the analog-to-digital conversion circuit 16 can be substantially only the impedance related to the PDAC 30. As a result, it is not necessary to reduce the output impedance of the driver for supplying the analog input signal to the analog-to-digital conversion circuit 16. In addition, since the circuit of the subsequent stage connected to the buffer 41 or the buffer 42 is separated from the conversion process when the continuous comparison process for the PDAC 30 is performed, the noise caused by the buffers 41 and 42 does not affect the conversion result.

[0112] <Third Embodiment>

[0113] In the third embodiment, an ADC core 21c will be described as another form of the ADC core 21 according to the first embodiment. In the description of the third embodiment, constituent elements described in the first embodiment are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

[0114] Fig.14 is a circuit diagram of an analog-to-digital conversion circuit according to a third embodiment. Fig.14 As shown in FIG. 1 , the ADC core 21c according to the third embodiment is obtained by adding a buffer 43 and switches SWA and SWB to the ADC core 21 according to the first embodiment. The buffer 43 is provided after the multiplexer 20 and the PDAC 30, NDAC 31 and before the sub-ADC 33. The switch SWA is provided between the output terminal of the buffer 43 and the PDAC 30, NDAC 31 and the sub-ADC 33. The switch SWB is provided to be connected in parallel with the series circuit of the buffer 43 and the switch SWA.

[0115] The operation of the ADC core 21 according to the third embodiment will now be described. Fig.15 1 is a timing chart for explaining the operation of the analog-to-digital conversion circuit according to the third embodiment. Fig.15 As shown, in the ADC core 21 according to the third embodiment, the operations of the switches SWA and SWB are added to the ADC core 21 according to the third embodiment. Figure 7 The operation of the ADC core 21 of the first embodiment is shown. The switches SWA and SWB are controlled by the successive comparison ADC control circuit 22.

[0116] The switch SWA is controlled to be closed in the first period of timing T1 to T3. In the first period, the switch SWB is controlled to be open. On the other hand, in the second and third periods, the switch SWA is controlled to be open and the switch SWB is controlled to be closed.

[0117] In the ADC core 21c according to the third embodiment, the buffer 43 supplies the analog input voltage to both the PDAC 30 and the NDAC 31 during the first sampling process performed in the first period to charge the capacitors of the PDAC 30 and the NDAC 31. At this time, the input capacity of the buffer 43 is loaded only from the signal source, and the input capacity of the buffer 43 is sufficiently smaller than the input capacity of the PDAC 30 and the NDAC 31.

[0118] On the other hand, in the second sampling process, since the switch SWA is controlled to be turned off, the buffer 43 is disconnected from the PDAC 30 and the NDAC 31. Instead of disconnecting the buffer 43, the switch SWB is closed to charge the analog input signal of the PDAC 30 from the signal source to the switch SWB. At this time, since most of the amount of charge to be charged is charged in the first period of performing the first sampling process, the signal source only needs to provide the offset of the buffer 43 and the voltage corresponding to the settling error. On the other hand, the capacitor on the NDAC 31 side is separated from the terminal to which the analog input signal VIN is input, and the capacitor on the NDAC 31 side is connected to one of the high potential side reference voltage AVREFT and the low potential side reference voltage AVREFB based on the control signal Sn generated according to the sub-ADC conversion result Rsa determined by the sub-ADC 33. Therefore, in the second sampling process, it is not necessary to provide the analog input signal from the signal source to the NDAC 31. The ADC core 21 c according to the third embodiment eliminates the disadvantage of connecting the NDAC 31 to the input terminal of the ADC core 21 c , and can make the sampling time equal to the conventional sampling time even when the impedance of the analog signal source is high.

[0119] Although the invention made by the inventors has been specifically described based on the embodiments, the present invention is not limited to the embodiments that have been described, and it goes without saying that various modifications can be made without departing from the gist thereof.

Claims

1. An analog-to-digital conversion circuit, comprising: a main analog-to-digital conversion circuit for converting an analog input signal into a digital value; A sub-analog-to-digital conversion circuit, used for converting the analog input signal into a digital value; as well as A continuous comparison control circuit, used to control the main analog-to-digital conversion circuit and to output a final result output value, Wherein the main analog-to-digital conversion circuit comprises: Comparison circuit, a first digital-to-analog conversion circuit having: a plurality of first capacitors having one end coupled to one of the differential input terminals of the comparison circuit; and a plurality of first switches selectively providing one of the analog input signal, a first reference voltage, and a second reference voltage to the other end of the plurality of first capacitors; and a second digital-to-analog conversion circuit, comprising: a plurality of second capacitors having one end coupled to another differential input terminal of the differential input terminals of the comparison circuit; and a plurality of second switches selectively providing one of the analog input signal, the first reference voltage, and the second reference voltage to the other end of the plurality of second capacitors, wherein the continuous comparison control circuit causes the plurality of first capacitors and the plurality of second capacitors to sample the analog value of the analog input signal in a first period, and obtains an intermediate digital value corresponding to the analog value of the analog input signal from the sub-analog-to-digital conversion circuit, wherein in a second time period after the first time period ends, the continuous comparison control circuit provides one of the first reference voltage and the second reference voltage to the other end of the plurality of second capacitors by switching the connection state of the plurality of second switches to a state corresponding to the intermediate digital value, wherein in a third period after the second period ends, a continuous comparison operation of the plurality of first switches is performed to obtain the final result output value, The analog-to-digital conversion circuit further includes: a buffer circuit, configured to transmit the analog input signal to the first digital-to-analog conversion circuit, the second digital-to-analog conversion circuit, and the sub-analog-to-digital conversion circuit, a third switch, arranged between the first digital-to-analog conversion circuit, the second digital-to-analog conversion circuit, the sub-analog-to-digital conversion circuit and the output terminal of the buffer circuit, and a fourth switch coupled in parallel to a series circuit formed by the buffer circuit and the third switch, The continuous comparison control circuit closes the third switch and opens the fourth switch in the first period, and opens the third switch and closes the fourth switch in the second period and the third period.

2. The analog-to-digital conversion circuit according to claim 1, further comprising: The selection circuit is configured to output a signal selected from a plurality of input signals having analog values ​​as the analog input signal.

3. The analog-to-digital conversion circuit according to claim 2, The selection circuit periodically switches the input signal output as the analog input signal.

4. The analog-to-digital conversion circuit according to claim 1, The sub-analog-to-digital conversion circuit is a flash memory type analog-to-digital conversion circuit.

5. The analog-to-digital conversion circuit according to claim 1, Wherein a total capacitance of the plurality of second capacitors has the same capacitance as a total capacitance of the plurality of first capacitors.

6. The analog-to-digital conversion circuit according to claim 1, The sub-analog-to-digital conversion circuit has a resolution that is less than or equal to a resolution of the main analog-to-digital conversion circuit.

7. The analog-to-digital conversion circuit according to claim 6, The continuous comparison control circuit controls the plurality of second switches through a control signal, wherein the control signal is generated by decoding the intermediate digital value output from the sub-analog-to-digital conversion circuit.

8. A signal conversion method of an analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprising: a main analog-to-digital conversion circuit for converting an analog input signal into a digital value; The main analog-to-digital conversion circuit includes: a comparison circuit; a first digital-to-analog conversion circuit having a plurality of first switches, coupled to one of the differential input terminals of the comparison circuit, and having a charge redistribution type circuit configuration; and a second digital-to-analog conversion circuit having a plurality of second switches, coupled to the other of the differential input terminals of the comparison circuit, and having a charge redistribution type circuit configuration, A sub-analog-to-digital conversion circuit, used for converting the analog input signal into a digital value; A continuous comparison control circuit, used for controlling the main analog-to-digital conversion circuit and for outputting a final result output value; a buffer circuit, configured to transmit the analog input signal to the first digital-to-analog conversion circuit, the second digital-to-analog conversion circuit, and the sub-analog-to-digital conversion circuit; A third switch is provided between the first digital-to-analog conversion circuit, the second digital-to-analog conversion circuit, the sub-analog-to-digital conversion circuit and the output terminal of the buffer circuit; and a fourth switch coupled in parallel to a series circuit formed by the buffer circuit and the third switch, The signal conversion method of the analog-to-digital conversion circuit includes: In a first time period, the analog value of the analog input signal is sampled by the first digital-to-analog conversion circuit and the second digital-to-analog conversion circuit, and an intermediate digital value corresponding to the analog value of the analog input signal is obtained from the sub-analog-to-digital conversion circuit; In a second time period after the first time period ends, the reference voltage provided to the second digital-to-analog conversion circuit is switched to a voltage value corresponding to the intermediate digital value of the analog input signal, and In a third time period after the second time period ends, the final result output value is obtained by continuous comparison operation of a plurality of first switches of the first digital-to-analog conversion circuit; During the first period, the third switch of the analog-to-digital conversion circuit is closed and the fourth switch of the analog-to-digital conversion circuit is opened, and The third switch of the analog-to-digital conversion circuit is opened and the fourth switch of the analog-to-digital conversion circuit is closed during the second period and the third period.

9. The signal conversion method of the analog-to-digital conversion circuit according to claim 8, further comprising: A signal is selected from a plurality of input signals having analog values ​​as the analog input signal.

10. The signal conversion method of the analog-to-digital conversion circuit according to claim 9, further comprising: The input signal to be output as the analog input signal is periodically switched.

11. The signal conversion method of the analog-to-digital conversion circuit according to claim 8, The total capacitance of the sampling capacitors in the second digital-to-analog conversion circuit has the same capacitance as the total capacitance of the sampling capacitors in the first digital-to-analog conversion circuit.

12. The signal conversion method of the analog-to-digital conversion circuit according to claim 8, The sub-analog-to-digital conversion circuit has a resolution that is less than or equal to a resolution of the main analog-to-digital conversion circuit.

13. The signal conversion method of the analog-to-digital conversion circuit according to claim 12, The reference voltage to be supplied to the second analog-to-digital conversion circuit is switched by a control signal generated by decoding the intermediate digital value output from the sub-analog-to-digital conversion circuit.

14. An analog-to-digital conversion circuit, comprising: a main analog-to-digital conversion circuit for converting an analog input signal into a digital value; A continuous comparison control circuit, used for controlling the main analog-to-digital conversion circuit and for outputting a final result output value; Comparison circuit; A first digital-to-analog conversion circuit having: a plurality of first capacitors having one end coupled to one of the differential input terminals of the comparison circuit; and a plurality of first switches for selectively providing one of an analog input signal, a first reference voltage, and a second reference voltage to the other ends of the plurality of first capacitors; A second digital-to-analog conversion circuit having: a plurality of second capacitors having one end coupled to another differential input terminal of the differential input terminals of the comparison circuit; and a plurality of second switches for selectively providing one of the analog input signal, the first reference voltage, and the second reference voltage to the other ends of the plurality of second capacitors; A sub-analog-to-digital conversion circuit, used for converting the analog input signal into a digital value; Continuous comparison control circuit for: causing the plurality of first capacitors and the plurality of second capacitors to sample the analog value of the analog input signal during a first period, and obtaining an intermediate digital value corresponding to the analog value of the analog input signal from the sub-analog-to-digital conversion circuit, wherein in a second time period after the first time period ends, the continuous comparison control circuit provides one of the first reference voltage and the second reference voltage to the other end of the plurality of second capacitors by switching the connection state of the plurality of second switches to a state corresponding to the intermediate digital value, wherein in a third period after the second period ends, a continuous comparison operation of the plurality of first switches is performed to obtain the final result output value, wherein the number of the plurality of second capacitors and the number of the plurality of second switches are set to be the same as the number of bits indicating the resolution of the sub-analog-to-digital conversion circuit, the analog-to-digital conversion circuit further comprising: a buffer circuit, configured to transmit the analog input signal to the first digital-to-analog conversion circuit, the second digital-to-analog conversion circuit, and the sub-analog-to-digital conversion circuit, a third switch, arranged between the first digital-to-analog conversion circuit, the second digital-to-analog conversion circuit, the sub-analog-to-digital conversion circuit and the output terminal of the buffer circuit, and a fourth switch coupled in parallel to a series circuit formed by the buffer circuit and the third switch, The continuous comparison control circuit closes the third switch and opens the fourth switch in the first period, and opens the third switch and closes the fourth switch in the second period and the third period.

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