Capacitance detection circuit for touch device, touch device and electronic device

Abstract

The present application provides a capacitance detection circuit of a touch device. The capacitance detection circuit is connected to a capacitor to be tested in a touch screen of the touch device. The capacitance detection circuit includes: a CCO, which is used to generate a first clock signal according to the capacitance value of the capacitor to be tested; a DLL circuit includes a digital phase detector and a digitally controlled delay circuit, wherein the first input end of the digital phase detector is connected to the output end of the CCO, and the second input end of the digital phase detector is connected to the output end of the digitally controlled delay circuit; the digital phase detector is used to output a first digital signal according to the first clock signal and the second clock signal output by the digitally controlled delay circuit; the digitally controlled delay circuit is used to control the delay time of the second clock signal according to the first digital signal. The present application also provides a touch device and an electronic device including the capacitance detection circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of capacitance detection, and more specifically, to a capacitance detection circuit, a capacitance detection system, and an electronic device. Background Art

[0002] Capacitive touch devices are widely used in electronic devices. For example, they can be used as input devices to provide input information, such as position, movement, force, and duration information. The core part of the capacitive touch device is the capacitance detection circuit. In the related technology of capacitance detection, capacitance detection based on time domain is a mainstream detection method. The specific implementation is to charge the capacitor to be tested, convert the charge of the capacitor to be tested into voltage, or convert the change in the charge charged by the capacitor to be tested into voltage, and further process the voltage to determine the capacitance value of the capacitor to be tested. For example, the voltage is converted into a digital signal after sampling by an analog to digital converter (ADC), and then capacitance detection can be performed according to the digital signal. The above method for capacitance detection will be affected by circuit noise, reducing the detection accuracy of capacitance detection. Summary of the invention

[0003] The embodiments of the present application provide a capacitance detection circuit for a touch device, a touch device, and an electronic device, which can reduce the influence of circuit noise on capacitance detection, thereby improving the detection accuracy of capacitance detection.

[0004] In a first aspect, the present application provides a capacitance detection circuit of a touch device, wherein the touch device further comprises a touch screen, the touch screen comprises a plurality of capacitors to be measured, the capacitance detection circuit is connected to the capacitors to be measured, and is characterized in that the capacitance detection circuit comprises:

[0005] A capacitance controlled oscillator CCO, used to generate a first clock signal according to the capacitance value of the capacitor to be measured, wherein a period of the first clock signal is positively correlated with the capacitance value of the capacitor to be measured;

[0006] A delay locked loop (DLL) circuit, comprising: a digital phase detector and a digitally controlled delay circuit, wherein the digital phase detector comprises a first input terminal, a second input terminal and an output terminal, the first input terminal of the digital phase detector is connected to the output terminal of the CCO, and the second input terminal of the digital phase detector is connected to the output terminal of the digitally controlled delay circuit;

[0007] The digital phase detector is used to receive the first clock signal and the second clock signal output by the digitally controlled delay circuit, and output a first digital signal according to a phase shift between the first clock signal and the second clock signal;

[0008] The digitally controlled delay circuit is used to control the delay time of the second clock signal according to the first digital signal, and output the second clock signal to the second input terminal of the digital phase detector;

[0009] When the DLL circuit is locked, the delay time between the second clock signal and the first clock signal is N cycles of the first clock signal, where N is a positive integer, and the first digital signal output by the digital phase detector is used to determine the capacitance value of the capacitor to be tested.

[0010] In some optional implementations, when the DLL circuit is locked, a delay time between the second clock signal and the first clock signal is a period of the first clock signal.

[0011] In some optional implementations, the capacitance detection circuit further includes:

[0012] A processing circuit is connected to the digital phase detector and the digitally controlled delay circuit, and is used to receive the first digital signal output by the digital phase detector, process the first digital signal, and output the processed first digital signal to the input end of the digitally controlled delay circuit, wherein the processed first digital signal is used to control the delay time of the second clock signal, and the processing includes at least one of the following: integration processing, signal amplification or reduction processing, and filtering processing.

[0013] In some optional implementations, the digitally controlled delay circuit includes:

[0014] a digital-to-analog converter DAC, comprising an input end and an output end, wherein the input end is connected to the output end of the processing circuit, the DAC is used to convert the first digital signal processed by the processing circuit into a first analog signal, and the output end of the DAC is used to output the first analog signal;

[0015] An analog controlled delay line comprises a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the analog controlled delay line is connected to the output terminal of the DAC and is used to receive the first analog signal, the second input terminal of the analog controlled delay line is used to input the first clock signal, the analog controlled delay line is used to control the delay time of the second clock signal according to the first analog signal and the first clock signal, and the output terminal of the analog controlled delay line is used to output the second clock signal.

[0016] In some optional implementations, the analog controlled delay line includes a plurality of delay units connected in series, each delay unit includes a first end and a second end, the first end of each delay unit is used to input the first clock signal, the second end of each delay unit is used to input the first analog signal, the first analog signal is used to control the delay time corresponding to each delay unit, and the delay time of the second clock signal is the total delay time of the plurality of delay units.

[0017] In some optional implementations, the first analog signal is an analog voltage, and the analog controlled delay line is a voltage-controlled delay line VCDL.

[0018] In some optional implementations, the capacitance detection circuit further includes:

[0019] a processing unit, configured to determine whether the capacitance value of the capacitor to be measured changes relative to a basic capacitance according to the processed first digital signal output by the processing circuit when the DLL is locked, wherein the basic capacitance is the capacitance value of the capacitor to be measured when the touch screen is not touched.

[0020] In some optional implementations, the capacitor to be tested is formed by the detection electrode and the driving electrode in the touch screen, or the capacitor to be tested is formed by the detection electrode and the ground in the touch screen, or the capacitor to be tested is formed by the detection electrode in the touch screen and an external object.

[0021] In some optional implementations, part or all of the capacitance detection circuit is integrated into a touch sensing chip.

[0022] In a second aspect, the present application provides a touch device, comprising:

[0023] A touch screen including a capacitor to be tested; and

[0024] As in the capacitance detection circuit in the first aspect or any optional implementation of the first aspect, the capacitance detection circuit is connected to the capacitor to be measured, and the capacitance detection circuit is used to detect the capacitance value of the capacitor to be measured.

[0025] According to a third aspect, an electronic device is provided, comprising the touch device according to the second aspect.

[0026] Based on the above technical solution, by using the output clock signal of the capacitor controlled oscillator 11, that is, the first clock signal, as the reference clock signal of the digitally controlled delay circuit 123, the digitally controlled delay circuit 123 can generate a second clock signal related to the output clock signal of the capacitor controlled oscillator 11, that is, the first clock signal CLK1. When the DLL circuit 12 is locked, the delay time of the second clock signal relative to the first clock signal is N cycles of the first clock signal. The cycle of the first clock signal CLK1 is positively correlated with the capacitance value of the capacitor to be measured, and the delay time of the second clock signal CLK2 is controlled according to the first digital signal D1. The first digital signal D1 is related to the capacitance value of the capacitor to be measured 20. Therefore, the capacitance value of the capacitor to be measured 20 can be determined according to the first digital signal D1.

[0027] Therefore, the present application generates clock signals of different periods or frequencies based on different capacitance values, and further performs capacitance detection based on the clock signal as a reference clock through the principle of phase locking through a DLL circuit. There is no need to perform a time domain charging and discharging process on the capacitor to be tested, which is beneficial to reducing the impact of circuit noise on the capacitance detection process, thereby improving the accuracy of capacitance detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a capacitance detection device according to an embodiment of the present application.

[0029] Figure 2 is a schematic structural diagram of a digitally controlled delay circuit according to an embodiment of the present application.

[0030] Figure 3 is a schematic circuit diagram of a voltage-controlled delay line according to an embodiment of the present application.

[0031] Figure 4 This is a typical structure of a PLL circuit.

[0032] Figure 5 is a schematic block diagram of a capacitance detection system according to an embodiment of the present application.

[0033] Figure 6 is a schematic block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and understandable, the specific embodiments of the present application are described in detail below in conjunction with the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided so that the present application will be comprehensive and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art.

[0035] In addition, the described features and structures may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that, without one or more of the specific details, or by adopting other structures, components, etc., the technical scheme of the present application may also be put into practice. In other cases, known structures or operations are not shown or described in detail to avoid blurring the present invention.

[0036] Further, the following terms are exemplary and are not intended to be limiting in any way. After reading this application, those skilled in the art will recognize that these terms are applicable to technologies, methods, physical elements, and systems (whether currently known or not), including extensions thereof that are inferred or inferred by those skilled in the art after reading this application.

[0037] Figure 1 is a schematic block diagram of a capacitance detection circuit 10 according to an embodiment of the present application, wherein the capacitance detection circuit 10 is connected to a capacitor 20 to be tested, such as Figure 1 As shown, the capacitance detection circuit 10 includes:

[0038] A capacitance controlled oscillator CCO11, used for generating a first clock signal CLK1 according to the capacitance value of the capacitor 20 to be measured, wherein a period of the first clock signal CLK1 is positively correlated with the capacitance value of the capacitor 20 to be measured;

[0039] The delay locked loop DLL circuit 12 comprises: a digital phase detector 121 and a digitally controlled delay circuit 123, wherein the digital phase detector 121 comprises a first input terminal 1211, a second input terminal 1212 and an output terminal 1213, the first input terminal 1211 of the digital phase detector 121 is connected to the output terminal of the CCO11, and the second input terminal 1212 of the digital phase detector 121 is connected to the output terminal of the digitally controlled delay circuit 123;

[0040] The digital phase detector 121 is used to receive the first clock signal CLK1 and the second clock signal CLK2 output by the digitally controlled delay circuit 123, and output a first digital signal D1 according to the phase shift between the first clock signal CLK1 and the second clock signal CLK2;

[0041] The digitally controlled delay circuit 123 is used to control the delay time of the second clock signal CLK2 according to the first digital signal D1, and output the second clock signal CLK2 to the second input terminal 1212 of the digital phase detector 121;

[0042] When the DLL circuit 12 is locked, the delay time between the second clock signal CLK2 and the first clock signal CLK1 is N cycles of the first clock signal CLK1, where N is a positive integer. The first digital signal D1 output by the digital phase detector 121 is used to determine the capacitance value of the capacitor 20 to be tested.

[0043] In the embodiment of the present application, a capacitive controlled oscillator (CCO) 11 is an oscillator controlled by the capacitance value of the capacitor to be measured 20, that is, a change in the capacitance value of the capacitor to be measured 20 can change the oscillation frequency or period of the CCO 11. Specifically, the CCO 11 can generate a first clock signal CLK1 according to the capacitance value of the capacitor to be measured 20. The period of the first clock signal CLK1 is positively correlated with the capacitance value of the capacitor to be measured 20, that is, the larger the capacitance value of the capacitor to be measured 20, the larger the period of the first clock signal CLK1, and vice versa. In other words, the frequency of the first clock signal CLK1 is inversely correlated with the capacitance value of the capacitor to be measured 20, that is, the larger the capacitance value of the capacitor to be measured 20, the smaller the frequency of the first clock signal CLK1, and vice versa.

[0044] In the embodiment of the present application, the DLL circuit 12 is a negative feedback system, which controls the second clock signal CLK2 and the first clock signal CLK1 to align the clock phases through the negative feedback mechanism. When the DLL circuit 12 is locked, or the phases are aligned, the delay time of the second clock signal CLK2 relative to the first clock signal CLK1 is N cycles of the first clock signal CLK1, where N is a positive integer, and typically, N is 1. It can be understood that the delay time of the second clock signal CLK2 relative to the first clock signal CLK1 is N cycles of the first clock signal CLK1, which can be understood as the phase misalignment between the first clock signal CLK1 and the second clock signal CLK2 will be gradually reduced until it disappears.

[0045] Specifically, the DLL circuit 12 includes a digital phase detector 121 and a digitally controlled delay circuit 123. The digital phase detector 121 outputs a first digital signal D1 by detecting the phase relationship between the first clock signal CLK1 output by the capacitor controlled oscillator 11 and the second clock signal CLK2 output by the digitally controlled delay circuit 123. For example, if the first clock signal CLK1 is ahead of the second clock signal CLK2 in phase, the digital phase detector 121 can output 1, or if the first clock signal CLK1 is delayed in phase than the second clock signal CLK2, the digital phase detector 121 can output 0, or vice versa, as long as the delay time adjustment logic of the digitally controlled delay circuit 123 is adjusted accordingly.

[0046] Furthermore, the input clock signal of the digitally controlled delay circuit 123 is configured as the first clock signal CLK1, so that the digitally controlled delay circuit 123 can control the delay time of the second clock signal CLK2 according to the first clock signal CLK1 and the first digital signal D1 output by the digital phase detector 121, and output the second clock signal CLK2 with adjusted delay time to the second input terminal 1212 of the digital phase detector 121.

[0047] The phase shift between the two clock signals is detected by the digital phase detector 121, and a corresponding digital signal is output. Further, the digitally controlled delay circuit 123 controls the delay time of the second clock signal CLK2 relative to the first clock signal CLK1 according to the digital signal, so that the delay time between the first clock signal CLK1 and the second clock signal CLK2 is finally locked to N cycles of the first clock signal CLK. At this time, the DLL circuit 12 is stable, or locked, and the output of the digital phase detector 121 is also stable.

[0048] In a specific implementation, when the DLL circuit 12 is locked, the delay time of the second clock signal CLK2 relative to the first clock signal CLK1 can be controlled to be one cycle of the first clock signal, that is, the second clock signal CLK2 is one clock cycle later than the first clock signal CLK1. In other words, the second clock signal CLK2 is phase-aligned with the first clock signal CLK1. In this case, the working state of the DLL circuit 12 is more stable, and accordingly, the output of the digital phase detector 121 is also more stable. In the following, the embodiment of the present application is described by taking the first clock signal and the second clock signal differing by one clock cycle as an example, but the present application is not limited thereto.

[0049] In summary, the present application designs the output clock signal (i.e., the first clock signal) of the capacitor-controlled oscillator 11 as the reference clock signal of the digitally controlled delay circuit 123, so that the digitally controlled delay circuit 123 can generate a second clock signal related to the output clock signal of the capacitor-controlled oscillator 11. When the DLL circuit 12 is locked, the first clock signal and the second clock signal differ by one clock cycle.

[0050] It can be known from the working principle of the capacitor controlled oscillator 11 that the period of the first clock signal CLK1 is positively correlated with the capacitance value of the capacitor to be measured 20, and the delay time of the second clock signal CLK2 is controlled according to the first digital signal D1, then the period of the first digital signal D1 is correlated with the period of the first clock signal CLK1, so that the first digital signal D1 is correlated with the capacitance value of the capacitor to be measured 20, and thus the capacitance value of the capacitor to be measured 20 can be determined according to the first digital signal D1. Therefore, the present application generates clock signals of different periods or frequencies based on different capacitance values, and further performs capacitance detection based on the principle of phase locking through the DLL circuit based on the clock signal as a reference clock, which does not require the capacitor to be measured to be charged and discharged in the time domain, which is conducive to reducing the influence of circuit noise on the capacitance detection process, thereby improving the accuracy of capacitance detection.

[0051] Optionally, the digital phase detector 121 can be implemented using a binary phase detector (Binary Phase Detector, Binary PD), a binary phase frequency detector (Binary Phase Frequency Detector, Binary PFD), etc., or can be implemented using other equivalent circuits, as long as the phase offset between signals can be converted into a digital signal so that the phases of the signals gradually approach each other. This application does not limit this.

[0052] Optionally, in some embodiments of the present application, Figure 1 As shown, the DLL circuit 12 may further include:

[0053] The processing circuit 122 is connected to the digital phase detector 121 and the digitally controlled delay circuit 123, and is used to receive the first digital signal D1 output by the digital phase detector 121, process the first digital signal, and output the processed first digital signal D1' to the digitally controlled delay circuit 123, so that the digitally controlled delay circuit 123 can control the delay time of the second clock signal CLK2 based on the processed first digital signal D1'.

[0054] In some embodiments of the present application, the processing of the first digital signal D1 by the processing circuit 122 includes but is not limited to at least one of the following: integration processing, amplification or reduction processing, and filtering processing.

[0055] It can be understood that different DLL circuits 12 correspond to corresponding performance indicators, such as the capacitance range of the capacitor that can be measured, stability, signal-to-noise ratio (SNR), etc. The processing circuit 122 can process the first digital signal accordingly according to the corresponding performance indicators to meet the performance indicators. In one implementation, the processing circuit 122 can integrate the first digital signal D1 output by the digital phase detector 121, and further amplify or reduce it so that the capacitance of the capacitor to be measured falls within the capacitance range of the capacitance detection circuit. Further, the digital signal after amplification or reduction can be filtered. In another implementation, the processing circuit 122 can also first amplify or reduce the first digital signal D1, further integrate it, and finally filter it and output it to the digitally controlled delay circuit 123, or other processing methods can be used to process the first digital signal D1, as long as the performance requirements of the DLL circuit 12 can be met, and this application does not limit this.

[0056] It should be understood that the first digital signal D1 output by the digital phase detector 121 for determining the capacitance value of the capacitor to be measured 20 may refer to that the first digital signal may be directly used to determine the capacitance value of the capacitor to be measured 20, or may refer to the signal after the processing circuit 122 processes the first digital signal, that is, D1' may be used to determine the capacitance value of the capacitor to be measured.

[0057] It should also be understood that the first digital signal D1 output by the digital phase detector 121 is used to determine the capacitance value of the capacitor 20 to be tested, which may include the first digital signal D1 output by the digital phase detector 121 being used to determine the change in the capacitance value of the capacitor 20 to be tested, or whether a change has occurred, etc.

[0058] According to the aforementioned capacitance detection principle, the processed first digital signal D1' can be used to control the delay time of the second clock signal CLK2, that is, the processed first digital signal D1' is related to the delay time of the second clock signal CLK2, and the delay time of the second clock signal CLK2 is related to the period of the first clock signal CLK1, then the processed first digital signal D1' is related to the period of the first clock signal CLK1, and the period of the first clock signal CLK1 is positively correlated with the capacitance value of the capacitor 20 to be measured, then the processed first digital signal D1' is related to the capacitance value of the capacitor 20 to be measured. Therefore, the capacitance value of the capacitor 20 to be measured can be determined according to the processed first digital signal D1'.

[0059] Optionally, in some embodiments, the capacitor to be tested 20 may be, for example but not limited to, a sensing element in a touch device, for example, a capacitor to be tested in a touch screen of a capacitive touch device. Specifically, the touch device includes a touch panel, which may also be referred to as a touch screen. The capacitor to be tested 20 is formed by a driving electrode and a detection electrode on the touch panel, or the capacitor to be tested 20 may be formed by a detection electrode and a ground on the touch panel, or the capacitor to be tested 20 may be formed by a detection electrode on the touch panel and an external object. The external object is a conductor, such as but not limited to a user's finger. In this scenario, the capacitance value of the capacitor to be tested 20 may be used to determine whether the touch device is touched, for example, the touch device may be determined based on whether the capacitance value of the capacitor to be tested 20 changes. Optionally, whether the capacitance value of the capacitor to be tested 20 changes may be whether the capacitance value of the capacitor to be tested 20 changes relative to the basic capacitance, where the basic capacitance is the capacitance value of the capacitor to be tested 20 when it is not contacted or approached by an external object, and the capacitance value may also be referred to as a nominal capacitance.

[0060] Optionally, in some embodiments of the present application, the capacitance detection circuit 10 may further include:

[0061] The processing unit is used to determine whether the capacitance value of the capacitor to be tested 20 has changed relative to the basic capacitance according to the processed first digital signal D1' output by the processing circuit 122 when the DLL circuit is locked, wherein the basic capacitance is the capacitance value of the capacitor to be tested 20 when it is not touched or approached by an external object. For example, taking a touch device as an example, the basic capacitance is the capacitance value of the capacitor to be tested 20 when the touch screen of the touch device is not touched by an external object.

[0062] Taking the above-mentioned capacitive touch detection scenario as an example, the processing unit can first determine that when the touch device is not touched, the first digital signal output by the processing circuit 122 is recorded as the nominal digital signal D1'_REF, and the nominal digital signal D1'_REF corresponds to the basic capacitance C_REF of the capacitor 20 to be tested, and the two can be converted through a specific relationship.

[0063] Furthermore, whether the touch device is touched can be determined based on the processed first digital signal D1'. For example, whether the touch device is touched can be determined based on the change of the first digital signal D1' output by the processing circuit 122 relative to the nominal digital signal D1'_REF. As an example, if the processed first digital signal D1' changes relative to the nominal digital signal D1'_REF, or the amount of change is greater than a certain threshold, it can be determined that the touch device is touched; otherwise, it is determined that the touch device is not touched.

[0064] In other embodiments, the processed first digital signal D1' may be further processed and converted into a corresponding capacitance value C, and whether the touch device is touched may be further determined based on the capacitance value C. For example, whether the touch device is touched may be determined based on a change in the capacitance value C corresponding to the processed first digital signal D1' relative to the basic capacitance C_REF. As an example, if the capacitance value C corresponding to the processed first digital signal changes relative to the basic capacitance C_REF, or the change is greater than a certain threshold, it may be determined that the touch device is touched; otherwise, it is determined that the touch device is not touched.

[0065] Optionally, in some embodiments, the processing unit may be a processing unit in a device or apparatus in which the capacitance detection circuit 10 is installed. For example, if part or all of the capacitance detection circuit 10 can be integrated in a touch sensing chip of a touch device, the touch sensing chip is electrically connected to a touch panel to drive the touch panel to perform a touch sensing operation. The processing unit may be a processing unit in the touch device, or may be a main control module in the electronic device in which the touch device is located.

[0066] It should be understood that in the embodiment of the present application, the digitally controlled delay circuit 123 can provide clock signals of different phases through an internal delay stage, and it can be implemented using any circuit that controls the delay time according to a digital signal, and the embodiment of the present application is not limited to this.

[0067] The following, combined Figure 2 , which illustrates a typical implementation of the digitally controlled delay circuit 123. Figure 2 As shown, the digitally controlled delay circuit 123 includes:

[0068] A digital-to-analog converter DAC1231, comprising an input end and an output end, wherein the input end is connected to the output end of the processing circuit 122, the DAC1231 is used to convert the first digital signal D1' obtained after being processed by the processing circuit 122 into a first analog signal A1, and the output end of the DAC1231 is used to output the first analog signal A1;

[0069] The analog controlled delay line 1232 includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the analog controlled delay line 1232 is connected to the output terminal of the DAC1231 for receiving the first analog signal A1. The second input terminal of the analog controlled delay line 1232 is used to input the first clock signal CLK1. The analog controlled delay line 1232 is used to control the delay time of the second clock signal CLK2 according to the first analog signal A1 and the first clock signal CLK1. The output terminal of the analog controlled delay line 1232 is used to output the second clock signal CLK2.

[0070] In some embodiments, the first analog signal A1 may be an analog voltage or an analog current, and correspondingly, the analog controlled delay line 1232 may be a voltage controlled delay line (VCDL) or a current controlled delay line (CCDL). Below, taking the first analog signal as an analog voltage as an example, a typical implementation of the analog controlled delay line 1232 is described. Of course, it may also be implemented in other ways, which is not limited here.

[0071] like Figure 3 As shown, the analog controlled delay line 1232 includes a plurality of delay units 12321 connected in series, each delay unit 12321 includes a first end and a second end, the first end of each delay unit 12321 is used to input the first clock signal CLK1, the second end of each delay unit 12321 is used to input the first analog signal (taking the first analog signal as the analog voltage V-REF as an example), the first analog signal V-REF is used to control the delay time corresponding to each delay unit 12321, and the delay time of the second clock signal CLK2 is the total delay time of the multi-stage delay unit.

[0072] Specifically, each level of delay unit of VCDL can output a certain phase shift, and the degree of phase shift output by each level of delay unit of VCDL is controlled by analog voltage V-REF, and the total delay of all delay units constitutes the delay time of VCDL, that is, the delay time of the second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 are compared in phase by digital phase detector 121, and the corresponding digital signal is output, which is converted into an analog signal after one step of processing, such as analog voltage V-REF, and the analog voltage V-REF is used to change the delay time of the delay unit in VCDL.

[0073] In some embodiments, the analog controlled delay line 1232 may use an inverter to implement a delay unit, and use a valid state machine to select an output signal.

[0074] Specifically, a single delay unit in VCDL represents the minimum delay time, such as the delay time of a basic inverter. Since each inverter can shift the phase by 180 degrees, VCDL can output an even number of inverters to provide the corresponding phase. VCDL needs to select a signal whose phase is closest to the phase of the first clock signal CLK1 as the output clock signal for feedback. Therefore, the output signal that needs to be implemented in VCDL is not necessarily the last stage output of VCDL, that is, the second clock signal is not necessarily output at the last stage of VCDL, but it must be output at a position closest to the phase of the first clock signal CLK1. Specifically, the corresponding signal can be generated by the effective state machine to select the output signal.

[0075] In a specific implementation, the delay of each delay unit has a certain relationship with the RC time constant in the delay unit. The larger the time constant, the larger the delay. The delay of each level of delay unit can be adjusted by changing the time constant of the delay unit, such as impedance R or load capacitance C.

[0076] Therefore, in the embodiment of the present application, by inputting the output clock of the CCO11 as a reference clock into the analog controlled delay line 1232, the delay time of the output second clock signal CLK2 can be related to the period of the first clock signal CLK1, and the delay time of the second clock signal CLK2 is controlled by the first analog signal A1, so that the first analog signal A1 and the period of the first clock signal CLK1 can be related. Further, the first analog signal A1 is obtained according to the processed first digital signal D1', so the processed first digital signal D1' is related to the period of the first clock signal CLK1, that is, related to the capacitance value of the capacitor 20 to be measured. Therefore, the processed first digital signal D1' can be used to determine the change in the capacitance value of the capacitor 20 to be measured. The specific determination method can refer to the relevant description of the aforementioned embodiment.

[0077] In other embodiments, the phase locking of the second clock signal may also be achieved by a PLL circuit, for example, Figure 4 As shown, the PLL circuit 40 includes a digital frequency detector 41, a digital filter 42 and a digital controlled oscillator DCO43. The specific connection relationship is as follows: Figure 1 The connection relationship between the digital phase detector 121, the processing circuit 122 and the digitally controlled delay circuit 123 in the DLL circuit 12 is similar, but the working principles are different.

[0078] Specifically, the digital frequency detector 41 can receive the first clock signal CLK1 and the second clock signal CLK2 output from the DCO43, and output the first digital signal D1 according to the frequency and phase difference between the two. The first digital signal D1 is further filtered by the digital filter 42, and the filtered first digital signal D1' is input to the DCO43. The DCO43 can output the second clock signal CLK2 according to the filtered first digital signal D1'. When the frequency and phase of the second clock signal CLK2 and the first clock signal CLK1 are infinitely close, the PLL40 circuit is locked. At this time, the output of the digital filter 42 is also stable.

[0079] Among them, the digital controlled oscillator DCO43 is usually implemented by DAC and voltage controlled oscillator (Voltage Controlled Oscillator, VCO). The DAC has the same function as the DAC1231 in the aforementioned embodiment. The VCO can output a clock signal of a certain frequency and phase according to the analog signal output by the DAC, such as an analog voltage. When the clock signal is infinitely close to the input clock signal of DCO43, the PLL circuit 40 is locked.

[0080] In the PLL circuit 40, the frequency difference between the first clock signal CLK1 and the second clock signal CLK2 is related to the first digital signal D1, and the period of the first clock signal CLK1 is positively correlated with the capacitance value of the capacitor to be measured 20. Therefore, the capacitance value of the capacitor to be measured 20 can also be determined according to the first digital signal. For example, the first digital signal filtered by the digital filter 42 can be integrated to determine the capacitance value of the capacitor to be measured 20.

[0081] However, in practical applications, the VCDL in the DLL circuit and the VCO in the PLL circuit are both major noise contributors. If the noise of the VCDL and VCO can be reduced, the overall noise of the system will be reduced. Due to the difference in their working principles, the phase noise generated by the VCDL in the DLL circuit will not accumulate, while the VCO in the PLL circuit usually accumulates more phase noise. Therefore, the noise generated by the VCDL is lower than that of the VCO. Using the DLL circuit to implement capacitance detection is more conducive to reducing system noise, thereby improving detection accuracy.

[0082] The present application also provides a capacitance detection system 50, such as Figure 5 As shown, the capacitance detection system 50 includes: a capacitor to be measured 51 and a capacitance detection circuit 52 , wherein the capacitance detection circuit 52 is connected to the capacitor to be measured 51 , and the capacitance detection circuit 52 is used to detect the capacitance value of the capacitor to be measured 51 .

[0083] Optionally, in some embodiments, the capacitance detection system 50 is a touch device, and the capacitance value of the capacitor to be tested 51 is used to determine whether the touch device is touched.

[0084] Optionally, the touch device includes, for example, a capacitive touch screen and a capacitance detection circuit 52. For example, the capacitive touch screen includes a mutual capacitance touch screen or a self capacitance touch screen.

[0085] In a mutual capacitance based touch system, the touch screen may include, for example, a drive area and a sensing area, such as drive lines (or drive electrodes) and sense lines (or detection electrodes). As an example, the drive lines may form multiple rows, and the sense lines may form multiple columns (e.g., orthogonal). Touch pixels may be arranged at the intersection of the rows and columns. During operation, the rows may be stimulated by an alternating current (AC) waveform, and mutual capacitance may be formed between the rows and columns of the touch pixels. When an object approaches the touch pixel, some of the charge coupled between the rows and columns of the touch pixel may be coupled to the object instead. This reduction in charge coupled to the touch pixel may result in a net reduction in mutual capacitance between the rows and columns and a reduction in the AC waveform coupled to the touch pixel. This reduction in the charge coupled AC waveform may be detected and measured by the touch system to determine whether there is a touch, and the touch position of the object on the touch screen. For a mutual capacitance touch screen, the capacitor to be measured 51 is formed by the detection electrode and the drive electrode on the mutual capacitance touch screen.

[0086] In a touch system based on self-capacitance, each touch pixel may be formed by an individual electrode that forms a self-capacitance to ground. When an object approaches the touch pixel, another capacitance to ground may be formed between the object and the touch pixel. The other capacitance to ground may result in a net increase in the self-capacitance experienced by the touch pixel. This increase in self-capacitance may be detected and measured by the touch system to determine whether there is a touch and the position of the object when it touches the touch screen. For a self-capacitive touch screen, the capacitor to be tested 20 is formed by a detection electrode on the touch screen and ground, or the capacitor to be tested 51 is formed by a detection electrode on the touch screen and an external object. The external object is, for example, but not limited to, a conductive object such as a user's finger.

[0087] The touch panel of the touch device of the present application may be a touch screen mounted externally on the display panel, or may be integrated into the display panel (Incell), etc. These technical solutions should all fall within the protection scope of the present application.

[0088] In addition, the capacitance detection system 50 may also be a fingerprint sensing device. Accordingly, the capacitance detection circuit 52 is a capacitance detection circuit in a fingerprint sensing device. The capacitor to be tested 51 is a capacitor to be tested in a fingerprint sensing device.

[0089] However, alternatively, the capacitance detection system 50 is not limited to the above-mentioned touch device or fingerprint sensing device.

[0090] The embodiment of the present application also provides an electronic device, Figure 6 A schematic structural diagram of an electronic device 60 according to an embodiment of the present application is shown. Figure 6As shown, the electronic device 60 may include a capacitance detection system 61, and the capacitance detection system 61 may be Figure 5 Capacitance detection system 50 in.

[0091] It should be understood that the electronic device 60 of the embodiment of the present application may include but is not limited to a smart phone, a tablet computer, a computer, a laptop computer, a smart wearable device, a smart door lock, etc. In order to realize the basic functions of the electronic device, in addition to the modules or components illustrated above, the electronic device in the embodiment of the present application may also include other necessary modules or components. Taking the electronic device as a smart phone as an example, it may also include a communication module, a speaker, a microphone, a battery, etc.

[0092] The above-mentioned processing unit may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step performed by the above-mentioned processing unit can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above-mentioned processor may be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The various methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware decoding processor to be executed, or the hardware and software modules in the decoding processor are combined and executed. The software module may be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware.

[0093] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A capacitance detection circuit of a touch device, wherein the touch device further comprises a touch screen, the touch screen comprises a plurality of capacitors to be tested, the capacitance detection circuit is connected to the capacitors to be tested, and is characterized in that: The touch screen includes a mutual capacitance touch screen or a self capacitance touch screen, and the capacitance detection circuit includes: A capacitance controlled oscillator, used to generate a first clock signal according to the capacitance value of the capacitor to be measured, wherein a period of the first clock signal is positively correlated with the capacitance value of the capacitor to be measured; A delay locked loop circuit, comprising: a digital phase detector and a digitally controlled delay circuit, wherein the digital phase detector comprises a first input terminal, a second input terminal and an output terminal, the first input terminal of the digital phase detector is connected to the output terminal of the capacitor controlled oscillator, and the second input terminal of the digital phase detector is connected to the output terminal of the digitally controlled delay circuit; The digital phase detector is used to receive the first clock signal and the second clock signal output by the digitally controlled delay circuit, and output a first digital signal according to a phase shift between the first clock signal and the second clock signal; The digitally controlled delay circuit is used to control the delay time of the second clock signal according to the first digital signal, and output the second clock signal to the second input terminal of the digital phase detector; When the delay phase-locked loop circuit is locked, the delay time between the second clock signal and the first clock signal is N periods of the first clock signal, where N is a positive integer, and the first digital signal output by the digital phase detector is used to determine the capacitance value of the capacitor to be tested.

2. The capacitance detection circuit according to claim 1, characterized in that: When the delay locked loop circuit is locked, the delay time between the second clock signal and the first clock signal is one cycle of the first clock signal.

3. The capacitance detection circuit according to claim 1, characterized in that: The capacitance detection circuit also includes: A processing circuit is connected to the digital phase detector and the digitally controlled delay circuit, and is used to receive the first digital signal output by the digital phase detector, process the first digital signal, and output the processed first digital signal to the input end of the digitally controlled delay circuit, wherein the processed first digital signal is used to control the delay time of the second clock signal, and the processing includes at least one of the following: integration processing, signal amplification or reduction processing, and filtering processing.

4. The capacitance detection circuit according to claim 3, characterized in that: The digitally controlled delay circuit comprises: a digital-to-analog converter, comprising an input end and an output end, wherein the input end is connected to the output end of the processing circuit, the digital-to-analog converter is used to convert the first digital signal processed by the processing circuit into a first analog signal, and the output end of the digital-to-analog converter is used to output the first analog signal; An analog controlled delay line comprises a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the analog controlled delay line is connected to the output terminal of the digital-to-analog converter for receiving the first analog signal, the second input terminal of the analog controlled delay line is used for inputting the first clock signal, the analog controlled delay line is used for controlling the delay time of the second clock signal according to the first analog signal and the first clock signal, and the output terminal of the analog controlled delay line is used for outputting the second clock signal.

5. The capacitance detection circuit according to claim 4, characterized in that: The analog controlled delay line includes a plurality of delay units connected in series, each delay unit includes a first end and a second end, the first end of each delay unit is used to input the first clock signal, the second end of each delay unit is used to input the first analog signal, the first analog signal is used to control the delay time corresponding to each delay unit, and the delay time of the second clock signal is the total delay time of the plurality of delay units connected in series.

6. The capacitance detection circuit according to claim 4, characterized in that: The first analog signal is an analog voltage, and the analog controlled delay line is a voltage-controlled delay line.

7. The capacitance detection circuit according to claim 3, characterized in that: The capacitance detection circuit also includes: a processing unit, configured to determine whether the capacitance of the capacitor to be measured changes relative to a basic capacitance according to the processed first digital signal output by the processing circuit when the delay locked loop circuit is locked, wherein the basic capacitance is the capacitance of the capacitor to be measured when the touch screen is not touched.

8. The capacitance detection circuit according to claim 7, characterized in that: The capacitor to be measured is formed by the detection electrode and the driving electrode in the touch screen, or the capacitor to be measured is formed by the detection electrode and the ground in the touch screen, or the capacitor to be measured is formed by the detection electrode in the touch screen and an external object.

9. The capacitance detection circuit according to claim 1, characterized in that: Part or all of the capacitance detection circuit is integrated into a touch sensing chip.

10. A touch device, characterized in that: include: A touch screen, comprising a capacitor to be tested; the touch screen comprises a mutual capacitance touch screen or a self-capacitance touch screen; The capacitance detection circuit according to any one of claims 1 to 9, wherein the capacitance detection circuit is connected to the capacitor to be measured, and the capacitance detection circuit is used to detect the capacitance value of the capacitor to be measured.

11. An electronic device, characterized in that: The invention comprises the touch device as claimed in claim 10.

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