Method for singulating semiconductor dies and singulated dies formed thereby

Abstract

The substrate semiconductor layer is attached to the carrier substrate by sacrificing a bonding material layer. A plurality of semiconductor dies contained within a continuous material layer are formed on the front side of the substrate semiconductor layer. Each of the continuous material layers extends continuously over the regions of the plurality of semiconductor dies. By anisotropically etching portions of the continuous material layer that are located between adjacent pairs of the semiconductor dies, a plurality of dicing channels are formed between adjacent pairs among the plurality of semiconductor dies. The plurality of dicing channels extend to the top surface of the sacrificial bonding material layer. Using an isotropic etching process, the sacrificial bonding material layer is selectively removed from the material of the surface portions of the plurality of semiconductor dies. Once the sacrificial bonding material layer is removed, the plurality of semiconductor dies are singulated from each other.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductor devices, and more particularly to a method for singulating semiconductor dies using a sacrificial bonding material layer and an anisotropic channel etching process and a singulated die formed therefrom. Background Art

[0002] A semiconductor wafer contains multiple semiconductor dies that need to be singulated before a packaging process that electrically connects each semiconductor die to pins in a chip package. The singulation process typically uses dicing, where the semiconductor wafer is diced along dicing channels provided between adjacent pairs of semiconductor dies. A mechanical saw is used to cut through each of the dicing channels. The dicing process applies large mechanical stresses on the semiconductor devices located within the semiconductor dies and can cause device failures. Additionally, mechanical dicing can be time-consuming and expensive because semiconductor wafers have a large thickness, typically greater than 600 microns. Although the backside of the semiconductor wafer can be polished prior to mechanical dicing to relieve stress during mechanical dicing, backside polishing is time-consuming and expensive. Summary of the Invention

[0003] According to one aspect of the present disclosure, a method of forming a singulated semiconductor die is provided, comprising: forming a sacrificial bonding material layer on a front surface of a carrier substrate; attaching a substrate semiconductor layer to the front side of the sacrificial bonding material layer; forming a plurality of semiconductor dies included within a continuous material layer on the front side of the substrate semiconductor layer, each of the continuous material layers continuously extending over an area of the plurality of semiconductor dies; forming a plurality of dicing channels between adjacent pairs among the plurality of semiconductor dies by anisotropically etching at least a portion of the continuous material layer located between adjacent pairs of semiconductor dies, wherein the plurality of dicing channels extend to a top surface of the sacrificial bonding material layer; and selectively removing the sacrificial bonding material layer from a surface portion of the plurality of semiconductor dies using an isotropic etching process, wherein the plurality of semiconductor dies are singulated from each other when the sacrificial bonding material layer is removed.

[0004] According to another aspect of the present disclosure, a three-dimensional memory device is provided, comprising: a three-dimensional memory device structure located on a front surface of a semiconductor substrate layer; a silicon nitride passivation layer contacting an entirety of a back surface of the semiconductor substrate layer; an interconnect-level dielectric layer containing metal interconnect structures and located above the substrate semiconductor layer; a cap silicon nitride passivation layer contacting metal contact pads that are electrically connected to the metal interconnect structures and located above the interconnect-level dielectric layer; and a silicon nitride passivation liner contacting an entirety of an outer sidewall of the interconnect-level dielectric layer and extending vertically between the silicon nitride passivation layer and the cap silicon nitride passivation layer.

[0005] According to yet another aspect of the present disclosure, there is provided a singulated semiconductor die including: a semiconductor device located on a front surface of a semiconductor substrate layer; an interconnect dielectric layer including a metal interconnect structure and located above the substrate semiconductor layer; and a silicon nitride passivation liner contacting an entirety of an outer sidewall of the interconnect dielectric layer and an entirety of an outer sidewall of the semiconductor substrate layer, wherein the singulated semiconductor die has a non-rectangular horizontal cross-sectional shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A-1E is a sequential vertical cross-sectional view of an exemplary structure during the formation of a composite substrate according to an embodiment of the present disclosure.

[0007] Figure 1F is a vertical cross-sectional view of an alternative embodiment of the exemplary structure.

[0008] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a semiconductor device, a lower interconnect dielectric layer including a silicon nitride layer, a lower metal interconnect structure, and a planar semiconductor material layer on a semiconductor substrate according to a first embodiment of the present disclosure.

[0009] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming a first-level alternating stack of a first insulating layer and a first spacer material layer according to an embodiment of the present disclosure.

[0010] Figure 4 is a vertical cross-sectional view of an exemplary structure after patterning a first-level stepped region and forming a first-level anti-step dielectric material portion on the first-level alternating stack according to an embodiment of the present disclosure.

[0011] Figure 5A is a vertical cross-sectional view of an exemplary structure after forming a first-level memory opening and a first-level support opening according to an embodiment of the present disclosure.

[0012] Figure 5B is along Figure 5A in a horizontal cross-sectional view of an exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to the plane of the Figure 5A vertical cross-sectional view.

[0013] Figure 6 is a vertical cross-sectional view of an exemplary structure after forming a sacrificial memory opening fill portion and a sacrificial support opening fill portion according to an embodiment of the present disclosure.

[0014] Figure 7A vertical cross-sectional view of an exemplary structure after forming a second hierarchical alternating stack of a second insulating layer and a second spacer material layer, a second hierarchical inverse stepped dielectric material portion, and a second insulating cap layer, according to an embodiment of the present disclosure.

[0015] Figure 8A A vertical cross-sectional view of an exemplary structure after forming an inter-level memory opening and an inter-level support opening, according to an embodiment of the present disclosure.

[0016] Figure 8B An exemplary structure along Figure 8A The horizontal cross-sectional view of the horizontal plane B-B' in. The serrated vertical plane A-A' corresponds to the plane of the Figure 8A vertical cross-sectional view.

[0017] Figure 9 A vertical cross-sectional view of an exemplary structure after forming a memory stack structure, according to an embodiment of the present disclosure.

[0018] Figure 10A-10H A sequential vertical cross-sectional view of an inter-level memory opening during the formation of a column channel portion, a memory stack structure, a dielectric core, and a drain region, according to an embodiment of the present disclosure.

[0019] Figure 11A A vertical cross-sectional view of an exemplary structure after forming a first through-stack via cavity, according to an embodiment of the present disclosure.

[0020] Figure 11B Is Figure 11A The horizontal cross-sectional view of the exemplary structure along the horizontal plane B-B' in. The serrated vertical plane A-A' corresponds to the plane of the Figure 11A vertical cross-sectional view.

[0021] Figure 12 A vertical cross-sectional view of an exemplary structure after forming a through-stack insulating material portion, according to an embodiment of the present disclosure.

[0022] Figure 13A A vertical cross-sectional view of an exemplary structure after forming a backside contact trench, according to an embodiment of the present disclosure.

[0023] Figure 13B An exemplary structure along Figure 13A The horizontal cross-sectional view of the horizontal plane B-B' in. The serrated vertical plane A-A' corresponds to the plane of the Figure 13A vertical cross-sectional view.

[0024] Figure 14AA vertical cross-sectional view of an exemplary structure after replacing a sacrificial material layer with a conductive layer and forming an insulating spacer and a backside contact via structure according to an embodiment of the present disclosure.

[0025] Figure 14B is a horizontal cross-sectional view of the exemplary structure along Figure 14A the horizontal plane B-B' in Figure 14A The sawtooth vertical plane A-A' corresponds to the plane of the

[0026] Figure 15A A vertical cross-sectional view of an exemplary structure after forming a drain contact via structure and a word line contact via structure according to an embodiment of the present disclosure.

[0027] Figure 15B is a horizontal cross-sectional view of the exemplary structure along Figure 15A the horizontal plane B-B' in Figure 15A The sawtooth vertical plane A-A' corresponds to the plane of the

[0028] Figure 16 A vertical cross-sectional view of an exemplary structure after forming a second through-stack via cavity and a through-dielectric via cavity according to an embodiment of the present disclosure.

[0029] Figure 17A A vertical cross-sectional view of an exemplary structure after forming a through-stack contact via structure and a through-dielectric contact via structure according to an embodiment of the present disclosure.

[0030] Figure 17B is Figure 17A a top view of the exemplary structure in Figure 17A The sawtooth vertical plane A-A' corresponds to the plane of the

[0031] Figure 18A A low-magnification vertical cross-sectional view of an exemplary structure after forming an upper metal interconnect structure and an upper interconnect-level dielectric layer according to an embodiment of the present disclosure.

[0032] Figure 18B is Figure 18A a medium-magnification vertical cross-sectional view of the exemplary structure of

[0033] Figure 18C is Figure 18B a high-magnification vertical cross-sectional view of a portion of the upper metal interconnect structure and the upper interconnect-level dielectric layer of

[0034] Figure 19A A vertical cross-sectional view of an exemplary structure after forming a patterned etch mask layer according to an embodiment of the present disclosure.

[0035] Figure 19BIs Figure 19A A low-magnification top view of an exemplary structure of

[0036] Figure 19C Is Figure 19A A low-magnification top view of a first alternative configuration of an exemplary structure of

[0037] Figure 19D Is Figure 19A A low-magnification top view of a second alternative configuration of an exemplary structure of

[0038] Figure 19E Illustrates Figure 19A-19D A schematic diagram of a first dicing channel configuration of an exemplary structure of

[0039] Figure 19F Illustrates Figure 19A-19D A schematic diagram of a second dicing channel configuration of an exemplary structure of

[0040] Figure 20 Is a vertical cross-sectional view of an exemplary structure after forming a dicing channel according to an embodiment of the present disclosure.

[0041] Figure 21 Is a vertical cross-sectional view of an exemplary structure after forming a continuous silicon nitride liner according to an embodiment of the present disclosure.

[0042] Figure 22 Is a vertical cross-sectional view of an exemplary structure after anisotropically etching a continuous silicon nitride liner and a backside silicon nitride passivation layer according to an embodiment of the present disclosure.

[0043] Figure 23 Is a vertical cross-sectional view of an exemplary structure after partially isotropically etching a sacrificial bonding material layer according to an embodiment of the present disclosure.

[0044] Figure 24A Is a vertical cross-sectional view of an exemplary structure after completely removing a sacrificial bonding material layer according to an embodiment of the present disclosure.

[0045] Figure 24B Is Figure 24A A high-magnification vertical cross-sectional view of an upper metal interconnect structure and a portion of an upper interconnect level dielectric layer of a semiconductor die in

[0046] Figure 25 Illustrates a processing sequence for forming a backside stress layer on a wafer according to an embodiment of the present disclosure.

[0047] Figure 26A-26C Illustrated are various configurations of patterning a backside stress layer on a semiconductor die in accordance with embodiments of the present disclosure.

[0048] Figure 27A and Figure 27B are additional configurations of patterning a backside stress layer on a semiconductor wafer in accordance with embodiments of the present disclosure.

[0049] Figure 28 is a vertical cross-sectional view of a semiconductor wafer having a front-side stress layer in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION

[0050] As discussed above, embodiments of the present disclosure relate to a method of singulating semiconductor dice using a sacrificial bonding material layer and an anisotropic channel etching process, and singulated dice formed therefrom, aspects of which are described in detail herein. Embodiments of the present disclosure provide a method of forming singulated semiconductor dice without generating mechanical stress during the singulation process, and thus, die yield and die reliability can be improved.

[0051] The drawings are not drawn to scale. In instances in which a single instance of an element is illustrated, multiple instances of the element may be replicated unless explicitly described otherwise or clearly indicated as excluding replication of the element. Like or similar elements are referred to by the same reference numeral. Elements having the same reference numeral are assumed to have the same material composition unless explicitly stated otherwise. Ordinal numbers such as “first,” “second,” and “third” are only used to identify similar elements, and different ordinal numbers may be used in the description and claims of the present disclosure. As used herein, a first element being “on” a second element may be on the outer side of the surface of the second element or on the inner side of the second element. As used herein, a first element is “directly on” a second element if there is physical contact between the surface of the first element and the surface of the second element. As used herein, a “processing” structure or a “transient” structure refers to a structure that is subsequently changed.

[0052] As used herein, a “layer” refers to a portion of material that includes a region having a thickness. A layer may extend over an entirety of a underlying or overlying structure, or may have a range less than a range of the underlying or overlying structure. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than that of the continuous structure. For example, a layer may be between a top surface and a bottom surface of a continuous structure or between any pair of horizontal planes at the top surface and the bottom surface. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above it, and / or below it.

[0053] As used herein, "memory level" or "memory array level" refers to the level of the overall region between a first horizontal plane corresponding to the top surface of an array containing memory elements (i.e., a plane parallel to the top surface of the substrate) and a second horizontal plane of the bottom surface of the array containing memory elements. As used herein, a "through-stack" element is an element that extends vertically through the memory level.

[0054] As used herein, "semiconductor material" refers to a material having a conductivity in the range from 1.0×10 -6 S / cm to 1.0×10 5 S / cm. As used herein, "semicond material" refers to a material having a conductivity in the range from 1.0×10 -6 S / cm to 1.0×10 5 S / cm in the absence of electrical dopants, and upon appropriate doping with electrical dopants, is capable of producing a doped material having a conductivity in the range from 1.0 S / cm to 1.0×10 5 S / cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / cm. As used herein, "insulating material" or "dielectric material" refers to a material having a conductivity less than 1.0×10 -6 S / cm. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with a sufficiently high atomic concentration of electrical dopants to become a conductive material (i.e., having a conductivity greater than 1.0×10 5 S / cm). A "doped semiconductor material" can be a heavily doped semiconductor material, or can be a semiconductor material containing electrical dopants (i.e., p-type dopants and / or n-type dopants) providing a conductivity in the range from 1.0×10 -6 S / cm to 1.0×10 5 S / cm. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semiconductive or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconductive or conductive, depending on the atomic concentration of electrical dopants therein. As used herein, "metal material" refers to a conductive material containing at least one metal element. All measurements of conductivity are made under standard conditions.

[0055] In a single - die three - dimensional memory array, multiple memory levels are formed above a single substrate, such as a semiconductor wafer, without an intervening substrate. The term "single - die" means that the layers of each level in the array are directly deposited on the layers of each underlying level in the array. In contrast, two - dimensional arrays can be formed separately and then packaged together to form a non - single - die memory device. For example, a non - single - die stacked memory has been constructed by forming memory levels on separate substrates and vertically stacking the memory levels, as described in U.S. Patent No. 5,915,167 entitled "Three - Dimensional Structure Memory". Before bonding, the substrates can be thinned or removed from the memory levels, but since the memory levels are initially formed on separate substrates, such a memory is not a truly single - die three - dimensional memory array. The substrate can contain integrated circuits fabricated thereon, such as driver circuits for memory devices.

[0056] A three - dimensional memory device according to various embodiments of the present disclosure includes a single - die three - dimensional NAND string memory device and can be fabricated using various embodiments described herein. The single - die three - dimensional NAND strings are located in a single - die, three - dimensional array of NAND strings located above a substrate. At least one memory cell in a first device level of the three - dimensional array of NAND strings is located above another memory cell in a second device level of the three - dimensional array of NAND strings.

[0057] Although the present disclosure describes embodiments in which each semiconductor die includes a three - dimensional memory device, various embodiments of the present disclosure can be practiced with any semiconductor chip that includes any semiconductor device known in the art. Accordingly, the methods and structures of the present disclosure are expressly contemplated for generalization to all compatible devices.

[0058] Reference Figure 1A , a carrier substrate 1110 is illustrated, which serves as a structural support element for the semiconductor layer of the substrate to be subsequently bonded thereto. The carrier substrate 1110 can include a semiconductor substrate, such as a commercially available silicon wafer, having a diameter in the range from 100 mm to 450 mm and a thickness in the range from 400 microns to 1 mm. Alternatively, the carrier substrate 1110 can include an insulating material such as sapphire and / or a conductive material such as metal. The carrier substrate 1110 is thick enough to allow mechanical handling and thermal cycling during subsequent fabrication of semiconductor dies on the semiconductor layer of the substrate. Accordingly, the carrier substrate 1110 includes materials capable of withstanding annealing at high temperatures up to 1000 degrees Celsius.

[0059] Reference Figure 1B, a sacrificial bonding material layer 1120 is formed on the front surface of the carrier substrate 1110. The sacrificial bonding material layer 1120 contains a bonding material that allows the carrier substrate 1110 to be bonded to a subsequently used substrate semiconductor layer. The sacrificial bonding material layer 1120 contains a material that can subsequently be selectively removed from the carrier substrate 1110. For example, the sacrificial bonding material layer 1120 may contain materials such as doped silicate glass, undoped silicate glass, organosilicate glass, and / or thermal silicon oxide. The sacrificial bonding material layer 1120 can be formed by deposition of the sacrificial bonding material or by oxidation of a surface portion of the carrier substrate 1110. In one embodiment, doped silicate glass (such as borosilicate glass), undoped silicate glass, or organosilicate glass can be deposited by chemical vapor deposition to form the sacrificial bonding material layer 1120. Alternatively, the carrier substrate 1110 may comprise a silicon wafer, and the sacrificial bonding material layer 1120 can be formed by thermal oxidation of the upper surface portion of the silicon wafer. In one embodiment, the sacrificial bonding material layer 1120 may contain a silicon oxide-based material that can be etched by hydrofluoric acid, sodium peroxide, hydrogen peroxide, or a combination or mixture thereof. In one embodiment, the sacrificial bonding material layer 1120 may have a uniform thickness in the range from 5 microns to 20 microns, although smaller or larger thicknesses can also be used. The uniform thickness of the sacrificial bonding material layer 1120 is referred to herein as the first thickness.

[0060] Reference Figure 1C , a backside silicon nitride passivation layer 1130 may optionally be formed on the top surface of the sacrificial bonding material layer 1120. The backside silicon nitride passivation layer 1130 is also referred to as the silicon nitride passivation layer. The backside silicon nitride passivation layer 1130 can be formed by depositing silicon nitride by chemical vapor deposition. The backside silicon nitride passivation layer 1130 is an intermediate dielectric material layer that is disposed between the sacrificial bonding material layer 1120 and a subsequently used substrate semiconductor layer. The thickness of the backside silicon nitride passivation layer 1130 can be in the range from 200 nm to 2000 nm, although smaller or larger thicknesses can also be used. The backside silicon nitride passivation layer 1130 can be used to assist in a subsequently used substrate bonding process and to minimize warping of the composite substrate and the bare die to be subsequently formed.

[0061] Reference Figure 1D , a substrate semiconductor layer 9 is provided, which contains a single crystal semiconductor material such as single crystal silicon. The thickness of the substrate semiconductor layer 9 can be in the range from 200 nm to 10 microns, although smaller or larger thicknesses can also be used. The thickness of the substrate semiconductor layer 9 is referred to herein as the second thickness. The substrate semiconductor layer 9 can have approximately the same lateral extent as the carrier substrate 1110.

[0062] In one embodiment, a substrate semiconductor layer 9 may be provided within a source substrate (9, 609, 611) that includes a stack of the substrate semiconductor layer 9, a buried hydrogen separation layer 609, and a matrix semiconductor material layer 611. The source substrate (9, 609, 611) may be formed by providing a commercial semiconductor wafer such as a single crystal silicon wafer and implanting hydrogen atoms from one side of the single crystal silicon wafer. The implanted hydrogen atoms form the buried hydrogen separation layer 609, the proximal portion of the semiconductor wafer on the ion implantation side constitutes the substrate semiconductor layer 9, and the distal portion of the semiconductor wafer on the opposite side of the ion implantation side constitutes the matrix semiconductor material layer 611.

[0063] The source semiconductor substrate (9, 609, 611) may be bonded to the front side of the sacrificial bonding material layer 1120. Specifically, the substrate semiconductor layer 9 may be bonded directly (if the backside silicon nitride passivation layer 1130 is absent) or through the backside silicon nitride passivation layer 1130 to the sacrificial bonding material layer 1120. Optionally, at least one surface bonding assist layer may be formed on the physically exposed surface of the backside silicon nitride passivation layer 1130 and / or on the physically exposed surface of the substrate semiconductor layer 9.

[0064] Reference Figure 1E , the matrix semiconductor material layer 611 (i.e., the distal portion of the source semiconductor substrate (9, 609, 611)) may be separated from the sacrificial bonding material layer 1120 by cleaving the source semiconductor substrate 9 at the buried hydrogen implantation layer 609. In one embodiment, annealing at a high temperature in the range from 200 degrees to 500 degrees may be used to separate the matrix semiconductor material layer 611 from the substrate semiconductor layer 9. The substrate semiconductor layer 9 is the remaining proximal portion of the source semiconductor substrate (9, 609, 611) attached to the sacrificial bonding material layer 1120. The substrate semiconductor layer 9 is attached to the front side of the sacrificial bonding material layer 1120, i.e., the side not in contact with the carrier substrate 1110. A compound substrate 8 is provided that includes the carrier substrate 1110, the sacrificial bonding material layer 1120, an optional backside silicon nitride passivation layer 1130, and the substrate semiconductor layer 9.

[0065] Reference Figure 1F , an alternative embodiment of an exemplary structure is illustrated that may be formed from Figure 1EExemplary structure derivatives. At least one additional intermediate dielectric material layer (1131, 901) may include a carrier-side intermediate dielectric material layer 1131 and / or a device-side intermediate dielectric material layer 901. The carrier-side intermediate dielectric material layer 1131 may be formed on the back-side silicon nitride passivation layer 1130, and / or the device-side intermediate dielectric material layer 901 may be formed on the surface of the substrate semiconductor layer 9. In one embodiment, the carrier-side intermediate dielectric material layer 1131 and / or the device-side intermediate dielectric material layer 901 may include a corresponding silicon oxide layer having a thickness that may range from 100 nm to 1000 nm. In some embodiments, the bonding between the back-side silicon nitride passivation layer 1130 (or the sacrificial bonding material layer 1120) and the substrate semiconductor layer 9 may be facilitated by the carrier-side intermediate dielectric material layer 1131 and / or the device-side intermediate dielectric material layer 901. In one embodiment, the bonding between the carrier substrate 1110 and the substrate semiconductor layer 9 may use an oxide-to-oxide bonding between the device-side intermediate dielectric material layer 901 and the carrier-side intermediate dielectric material layer 1131.

[0066] Reference Figure 2 , a semiconductor device 710 may be formed on a substrate semiconductor layer 9 in a composite substrate 8. Shallow trench isolation structures 720 may be formed in an upper portion of the substrate semiconductor layer 9 to provide electrical isolation between semiconductor devices. The semiconductor device 710 may include, for example, a field effect transistor that includes corresponding transistor active regions 742 (i.e., source regions and drain regions), a channel region 746, and a gate structure 750. The field effect transistors may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, dielectric gate spacers 756, and a gate cap dielectric 758. The semiconductor device may include any semiconductor circuit to support the operation of a memory structure to be subsequently formed, which is typically referred to as a driver circuit and is also known as a peripheral circuit. As used herein, a peripheral circuit refers to any, each, or all of a word line decoder circuit, a word line switching circuit, a bit line decoder circuit, a bit line sensing and / or switching circuit, a power supply / distribution circuit, a data buffer and / or latch, or any other semiconductor circuit that can be implemented outside of the memory array structure of a memory device. For example, the semiconductor device may include a word line switching device to electrically bias the word lines of a three-dimensional memory structure to be subsequently formed.

[0067] A dielectric material layer is formed over the semiconductor device, which is referred to herein as the lower interconnect level dielectric layer 760. The lower interconnect level dielectric layer 760 constitutes a dielectric layer stack, where each lower interconnect level dielectric layer 760 is above or below other lower interconnect level dielectric layers 760. The lower interconnect level dielectric layer 760 may include, for example, a dielectric liner 762 such as silicon nitride liner that blocks the diffusion of mobile ions and / or applies appropriate stress to the underlying structure, at least one first dielectric material layer 764 over the dielectric liner 762, a silicon nitride layer (e.g., hydrogen diffusion barrier) 766 over the dielectric material layer 764, and at least one second dielectric layer 768.

[0068] The dielectric layer stack including the lower interconnect level dielectric layer 760 functions as a substrate for the lower metal interconnect structure 780, which provides electrical wiring between various nodes of the semiconductor device and the landing pads for the through-stack contact via structures to be formed subsequently. The lower metal interconnect structure 780 is included within the dielectric layer stack of the lower interconnect level dielectric layer 760 and includes a lower metal line structure that is located beneath the bottom surface of the silicon nitride layer 766 and optionally contacts the bottom surface of the silicon nitride layer 766.

[0069] For example, the lower metal interconnect structure 780 may be included within at least one first dielectric material layer 764. The at least one first dielectric material layer 764 may be a plurality of dielectric material layers, where various components of the lower metal interconnect structure 780 are sequentially included. Each dielectric material layer among the at least one first dielectric material layer 764 may include any material such as doped silicate glass, undoped silicate glass, organosilicate glass, silicon nitride, silicon oxynitride, and dielectric metal oxides (such as aluminum oxide). In one embodiment, the at least one first dielectric material layer 764 may include or consist essentially of a dielectric material layer having a dielectric constant not exceeding 3.9, the dielectric constant of undoped silicate glass (silicon oxide).

[0070] The lower metal interconnect structure 780 may include various device contact via structures 782 (e.g., source electrodes and drain electrodes that contact the corresponding source and drain nodes of the device or gate electrode contacts), intermediate lower metal line structures 784, lower metal via structures 786, and a topmost lower metal line structure 788 that is configured to function as a landing pad for the through-stack contact via structures to be formed subsequently. In this case, the at least one first dielectric material layer 764 may be a plurality of dielectric material layers that integrate the components of the lower metal interconnect structure 780 within each corresponding level while being formed layer by layer.

[0071] The topmost lower metal line structure 788 may be formed within the topmost dielectric material layer of at least one first dielectric material layer 764 (which may be a plurality of dielectric material layers). Each of the lower metal interconnect structures 780 may include a metal nitride liner 78A and a metal fill portion 78B. Each metal nitride liner 78A may include a conductive metal nitride material such as TiN, TaN, and / or WN. Each metal fill portion 78B may include a elemental metal (such as Cu, W, Al, Co, Ru) or an intermetallic alloy of at least two metals. The top surface of the topmost lower metal line structure 788 and the top surface of at least one first dielectric material layer 764 may be planarized by a planarization process such as chemical mechanical planarization. In this case, the top surface of the topmost lower metal line structure 788 and the top surface of at least one first dielectric material layer 764 may be in a horizontal plane parallel to the top surface of the substrate 8.

[0072] The silicon nitride layer 766 may be formed directly on the top surface of the topmost lower metal line structure 788 and the top surface of at least one first dielectric material layer 764. At least one second dielectric material layer 768 may include a single dielectric material layer or a plurality of dielectric material layers. Each dielectric material layer among the at least one second dielectric material layer 768 may include any material among doped silicate glass, undoped silicate glass, and organic silicate glass.

[0073] Optional metal material layers and semiconductor material layers may be deposited on or within the patterned recesses of at least one second dielectric material layer 768 and patterned lithographically to provide an optional planar conductive material layer 6 and a planar semiconductor material layer 10. The optional planar conductive material layer 6, for example, may include a tungsten layer, the thickness of the tungsten layer may be in the range from 3 nm to 100 nm, although smaller or larger thicknesses may also be used. A metal nitride layer (not shown) may be provided as a diffusion barrier layer on top of the planar conductive material layer 6. Layer 6 may function as a particular source line in the completed device. Alternatively, layer 6 may include an etch stop layer and may include any suitable conductive, semiconductor, or insulating layer.

[0074] The planar semiconductor material layer 10 may include horizontal semiconductor channels and / or source regions of a three-dimensional array of memory devices to be subsequently formed. The optional planar conductive material layer 6 may include a metal compound material such as a conductive metal nitride (e.g., TiN) and / or a metal (e.g., W). The thickness of the optional planar conductive material layer 6 may range from 5 nm to 100 nm, although smaller or larger thicknesses may also be used. The planar semiconductor material layer 10 includes a polycrystalline semiconductor material such as polysilicon or a polysilicon-germanium alloy. The thickness of the planar semiconductor material layer 10 may range from 30 nm to 300 nm, although smaller or larger thicknesses may also be used. In one embodiment, the planar semiconductor material layer 10 or a portion thereof may be doped with an electrical dopant, which may be a p-type dopant or an n-type dopant. The conductivity type of the dopant in the planar semiconductor material layer 10 is referred to herein as the first conductivity type. The optional planar conductive material layer 6 and the planar semiconductor material layer 10 may be patterned to provide openings in regions where through-stack contact via structures and through-dielectric contact via structures are to be subsequently formed.

[0075] The region of the combination of the semiconductor device 710 and the lower interconnect level dielectric layer 760 and the lower metal interconnect structure 780 is referred to herein as the underlying peripheral device region 700, which is located below the memory level components to be subsequently formed and includes the peripheral devices of the memory level components. The lower metal interconnect structure 780 is included in the lower interconnect level dielectric layer 760.

[0076] Reference Figure 3 , a first material layer and a second material layer are subsequently formed in an alternating stack. Each first material layer may include a first material, and each second material layer may include a second material different from the first material. In the case where at least another alternating stack of material layers is subsequently formed over the alternating stack of the first material layer and the second material layer, the alternating stack is referred to herein as the first level alternating stack. The level of the first level alternating stack is referred to herein as the first level, and the level of the alternating stack to be subsequently formed adjacent and above the first level is referred to herein as the second level, and so on.

[0077] In one embodiment, the first material layer and the second material layer may be the first insulating layer 132 and the first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may comprise a first insulating material, and each first sacrificial material layer 142 may comprise a first sacrificial material. A plurality of alternating first insulating layers 132 and first sacrificial material layers 142 are formed over the planar semiconductor material layer 10. As used herein, a "sacrificial material" refers to a material that is removed during subsequent processing steps. As used herein, an alternating stack of a first element and a second element refers to a structure in which instances of the first element and instances of the second element alternate. In one embodiment, instances of the first element and instances of the second element may form cells, which are repeated periodically in the alternating multiplicity.

[0078] The second material of the first sacrificial material layer 142 is a sacrificial material that can be selectively removed relative to the first material of the first insulating layer 132. As used herein, if a removal process removes the first material at a rate that is at least twice the rate of removing the second material, the removal of the first material is "selective" "with respect to" the second material. The ratio of the rate of removing the first material to the rate of removing the second material is referred to herein as the "selectivity" of the removal process of the first material with respect to the second material. In one embodiment, the first insulating layer 132 may comprise silicon oxide, and the sacrificial material layer may comprise a silicon nitride sacrificial material layer.

[0079] The thicknesses of the first insulating layer 132 and the first sacrificial material layer 142 may range from 20 nm to 50 nm, although smaller or larger thicknesses may be used for each first insulating layer 132 and for each first sacrificial material layer 142. The number of repetitions of pairs of the first insulating layer 132 and the first sacrificial material layer 142 may range from 2 to 1024, and typically from 8 to 256, although smaller or larger numbers of repetitions may be used. In one embodiment, each first sacrificial material layer 142 in the first hierarchical alternating stack (132, 142) may have a uniform thickness that is substantially constant within each respective first sacrificial material layer 142.

[0080] A first insulating capping layer 170 is then formed over the stack (132, 142). The first insulating capping layer 170 comprises a dielectric material, which may be any dielectric material capable of being used for the first insulating layer 132. In one embodiment, the first insulating capping layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the insulating capping layer 170 may range from 20 nm to 300 nm, although smaller or larger thicknesses may also be used.

[0081] Reference Figure 4, the first insulating cap layer 170 and the first hierarchical alternating stack (132, 142) can be patterned to form a first stepped surface in the word line contact via region 200. The word line contact via region 200 can include a corresponding first stepped region in which the first stepped surface is formed, and a second stepped region in which additional stepped surfaces are to be formed subsequently in a second hierarchical structure (to be formed subsequently on top of the first hierarchical structure) and / or additional hierarchical structures. A dielectric material can be deposited to fill the first stepped cavity to form a first hierarchical anti-stepped dielectric material portion 165. As used herein, an "anti-stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases as a function of the vertical distance from the top surface of the elements existing above the substrate. The first hierarchical alternating stack (132, 142) and the first hierarchical anti-stepped dielectric material portion 165 collectively constitute the first hierarchical structure, which is a structure in the process to be subsequently modified.

[0082] Reference Figure 5A and Figure 5B , an inter-level dielectric layer 180 can optionally be deposited on top of the first hierarchical structure (132, 142, 165, 170). The inter-level dielectric layer 180 includes a dielectric material such as silicon oxide. The thickness of the inter-level dielectric layer 180 can range from 30 nm to 300 nm, although smaller or larger thicknesses can also be used. The position of the step S in the first hierarchical alternating stack (132, 142) is illustrated as a dotted line.

[0083] A first hierarchical memory opening 149 and a first hierarchical support opening 119 can be formed. The first hierarchical memory opening 149 and the first hierarchical support opening 119 extend through the first hierarchical alternating stack (132, 142) at least to the top surface of the planar semiconductor material layer 10. The first hierarchical memory opening 149 can be formed in the memory array region 100 at a position where a memory stack structure including a vertical stack of memory elements is to be subsequently formed. The first hierarchical support opening 119 can be formed in the word line contact via region 200. Optionally, the portions of the first hierarchical memory opening 149 and the first hierarchical support opening 119 at the level of the inter-level dielectric layer 180 can be laterally extended by isotropic etching.

[0084] Reference Figure 6, a sacrificial memory opening fill portion 148 may be formed in the first-level memory opening 149, and a sacrificial support opening fill portion 118 may be formed in the first-level support opening 119. For example, a sacrificial fill material layer is deposited in the first-level memory opening 149 and the first-level support opening 119. The sacrificial fill material layer includes a sacrificial material that is subsequently selectively removed with respect to the materials of the first insulator layer 132 and the first sacrificial material layer 142. In one embodiment, the sacrificial fill material layer may include amorphous silicon or a carbon-containing material (such as amorphous carbon or diamond-like carbon), which may subsequently be removed by ashing.

[0085] Portions of the deposited sacrificial material may be removed from above the first insulating cap layer 170 (and optional inter-level dielectric layer 180, if present). Each remaining portion of the sacrificial material in the first-level memory opening 149 constitutes a sacrificial memory opening fill portion 148. Each remaining portion of the sacrificial material in the first-level support opening 119 constitutes a sacrificial support opening fill portion 118.

[0086] Reference Figure 7 , a second-level structure may be formed over the first-level structure (132, 142, 170, 148, 118). The second-level structure may include an additional alternating stack of an insulating layer and a spacer material layer (which may be a sacrificial material layer). In one embodiment, each second insulator layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second stack (232, 242) may include a plurality of alternating second insulator layers 232 and second sacrificial material layers 242. The sacrificial material that can be used for the second sacrificial material layer 242 may be any material that can be used for the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

[0087] The thickness of the second insulator layer 232 and the second sacrificial material layer 242 may be in the range from 20 nm to 50 nm, although smaller or larger thicknesses may be used for each second insulator layer 232 and for each second sacrificial material layer 242. The number of repetitions of the pairs of the second insulator layer 232 and the second sacrificial material layer 242 may be in the range from 2 to 1024, and typically from 8 to 256, although smaller or larger numbers of repetitions may be used.

[0088] With the pattern of at least one mask layer being appropriately adjusted, the same set of processing steps used to form the first stepped surface in the first stepped region can be used to form the second stepped surface in the second stepped region in the word line contact via region 200. The second hierarchical inverse stepped dielectric material portion 265 can be formed over the second stepped surface in the word line contact via region 200. The second insulating cap layer 270 can then be formed over the second alternating stack (232, 242). Generally, at least one alternating stack of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be formed over the planar semiconductor material layer 10, and at least one inverse stepped dielectric material portion (165, 265) can be formed over the stepped regions on the at least one alternating stack (132, 142, 232, 242). Optionally, the drain select level shallow trench isolation structure 72 can be formed to pass through a subset of the upper portions of the second hierarchical alternating stack (232, 242).

[0089] Reference Figure 8A and Figure 8B , the second hierarchical memory opening 249 and the second hierarchical support opening 219 extending through the second hierarchical structure (232, 242, 270, 265) are formed in the region above the sacrificial memory opening fill portion 148. The top surface of the underlying sacrificial memory opening fill portion 148 can be physically exposed at the bottom of each second hierarchical memory opening 249. The top surface of the underlying sacrificial support opening fill portion 118 can be physically exposed at the bottom of each second hierarchical support opening 219. After the top surfaces of the sacrificial memory opening fill portion 148 and the sacrificial support opening fill portion 118 are physically exposed, an etching process can be performed to selectively remove the sacrificial materials of the sacrificial memory opening fill portion 148 and the sacrificial support opening fill portion 118 from the materials of the second hierarchical alternating stack (232, 242) and the first hierarchical alternating stack (132, 142).

[0090] Once the sacrificial memory opening fill portion 148 is removed, each vertically adjacent pair of the second-level memory openings 249 and the first-level memory openings 149 forms a continuous cavity that extends through the first-level alternating stack (132, 142) and the second-level alternating stack (232, 242). Similarly, once the sacrificial support opening fill portion 118 is removed, each vertically adjacent pair of the second-level support openings 219 and the first-level support openings 119 forms a continuous cavity that extends through the first-level alternating stack (132, 142) and the second-level alternating stack (232, 242). The continuous cavities are referred to herein as memory openings (or inter-level memory openings) and support openings (or inter-level support openings), respectively. The top surface of the planar semiconductor material layer 10 can be physically exposed at the bottom of each memory opening and at the bottom of each support opening.

[0091] Reference Figure 9 , a memory opening fill structure 58 is formed in each memory opening, and a support pillar structure 20 is formed in each support opening. The memory opening fill structure 58 and the support pillar structure 20 can comprise the same set of components and can be formed simultaneously.

[0092] Figure 10A-10H Sequential cross-sectional views of the memory opening 49 or the support openings (119, 219) are provided during the formation of the memory opening fill structure 58 or the support pillar structure 20. Although structural changes in the memory opening 49 are illustrated in Figure 10A-10H , it should be understood that the same structural changes occur in each memory opening 49 and in each of the support openings (119, 219) during the same set of processing steps.

[0093] Reference Figure 10A , the memory opening 49 in the exemplary device structure of FIG. 14 is illustrated. The memory opening 49 extends through the first-level structure and the second-level structure. Similarly, each support opening (119, 219) extends through the first-level structure and the second-level structure.

[0094] Reference Figure 10B , an optional pedestal channel portion (e.g., an epitaxial pedestal) 11 can be formed, for example, by a selective semiconductor deposition process at the bottom portion of each memory opening 49 and each support opening (119, 219). A cavity 49' exists in the unfilled portion of the memory opening 49 (or the support opening) above the pedestal channel portion 11. In one embodiment, the pedestal channel portion 11 can have the same doping as the conductivity type of the planar semiconductor material layer 10.

[0095] Reference Figure 10C, a stack of layers including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and an optional first semiconductor channel layer 601 can be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 can include a single dielectric material layer or a stack of multiple dielectric material layers. The charge storage layer 54 can be a continuous layer or a patterned discrete portion of a charge trapping material, and the charge trapping material includes a dielectric charge trapping material, which can be, for example, silicon nitride. The tunneling dielectric layer 56 includes a dielectric material, and charge tunneling can occur through the dielectric material under appropriate electrical bias conditions. Charge tunneling can be carried out by hot carrier injection or by charge transfer induced by Fowler-Nordheim tunneling, depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed. The optional first semiconductor channel layer 601 includes a semiconductor material. A cavity 49' is formed within the volume of the unfilled deposited material layers (52, 54, 56, 601) in each memory opening 49.

[0096] Reference Figure 10D , using at least one anisotropic etching process, the optional first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 are sequentially anisotropically etched. Each remaining portion of the first semiconductor channel layer 601 can have a tubular configuration. The collection of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 in the memory opening 49 constitutes a memory film 50, which includes a plurality of charge storage regions (including the charge storage layer 54) insulated from the surrounding materials by the blocking dielectric layer 52 and the tunneling dielectric layer 56.

[0097] Reference Figure 10E , the second semiconductor channel layer 602 can be directly deposited on the semiconductor surface of the base channel portion 11, or directly deposited on the semiconductor material layer 10 if the base channel portion 11 is omitted, and directly deposited on the first semiconductor channel layer 601. The second semiconductor channel layer 602 includes a semiconductor material. The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as semiconductor channel materials.

[0098] Reference Figure 10F , in the case where the cavity 49' in each memory opening is not completely filled by the second semiconductor channel layer 602, a dielectric core layer 62L can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer 62L includes a dielectric material, such as silicon oxide or organosilicate glass.

[0099] Reference Figure 10G, the horizontal portion of the dielectric core layer 62L can be removed above the top surface of the second insulating capping layer 270, for example, by recess etching. Each remaining portion of the dielectric core layer 62L constitutes a dielectric core 62. Each adjacent pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60. Each adjacent set of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 collectively constitutes a memory film 50, which is capable of storing charge with a macroscopic retention time. As used herein, the macroscopic retention time refers to the retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0100] Reference Figure 10H , the top surface of each dielectric core 62 can be further recessed, for example, by recess etching, within each memory opening to a depth located between the top surface and the bottom surface of the second insulating capping layer 270. A drain region 63 can be formed by depositing a doped semiconductor material within each recessed region above the dielectric core 62. The drain region 63 can be doped with a second conductivity type opposite to the first conductivity type. Each combination of the memory film 50 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) within the memory opening 49 constitutes a memory stack structure 55. Each combination of the base channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Each combination of the base channel portion 11 (if present), the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening (119, 219) fills the corresponding support opening (119, 219) and constitutes a support pillar structure 20.

[0101] The first hierarchical structure (132, 142, 170, 165), the second hierarchical structure (232, 242, 270, 265), the inter-level dielectric layer 180, the memory opening fill structure 58, and the support pillar structure 20 collectively constitute a memory-level component. The memory-level component is formed on the planar semiconductor material layer 10 such that the planar semiconductor material layer 10 includes a horizontal semiconductor channel electrically connected to the vertical semiconductor channel 60 within the memory stack structure 55.

[0102] Reference Figure 11A and Figure 11B , a first contact-level dielectric layer 280 can be formed on the memory-level component. The first contact-level dielectric layer 280 is formed at the contact level and then various contact via structures are formed through the contact level to the drain region 63 and various conductive layers that replace the sacrificial material layers (142, 242) in subsequent processing steps.

[0103] For example, by applying and patterning a photoresist layer to form an opening therein, and by anisotropically etching portions of the first contact-level dielectric layer 280, the alternating stack (132, 146, 232, 246), and at least one second dielectric material layer 768 that are below the opening in the photoresist layer, the first through-stack via cavity 585 can be formed in the memory array region 100. In one embodiment, each of the first through-stack via cavities 585 can be formed within a corresponding three-dimensional memory array such that each first through-stack via cavity 585 is laterally surrounded by the memory opening fill structure 58. The bottom surface of each first through-stack via cavity 585 can be formed at or above the silicon nitride layer 766.

[0104] Reference Figure 12 , a dielectric material is deposited in the first through-stack via cavity 585. The dielectric material can comprise a silicon oxide-based material such as undoped silicate glass, doped silicate glass, or a flowable oxide material. The dielectric material can be deposited by a conformal deposition method such as chemical vapor deposition or spin coating. The excess of the deposited dielectric material can be removed from above a horizontal plane that includes the top surface of the first contact-level dielectric layer 280. Each remaining dielectric material portion that fills a corresponding one of the first through-stack via cavities 585 constitutes a through-stack insulating material portion 584.

[0105] Reference Figure 13A and Figure 13B , the backside contact trench 79 is then formed to extend through the first contact-level dielectric layer 280 and the memory-level components. For example, a photoresist layer can be applied over the first contact-level dielectric layer 280 and lithographically patterned to form a narrow opening that extends along a first horizontal direction hd1. An anisotropic etch is performed to transfer the pattern in the patterned photoresist layer through the first contact-level dielectric layer 280 and the memory-level components to the top surface of the planar semiconductor material layer 10. The photoresist layer can then be removed, for example, by ashing.

[0106] The backside contact trench 79 extends along the first horizontal direction hd1 and is thus narrow along the first horizontal direction hd1. The backside contact trenches 79 can be laterally spaced from each other along a second horizontal direction hd2 that can be perpendicular to the first horizontal direction hd1. The backside contact trenches 79 can extend through the memory array region (e.g., memory plane) 100 and the word line contact via region 200. A first subset of the backside contact trenches 79 laterally divides the memory-level components (e.g., into memory blocks).

[0107] Reference Figure 14A and Figure 14B, the material of the first and second sacrificial material layers (142, 242) can be selectively etched by introducing an etchant for the materials of the first and second insulating layers (132, 232), the first and second insulating capping layers (170, 270), and the outermost layer of the memory film 50, for example, using an isotropic etching process, into the backside contact trench 79. A first backside recess is formed in the volume from which the first sacrificial material layer 142 is removed. A second backside recess is formed in the volume from which the second sacrificial material layer 242 is removed. The isotropic etching process can be a wet etching process using a wet etching solution or can be a vapor phase (dry) etching process in which the etchant is introduced into the backside contact trench 79 in a vapor phase.

[0108] A plurality of first backside recesses can be formed in the volume from which the material of the first sacrificial material layer 142 is removed. A plurality of second backside recesses can be formed in the volume from which the material of the second sacrificial material layer 242 is removed. In one embodiment, after removing the first and second sacrificial material layers (142, 242), the sidewall surfaces of each pedestal channel portion 11 can be physically exposed at each bottommost first backside recess. Additionally, the top surface of the planar semiconductor material layer 10 can be physically exposed at the bottom of each backside contact trench 79. An annular dielectric spacer (not shown) can be formed around each pedestal channel portion 11 by oxidizing the physically exposed peripheral portions of the pedestal channel portion 11. Additionally, a semiconductor oxide portion (not shown) can be formed from each physically exposed surface portion of the planar semiconductor material layer 10 simultaneously with the formation of the annular dielectric spacer.

[0109] A backside blocking dielectric layer (not shown) can optionally be deposited in the backside recesses and the backside contact trench 79 and on top of the first contact level dielectric layer 280. At least one conductive material can be deposited in the plurality of backside recesses, on the sidewalls of the backside contact trench 79, and on top of the first contact level dielectric layer 280. The at least one conductive material can comprise at least one metal material, i.e., a conductive material comprising at least one metal element. A plurality of first conductive layers 146 can be formed in the plurality of first backside recesses, and a plurality of second conductive layers 246 can be formed in the plurality of second backside recesses. A continuous metal material layer (not shown) formed on the sidewalls of each backside contact trench 79 and on top of the first contact level dielectric layer 280 can be removed by recess etching.

[0110] Each of the memory stack structures 55 includes a vertical stack of memory elements at each level of the conductive layers (146, 246). A subset of the conductive layers (146, 246) may include word lines of the memory elements. The semiconductor devices in the underlying peripheral device region 700 may include word line switching devices configured to control the biasing of the corresponding word lines. The memory level assembly is located above the substrate semiconductor layer 9. The memory level assembly includes at least one alternating stack (132, 146, 232, 246) and the memory stack structures 55 that extend vertically through at least one alternating stack (132, 146, 232, 246). Each of the at least one alternating stack (132, 146, 232, 246) includes an alternating layer of a corresponding insulating layer (132 or 232) and a corresponding conductive layer (146 or 246). The at least one alternating stack (132, 146, 232, 246) includes a stepped region that includes a stepped platform, where each underlying conductive layer (146, 246) in the stepped platform extends further in a first horizontal direction hd1 than any upper conductive layer (146, 246) in the memory level assembly.

[0111] Dopants of a second conductivity type (opposite to the first conductivity type of the planar semiconductor material layer 10) may be implanted into the surface portion of the planar semiconductor material layer 10 to form source regions 61 below the bottom surface of each backside contact trench 79. Insulating spacers 74 including dielectric materials may be formed at the periphery of each backside contact trench 79, for example, by depositing a conformal insulating material such as silicon oxide and subsequent anisotropic etching. Backside contact via structures 76 may be formed in the remaining volume of each backside contact trench 79.

[0112] Reference Figure 15A and Figure 15B , a second contact level dielectric layer 282 may optionally be formed above the first contact level dielectric layer 280. The drain contact via structure 88 of the contact drain region 63 may extend through the contact level dielectric layers (280, 282) and the second insulating capping layer 270 in the memory array region 100. The source connection via structure 91 may extend through the contact level dielectric layers (280, 282) to provide an electrical connection to the laterally elongated contact via structure 76.

[0113] Various contact via structures can be formed to pass through the contact-level dielectric layers (280, 282) and the anti-step dielectric material portions (165, 265). For example, the word line contact via structure 86 can be formed in the word line contact region 200. A subset of the word line contact via structure 86 that contacts the second conductive layer 246 extends through the second-level anti-step dielectric material portion 265 in the word line contact region 200 and does not extend through the first-level anti-step dielectric material portion 165. Another subset of the word line contact via structure 86 that contacts the first conductive layer 146 extends through the second-level anti-step dielectric material portion 265 and through the first-level anti-step dielectric material portion 165 in the word line contact region 200.

[0114] Reference Figure 16 , a photoresist layer is applied over the second contact-level dielectric layer 282 and lithographically patterned to form openings over the through-stack insulator portions 584 in the memory array region 100, as well as additional memory openings in which there are no layers of the alternating stacks (132, 146, 232, 246), i.e., in the peripheral region 400 located outside the memory array region 100 and the contact region 200.

[0115] Via cavities (487, 587) are formed by an anisotropic etching process that transfers the pattern of the openings in the photoresist layer to the top surface of the topmost underlying metal line structure 788. For example, the through-stack via cavity 587 is formed to pass through the through-stack insulator portion 584 such that the remaining portion of each through-stack insulator portion 584 constitutes a through-stack insulating spacer 586 after the through-stack via cavity 587 is formed. Additionally, the through-dielectric via cavity 487 can be formed in the peripheral region, passing through the contact-level dielectric layers (280, 282), the anti-step dielectric material portions (165, 265), at least one second dielectric material layer 768, and the silicon nitride layer 766, to the top surface of a corresponding one of the topmost underlying metal pad structures 788.

[0116] Reference Figure 17A and Figure 17B, at least one conductive material can be simultaneously deposited in the through-stack via cavity 587 and the through-dielectric via cavity 487. The excess portion of the at least one conductive material can be removed from outside the through-stack via cavity 587 and the through-dielectric via cavity 487. Each remaining portion of the at least one conductive material in the through-stack via cavity 587 constitutes a through-stack contact via structure 588 that contacts the top surface of a corresponding one of the topmost lower metal line structures 788. Each remaining portion of the at least one conductive material in the through-dielectric via cavity 487 that contacts the top surface of a corresponding one of the topmost lower metal line structures 788 constitutes a through-dielectric contact via structure 488.

[0117] Reference Figure 18A and Figure 18B , at least one upper interconnect-level dielectric layer 284 can be formed over the contact-level dielectric layers (280, 282). Various upper interconnect-level metal interconnect structures can be formed in the at least one upper interconnect-level dielectric layer 284. For example, the various upper interconnect-level metal interconnect structures can include line-level metal interconnect structures (96, 98, 99). The line-level metal interconnect structures (96, 98, 99) can include a first upper metal line structure 99 that contacts the top surface of a corresponding one of the through-stack contact via structures 588, a second upper metal line structure 96 that contacts the top surface of a corresponding one of the through-dielectric contact via structures 488, and bit lines 98 that contact a corresponding one of the drain contact via structures 88 and extend along a second horizontal direction (e.g., the bit line direction) hd2 and perpendicular to a first horizontal direction (e.g., the word line direction) hd1.

[0118] At least a subset of the upper metal interconnect structures (which include the line-level metal interconnect structures (96, 98, 99)) are formed over the three-dimensional memory array. The upper metal interconnect structures include upper metal line structures (such as the first upper metal line structure 99) formed directly on the through-stack contact via structures 588.

[0119] In one embodiment, the memory stack structure 55 may include memory elements of a vertical NAND device. The conductive layers (146, 246) may include or may be electrically connected to corresponding word lines of the vertical NAND device. The substrate 8 may include a silicon substrate. The vertical NAND device may include an array of monolithic three-dimensional NAND strings over the silicon substrate. At least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located above another memory cell in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate may contain integrated circuits, including word line driver circuits and bit line driver circuits of the memory device. The array of monolithic three-dimensional NAND strings may include a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels (such as the vertical semiconductor channel 60) extends substantially perpendicular to the top surface of the composite substrate 8, a plurality of charge storage elements (including portions of the memory material layer 54 located at each word line level), each charge storage element located adjacent to a corresponding one of the plurality of semiconductor channels (59, 11, 60), and a plurality of control gate electrodes (including a subset of the conductive layers (146, 246) having a strip shape extending substantially parallel to the top surface of the substrate 8 (e.g., along a first horizontal direction hd1)), the plurality of control gate electrodes including at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

[0120] Reference Figure 18A-18C, an upper dielectric material layer 380 may be formed over at least one upper interconnect level dielectric layer 284. The upper dielectric material layer 380 may include an additional upper interconnect level dielectric layer 382 containing upper metal interconnect structures 388, a capping silicon nitride passivation layer 384 containing openings in which metal contact pads 392 are located, and a sacrificial capping silicon oxide layer 386 over the capping silicon nitride passivation layer 384. The upper metal interconnect structures 388 may be electrically connected to various nodes of the underlying three-dimensional memory array and / or various nodes of the semiconductor device 710. The metal contact pads 392 may be included in the topmost layer of the additional upper interconnect level dielectric layer 382. The capping silicon nitride passivation layer 384 and the metal contact pads 392 may collectively form a continuous structure that covers the entire area of the exemplary structure. The capping silicon nitride passivation layer may laterally surround the upper portions of each of the metal contact pads 392, or may contact the top surface of the metal contact pads 392 having openings therethrough, such that the metal contact pads 392 may subsequently be bonded to corresponding bonding structures, such as solder balls or bonding wires. The thickness of the capping silicon nitride passivation layer 384 may be in the range from 100 nm to 500 nm, although smaller or larger thicknesses may also be used. The sacrificial capping silicon oxide layer 386 is optional and may include silicon oxide material for temporarily protecting the capping silicon nitride passivation layer 384. The sacrificial capping silicon oxide layer 386 includes silicon oxide and may have a thickness in the range from 1 micron to 5 microns. In one embodiment, the sacrificial capping silicon oxide layer 386 may have a higher etching rate in dilute hydrofluoric acid than the material of the sacrificial bonding material layer 1120. For example, the sacrificial bonding material layer 1120 may include borosilicate glass, and the sacrificial capping silicon oxide layer 386 may include undoped silicate glass.

[0121] The exemplary structure includes a plurality of semiconductor dice 1000 between the sacrificial bonding material layer 1120 and the topmost surface of the upper dielectric material layer 380. The plurality of semiconductor dice are included within various continuous material layers (380, 284, 282, 280, 180, 760) located on the front side of the substrate semiconductor layer 9. Each of the continuous material layers (380, 284, 282, 280, 180, 760) extends continuously over the area of the plurality of semiconductor dice 1000. Each of the plurality of semiconductor dice 1000 includes a corresponding set of semiconductor devices 710 formed within or directly on the substrate semiconductor layer 9.

[0122] When measured from the bottom surface of the lowermost layer within the continuous material layers (380, 284, 282, 280, 180, 760) to the top surface of the uppermost layer within the continuous material layers (380, 284, 282, 280, 180, 760), the total thickness of the continuous material layers (380, 284, 282, 280, 180, 760) can range from 20 micrometers to 100 micrometers. Thus, the semiconductor die 100 can have a sufficient thickness such that it can be mechanically handled without cracking during dicing. Note that the three-dimensional memory device occupies a large portion of the total thickness of the continuous material layers (380, 284, 282, 280, 180, 760).

[0123] In one embodiment, each of the semiconductor dies 1000 can include a corresponding three-dimensional memory device contained within the continuous material layers (380, 284, 282, 280, 180, 760). Thus, each of the semiconductor dies 1000 can include a corresponding three-dimensional array of memory elements. In one embodiment, each of the three-dimensional memory devices includes a two-dimensional array of vertical NAND strings extending through an alternating stack {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246). In one embodiment, each of the semiconductor dies 1000 can include a corresponding set of complementary metal oxide semiconductor (CMOS) devices formed directly on the front surface of the substrate semiconductor layer 9, which can be components of the semiconductor device 710.

[0124] In one embodiment, the continuous material layers (380, 284, 282, 280, 180, 760) include a lower dielectric material layer 760 embedding the lower metal interconnect structure 780, which is electrically connected to the CMOS devices and electrically connected to the three-dimensional memory device and is located between the front surface of the substrate semiconductor layer 9 and the three-dimensional memory device. In one embodiment, the continuous material layers (380, 284, 282, 280, 180, 760) include upper interconnect level dielectric layers (382, 284, 282, 280) that contain metal interconnect structures, such as upper metal interconnect structures (388, 96, 98, 99), within a plurality of semiconductor dies 1000, and a capping silicon nitride passivation layer 384 that contacts metal contact pads 392 electrically connected to the metal interconnect structures (388, 96, 98, 99).

[0125] Reference Figure 19A-19D, a patterned etch mask layer 1077 can be formed over the exemplary structure to cover each of the plurality of semiconductor dies 1000, without covering the areas of the singulation channels that separate adjacent pairs of semiconductor dies 1000. The patterned etch mask layer 1077 can be a layer of photoresist material that is lithographically patterned, or can be a disposable hard mask material layer that is patterned by applying and patterning a photoresist layer thereon and by subsequent pattern transfer into the disposable hard mask material layer. If a photoresist material layer is used for the patterned etch mask layer 1077, the thickness of the photoresist material layer can be in the range from 5 microns to 100 microns, although smaller or larger thicknesses can also be used.

[0126] According to aspects of the present disclosure, the areas and orientations of the singulation channels between adjacent pairs of semiconductor dies 1000 are not limited to a rectangular grid shape. The horizontal cross-sectional shape of each semiconductor die 1000 can be a rectangular shape, or a non-rectangular shape. Generally, the horizontal cross-sectional shape of each semiconductor die 1000 can be any two-dimensional closed shape that defines a single continuous isolation region. In one embodiment, each of the plurality of semiconductor dies 1000 can have a non-rectangular horizontal cross-sectional shape, as Figure 19B shown. In one embodiment, each of the plurality of semiconductor dies 1000 can have a non-rectangular horizontal cross-sectional shape, as Figure 19C and Figure 19D shown. In one embodiment, a plurality of singulation channels can extend laterally along at least three different horizontal directions (e.g., along the sides of a hexagon), as Figure 19C shown. In one embodiment, at least one of the plurality of semiconductor dies 1000 can have a curved horizontal cross-sectional shape (such as circular, oval, or elliptical), as Figure 19D shown. The spacing between adjacent pairs of semiconductor dies 1000 can be uniform, as Figure 19B and Figure 19C shown, or can be non-uniform, as Figure 19D shown. Thus, semiconductor dies 1000 can be formed with two-dimensional cross-sectional shapes that arbitrarily define a single continuous region. Additionally, each semiconductor die 1000 can be formed as a set of two or more separate structures having the same or different shapes.

[0127] Figure 19E and 19F illustrate singulation channel configurations that can be used for the exemplary structure shown in Figure 19A-19D . In one embodiment, after the processing step shown in Figure 19A-19D , the singulation channels can completely surround each semiconductor die 1000 laterally, as Figure 19E shown. In another embodiment, after Figure 19A-19DAfter the processing steps, there can be bridges connecting adjacent pairs of semiconductor dice 1000, as Figure 19F shown. In the case of using the Figure 19E dicing channel configuration, the semiconductor dice 1000 can be completely physically isolated from each other after subsequent removal of the sacrificial bonding material layer 1120. In the case of using the Figure 19F dicing channel configuration, additional wafer-level processing steps (such as wafer bumping or attaching bonding and / or adhesive materials for die stacks) can be performed after subsequent removal of the sacrificial bonding material layer 1120.

[0128] Referring to Figure 20 , using the patterned etch mask layer 1077 as an etch mask (i.e., a mask that protects the underlying material portions from the etchant in an anisotropic etching process), anisotropic etching is performed through all the material layers of the semiconductor die 1000. The pattern in the patterned etch mask layer 1077 is transferred through all the material portions of the exemplary structure that are located above the backside silicon nitride passivation layer 1130 and are not covered by the patterned etch mask layer 1077 to form in-process dicing channels 1079'. Each of the in-process dicing channels 1079' includes a pair of straight sidewalls that extend from the top surface of the backside silicon nitride passivation layer 1130 to the topmost surface of the upper dielectric material layer 380. The straight sidewalls of the in-process dicing channels 1079' can be vertical or substantially vertical, having a taper angle of less than 3 degrees with respect to the vertical direction. Generally, by anisotropically etching the portions of the continuous material layers (380, 284, 282, 280, 180, 760) that are directly adjacent to pairs of semiconductor dice 1000 and are not covered by the patterned etch mask layer 1077, a plurality of in-process dicing channels 1079 can be formed between adjacent pairs among the plurality of semiconductor dice 1000. The plurality of in-process dicing channels 1079' extend to the top surface of the backside silicon nitride passivation layer 1130.

[0129] Referring to Figure 21 , the patterned etch mask layer 1077 can be selectively removed from the materials of various physically exposed sidewall surfaces of the semiconductor die 1000. For example, if the patterned etch mask layer 1077 includes a photoresist material, the patterned etch mask layer 1077 can be removed by ashing. If the patterned etch mask layer 1077 includes a polymer material, the patterned etch mask layer 1077 can be dissolved in an organic solvent.

[0130] A continuous silicon nitride liner 1074L can be deposited on the physically exposed surfaces of the semiconductor die 1000 and on the physically exposed portions of the top surface of the backside silicon nitride passivation layer 1130. The continuous silicon nitride liner 1074L can be formed on the sidewalls of the plurality of semiconductor dies 1000 and over the plurality of semiconductor dies 1000. A chemical vapor deposition process can be used to deposit the continuous silicon nitride liner 1074L. The continuous silicon nitride liner 1074L may or may not be conformal. The average thickness of the continuous silicon nitride liner 1074L on the sidewalls of the semiconductor die 1000 can range from 100 nm to 1000 nm, although smaller or larger thicknesses can also be used.

[0131] Reference Figure 22 , the portions of the continuous silicon nitride liner 1074L and the backside silicon nitride passivation layer 1130 below the singulation channel 1079' in processing are etched by an anisotropic etching process. The anisotropic etching process anisotropically etches the continuous silicon nitride liner 1074L and the backside silicon nitride passivation layer 1130 to vertically extend the singulation channel 1079' in processing. Once the horizontal portions of the continuous silicon nitride liner 1074L are removed from above each semiconductor die 1000, the top surface of the sacrificial capping silicon oxide layer 386 can be physically exposed. The vertically extended singulation channel 1079' in processing constitutes the plurality of singulation channels 1079. The plurality of singulation channels 1079 extend to the top surface of the sacrificial bonding material layer 1120.

[0132] The remaining portions of the continuous silicon nitride liner 1074L include discrete tubular portions that laterally surround a respective one of the semiconductor dies 1000. Each remaining portion of the continuous silicon nitride liner 1074L is herein referred to as a silicon nitride passivation liner 1074, which can function as a diffusion barrier layer to protect each semiconductor die 1000 from the intrusion of moisture or contaminants through the sidewalls of the semiconductor die 1000. The sidewalls of the plurality of singulation channels 1079 include the outer sidewalls of the silicon nitride passivation liner 1074 and the sidewalls of the remaining portions of the silicon nitride passivation layer 1130. Each silicon nitride passivation liner 1074 laterally surrounds a respective one of the plurality of semiconductor dies 1000. Portions of the top surface of the sacrificial bonding material layer 1120 are physically exposed between each adjacent pair of semiconductor dies 1000.

[0133] In one embodiment, the top surface of the silicon nitride passivation liner 1074 may be adjacent to the remainder of the capping silicon nitride passivation layer 384, and the bottom surface of the silicon nitride passivation liner 1074 may be adjacent to the backside silicon nitride passivation layer 1130. In this case, each semiconductor die 1000 may be completely encapsulated by a combination of the remainder of the capping silicon nitride passivation layer 384, the silicon nitride passivation liner 1074, the backside silicon nitride passivation layer 1130, and the respective set of metal contact pads 392.

[0134] Reference Figure 23 , an isotropic etching process may be used to selectively remove the sacrificial bonding material layer 1120 from the surface portions of the plurality of semiconductor dice 1000. Figure 23 Illustrated is an exemplary structure during the isotropic etching process after the sacrificial bonding material layer 1120 has been partially removed, after the etchant of the isotropic etching process has etched the proximal portion of the sacrificial bonding material layer 1120d from the dicing channel 1079, and before the etchant of the isotropic etching process has etched the distal portion of the sacrificial bonding material layer 1120.

[0135] For example, an isotropic etching process may be used to selectively etch the material of the sacrificial bonding material layer 1120 from the materials of the remainder of the capping silicon nitride passivation layer 384, the silicon nitride passivation liner 1074, the backside silicon nitride passivation layer 1130, and the metal contact pads 392. The isotropic etching process may use an etch chemistry that selectively removes the material of the sacrificial bonding material layer 1120 from silicon nitride. If the sacrificial bonding material layer 1120 comprises a silicon oxide-based material, such as doped silicate glass (e.g., borosilicate glass), undoped silicate glass, organosilicate glass, and thermal silicon oxide, the isotropic etching process may use wet etching chemicals including at least one of hydrofluoric acid, sodium hydroxide, and potassium hydroxide. The sacrificial capping silicon oxide layer 386 may be incidentally removed selectively during the isotropic etching process from the remainder of the backside silicon nitride passivation layer 1130 and the metal contact pads 392.

[0136] Reference Figure 24A and Figure 24B , the isotropic etching process may be further continued until the sacrificial bonding material layer 1120 is completely removed. Once the sacrificial bonding material layer 1120 is removed, the plurality of semiconductor dice 1000 are singulated from each other. Thus, the semiconductor dice 1000 may be singulated without applying external mechanical forces typically associated with physical dicing or grinding known in the art. Because the semiconductor dice 1000 do not experience mechanical stress during singulation, the semiconductor dice 1000 are less prone to stress-induced device failures and the reliability of the semiconductor devices in the semiconductor dice 1000 is enhanced.

[0137] In one embodiment, the physically exposed surface of each of the plurality of semiconductor dice 1000 after singulation includes the surface of the remaining portion of the backside silicon nitride passivation layer 1130, the surface of the silicon nitride passivation liner 1074, the surface of the remaining portion of the cap silicon nitride passivation layer 384, and the surface of a subset of the metal contact pads 392. The carrier substrate 1110 can be reused to be bonded to another semiconductor substrate layer 9 through a sacrificial bonding material layer, and the processing steps of the embodiments of the present disclosure can be used again to provide additional singulated semiconductor dice 1000.

[0138] The backside silicon nitride passivation layer 1130 can function as a passivation layer that blocks the diffusion of impurity materials and moisture from the backside into each semiconductor die 1000. Additionally, the backside silicon nitride passivation layer 1130 can be formed to have an internal tensile stress or an internal compressive stress such that the backside silicon nitride passivation layer 1130 compensates for or balances the (built-in) stress inherent in the upper portion of each semiconductor die 1000. Further, the backside silicon nitride passivation layer 1130 can be patterned and / or can be provided with a suitable thickness gradient or variation across the backside of each semiconductor die 1000 (e.g., by employing a combination of a lithographic backside mask and an etching process) to function as a patterned stress balancing layer. In the case where the backside silicon nitride passivation layer 1130 functions as a patterned stress balancing layer, the local stress applied by the backside silicon nitride passivation layer 1130 can be adjusted by the pattern of the backside silicon nitride passivation layer 1130 or the thickness variation across the backside of the semiconductor die 1000. The stress applied by the backside silicon nitride passivation layer 1130 as a patterned stress balancing layer can be in-plane anisotropic on the backside surface of the semiconductor die 1000. In other words, the stress applied by the backside silicon nitride passivation layer 1130 as a patterned stress balancing layer can have different strengths and / or polarities depending on the azimuthal orientation around the center of the set of semiconductor dice 1000 in the plane containing the backside surface of the semiconductor die 1000. In this case, the warpage of the semiconductor die 1000 can be effectively offset by adjusting the thickness of the backside silicon nitride passivation layer 1130 as a patterned stress balancing layer. In one embodiment, the stress applied by the backside silicon nitride passivation layer 1130 as a patterned stress balancing layer can include a local compressive stress that has the effect of enhancing the die strength of the semiconductor die 1000.

[0139] With reference to all the accompanying drawings and in accordance with various embodiments of the present disclosure, a method of forming singulated semiconductor dies is provided, which may include: forming a sacrificial bonding material layer on a front surface of a carrier substrate; attaching a substrate semiconductor layer to a front side of the sacrificial bonding material layer; forming a plurality of semiconductor dies included within a continuous material layer on a front side of the substrate semiconductor layer, each of the continuous material layers continuously extending over regions of the plurality of semiconductor dies; forming a plurality of dicing channels between adjacent pairs among the plurality of semiconductor dies by at least anisotropically etching portions of the continuous material layer located between the adjacent pairs of semiconductor dies, wherein the plurality of dicing channels extend to a top surface of the sacrificial bonding material layer; and selectively removing the sacrificial bonding material layer from a surface portion of the plurality of semiconductor dies using an isotropic etching process, wherein upon removal of the sacrificial bonding material layer, the plurality of semiconductor dies are singulated from each other.

[0140] With reference to all the accompanying drawings and in accordance with various embodiments of the present disclosure, a three-dimensional memory device on a singulated semiconductor die 1000 is provided, which may include: a three-dimensional memory device structure 710 located on a front surface of a semiconductor substrate layer 9; a silicon nitride passivation layer 1130 (such as a backside silicon nitride passivation layer 1130) contacting an entirety of a back surface of the semiconductor substrate layer 9; an interconnect-level dielectric layer (760, 280, 282, 284, 282) including metal interconnect structures (780, 96, 98, 99, 288) and located above the substrate semiconductor layer 9; a capping silicon nitride passivation layer 384 contacting a metal contact pad 392, the metal contact pad 392 being electrically connected to the metal interconnect structures (780, 96, 98, 99, 288) and located above the interconnect-level dielectric layer (780, 96, 98, 99, 288); and a silicon nitride passivation liner 1074 contacting an entirety of an outer sidewall of the interconnect-level dielectric layer (780, 96, 98, 99, 288) and extending vertically between the silicon nitride passivation layer 1130 and the capping silicon nitride passivation layer 384.

[0141] With reference to all the accompanying drawings and in accordance with various embodiments of the present disclosure, a singulated semiconductor die 1000 is provided, which may include: a semiconductor device 710 located on a front surface of a semiconductor substrate layer 9; an interconnect-level dielectric layer (780, 96, 98, 99, 288) including metal interconnect structures (780, 96, 98, 99, 288) and located above the substrate semiconductor layer 9; and a silicon nitride passivation liner 1074 contacting an entirety of an outer sidewall of the interconnect-level dielectric layer (780, 96, 98, 99, 288) and an entirety of an outer sidewall of the semiconductor substrate layer 9, wherein the singulated semiconductor die 1000 has a non-rectangular horizontal cross-sectional shape.

[0142] As semiconductor dies, such as dies including three-dimensional memory devices, are singulated by removing a sacrificial bonding material layer and an anisotropic channel etching process, various embodiments form a singulated semiconductor die without generating mechanical stress during the singulation process. Accordingly, yield is improved because damage caused by mechanical stress is reduced or eliminated. Further costs and time for sawing are eliminated. Accordingly, various embodiments can increase dicing yield and die reliability, as well as reduce manufacturing costs.

[0143] Reference Figure 25 , illustrates a processing sequence for forming a backside stress layer 620 on the backside surface of a substrate 8 after a thinning process, according to an embodiment of the present disclosure. The substrate 8 of various embodiments of the present disclosure can be thinned (e.g., by grinding) before dicing, and the backside stress layer 620 is deposited (e.g., by CVD) on the backside surface of the thinned substrate 8. The backside stress layer 620 includes a stress-generating dielectric material, such as silicon nitride or silicon oxide. In one embodiment, semiconductor structures (100, 700) (e.g., memory array region 100 and peripheral device region 700 and optionally contact region 200 and peripheral region 400) formed on the front side of the substrate 8 may generate compressive stress, and the backside stress layer 620 can apply compressive stress that balances warping (e.g., strain caused by stress applied by the semiconductor structures (100, 700) on the front side of the substrate 8) to minimize warping of the substrate 8.

[0144] Reference Figure 26A-26C , the backside stress layer 620 can be patterned or can employ multiple layers that apply different stresses. Localized stress can be generated to reduce wafer warping before dicing the wafer. Figure 26A Illustrates a configuration where only portions of the backside stress layer 620 above the backside surface of the substrate (i.e., wafer) are thinned. Figure 26B Illustrates an embodiment where a composite layer is used for the backside stress layer 620 above the wafer. Specifically, a first backside stress layer that applies a low level of compressive stress can be formed and patterned on the backside of the substrate 8, and a second backside stress layer that applies a higher level of compressive stress can be formed on the patterned first backside stress layer. The second backside stress layer can be planarized, e.g., by chemical mechanical planarization, to provide a backside stress layer 60 formed as a composite material layer with composition adjustment. Figure 26C Illustrates a configuration where portions of the backside stress layer 620 are completely removed.

[0145] Figure 27A and Figure 27BIllustrated is an exemplary layout of a patterned backside stress layer 620 on a silicon wafer 8W. The stress layer 620 can be patterned into stripes that extend along a dicing channel 1079 between semiconductor dice 1000 non-parallel (e.g., at an angle between 30 and 60 degrees, such as 45 degrees) to the die singulation direction, as Figure 27A shown. Alternatively, the stress layer 620 can be patterned into stripes that extend along a dicing channel 1079 between semiconductor dice 1000 parallel to one die singulation direction, as Figure 27B shown.

[0146] Referring Figure 28 , a vertical cross-sectional view of a semiconductor wafer is illustrated that includes a front-side stress layer 621 and an overlying insulating layer 622. The front-side stress layer 621 can include silicon nitride and can have a thickness in the range from 150 nm to 600 nm, such as 300 nm. The front-side stress layer can generate a stress that is of an opposite type of stress to that generated by semiconductor structures (100, 700) formed on the front side of the substrate 8. For example, if the semiconductor structures formed on the front side of the substrate 8 generate compressive stress, the front-side stress layer can generate tensile stress. The strength of the stress generated by the front-side stress layer 621 can be in the range from 100 MPa to 2 GPa, such as 130 MPa.

[0147] Although the foregoing relates to specific embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will recognize that various modifications can be made to the disclosed embodiments, and such modifications are intended to be within the scope of the present disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. The words "comprising" or "including" encompass all embodiments with the words "consisting essentially of" or "consisting of" substituted for the words "comprising" or "including", unless expressly specified otherwise. Where specific structures and / or configurations are illustrated in the present disclosure for embodiments, it should be understood that the claims can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or known to be impossible to those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A method of forming singulated semiconductor dies, comprising: Forming a sacrificial bonding material layer on a front surface of a carrier substrate; Attaching a substrate semiconductor layer to a front side of the sacrificial bonding material layer; Forming a plurality of unsingulated semiconductor dies, the plurality of unsingulated semiconductor dies being included within one or more continuous material layers on a front side of the substrate semiconductor layer; Forming a plurality of dicing channels by at least anisotropically etching one or more portions of the one or more continuous material layers that are located between adjacent pairs of the plurality of unsingulated semiconductor dies, a respective one of the plurality of dicing channels being located between the adjacent pairs among the plurality of unsingulated semiconductor dies, wherein the plurality of dicing channels extend to a front surface of the sacrificial bonding material layer; And Selectively removing the sacrificial bonding material layer from any exposed surface portions of the plurality of unsingulated semiconductor dies using an isotropic etching process, wherein the plurality of unsingulated semiconductor dies are singulated from each other when the sacrificial bonding material layer is removed to form a plurality of singulated semiconductor dies.

2. The method of claim 1, wherein attaching the substrate semiconductor layer to the front side of the sacrificial bonding material layer includes bonding the substrate semiconductor layer directly or through an intermediate dielectric material layer to the sacrificial bonding material layer.

3. The method of claim 2, wherein: The substrate semiconductor layer comprises a single crystal semiconductor material; and Each of the plurality of unsingulated semiconductor dies includes a respective set of semiconductor devices formed directly on the substrate semiconductor layer.

4. The method of claim 3, further comprising: Bonding a source semiconductor substrate including a buried hydrogen implantation layer to the front side of the sacrificial bonding material layer; And Separating a distal portion of the source semiconductor substrate from the sacrificial bonding material layer by cleaving the source semiconductor substrate at the buried hydrogen implantation layer, wherein a remaining proximal portion of the source semiconductor substrate attached to the sacrificial bonding material layer constitutes the substrate semiconductor layer.

5. The method of claim 2, wherein: The substrate semiconductor layer is bonded to the sacrificial bonding material layer through the intermediate dielectric material layer; and The intermediate dielectric material layer comprises a silicon nitride passivation layer.

6. The method of claim 5, further comprising: Depositing a continuous silicon nitride liner on a top surface of the silicon nitride passivation layer; And Performing an anisotropic etching process that anisotropically etches the continuous silicon nitride liner and the silicon nitride passivation layer to form the plurality of dicing channels, wherein remaining portions of the continuous silicon nitride liner include a plurality of silicon nitride passivation liners, each silicon nitride passivation liner laterally surrounding a respective one of the plurality of unsingulated semiconductor dies, and portions of the top surface of the sacrificial bonding material layer are physically exposed between each adjacent pair of semiconductor dies among the plurality of unsingulated semiconductor dies.

7. The method according to claim 6, wherein the isotropic etching process uses an etching chemistry that selectively removes the material of the sacrificial bonding material layer from the silicon nitride passivation liner and the silicon nitride passivation layer.

8. The method according to claim 7, wherein the isotropic etching process uses a wet etching chemical including at least one of hydrofluoric acid, sodium hydroxide, and potassium hydroxide.

9. The method according to claim 7, wherein the sacrificial bonding material layer comprises a material selected from one of doped silicate glass, undoped silicate glass, organosilicate glass, and thermal silicon oxide.

10. The method according to claim 6, wherein the continuous material layer comprises: an interconnection-level dielectric layer; a metal interconnection structure located within the interconnection-level dielectric layer; a metal contact pad electrically connected to the metal interconnection structure; and a capping silicon nitride passivation layer contacting the metal contact pad.

11. The method according to claim 10, wherein the surface portion of each of the plurality of unsingulated semiconductor dice exposed after singulation is constituted by the side surface of the remaining portion of the silicon nitride passivation layer, the surface of the silicon nitride passivation liner, the surface of the remaining portion of the capping silicon nitride passivation layer, and the surface of a subset of the metal contact pads.

12. The method according to claim 6, wherein the sidewalls of the plurality of dicing channels comprise the outer sidewalls of the silicon nitride passivation liner and the sidewalls of the remaining portion of the silicon nitride passivation layer.

13. The method according to claim 1, wherein: the sacrificial bonding material layer has a first thickness in the range from 5 micrometers to 20 micrometers; and the substrate semiconductor layer has a second thickness in the range from 200 nm to 10 micrometers.

14. The method according to claim 1, wherein: the continuous material layer has a total thickness in the range from 20 micrometers to 100 micrometers; and each of the plurality of unsingulated semiconductor dice comprises a corresponding three-dimensional memory device, and the corresponding three-dimensional memory device is included within the continuous material layer.

15. The method according to claim 14, wherein: each corresponding three-dimensional memory device comprises a two-dimensional array of vertical NAND strings extending through an alternating stack of insulating layers and conductive layers; each of the plurality of unsingulated semiconductor dice of the plurality of unsingulated semiconductor dice further comprises a corresponding set of complementary metal-oxide semiconductor (CMOS) devices formed directly on the front side of the substrate semiconductor layer; and the continuous material layer comprises: a lower-level dielectric material layer; and a lower-level metal interconnection structure electrically connected to the corresponding set of complementary metal-oxide semiconductor devices and the three-dimensional memory device.

16. The method according to claim 1, wherein each of the plurality of unsingulated semiconductor dice has a non-rectangular horizontal cross-sectional shape.

17. The method according to claim 16, wherein at least one of the plurality of non-singulated semiconductor dies has a curved horizontal cross-sectional shape.

18. The method according to claim 1, wherein the plurality of dicing channels extend laterally along at least three different horizontal directions.

19. A three-dimensional memory device, wherein, The three-dimensional memory device is singulated by removing a sacrificial bonding material layer and an anisotropic channel etching process, and the three-dimensional memory device includes: A three-dimensional device structure located on a front surface of a substrate semiconductor layer; A silicon nitride passivation layer contacting an entirety of a back surface of the substrate semiconductor layer; An interconnection-level dielectric layer including a metal interconnection structure and located above the substrate semiconductor layer; A cap silicon nitride passivation layer contacting a metal contact pad, the metal contact pad being electrically connected to the metal interconnection structure and located above the interconnection-level dielectric layer; and A silicon nitride passivation liner contacting an entirety of an outer sidewall of the interconnection-level dielectric layer and vertically extending between the silicon nitride passivation layer and the cap silicon nitride passivation layer.

20. A singulated semiconductor die, wherein, The singulated semiconductor die is singulated by removing a sacrificial bonding material layer and an anisotropic channel etching process, and the singulated semiconductor die includes: A semiconductor device located on a front surface of a substrate semiconductor layer; An interconnection-level dielectric layer including a metal interconnection structure and located above the substrate semiconductor layer; and A silicon nitride passivation liner contacting an entirety of an outer sidewall of the interconnection-level dielectric layer and an entirety of an outer sidewall of the substrate semiconductor layer, wherein the singulated semiconductor die has a non-rectangular horizontal cross-sectional shape.

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