Data processing device and data processing method

Abstract

The present disclosure provides a data processing device and a data processing method. The present disclosure describes a vector add with carry instruction, which uses some elements of a target vector register or corresponding fields of a predicate register to provide carry information corresponding to the result of an add with carry operation. This helps to speed up calculations involving multiplication of long integer values.

Description

Technical Field

[0001] The present technology relates to the field of data processing. Background Art

[0002] Some data processing systems support processing of vector instructions, which act on or generate vector operands containing multiple data elements. By supporting the processing of multiple different data elements in response to a single instruction, code density can be improved and the overhead of fetching and decoding instructions can be reduced compared to performing the same operation using scalar instructions. Summary of the invention

[0003] At least some examples provide an apparatus comprising:

[0004] processing circuitry for performing data processing;

[0005] an instruction decoding circuit for decoding instructions to control the processing circuit to perform data processing; and

[0006] A plurality of vector registers for storing vector operands, the vector operands comprising a plurality of data elements; wherein:

[0007] The instruction decoding circuitry, in response to a vector add-with-carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, and a carry source vector register, controls the processing circuitry for each data element pair of the destination vector register, at least the destination vector register and the carry source vector register each specifying an operand including at least one data element pair, each data element pair including a first data element and a second data element:

[0008] updating a first data element of the pair of data elements of the destination vector register with a value corresponding to a result of an addition of a first source data value obtained from a selected data element of the first data source vector register, a second source data value obtained from a selected data element of the second data source vector register, and a carry value obtained from a second data element of the corresponding pair of data elements of the carry source vector register; and

[0009] A second data element of the pair of data elements of the target vector register is updated with a value corresponding to the carry out of the addition.

[0010] At least some examples provide a computer for controlling a host processing device to provide an instruction execution environment to execute target program code instructions, the computer program comprising:

[0011] Instruction decoding program logic for decoding the target program code instructions to control the processing program logic to perform data processing; and

[0012] A vector register data structure for storing data, the data representing a plurality of vector registers for storing vector operands, the vector operands comprising a plurality of data elements; wherein:

[0013] The instruction decode program logic, in response to a vector add-with-carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, and a carry source vector register, controls the processing program logic to update the vector register data structure for each data element pair of the destination vector register, at least the destination vector register and the carry source vector register each specifying an operand including at least one data element pair, each data element pair including a first data element and a second data element:

[0014] updating a first data element of the pair of data elements of the destination vector register with a value corresponding to a result of an addition of a first source data value obtained from a selected data element of the first data source vector register, a second source data value obtained from a selected data element of the second data source vector register, and a carry value obtained from a second data element of the corresponding pair of data elements of the carry source vector register; and

[0015] A second data element of the pair of data elements of the target vector register is updated with a value corresponding to the carry out of the addition.

[0016] At least some examples provide a data processing method comprising the steps of:

[0017] decoding a vector add-with-carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, and a carry source vector register, at least the destination vector register and the carry source vector register each specifying an operand including at least one data element pair, each data element pair including a first data element and a second data element; and

[0018] In response to decoding of the vector add-with-carry instruction, for each data element of the target vector register, control processing circuitry:

[0019] updating a first data element of the pair of data elements of the destination vector register with a new value corresponding to a result of an addition of a first source data value obtained from a selected data element of the first data source vector register, a second source data value obtained from a selected data element of the second data source vector register, and a carry value obtained from a second data element of the corresponding pair of data elements of the carry source vector register; and

[0020] A second data element of the pair of data elements of the target vector register is updated with a value corresponding to the carry out of the addition.

[0021] At least some examples provide an apparatus comprising:

[0022] processing circuitry for performing data processing;

[0023] An instruction decoding circuit, used for decoding instructions to control the processing circuit to perform the data processing;

[0024] a plurality of vector registers for storing vector operands, the vector operands comprising a plurality of data elements; and

[0025] a plurality of predicate registers including a plurality of predicate fields to store predicate values ​​of masks used to control operations performed by the processing circuit; wherein:

[0026] The instruction decoding circuit, in response to a vector add with carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, an input predicate register, and an output predicate register, controls the processing circuit for a given data element of the destination vector register:

[0027] updating the given data element of the target vector register with a value corresponding to a result of an addition of a first source data value obtained from a corresponding data element of the first data source vector register, a second source data value obtained from a corresponding data element of the second data source vector register, and a carry value obtained from a corresponding predicate field of the input predicate register; and

[0028] The corresponding predicate field of the output predicate register is updated with the value corresponding to the carry output of the addition.

[0029] At least some examples provide a computer program for controlling a host processing device to provide an instruction execution environment for executing target program code instructions, the computer program comprising:

[0030] Instruction decoding program logic for decoding the target program code instructions to control the processing program logic to perform data processing; and

[0031] a register data structure for storing data representing a plurality of vector registers for storing vector operands comprising a plurality of data elements and a plurality of predicate registers for storing predicate values ​​for masks for controlling vector operations performed by the processing program logic; wherein:

[0032] The instruction decode program logic, in response to a vector add with carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, an input predicate register, and an output predicate register, controls the processing circuitry to update the register data structure for a given data element of the destination vector register:

[0033] updating a given data element of the destination vector register with a value corresponding to a result of a first source data value obtained from a corresponding data element of the first data source vector register, a second source data value obtained from a corresponding data element of the second data source vector register, and a carry value obtained from a corresponding predicate field of the input predicate register; and

[0034] The corresponding predicate field of the output predicate register is updated with the value corresponding to the carry output of the addition.

[0035] At least some examples provide a data processing method comprising the steps of:

[0036] decoding a vector add with carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, an input predicate register, and an output predicate register selected from a plurality of predicate registers for storing predicate values ​​for controlling a vector operation mask; and

[0037] In response to decoding of the vector add-with-carry instruction, controlling processing circuitry for a given data element of the target vector register:

[0038] updating a given data element of the destination vector register with a value corresponding to a result of an addition of a first source data value obtained from a corresponding data element of the first data source vector register, a second source data value obtained from a corresponding data element of the second data source vector register, and a carry value obtained from a corresponding predicate field of the input predicate register; and

[0039] The corresponding predicate field of the output predicate register is updated with the value corresponding to the carry output of the addition. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Further aspects, features and advantages of the present technology will become apparent from the following exemplary description when read in conjunction with the accompanying drawings, in which:

[0041] Figure 1 An example of a data processing device supporting execution of vector instructions is schematically shown;

[0042] Figure 2 An example of a vector operation with a predicate is shown;

[0043] Figure 3 and Figure 4 shows addition and subtraction variants of a vector add-with-carry instruction according to a first example;

[0044] Figure 4A A predicated variant of a vector add with carry instruction is shown;

[0045] Figure 5 is a flow chart illustrating a method of processing a vector add with carry instruction;

[0046] Figure 6 An example of vectorization of multiplication of long integer values ​​according to Karatsuba's algorithm is shown;

[0047] Figure 7 shows an example of partial products to be added when performing a multiplication of two 256-bits using a 64-bit vector element size;

[0048] Figure 8 Shown include Figure 3 An example instruction sequence for a vector add with carry instruction is shown;

[0049] Fig. 9 A second example of an instruction sequence using a vector add with carry instruction is shown;

[0050] FIG. 10A to FIG. 10I Shows Fig. 9 A series diagram of the processing of the instruction sequence;

[0051] Fig.11 A second example of a vector add-with-carry instruction using a predicate register to transfer a carry value for an addition or subtraction is shown;

[0052] Fig.12 is based on Fig.11 An example of a flowchart showing the processing of a vector add with carry instruction; and

[0053] Fig.13 An example of a simulator that can be used is shown. DETAILED DESCRIPTION

[0054] Some processing workloads may require applying mathematical operations to very large integer values ​​(such as 1024-bit, 2048-bit, or 4096-bit values). For example, cryptographic workloads may rely on the difficulty of factoring large numbers, and therefore may require multiplying such large numbers to encrypt or decrypt information. For example, in RSA 2048, there are many sequential multiplications of 2048-bit numbers to produce 4096-bit products. Some financial processing applications also need to process long integer values. If each bit of an operand is multiplied by each bit of another operand using a standard textbook method, the complexity of performing the multiplication will generally be amplified with the square value of the number of bits. However, some algorithms that reduce complexity are known, making the computational cost slower in proportion to the number of bits amplified. For example, the Karatsuba algorithm divides the long number to be multiplied into smaller parts to be multiplied individually, which can be balanced between the required number of multiplications and some additional additions, subtractions, or shift operations. Thus, multiplication of long integers can be broken down into several smaller multiplications and several additions, subtractions, and shifts. Vector instructions can be used to accelerate such computations by mapping different sub-multiplications onto different vector lanes so that a single instruction can control the computation of portions of several independent sub-multiplications. In this case, most workloads can be efficiently applied to a series of additions or subtractions that perform partial products of various multiplications. However, this creates a design challenge in managing the transfer of carry information between partial product additions, because the carry information from one addition may need to be input to the next addition performed on values ​​of equivalent significance, and therefore the carry information from one instruction may need to be saved as input to another instruction.

[0055] One approach can effectively reduce the element size of the real data being processed within each vector lane and save one or more bits at the top of each lane for storing carry information from additions in that lane so that subsequent instructions can read the carry information. However, the inventors have recognized that when using this approach, because of the need to include additional carry information within each lane, many additional instructions may be required to unpack the input data vector (with elements that fully occupy the vector lanes) and resize these components to spread them across multiple vector lanes with the reduced effective data element size. Furthermore, if the input data includes multiple elements of a given element size, then the same amount of input data will require a larger total number of vector lanes when spread across lanes with space reserved for carry. For example, four 64-bit element input vectors, when spread across vector lanes with 56 bits of real data and 8 bits reserved for carry, will require five lanes to be allocated to accommodate the same number of bits (256 bits) of input data, since each of the four lanes of 56 bits only provides 224 bits and therefore a fifth lane is required to accommodate the last 32 bits. Since the number of partial products to be computed scales with the square of the number of vector components, this can significantly increase the number of multiplications and partial product additions required, which can further degrade performance.

[0056] The techniques discussed below provide techniques for implementing vector add-with-carry instructions such that no unpacking of input data is required because the instruction can operate directly on source data elements that occupy an entire vector lane.

[0057] In one method, a vector add with carry instruction specifies a destination vector register, a first data source vector register, a second data source vector register, and a carry source vector register. At least the destination vector register and the carry source vector register each specify an operand including at least one data element pair, wherein each data element pair includes a first data element and a second data element. In response to the instruction, an instruction decoder controls processing circuitry for each data element pair of the destination vector register to update a first data element of the data element pair of the destination vector register with a value corresponding to an addition result of a first source data value, a second source data value, and a carry value, the first source data value being obtained from a selected data element of the first data source vector register, the second source data value being obtained from a selected data element of the second data source vector register, and the carry value being obtained from a second data element of the corresponding data element pair of the carry source vector register. Furthermore, the second data element of the data element pair of the destination vector register is updated with a value corresponding to a carry output of the addition.

[0058] Thus, the second data element of each pair of elements in the destination vector register is retained to provide the carry-out of the addition, and similarly, the second data element of each pair in the carry-source vector register is used to provide the carry-in of the addition. Thus, the destination vector registers and the carry-source vector registers have corresponding layouts, and in practice typically when these instructions are actually used, the destination vector register produced by one instance of the vector add-with-carry instruction can be used as the carry-source vector register for a subsequent instance of the vector add-with-carry instruction.

[0059] This approach is counter-intuitive because it effectively halves the number of data elements available to carry the source data and the addition result value, which goes against a common design principle in vector processors to improve the efficiency of computation by maximizing the utilization of the vector register file. In other words, using half the vector lanes to provide carry values ​​would appear to waste the capacity of the vector processor and the vector register file, and would double the number of instructions required to process a given number of data elements.

[0060] However, surprisingly, the inventors have recognized that, although more add-with-carry instructions may be required to execute a given workload, the benefit of placing the carry into the second data element of each pair of elements is that the first data element can occupy the full lane size, which means that there is no need to unpack or resize elements from the input vector, and thus the vector add-with-carry instructions can operate directly on the packed source data. In fact, for workloads involving long integer multiplication, it has been found that even though additional instructions are required to compensate for the effective reduction in the number of elements processed by the vector add-with-carry instructions, overall performance is still higher because (a) the unpacking / resizing overhead is avoided, and (b) the increase in the number of partial products caused by reducing the effective lane size is avoided through the aforementioned carry-within-lane approach. Therefore, overall performance can be improved. In any case, in some micro-architectures, even if a single vector add-with-carry instruction operates on half the elements at the architectural level, the two instruction instances combined to operate on all elements can be "fused" together as a single micro-instruction to be processed by the processing pipeline, or can be processed in parallel to avoid the obvious performance loss of halving the number of elements processed per macro-instruction. This is possible, for example, if the micro-architecture supports multiple simultaneous writes to the result bus. There are also parallel approaches in the form of independent carry chains.

[0061] In some embodiments, the destination vector register may be specified by the instruction separately from the first and second source vector registers and the carry source vector register to provide a non-destructive instruction format which preserves all source vectors in the register file after execution of the instruction since the result is written to a register different from all the source registers.

[0062] However, in other embodiments, the first data source vector register may be the same register as the target vector register, and for each pair, the first source data value may include the previous value of the first data element of the pair of data elements of the target vector register. In practice, an accumulation operation (in which the old accumulator value is added to the second source data value and the carry value and written back to the same register) is useful for many workloads involving long integer multiplication (for adding the respective partial products of the multiplication), so it is not necessary to specify the first source data vector register independently from the target vector register. By specifying a single register as both the target vector register and the first data source vector register, instructions encoding space in the instruction set architecture can be saved for other purposes. Another advantage of the destructive instruction format (the same register as both a target register and a source register) is that, since it may sometimes be necessary to limit the number of source register ports required for an instruction, and in some microarchitectures, in the case of an operation with a merge predicate (in which the predicate of the target register saves their previous value), the target register may already need to be read, and only having two further register accesses (for the second source vector register and the carry vector register) may be beneficial.

[0063] The vector element size and / or sum length of the vector operands may vary. Some embodiments may hardwire the element size and / or vector length to a specific fixed value. However, other systems may support variable vector element sizes and vector lengths. For some vector element sizes or vector lengths, the vector may only include two elements, and in this case the target vector register and the carry source vector register may include a single data element pair, i.e. a first data element and a second data element.

[0064] However, it is useful to have the instruction decoding circuitry and processing circuitry support at least one instance of executing a vector add with carry instruction, the destination vector register and the carry source vector register comprising a plurality of data element pairs, i.e. they comprising at least four elements (two or more of each of the first and second data elements). This enables the system to support the computation of multiple additions in response to a single instruction, which may be useful for speeding up the computation of multiplications involving long integer operands. For example, each pair of elements may represent the addition of partial products of a different sub-multiplication of the Karatsuba algorithm.

[0065] Mapping pairs of data elements onto vector operand elements may be accomplished in a variety of ways. For example, in one example, the first element of each pair may be located in one half of the register, and the second element of each pair may be located in the other half. For example, in an example with 4 pairs of first and second elements, these elements may be arranged in the order of 2d, 2c, 2b, 2a, 1d, 1c, 1b, 1a (where 1a is the first element corresponding to the second element 2a, and the same is true for the pairs b, c, d).

[0066] However, in one embodiment, each data element pair may include a pair of adjacent data elements. Therefore, when the number of data element pairs in the target vector register and the carry source vector register is at least two, the first data element of the data element pair may be interleaved with the second data element of the data element pair. For example, with 4 pairs of first and second elements, these elements may be arranged in the order of 2d, 1d, 2c, 1c, 2b, 1b, 2a, 1a (or the order of the first and second elements in each pair may be transposed). Since this may make the hardware design more efficient, the method may be implemented more efficiently by hardware because the source operands and result values ​​to be combined in a given sub-computation of a vector instruction may be restricted to being located in the same vector lane, or only dispersed in adjacent vector lanes, rather than requiring a longer cross-lane signal path across two or more vector lanes. Therefore, by interleaving the first and second data elements of each pair, the complexity and length of the required wiring may be reduced.

[0067] The carry value can be obtained from the least significant bit of the second data element of the corresponding data element pair of the carry source vector register. In response to the vector carry addition instruction, the processing circuit can utilize the value corresponding to the addition carry output to update the least significant bit of the second data element of the data element pair of the target vector register. It can be more efficient to provide the carry using the least significant bit of the second data element, because the least significant bit can be adjacent to the most significant bit of the first data element of the corresponding pair, so that the carry and the data value can be written to the continuous part of the target vector register. The remaining bits of the second data element except the least significant bit can be unused in the carry source vector register and the accumulator vector register. Although leaving many unused bits seems to waste space in the vector register file, and wastes the processing resources in the vector processing unit, as discussed above, the overall performance when performing long integer multiplication can be improved by this method.

[0068] The vectors processed by the add-with-carry instruction can have two N The second source data value may also include 2 N bits, where N is an integer. Therefore, since the second source data value has the same size as the vector track itself (corresponding to an exact power of two bit numbers), the second source data value occupies the entire vector track, and therefore no data elements from the input vector (or results of previous vector instructions) need to be resized or unpacked to allow the vector add with carry instruction to operate on the input. Instead, the vector add with carry instruction can operate directly on the selected elements from the input vector. This is possible because the carry is stored in a different vector element than the data result.

[0069] The second source data value may be obtained from any element of the second source data vector register.Different variants of the instruction may be provided to select source data values ​​from different elements of the second source data vector register.

[0070] In one example, the second data source vector register may provide an operand including at least one data element pair, which may be set in a manner corresponding to the element pair in the target and carry source vector registers. For example, the first data element and the second data element of each pair may be interleaved. A first variant and a second variant of a vector carry addition instruction may be provided. For the first variant, the second source data value may include the first data element of the corresponding data element pair of the second data source vector register (the instruction result may be independent of the second element of each pair). For the second variant, the second source data value may include the corresponding second data element of the pair (the instruction result may be independent of the first element of each pair). By providing two instruction variants to select different elements as the second source data value, this enables that no additional reordering or unpacking of the second source vector element is required before executing two vector carry addition instructions (one of each of the first / second variants), i.e., all elements of the input vector can be processed, because the combination of the two instruction variants can process each element of the second source vector.

[0071] In embodiments where the instruction specifies a first data source vector register that is different from the target vector register, the first source data value may similarly be extracted from the first element of each pair (for the first instruction variant) or the second element of each pair (for the second instruction variant).

[0072] On the other hand, if the first data source vector register is the same register as the destination vector register, then for each addition, the first source data value may be extracted from the first data element of the corresponding element pair in the destination vector register (regardless of whether the instruction variant executed is the first variant or the second variant), since the second data element of the destination vector register will be used to present the carry information.

[0073] Furthermore, a predicated variant of the add with carry instruction may be provided, which is associated with a predicate value specifying at least one predicate indication, each predicate indication corresponding to one of the at least one data element pair of the target vector register. In response to the predicated variant, the instruction decoding circuitry may control the processing circuitry to perform an update of the first / second data element of the data element pair of the target vector register (the corresponding predicate indication has a first value) as described above, and to suppress the update of the data element pair (the corresponding predicate indication has a second value). The predicate value may be associated with the instruction, by decoding the instruction including a predicate register designator (identifying the predicate register storing the predicate value), or a default predicate register may be used to provide the predicate value to all instances of the add with carry instruction predicate variant, regardless of the encoding of the instruction. For the element pair of the target vector register (the corresponding predicate indication has the second value), the element pair may keep the previous value stored in this portion of the target vector register, or may be cleared to zero or another predetermined value. Therefore, when the add with carry instruction is predicated, the predicate may act at the granularity of the data element pair, relative to acting at the granularity of the individual data elements of the vector.

[0074] Addition and subtraction variants of vector carry addition instructions can be provided. For the addition variant, addition includes adding the first and second source data values ​​and the carry value obtained from the second data element of the carry source vector register. For the subtraction variant, the operation includes subtracting the second source data value from the first source data value, and the carry value indicates the borrow value of the subtraction. For the subtraction variant, the carry output represents the borrow output of the subtraction. Note that subtraction can still be considered as addition, because the subtraction of two operands is equal to the addition of two operands (when one operand is 2's complement before performing addition). Similarly, the borrow value of subtraction can be considered as the carry value of addition, because the borrow value only corresponds to the carry of -1 rather than the carry of +1 for addition.

[0075] When more than one variant of the vector add with carry instruction is provided, the variants (first / second, or addition / subtraction) can be distinguished in a variety of ways. For example, different variants of the add with carry instruction may have different instruction opcodes. Alternatively, the variants may share a common opcode, but may have another field in the instruction encoding to distinguish the variants. In another example, different variants of the instruction may have the same instruction encoding, but may be distinguished by a mode parameter stored in a control register of the device, which may be set by a preamble instruction to select which instruction variant should be used when encountering a subsequent vector add with carry instruction. For the first / second variant, the first / second element selection may also be presented in a predicate or mask register read by the instruction.

[0076] An advantage of the vector add-with-carry instruction form discussed above (using some elements of the carry source vector register and the target vector register to transfer carry information for addition / subtraction) may be that it may be relatively efficiently implemented in a micro-architecture because only one register (the target vector register) needs to be written in response to the instruction. Furthermore, in the example where the accumulator register is specified as both the target and first source vector register, the instruction only needs to specify one target register designator and two vector source registers.

[0077] However, an alternative solution to the problem of implementing large integer value calculations may be to provide a vector add-with-carry instruction that uses a predicate register to pass carry information. The data processing apparatus may have a plurality of predicate registers, the predicate registers including a predicate field to store a predicate value to control a mask of operations performed by processing circuitry. While for other types of vector instructions the predicate field may control a mask of vector processing, for the vector add-with-carry instruction the predicate register may be used again to present the carry-out of the addition, and the carry-in of the addition may also be obtained from the predicate field of the predicate register.

[0078] Therefore, the instruction decoding circuit can respond to the vector add with carry instruction (specifying the target vector register, the first data source vector register, the second data source vector register, the input predicate register and the output predicate register) to control the processing circuit to update the given data element of the target vector register with a value corresponding to the addition result of the first source data value, the second source data value and the carry value, the first source data value is obtained from the corresponding data element of the first data source vector register, the second source data value is obtained from the corresponding data element of the second data source vector register, and the carry value is obtained from the corresponding predicate field of the input predicate register. Furthermore, the corresponding predicate field of the output predicate register can be updated with a value corresponding to the carry output of the addition.

[0079] Although this approach may require a more complex micro-architecture (e.g., faster read / write paths to the predicate register file, and the ability to write to both the vector register file and the predicate register file simultaneously in response to the same instruction), the advantage of this approach is that the carry is not stored in an element of the target vector register, so each element of the target vector register can be used to store the addition result value (and each element of the first / second data source vector register can be used as a source input), effectively doubling the number of operands that can be executed in response to a single instruction, thereby improving performance.

[0080] In short, the two examples discussed above have the advantage of being able to operate directly on complete data elements from the input vector without unpacking or resizing the operation, because the carry information is not stored in the same lane as the data result, but is stored in another vector register lane or in the corresponding predicate field of the predicate register. This is very useful for accelerating long integer multiplication.

[0081] Both of the instruction forms discussed above may be implemented by hardware using an instruction decoder that controls the processing circuitry to perform the desired operation in response to a vector add with carry instruction. For example, the instruction decoder may include logic gates for interpreting the encoding of the vector add with carry instruction to selectively enable appropriate control signal paths to update the result register based on the input as described above to control the processing circuitry.

[0082] However, the technology can also be implemented by processor architecture simulation rather than physical hardware. Therefore, an emulator computer program can be provided to control a host processing device (which itself may not support the instructions discussed above) to provide an instruction execution environment to execute target program code instructions, and to simulate the execution of the target program code on a target processing device that does not support these instructions. The functions of the instruction decoder and processing circuit can be performed by the instruction decoding program logic and the processing program logic in the emulator program, and the register can be implemented as a simulation register data structure in a memory, and the data structure stores data to represent the register of the simulated target processing device. The computer program can be stored on a storage medium. The storage medium can be a non-transient storage medium.

[0083] Figure 1 An example of a data processing device 2 is schematically illustrated, and the data processing device 2 has a processing circuit 4 to perform a data processing operation in response to an instruction decoded by an instruction decoder 6. Program instructions are obtained from a memory system 8, which may include one or more caches and memories. The instruction decoder 6 decodes the instruction to generate a control signal, which controls the processing circuit 4 to process the instruction and perform the corresponding operation defined by the instruction set architecture. For example, the decoder 6 may include a logic gate to interpret the opcode and any additional instruction control field to generate a control signal, which causes the processing circuit 4 to enable the appropriate hardware unit to perform the operation (such as an arithmetic operation, a logical operation, or a load / store operation). The register 10 stores the data value to be processed by the processing circuit 4 in response to the instruction, and the control information for configuring the processing circuit operation. In response to an arithmetic or logical instruction, the processing circuit 4 reads the operand from the register 10 and writes the instruction result back to the register 10. In response to a load / store instruction, the data value is transferred between the register 10 and the memory system 8 via the processing logic 4.

[0084] The register 10 includes a scalar register file 12, including a plurality of scalar registers to store scalar values, the scalar value comprising a single data element. The scalar registers may include integer registers to store integer operands, and floating point registers to store floating point numbers. Alternatively, integer values ​​and floating point numbers may be stored in the same register set. Some instructions supported by the instruction decoder 6 in the instruction set architecture are scalar instructions, which control the processing circuit 4 to process the scalar operands read from the scalar register 12 to generate a scalar result to be written back to the scalar register 12.

[0085] The registers also include a vector register file 14 and a predicate register file 16. The vector register file 14 includes a plurality of vector registers that support storing vector operands including a plurality of data elements. The instruction decoder 6 supports vector instructions that control the processing circuit 4 to perform a plurality of vector processing paths on respective vector operand elements read from the vector registers to generate a scalar result to be written to the scalar register 12, or another vector result to be written to the vector register 14. Some vector instructions may also generate vector results from one or more scalar operands, or may perform additional scalar operations on scalar operands in the scalar register file, and perform vector processing on operands read from the vector register file. Therefore, some instructions may be scalar-vector hybrid instructions. Like vector arithmetic or logic instructions that trigger arithmetic or logic operations within the processing circuit, the decoder 6 may also support vector load / store instructions that may transfer data between the vector register 14 and the memory system 8.

[0086] Figure 2An example vector operation controlled by predicate information in one of the predicate registers 16 is shown. In this example, the vector instruction is a vector addition instruction, which controls the processing circuit 4 to perform a plurality of independent addition operations, each operation adding corresponding pairs of data elements of two input vectors Zm, Zn, and writing the addition result to the corresponding element of the target vector Zd. Of course, other arithmetic or logical operations may be applied as core operations to be performed in each vector lane, rather than just addition. Each predicate field of the predicate register P controls whether the corresponding element of the target register is updated by the addition result. For example, in this example, vector lanes 1, 2, and 5 are masked (because the corresponding predicate fields of these lanes are 0), and therefore the corresponding element of the target register Zd is not set to the addition result. For example, the masked lanes may retain their previous values. Alternatively, a clear / zero-fill form of predicate may clear the masked elements of the target register to zero or another predetermined value, while the non-masked lanes are written by the addition result in this lane. Thus, the predicate register 16 may be used generally to control the masking of vector operations in a particular lane. For example, a conditional vector instruction may perform comparisons to test whether input elements in each lane of a given vector meet some condition, and set a predicate value in a predicate register based on the comparison results in the corresponding lane, and then mask subsequent vector instructions depending on the predicate so that the effect of this instruction in each vector lane is made conditional and dependent on comparisons performed by previous conditional vector instructions.

[0087] although Figure 2 It is illustrated that all additions are performed in parallel for a given vector, but this is not necessary. The processing circuit 4 can support the processing of vectors with various different data element sizes and different vector lengths. For example, a 256-bit vector register 14 can be divided into 32 8-bit data elements, 16 16-bit data elements, 8 32-bit data elements, 4 64-bit data elements, or 2 128-bit data elements, or can be interpreted as a single 256-bit element. Furthermore, vector registers of different sizes can be supported, such as 128, 256 or 512 bits. For example, the vector register library 14 can be partitioned in various ways to provide various vector register sizes (for example, multiple physical registers of fixed size can be combined and operated by a single vector instruction to present a larger register size). Therefore, as Figure 1As shown, register 10 may also include control information for controlling vector processing, such as element size parameter 18 (the number of bits in one data element of a vector) specifying the size of the data element used for the vector operation, and vector length parameter 20 (the total number of bits in the vector, including all elements) specifying the length of the vector register. In some embodiments, these values ​​may be hard-wired so that they are always the same for all instructions. Providing registers for specifying element size 18 and vector length 20 may still be useful so that in order to execute the written code on various platforms with different element sizes or vector lengths, the specific element size or vector length implemented on the system executing this code may be read. However, in other examples, element size and (or) vector length may be programmed so that instructions may specify which element size or vector length to use for a given operation. Alternatively, element size and (or) vector length may be specified by vector instruction encoding rather than by parameters in control registers.

[0088] Thus, the element size or vector length may vary. Depending on the particular size selected, the vector processing circuit may not always have enough processing hardware to process the entire vector in parallel. If the processing logic is narrower than the vector length for a given operation, the vector may be processed multiple times through the narrower processing logic by multiple cycles. Therefore, although a vector instruction may trigger the processing circuit 4 to perform operations in multiple lanes in response to a single instruction, this does not necessarily imply that all of these lanes must be processed in parallel. At one extreme, some vector implementations may only provide processing logic corresponding to a single lane, and then process all vector lanes in sequence. At another extreme, a higher performance implementation may use multiple parallel execution units to process all vector lanes in parallel. Other implementations may process multiple lanes in parallel, but process the vector as a whole by multiple sequential blocks.

[0089] It will be appreciated that the element size and vector length indications 18, 20 are only some examples of control information that may be stored in registers 10. Other examples may include a program counter register to indicate the instruction address representing the current execution point, a stack pointer register to indicate the address of the location in memory 8 of a stack data structure (to store or restore state when handling exceptions), and a link register to store a function return address to which the handler branches after execution of the function.

[0090] Figure 3 and Figure 4 The addition and subtraction variants of the vector add with carry instruction according to one example are shown. For both the addition and subtraction variants, a first variant and a second variant of a further instruction are shown:

[0091] ADCLB Zda, Zn, Zm / / Long addition with carry (base) - first variant, addition variant

[0092] ADCLT Zda, Zn, Zm / / Long addition with carry (top) - second variant, addition variant

[0093] SBCLB Zda, Zn, Zm / / Long subtraction with carry (base) - first variant, subtraction variant

[0094] SBCLT Zda, Zn, Zm / / Long Subtraction with Carry (Top) - Second Variant, Subtraction Variant For each variant, Zda represents the destination vector register (also known as the first source data vector register and may be referred to as the accumulator vector register), Zn represents the second source data vector register, and Zm represents the carry source vector data register. These instructions may be used to speed up processing of large integers by performing addition or subtraction such that carry or borrow input information is interleaved with the actual data value in the accumulator vector register and the carry source vector register.

[0095] Therefore, the carry information is an integral part of the source and destination vector registers. It is useful to restrict the location of the carry (or borrow) information within the source and destination vectors to those adjacent to the mathematical operations that perform (or generate) the carry as an input. Figure 3 and Figure 4 , wherein registers Zda, Zn, Zm are divided into element pairs. Each pair includes a "bottom" element (first element) corresponding to an even number of elements, and a "top" element (second element) corresponding to an odd number of elements. For registers Zda, Zm, carry information is located in the top element of each pair, and the bottom element provides corresponding data. Although other examples can be set by different ways for each pair of data / carry elements (e.g., all data elements are placed in one half of the register and the corresponding carry element is placed in the other half), interleaving data with carry elements can be more efficient, because the input for generating adjacent pairs of elements in Zda is selected from the corresponding Zn, Zm pairs of elements, and avoids the need to use any longer cross-element paths (extending across two or more elements of a vector), which can make the micro-architecture implementation of the processing circuit more efficient. Therefore, these operations effectively divide each vector into "granularity" or segments, which are twice the size of the vector elements.

[0096] Figure 3The operation of ADCLB and ADCLT instructions is shown. For clear explanation, only the detailed operation of a "granularity" (adjacent top element and bottom element pair) is illustrated. It will be understood that each other granularity (element pair) is performed corresponding operation. The ADCLB instruction adds the even element B (odd element T in the case of ADCLT variant) of a source Zn to the even element of the target vector register, using the least significant bit of the upper half of each granularity (odd element) in the second source Zm as the carry input. The summation produced is written into the lower half of each granularity in the target vector, and the carry information produced is written into the least significant bit of the upper half of each granularity in the target. The remaining bits of the upper half of each granularity in Zda remain unused. The result is independent of the position of the bottom (even number) element of each granularity in the carry source register Zm. Moreover, for ADCLB, the result is independent of the unselected (top / odd number) element of the data source register Zn, and for ADCLT, the result is independent of the unselected (bottom / even number) element of Zn.

[0097] By interleaving the carry information with the input or result data in this way, it is ensured that the carry chain is part of the usual data flow. This enables several levels of parallelism. First, there can be more than one carry chain in progress at the same time because the dependencies are resolved at the granularity of the vector registers. Second, the B / T variants of the instruction can be calculated independently (in some microarchitectures, they can be calculated simultaneously if the B / T variants can be fused into a single micro-operation, or the two variants can be processed in parallel by the pipeline). Since the ADCL instruction usually consumes the partial product generated by the previous multiplication step, these instructions make it possible to design the program sequence so that the multiplication and addition steps are "simplified" and there is no additional operation for handling the carry because the carry is essentially already combined with the accumulator. This reduces the overhead of managing the carry information.

[0098] Despite Figure 3 and Figure 4 The "first element" of each pair of elements in the register is located at a lower element position than the second element, so that the result is written to the bottom element of each pair, but in other embodiments, the first element and the second element may be transposed within the register so that the result updates the top element of each pair and the carry is written to the bottom element. However, it is more efficient in the microarchitecture to provide the carry in the more significant element of each pair, because this may correspond to the order in which the bits may be output by the addition circuit, since the carry represents a bit position greater than the most significant bit of the addition data result.

[0099] Figure 4The corresponding processing of the first / second variant of the subtraction variant of the vector carry addition instruction is shown. The operation or data flow of the SBCLB and SBCLT instructions is similar to that of ADCLB and ADCLT, respectively, except that the core operation is "subtraction" (i.e., the same addition, but the elements selected from Zn are 2-complemented before addition), and "borrow" information is used as input and generated at the output instead of "carry" information (borrow represents a carry of -1). The 2-complementation of the Zn data input and the borrow inversion can be simply implemented by reversing the input adder of the Zn data source input and the borrow input value. It is not necessary to add 1 to the Zn data source input respectively, because the inversion of the borrow input value effectively provides this effect. In the case where the borrow value is 0, the inverted borrow input value 1 provides an addition of 1 to the 2's complement, and no borrow is required. In the case where the borrow value is 1, the inverted borrow input value 0 reflects that the subtraction of 1 for the borrow offsets the addition of 1 for the 2's complement. Thus, once both the data input and the borrow input values ​​have been inverted, addition may be performed in the same manner as the addition variant.

[0100] Figure 4A An example of a predicated variant of a vector add with carry instruction is shown. In this example, the predicate is applied to Figure 3 The ADCLB variant shown is not a predicated version of ADCLT, SBCLB, and SBCLT, but similar predicated versions of ADCLT, SBCLB, and SBCLT can be provided. The core add-with-carry operation is performed on each pair of adjacent top / bottom elements of the destination register Zda, with Figure 3 However, the instruction is also associated with a predicate value P, which is stored, for example, in one of the predicate registers 16. The predicate value includes a value similar to Figure 2 Multiple predicate fields for the predicate field, but for Figure 3 and Figure 4 For vector add-with-carry instructions of the type shown, only half of the predicate fields are valid, since the predicate is applied at the granularity of adjacent pairs of elements, rather than for each element. In this example, the valid predicate fields are the fields corresponding to the bottom (even) elements of each pair (and so the result is independent of the predicate fields corresponding to the top elements of each pair, which are marked by an X to indicate that the values ​​of these fields do not affect the result). However, other embodiments may choose to use the top (odd) predicate fields for each pair of elements as the valid predicate fields.

[0101] For pairs of elements of the target vector where the corresponding predicate indicates 1, Figure 3The carry-in addition operation is performed in the same manner, updating the first element of this pair with the data D generated by the addition, and updating the second element of this pair with the carry-in addition output C. However, for the element pairs where the corresponding predicate indicates 0 (such as elements 4 and 5 shown in this example), the update of these elements of the target vector Zda' is suppressed. In contrast, these elements of the target vector Zda' can maintain their previous values ​​(merge predicate), or can be cleared to zero or another predetermined value (fill zero predicate). Therefore, the predicate is applied to each granularity (element pair), rather than to each individual element. It will be understood that Figure 4A One example format for the predicate register 16 is shown, but any other technique for providing a predicate indication indicating whether each pair of elements of the target register Zda' should be masked may be used.

[0102] Figure 5 is a flow chart showing the processing of a vector add with carry instruction, which specifies a target (accumulator) vector register Zda, a second data source vector register Zn, and a carry source vector register Zm (in this example, the target vector register Zda also serves as the first data source vector register). At step 50, the instruction decoder determines whether such a vector add with carry instruction has been detected, and if not detected, processes the current instruction according to the operation represented by the current instruction. When a vector add with carry instruction is encountered, the instruction decoder determines at step 52 whether the instruction is a "top" (second) or "bottom" (first) variant. If the instruction is a top variant, then at step 54, the element selected from each pair of elements in the second data source vector register Zn will be the top element of the pair (in other words, the odd element (second element)), and if the instruction is a bottom (first) variant, then at step 56, the bottom (first or even) element of each pair is selected from the second data source vector register Zn.

[0103] At step 58, the instruction decoder determines whether the instruction is an addition variant or a subtraction variant. If the instruction is an addition variant, then at step 60, for each pair of elements in the destination vector register Zda, the new value Zda(B)' of the bottom (first) element of the pair is set to: (1) the previous value Zda(B) of the bottom element of the pair in the destination vector register; (2) the selected element (top or bottom) of the corresponding pair in the second data source register Zn selected in step 54 or 56; and (3) the carry-in extracted from the top element Zm(T) of the corresponding pair in the carry-source vector register Zm. Furthermore, the least significant bit of the top element Zda(T)' of the corresponding pair in the destination vector register Zda is set to the carry-out of the addition.

[0104] If the instruction is a subtraction variant, then at step 62, the bottom element Zda(B)' of each pair of elements of the destination vector register is set to the previous value Zda(B) of the bottom element minus the value of the corresponding pair of elements in the data source vector Zn selected in step 54 or 56 minus the borrow value represented by the carry value extracted from the top element Zm(T) of the corresponding pair of elements in the carry source vector register Source Zm. Furthermore, the least significant bit of the top element Zda(T)' of the corresponding pair of elements of the destination vector register is set to the borrow output of the subtraction (i.e., the lsb of Zda(T) is set to the output value at the carry output of the adder circuit performing the subtraction).

[0105] although Figures 3 to 5 The example shows a destructive instruction format (in which the same register Zda serves as both the target register and the first data source register), and a non-destructive instruction format may be provided in which another vector register different from the target register is specified as the first data source register to avoid overwriting the first source vector when writing the result to the target register.

[0106] Example usage of these instructions is discussed below.

[0107] The most time-consuming parts of several important cryptographic workloads involve routines that perform mathematical operations on large integer values. In addition to cryptographic schemes, mathematical operations involving large numbers support libraries such as the GNU Multiprecision Arithmetic (GMP) library for financial software and some scientific applications. Such numbers are often used in instances where floating-point operations (regardless of their range) are not suitable due to reproducibility or mathematical rigor considerations. The RSA algorithm is the most commonly used public key cryptography algorithm. The security of the RSA algorithm relies on the perceived difficulty of factoring large numbers. In order to encrypt or decrypt information, the processor needs to multiply large numbers as quickly as possible in a technique called modular exponentiation. For example, in RSA2048, there are many consecutive multiplications of 2048-bit numbers, giving a 4096-bit product, which is then reduced.

[0108] The most direct method for multiplying integers (often called the "textbook" method) requires O(n 2 ) steps, because each bit in one source needs to be multiplied by each bit in the other source. There are "addition" and "data realignment" (shift) operations required, as shown in the following example:

[0109] 111*543=333+(444<<1 digit)+(555<<2 digits)=60273

[0110] However, Karatsuba's algorithm can reduce the multiplication of two n-digit numbers to at most Single-digit multiplication. This method trades off "multiplication" against "addition", "subtraction", etc., and yields good performance advantages under large "n". Each multiplication with input operands of size "n" is divided into multiple smaller multiplications with input operands of size "n / 2", and some auxiliary operations: "addition", "subtraction", etc. The expression for multiplying two n-bit integers A and B to produce a 2n-bit result C can be formally written as Figure 6 The top equation is shown. Note that in this example, a subtractive variant of Karatsuba's algorithm is used to ensure that the partial products do not have unmanageable sizes. Therefore, the multiplication of two 2048-bit integers can be decomposed into three sub-multiplications of 1024-bit integers, as Figure 6 Each 1024-bit multiplication can itself be decomposed into three 512-bit integer multiplications in the same manner. Each 512-bit multiplication can then be further decomposed into three 256-bit integer multiplications. Eventually, a point is reached where further decomposition of the multiplications incurs a large summing cost due to the extra additions, subtractions, or shifts required to recombine the overall result.

[0111] Because the sub-multiplications are independent, it is possible to vectorize the Karatsuba algorithm with proper data layout and organization, such as Figure 6 For example, if the leaf nodes of the Karatsuba tree provide 256-bit sub-multiplications, each of the three 256-bit sub-multiplications of a given branch of the Karatsuba tree can be assigned to a separate lane A, B, C of the vector, as shown in Figure 6 Furthermore, at larger vectors, the six 256-bit sub-multiplications of the different 512x512-bit multiplications at the higher level of the Karatsuba tree can be distributed to six lanes of 8-element vectors (each set of three lanes A, B, C represents three 256x256-bit multiplications corresponding to 512-bit nodes), as shown in the example above. Figure 6 The example below is shown in the middle.

[0112] For example, if a 64-bit element size is chosen, two 256-bit integers A and B can be multiplied as follows: A x B = {a3, a 2, a1,a0}x{b3,b2,b1,b0}. Figure 7 The partial products belonging to this multiplication are plotted. Note that the products are staggered from right to left because each partial product needs to be "realigned" to accumulate in the proper column.

[0113] Figure 8 shows the code sequence, presented in order to execute Figure 7An example of a possible instruction sequence required to compute the second "leg" of a1 x{b3,b2,b1,b0} to compute the partial product a1 x{b3,b2,b1,b0}. The code sequence begins with some multiplications to produce the low and high 64-bit portions of each partial product. Note that each 256-bit x 256-bit multiplication instance occupies a single lane in vector processing, and that the 64-bit components of each 256-bit operand are distributed vertically (in separate registers acted upon by separate instructions), rather than across each vector. This implies that in order to produce the partial product computed for a1 x{b3,b2,b1,b0}, register z1 (containing a1 from a different source operand) needs to be multiplied by z4 (providing b0 from multiple different source operands), z5(b1), z6(b2), and z7(b3) ( Figure 8 Each of lines 1 to 8 of ).

[0114] exist Figure 8 In , the adclb and adclt instructions are used to add partial products to the accumulator for each lane: zacc1LB, zacc1LT, zacc0HB, etc. The corresponding pairs of adclb and adclt instructions are executed to process the even and odd elements of the partial products from the multiplication respectively. The instructions are used in a way that exposes 4-way parallel processing: the B&T variants are independent and can therefore be beneficially scheduled. In addition, there are two carry chains that can be processed simultaneously. One carry chain starts at line 10 and the other carry chain starts at line 12. The first carry chain of the "B" variant can then be traced by the instructions on lines 14, 18, 26. The second carry chain can be traced by the instructions on lines 16, 20, 29. There is a similar chain for the "T" variant. The instructions on lines 32, 33 are used to merge the previous independent carry chains while adding the final partial product (a1×b3(H)) to the accumulator.

[0115] Fig. 9 and FIG. 10A to FIG. 10I Another example of using a vector add with carry instruction is shown. Fig. 9 shows the method for performing the multiplication {a3,a2,a1,a0}xb i , which represents a single leg of a larger multiplication, which may be part of a Karatsuba tree for multiplying large integers. Fig. 9 It is assumed that the partial products have been generated and stored in vector register P 0i lo,P 1i lo…,P 3i hi(where P ji lo and P ji hi represents a j With b iAccB[i] to AccB[i+4] represent five accumulator registers, which are used to store the products {a3, a2, a1, a0}xb shown in columns 0 to 4, respectively. i Each pair of traces represents a completely independent calculation (compared to the other traces) applied to different input values, so for Figure 7 Each partial product addition required for a given computation type is shown by Fig. 9 The instruction sequence is executed within a single pair of lanes (e.g., the computations in each pair of lanes correspond to different nodes of the Karatsuba tree). For simplicity, FIG. 10A to FIG. 10I Only the ADCLB instruction executed on the even vector lanes is shown, and the corresponding ADCLT instruction not shown may be executed on the odd lanes. For clarity of illustration, the first carry chain is shown without an asterisk (e.g., C AccBi ) and the second carry chain is shown with an asterisk (e.g. C AccBi* ), to distinguish between two independent carry chains.

[0116] Fig. 10A : AccB[i] represents the accumulation in column 0. For each pair of elements in AccB[i], the lower (even) element of the pair is set to the sum of: the previous value of the lower element in AccB[i]; P 0i lo; and 0 as the carry-in (since this is the least significant part of the result and so no carry from the lower addition is needed). The result of the addition has presented the terminal result value Res[i] for this partial result, since no further carries can be injected into the least significant part of the result. The carry-out C from the addition accBi The least significant bit of the top element of the pair is written into AccB[i] and represents the carry bit that is equally significant to the least significant bit of column 1.

[0117] Fig. 10B : AccB[i+1] represents the accumulation in column 1. For each pair of elements in AccB[i+1], the lower (even) element of the pair is set to the sum of: the previous value of the lower element in AccB[i+1]; P 1i The bottom element of the corresponding pair of elements in lo; and C as the carry-in accBi In other words, the destination register AccB[i] of the previous ADCLB instruction is designated as the carry source vector register of the next ADCLB instruction, so that the carry C generated by the previous addition in column 0 is accBi is input as the carry-in for the addition in column 1. The carry-out C from the accumulation in column 1 accBi+1The least significant bit of the top element of each pair is stored in AccB[i+1] to represent the carry to be applied to the least significant bit of the accumulation in column 2.

[0118] Fig. 10C : AccB[i+2] represents the accumulation in column 2. Again, the result vector AccB[i+1] of the previous instruction becomes the carry source vector register for the next instruction, so that for each pair of elements, the carry generated by the previous addition in column 1 is accBi+1 The top element of the corresponding pair is extracted from AccB[i+1] and added to AccB[i+2] and P 2i lo is accumulated, which is written to the bottom of the pair of elements in AccB[i+2], and the carry output C is generated accBi+2 is stored in the top element of each pair of elements in AccB[I+2].

[0119] Fig. 10D : This instruction marks the beginning of the second carry chain, independent of the FIG. 10A to FIG. 10C The carry chain taken. This instruction represents the partial product P 0i The first column of hi has Fig. 10B Note that the carry values ​​in the odd elements of AccB[i+1] have been Fig. 10C is consumed, so it can be replaced by the new carry value C accBi+1* Overwrite in odd elements, new carry value C accBi+1* The even elements from AccB[i+1] and P 0i Every addition of the even elements of hi.

[0120] Fig.10E : This instruction is part of the first carry chain and uses the Fig. 10C The carry output C accBi+2 (stored in AccB[i+2] for each pair of elements) as the pair AccB[i+3] and P 3i The carry-in for the addition of the low element of each pair of elements in lo (representing the addition in column 3). The carry-out C generated accBi+2 The high element of each pair of elements is stored in AccB[i+3].

[0121] Fig.10F : This instruction uses the Fig. 10D The carry output C accBi+1* (Equally effective for the least significant bit of the second column), as the second column AccB[i+2] and P 1i hi Carry input for addition.

[0122] Figure 10G:This instruction performs an even-numbered operation on AccB[i+4] and P in the first carry chain. 3i hi performs vector addition, and the carry input of each addition comes from the odd lane of AccB[i+3] (from Fig.10E ). Although instructions may still write the carries out of their respective additions into the least significant bits of the odd elements of AccB[i+4], these carries are not actually needed by any subsequent instructions since this accumulation represents the most significant bits of the result.

[0123] Fig. 10H :This instruction performs an even-numbered operation on AccB[i+3] and P in the second carry chain. 2i hi performs vector addition, and the carry bit of each addition is input to C accBi+2* Odd lanes from AccB[i+2] (from Fig.10F ).

[0124] Fig.10I Finally, this instruction performs a vector addition on the even lanes of AccB[i+4] with the zeroed data source register in the second carry chain (the second data input is zero because only one partial product is to be added to the most significant column, which is already determined by Figure 10G Each addition carries into C. accBi+2* Odd lanes from AccB[i+3] (from Figure 10G ). The result of each addition is written to the even lane of the accumulator register AccB[i+4]. Again, although the carry-out from each addition may be written to the odd lane as part of the normal behavior of the instruction, these carries are not needed for any further instructions.

[0125] Thus, this example shows how the ADCLB instruction efficiently allows the carry information of the addition of the multiplication partial products to be transmitted along with the data result itself, so as to enable application to an input vector of elements of two-digit powers (e.g., P 0i lo to P 3i hi) This efficient computation of the multiplication eliminates the need to unpack the result of the vector multiplication instruction before performing the addition. This improves the performance of computations involving long integer multiplications, such as using the Karatsuba algorithm.

[0126] Fig.11An alternative way of implementing an add with carry instruction is shown. Instead of taking a carry input from alternating elements of a vector register, a carry input from the corresponding predicate field of the input predicate register Pm is obtained from the predicate register file 16. Similarly, the carry output is written to the corresponding predicate field in the target predicate register Pd2. By this method, the vector can be completely occupied by real data values ​​because there is no need to present a carry in every other element. Therefore, for an eight-element vector, this will allow eight separate accumulations to be performed in response to the same instruction. Each element of the result vector Zda1 is set to the sum or difference of the previous value of this element and the corresponding element of the data source vector Zn. The carry input of the addition is extracted from the corresponding predicate field of the input predicate register Pm, and the carry output from the addition is written to the corresponding predicate field of the output predicate register Pd2. Again, it can be similar to Figure 3 and Figure 4 Addition and subtraction variants are provided as shown so that the carry input / output can represent carry or borrow information (borrow represents subtraction from the next most significant bit, while carry represents addition to the next most significant bit, i.e., borrow is carry-1).

[0127] although Fig.11 The approach shown in may produce a more tightly packed vector register file and thus enable accumulation to be performed in half the number of instructions (e.g., no separate ADCLB and ADCLT instructions are needed since all elements of the metadata vector can be processed in one instruction), but this may require more complex microarchitectural modifications since instructions may need to write to the predicate register file in addition to the vector register file, which is uncommon for many vector microarchitectures. Therefore, to use Figure 3 , 4 or Fig.11 The approach in may depend on the trade-off between software efficiency and hardware microarchitectural efficiency.

[0128] Fig.12 A flow chart of the processing of the predicate form of an add with carry instruction is shown. At step 100, it is detected whether such a vector add with carry instruction is encountered, and if not detected, the instruction decoder 6 controls the processing circuit 4 to perform other operations represented by the detected instruction type. If the instruction is a vector add with carry instruction, then at step 102, it is detected whether the instruction is an addition variant or a subtraction variant. Note that there are no first and second (top or bottom) variants for this instruction, because by moving the carry information to separate the predicate register, it is not necessary to save half of the elements for the carry, and it is therefore possible to process all elements of the data source register in a single instruction.

[0129] If the vector add with carry instruction is an addition variant, then at step 104, the new value of each element i of the destination register Zda1(i)' is set equal to the sum of the previous value of this data element Zda1(i), the corresponding data element Zn(i) of the data source vector register, and the carry input obtained from the corresponding predicate field i of the input predicate register Pm(i). Furthermore, the corresponding predicate field Pd2(i) of the output predicate register is set equal to the carry output of the addition.

[0130] If the instruction is a subtraction variant, then at step 106, each element Zda1(i)' of the destination register is set to a new value corresponding to the previous value of that element Zda1(i) minus the corresponding element Zn(i) of the data source register, minus the borrow value indicated by the corresponding predicate field of the input predicate register Pm(i). Again, the corresponding predicate field Pd2(i) of the output predicate register is set equal to the borrow output of the subtraction. It will be appreciated that steps 104 and 106 are performed separately for each respective element position (i.e., i=0...N-1, where N is the total number of elements in the vector).

[0131] Despite Fig.11 and Fig.12 An example is shown in which the same register Zda1 acts as both the destination vector register and the first source vector register, but a non-destructive variant may equally be provided in which a separate register is designated as the first source vector register.

[0132] Also available Fig.11 The predicated variant of the add with carry instruction is shown in Figure 1, where the Figure 2 The predicate is applied element-wise in a similar manner as shown.

[0133] Fig.13Illustrated are usable emulator embodiments. Although the aforementioned embodiments are implemented in the apparatus and method for operating the specific processing hardware supporting the related technology, the instruction execution environment implemented by using a computer program according to the embodiments described herein can also be provided. This computer program is generally referred to as an emulator, as long as they provide a software-based implementation of the hardware architecture. Various emulator computer programs include emulators, virtual machines, models, and binary translators (including dynamic binary translators). Generally speaking, the emulator implementation can be run on a host processor 230, optionally running a host operating system 220 supporting the emulator 210. In some settings, there can be multiple simulation layers between the hardware and the instruction execution environment provided and / or a plurality of different instruction execution environments provided on the same host processor. In the past history, a powerful processor was needed to provide an emulator implementation executed at a reasonable speed, but this method can be solved in some cases, such as when the native code of another processor needs to be run due to compatibility or reuse reasons. For example, the emulator implementation can provide an instruction execution environment with additional functions that the host processor hardware does not support, or provide an instruction execution environment that is usually associated with different hardware architectures. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques" by Robert Bedichek (Winter 1990 USENIX Conference), pages 53-63.

[0134] To the extent that embodiments have been previously described with reference to specific hardware constructs or features, in simulated embodiments, equivalent functionality may be provided by suitable software constructs or features. For example, specific circuits may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware, such as registers or caches, may be implemented in simulated embodiments as software data structures. In settings where one or more of the hardware components mentioned in the foregoing embodiments are present on host hardware (e.g., host processor 230), some simulated embodiments may use the host hardware when appropriate.

[0135] The emulator program 210 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provide a program interface (instruction execution environment) to the target code 200 (which may include applications, operating systems, and managers), and the program interface is the same as the application program interface of the hardware architecture modeled by the emulator program 210. Therefore, the program instructions of the target code 200 can be executed from the instruction execution environment using the emulator program 210, so that the host computer 230 that does not actually have the hardware features of the aforementioned device 2 can emulate these features. For example, the emulator program 210 may include an instruction decoding program logic 212, a processing program logic 214, and a register data structure 216 (functionally corresponding to the instruction decoder 6), the processing circuit 4, and the register 10, respectively. For example, the decoding program logic 212 may include a series of "if" statements of the emulator program 210 to check the instruction encoding of the instructions of the target code 200 to determine the operation to be performed, and the processing program logic 214 may correspond to a "then" routine to be enabled for specific instructions to map them to corresponding instructions to be executed by the host operating system 220. Register data structure 216 may include memory areas allocated to emulate registers of emulated device 2 being emulated by emulator program 210 .

[0136] In this application, the phrase "configured to..." is used to indicate that components of a device have a configuration that enables the performance of a defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, a device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device components need to be changed in any way in order to provide the defined operation.

[0137] Although exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the present invention is not limited to these precise embodiments and that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A data processing device, comprising: processing circuitry for performing data processing; an instruction decoding circuit, used for decoding instructions to control the processing circuit to perform the data processing; as well as A plurality of vector registers for storing vector operands including a plurality of data elements; wherein: The instruction decoding circuit, in response to a vector add-with-carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, and a carry source vector register, controls the processing circuit to perform the following operation for each data element pair of the destination vector register, wherein at least the destination vector register and the carry source vector register each specify an operand including at least one data element pair, each data element pair including a first data element and a second data element, and the operation includes: updating the first data element of the pair of data elements of the destination vector register with a value corresponding to a result of an addition of a first source data value obtained from a selected data element of the first data source vector register, a second source data value obtained from a selected data element of the second data source vector register, and a carry value obtained from the second data element of the corresponding pair of data elements of the carry source vector register; and updating the second data element of the pair of data elements of the target vector register with a value corresponding to a carry out of the addition, wherein the first data element of the pair of data elements of the target vector register updated with a value corresponding to a result of the addition and the second data element of the pair of data elements of the target vector register updated with a value corresponding to a carry output of the addition are data elements of the same vector register.

2. The device according to claim 1, wherein: The first data source vector register is the same register as the destination vector register, and the first source data value comprises a previous value of the first data element of the pair of data elements of the destination vector register.

3. The device according to any one of claims 1 and 2, wherein: Each data element pair includes adjacent data element pairs.

4. The device according to claim 1, wherein: When the number of pairs of data elements in the destination vector register and the carry source vector register is at least two, the first data elements of the pairs of data elements and the second data elements of the pairs of data elements are interleaved.

5. The device according to claim 1, wherein: The instruction decoding circuit is configured to control the processing circuit to perform the following operations in response to the vector add with carry instruction: obtaining the carry value from the least significant bit of the second data element of the corresponding pair of data elements of the carry source vector register, and A least significant bit of the second data element of the pair of data elements of the target vector register is updated with a value corresponding to the carry output of the addition.

6. The device according to claim 5, wherein: In response to the vector add-with-carry instruction, remaining bits of the second data element other than the least significant bit are unused for both the carry source vector register and the target vector register.

7. The device according to claim 1, wherein: Each data element consists of 2 N digits, and the second source data value includes 2 N Units digit, where N is an integer.

8. The device according to claim 1, wherein: The second data source vector register also specifies an operand including at least one data element pair, each data element pair including a first data element and a second data element; In response to the first variant of the vector add-with-carry instruction, the second source data value comprises a value obtained from the first data element of a corresponding pair of data elements of the second data source vector register; as well as In response to the second variant of the vector add-with-carry instruction, the second source data value comprises a value obtained from the second data element of the corresponding pair of data elements of the second data source vector register.

9. The device according to claim 1, wherein: In response to a predicated variant of the vector add-with-carry instruction, wherein the predicated variant is associated with a predicate value specifying at least one predicate indication and each predicate indication corresponds to one of the at least one pair of data elements of the target vector register, the instruction decoding circuitry is configured to control the processing circuitry to: for a pair of data elements for which a corresponding predicate indicates a first value, performing said updating of said first data element of said pair of data elements with a value corresponding to a result of said addition and said updating of said second data element of said pair of data elements with said carry-out of said addition; as well as For a data element pair for which the corresponding predicate indicates a second value, the updating of the first data element of the data element pair with a value corresponding to a result of the addition and the updating of the second data element of the data element pair with the carry output of the addition are suppressed.

10. The apparatus of claim 1, wherein in response to an add variant of the vector add-with-carry instruction, the adding comprises adding the first source data value, the second source data value, and the carry value; and In response to a subtraction variant of the vector add-with-carry instruction, the addition comprises subtracting the second source data value from the first source data value, wherein, The carry value indicates a borrow value of the subtraction, and the carry output comprises a borrow output of the subtraction.

11. A computer readable storage medium comprising a computer program for controlling a host processing device to provide an instruction execution environment for executing target program code instructions, the computer program comprising: Instruction decoding program logic for decoding the target program code instructions to control the processing program logic to perform data processing; as well as A vector register data structure for storing data representing a plurality of vector registers for storing a vector operand comprising a plurality of data elements; wherein: The instruction decode program logic, in response to a vector add-with-carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, and a carry source vector register, controls the processing program logic to update the vector register data structure to perform the following operations for each data element pair of the destination vector register, wherein at least the destination vector register and the carry source vector register each specify an operand including at least one data element pair, each data element pair including a first data element and a second data element, the operations comprising: updating the first data element of the pair of data elements of the destination vector register with a value corresponding to a result of an addition of a first source data value obtained from a selected data element of the first data source vector register, a second source data value obtained from a selected data element of the second data source vector register, and a carry value obtained from the second data element of the corresponding pair of data elements of the carry source vector register; and updating the second data element of the pair of data elements of the target vector register with a value corresponding to a carry out of the addition, wherein the first data element of the pair of data elements of the target vector register updated with a value corresponding to a result of the addition and the second data element of the pair of data elements of the target vector register updated with a value corresponding to a carry output of the addition are data elements of the same vector register.

12. A data processing method comprising the following steps: decoding a vector add-with-carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, and a carry source vector register, at least the destination vector register and the carry source vector register each specifying an operand including at least one data element pair, each data element pair including a first data element and a second data element; and In response to decoding of the vector add with carry instruction, the control processing circuit performs the following operations for each data element of the target vector register: updating the first data element of the pair of data elements of the destination vector register with a new value corresponding to a result of an addition of a first source data value obtained from a selected data element of the first data source vector register, a second source data value obtained from a selected data element of the second data source vector register, and a carry value obtained from the second data element of the corresponding pair of data elements of the carry source vector register; as well as updating the second data element of the pair of data elements of the target vector register with a value corresponding to a carry out of the addition, wherein the first data element of the pair of data elements of the target vector register updated with a value corresponding to a result of the addition and the second data element of the pair of data elements of the target vector register updated with a value corresponding to a carry output of the addition are data elements of the same vector register.

13. A data processing device comprising: processing circuitry for performing data processing; an instruction decoding circuit, used for decoding instructions to control the processing circuit to perform the data processing; a plurality of vector registers for storing vector operands including a plurality of data elements; as well as a plurality of predicate registers including a plurality of predicate fields for storing predicate values ​​for controlling a mask for an operation performed by the processing circuit; wherein: The instruction decoding circuit, in response to a vector add with carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, an input predicate register, and an output predicate register, controls the processing circuit to perform the following operations for a given data element of the destination vector register: updating the given data element of the target vector register with a value corresponding to a result of an addition of a first source data value obtained from a corresponding data element of the first data source vector register, a second source data value obtained from a corresponding data element of the second data source vector register, and a carry value obtained from a corresponding predicate field of the input predicate register; and A corresponding predicate field of the output predicate register is updated with a value corresponding to a carry output of the addition.

14. A computer readable storage medium comprising a computer program for controlling a host processing device to provide an instruction execution environment for executing target program code instructions, the computer program comprising: Instruction decoding program logic for decoding the target program code instructions to control the processing program logic to perform data processing; as well as a register data structure for storing data representing a plurality of vector registers for storing vector operands comprising a plurality of data elements and a plurality of predicate registers for storing predicate values ​​for controlling masks for vector operations performed by the processing program logic; wherein: The instruction decode program logic, in response to an add-with-carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, an input predicate register, and an output predicate register vector, controls the processing circuitry to update the register data structure to perform the following operations for a given data element of the destination vector register: updating the given data element of the destination vector register with a value corresponding to a result of a first source data value obtained from a corresponding data element of the first data source vector register, a second source data value obtained from a corresponding data element of the second data source vector register, and a carry value obtained from a corresponding predicate field of the input predicate register; and A corresponding predicate field of the output predicate register is updated with a value corresponding to a carry output of the addition.

15. A data processing method, comprising: decoding a vector add with carry instruction specifying a destination vector register, a first data source vector register, a second data source vector register, an input predicate register, and an output predicate register, the input predicate register and the output predicate register being selected from a plurality of predicate registers for storing predicate values, the predicate values ​​being used to control a mask for a vector operation; and In response to decoding of the vector add-with-carry instruction, the processing circuit is controlled to perform the following operations for a given data element of the target vector register: updating the given data element of the target vector register with a value corresponding to a result of an addition of a first source data value obtained from a corresponding data element of the first data source vector register, a second source data value obtained from a corresponding data element of the second data source vector register, and a carry value obtained from a corresponding predicate field of the input predicate register; and A corresponding predicate field of the output predicate register is updated with a value corresponding to a carry output of the addition.

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